rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `I2C1` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR1` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr1 = 0,
    /// `CR2` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Cr2 = 1,
    /// `OAR1` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Oar1 = 2,
    /// `OAR2` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Oar2 = 3,
    /// `TIMINGR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Timingr = 4,
    /// `TIMEOUTR` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Timeoutr = 5,
    /// `ISR` at offset `0x18`, resets to `0x0000_0001`, read-write.
    Isr = 6,
    /// `ICR` at offset `0x1C`, resets to `0x0000_0000`, write-only.
    Icr = 7,
    /// `PECR` at offset `0x20`, resets to `0x0000_0000`, read-only.
    Pecr = 8,
    /// `RXDR` at offset `0x24`, resets to `0x0000_0000`, read-only.
    Rxdr = 9,
    /// `TXDR` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Txdr = 10,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 11] = [Self::Cr1, Self::Cr2, Self::Oar1, Self::Oar2, Self::Timingr, Self::Timeoutr, Self::Isr, Self::Icr, Self::Pecr, Self::Rxdr, Self::Txdr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR1`.
pub mod cr1 {
    use super::FieldSpec;
    /// `PE`, bit 0.
    pub const PE: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `TXIE`, bit 1.
    pub const TXIE: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `RXIE`, bit 2.
    pub const RXIE: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `ADDRIE`, bit 3.
    pub const ADDRIE: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `NACKIE`, bit 4.
    pub const NACKIE: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `STOPIE`, bit 5.
    pub const STOPIE: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `TCIE`, bit 6.
    pub const TCIE: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `ERRIE`, bit 7.
    pub const ERRIE: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `DNF`, bits 8..=11.
    pub const DNF: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `ANFOFF`, bit 12.
    pub const ANFOFF: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `TXDMAEN`, bit 14.
    pub const TXDMAEN: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `RXDMAEN`, bit 15.
    pub const RXDMAEN: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `SBC`, bit 16.
    pub const SBC: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `NOSTRETCH`, bit 17.
    pub const NOSTRETCH: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `WUPEN`, bit 18.
    pub const WUPEN: &FieldSpec = &super::REGISTERS[0].fields[14];
    /// `GCEN`, bit 19.
    pub const GCEN: &FieldSpec = &super::REGISTERS[0].fields[15];
    /// `SMBHEN`, bit 20.
    pub const SMBHEN: &FieldSpec = &super::REGISTERS[0].fields[16];
    /// `SMBDEN`, bit 21.
    pub const SMBDEN: &FieldSpec = &super::REGISTERS[0].fields[17];
    /// `ALERTEN`, bit 22.
    pub const ALERTEN: &FieldSpec = &super::REGISTERS[0].fields[18];
    /// `PECEN`, bit 23.
    pub const PECEN: &FieldSpec = &super::REGISTERS[0].fields[19];
}

/// The fields of `CR2`.
pub mod cr2 {
    use super::FieldSpec;
    /// `SADD0`, bit 0.
    pub const SADD0: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `SADD1`, bit 1.
    pub const SADD1: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `SADD2`, bit 2.
    pub const SADD2: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `SADD3`, bit 3.
    pub const SADD3: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `SADD4`, bit 4.
    pub const SADD4: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `SADD5`, bit 5.
    pub const SADD5: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `SADD6`, bit 6.
    pub const SADD6: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `SADD7`, bit 7.
    pub const SADD7: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `SADD8`, bit 8.
    pub const SADD8: &FieldSpec = &super::REGISTERS[1].fields[8];
    /// `SADD9`, bit 9.
    pub const SADD9: &FieldSpec = &super::REGISTERS[1].fields[9];
    /// `RD_WRN`, bit 10.
    pub const RD_WRN: &FieldSpec = &super::REGISTERS[1].fields[10];
    /// `ADD10`, bit 11.
    pub const ADD10: &FieldSpec = &super::REGISTERS[1].fields[11];
    /// `HEAD10R`, bit 12.
    pub const HEAD10R: &FieldSpec = &super::REGISTERS[1].fields[12];
    /// `START`, bit 13.
    pub const START: &FieldSpec = &super::REGISTERS[1].fields[13];
    /// `STOP`, bit 14.
    pub const STOP: &FieldSpec = &super::REGISTERS[1].fields[14];
    /// `NACK`, bit 15.
    pub const NACK: &FieldSpec = &super::REGISTERS[1].fields[15];
    /// `NBYTES`, bits 16..=23.
    pub const NBYTES: &FieldSpec = &super::REGISTERS[1].fields[16];
    /// `RELOAD`, bit 24.
    pub const RELOAD: &FieldSpec = &super::REGISTERS[1].fields[17];
    /// `AUTOEND`, bit 25.
    pub const AUTOEND: &FieldSpec = &super::REGISTERS[1].fields[18];
    /// `PECBYTE`, bit 26.
    pub const PECBYTE: &FieldSpec = &super::REGISTERS[1].fields[19];
}

/// The fields of `OAR1`.
pub mod oar1 {
    use super::FieldSpec;
    /// `OA1`, bits 0..=9.
    pub const OA1: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `OA1MODE`, bit 10.
    pub const OA1MODE: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `OA1EN`, bit 15.
    pub const OA1EN: &FieldSpec = &super::REGISTERS[2].fields[2];
}

/// The fields of `OAR2`.
pub mod oar2 {
    use super::FieldSpec;
    /// `OA2`, bits 1..=7.
    pub const OA2: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `OA2MSK`, bits 8..=10.
    pub const OA2MSK: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `OA2EN`, bit 15.
    pub const OA2EN: &FieldSpec = &super::REGISTERS[3].fields[2];
}

/// The fields of `TIMINGR`.
pub mod timingr {
    use super::FieldSpec;
    /// `SCLL`, bits 0..=7.
    pub const SCLL: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `SCLH`, bits 8..=15.
    pub const SCLH: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `SDADEL`, bits 16..=19.
    pub const SDADEL: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `SCLDEL`, bits 20..=23.
    pub const SCLDEL: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `PRESC`, bits 28..=31.
    pub const PRESC: &FieldSpec = &super::REGISTERS[4].fields[4];
}

/// The fields of `TIMEOUTR`.
pub mod timeoutr {
    use super::FieldSpec;
    /// `TIMEOUTA`, bits 0..=11.
    pub const TIMEOUTA: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `TIDLE`, bit 12.
    pub const TIDLE: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `TIMOUTEN`, bit 15.
    pub const TIMOUTEN: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `TIMEOUTB`, bits 16..=27.
    pub const TIMEOUTB: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `TEXTEN`, bit 31.
    pub const TEXTEN: &FieldSpec = &super::REGISTERS[5].fields[4];
}

/// The fields of `ISR`.
pub mod isr {
    use super::FieldSpec;
    /// `TXE`, bit 0.
    pub const TXE: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `TXIS`, bit 1.
    pub const TXIS: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `RXNE`, bit 2, read-only.
    pub const RXNE: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `ADDR`, bit 3, read-only.
    pub const ADDR: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `NACKF`, bit 4, read-only.
    pub const NACKF: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `STOPF`, bit 5, read-only.
    pub const STOPF: &FieldSpec = &super::REGISTERS[6].fields[5];
    /// `TC`, bit 6, read-only.
    pub const TC: &FieldSpec = &super::REGISTERS[6].fields[6];
    /// `TCR`, bit 7, read-only.
    pub const TCR: &FieldSpec = &super::REGISTERS[6].fields[7];
    /// `BERR`, bit 8, read-only.
    pub const BERR: &FieldSpec = &super::REGISTERS[6].fields[8];
    /// `ARLO`, bit 9, read-only.
    pub const ARLO: &FieldSpec = &super::REGISTERS[6].fields[9];
    /// `OVR`, bit 10, read-only.
    pub const OVR: &FieldSpec = &super::REGISTERS[6].fields[10];
    /// `PECERR`, bit 11, read-only.
    pub const PECERR: &FieldSpec = &super::REGISTERS[6].fields[11];
    /// `TIMEOUT`, bit 12, read-only.
    pub const TIMEOUT: &FieldSpec = &super::REGISTERS[6].fields[12];
    /// `ALERT`, bit 13, read-only.
    pub const ALERT: &FieldSpec = &super::REGISTERS[6].fields[13];
    /// `BUSY`, bit 15, read-only.
    pub const BUSY: &FieldSpec = &super::REGISTERS[6].fields[14];
    /// `DIR`, bit 16, read-only.
    pub const DIR: &FieldSpec = &super::REGISTERS[6].fields[15];
    /// `ADDCODE`, bits 17..=23, read-only.
    pub const ADDCODE: &FieldSpec = &super::REGISTERS[6].fields[16];
}

/// The fields of `ICR`.
pub mod icr {
    use super::FieldSpec;
    /// `ADDRCF`, bit 3.
    pub const ADDRCF: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `NACKCF`, bit 4.
    pub const NACKCF: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `STOPCF`, bit 5.
    pub const STOPCF: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `BERRCF`, bit 8.
    pub const BERRCF: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `ARLOCF`, bit 9.
    pub const ARLOCF: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `OVRCF`, bit 10.
    pub const OVRCF: &FieldSpec = &super::REGISTERS[7].fields[5];
    /// `PECCF`, bit 11.
    pub const PECCF: &FieldSpec = &super::REGISTERS[7].fields[6];
    /// `TIMOUTCF`, bit 12.
    pub const TIMOUTCF: &FieldSpec = &super::REGISTERS[7].fields[7];
    /// `ALERTCF`, bit 13.
    pub const ALERTCF: &FieldSpec = &super::REGISTERS[7].fields[8];
}

/// The fields of `PECR`.
pub mod pecr {
    use super::FieldSpec;
    /// `PEC`, bits 0..=7.
    pub const PEC: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The fields of `RXDR`.
pub mod rxdr {
    use super::FieldSpec;
    /// `RXDATA`, bits 0..=7.
    pub const RXDATA: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `TXDR`.
pub mod txdr {
    use super::FieldSpec;
    /// `TXDATA`, bits 0..=7.
    pub const TXDATA: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 11] = [
    RegisterSpec { name: "CR1", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADDRIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NACKIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STOPIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ERRIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DNF", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ANFOFF", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXDMAEN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXDMAEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SBC", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NOSTRETCH", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WUPEN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GCEN", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMBHEN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMBDEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ALERTEN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PECEN", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR2", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SADD0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SADD1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SADD2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SADD3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SADD4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SADD5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SADD6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SADD7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SADD8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SADD9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RD_WRN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADD10", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HEAD10R", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "START", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STOP", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NACK", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NBYTES", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RELOAD", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AUTOEND", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PECBYTE", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OAR1", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OA1", bit: 0, width: 10, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OA1MODE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OA1EN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OAR2", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OA2", bit: 1, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OA2MSK", bit: 8, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OA2EN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TIMINGR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SCLL", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCLH", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SDADEL", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCLDEL", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PRESC", bit: 28, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TIMEOUTR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TIMEOUTA", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIDLE", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMOUTEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMEOUTB", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEXTEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ISR", offset: 0x18, width: Width::W32, reset: 0x0000_0001, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TXE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXIS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXNE", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADDR", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NACKF", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STOPF", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TC", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCR", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BERR", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARLO", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVR", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PECERR", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMEOUT", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ALERT", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSY", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADDCODE", bit: 17, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ICR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDRCF", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NACKCF", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STOPCF", bit: 5, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BERRCF", bit: 8, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARLOCF", bit: 9, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVRCF", bit: 10, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PECCF", bit: 11, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMOUTCF", bit: 12, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ALERTCF", bit: 13, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PECR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PEC", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RXDR", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXDATA", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TXDR", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TXDATA", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];