rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `ADC3_Common` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CSR` at offset `0x0`, resets to `0x0000_0000`, read-only.
    Csr = 0,
    /// `CCR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Ccr = 1,
    /// `CDR` at offset `0xC`, resets to `0x0000_0000`, read-only.
    Cdr = 2,
    /// `CDR2` at offset `0x10`, resets to `0x0000_0000`, read-only.
    Cdr2 = 3,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 4] = [Self::Csr, Self::Ccr, Self::Cdr, Self::Cdr2];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CSR`.
pub mod csr {
    use super::FieldSpec;
    /// `ADRDY_MST`, bit 0.
    pub const ADRDY_MST: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `EOSMP_MST`, bit 1.
    pub const EOSMP_MST: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `EOC_MST`, bit 2.
    pub const EOC_MST: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `EOS_MST`, bit 3.
    pub const EOS_MST: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `OVR_MST`, bit 4.
    pub const OVR_MST: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `JEOC_MST`, bit 5.
    pub const JEOC_MST: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `JEOS_MST`, bit 6.
    pub const JEOS_MST: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `AWD1_MST`, bit 7.
    pub const AWD1_MST: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `AWD2_MST`, bit 8.
    pub const AWD2_MST: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `AWD3_MST`, bit 9.
    pub const AWD3_MST: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `JQOVF_MST`, bit 10.
    pub const JQOVF_MST: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `ADRDY_SLV`, bit 16.
    pub const ADRDY_SLV: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `EOSMP_SLV`, bit 17.
    pub const EOSMP_SLV: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `EOC_SLV`, bit 18.
    pub const EOC_SLV: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `EOS_SLV`, bit 19.
    pub const EOS_SLV: &FieldSpec = &super::REGISTERS[0].fields[14];
    /// `OVR_SLV`, bit 20.
    pub const OVR_SLV: &FieldSpec = &super::REGISTERS[0].fields[15];
    /// `JEOC_SLV`, bit 21.
    pub const JEOC_SLV: &FieldSpec = &super::REGISTERS[0].fields[16];
    /// `JEOS_SLV`, bit 22.
    pub const JEOS_SLV: &FieldSpec = &super::REGISTERS[0].fields[17];
    /// `AWD1_SLV`, bit 23.
    pub const AWD1_SLV: &FieldSpec = &super::REGISTERS[0].fields[18];
    /// `AWD2_SLV`, bit 24.
    pub const AWD2_SLV: &FieldSpec = &super::REGISTERS[0].fields[19];
    /// `AWD3_SLV`, bit 25.
    pub const AWD3_SLV: &FieldSpec = &super::REGISTERS[0].fields[20];
    /// `JQOVF_SLV`, bit 26.
    pub const JQOVF_SLV: &FieldSpec = &super::REGISTERS[0].fields[21];
}

/// The fields of `CCR`.
pub mod ccr {
    use super::FieldSpec;
    /// `DUAL`, bits 0..=4.
    pub const DUAL: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `DELAY`, bits 8..=11.
    pub const DELAY: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `DAMDF`, bits 14..=15.
    pub const DAMDF: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `CKMODE`, bits 16..=17.
    pub const CKMODE: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `PRESC`, bits 18..=21.
    pub const PRESC: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `VREFEN`, bit 22.
    pub const VREFEN: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `VSENSEEN`, bit 23.
    pub const VSENSEEN: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `VBATEN`, bit 24.
    pub const VBATEN: &FieldSpec = &super::REGISTERS[1].fields[7];
}

/// The fields of `CDR`.
pub mod cdr {
    use super::FieldSpec;
    /// `RDATA_MST`, bits 0..=15.
    pub const RDATA_MST: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `RDATA_SLV`, bits 16..=31.
    pub const RDATA_SLV: &FieldSpec = &super::REGISTERS[2].fields[1];
}

/// The fields of `CDR2`.
pub mod cdr2 {
    use super::FieldSpec;
    /// `RDATA_ALT`, bits 0..=31.
    pub const RDATA_ALT: &FieldSpec = &super::REGISTERS[3].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 4] = [
    RegisterSpec { name: "CSR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADRDY_MST", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOSMP_MST", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOC_MST", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOS_MST", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVR_MST", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEOC_MST", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEOS_MST", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWD1_MST", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWD2_MST", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWD3_MST", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JQOVF_MST", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADRDY_SLV", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOSMP_SLV", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOC_SLV", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOS_SLV", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVR_SLV", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEOC_SLV", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEOS_SLV", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWD1_SLV", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWD2_SLV", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWD3_SLV", bit: 25, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JQOVF_SLV", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DUAL", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DELAY", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DAMDF", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKMODE", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PRESC", bit: 18, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VREFEN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VSENSEEN", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VBATEN", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CDR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RDATA_MST", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RDATA_SLV", bit: 16, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CDR2", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RDATA_ALT", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];