rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `COMP1` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `SR` at offset `0x0`, resets to `0x0000_0000`, read-only.
    Sr = 0,
    /// `ICFR` at offset `0x4`, resets to `0x0000_0000`, write-only.
    Icfr = 1,
    /// `OR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Or = 2,
    /// `CFGR1` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Cfgr1 = 3,
    /// `CFGR2` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Cfgr2 = 4,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 5] = [Self::Sr, Self::Icfr, Self::Or, Self::Cfgr1, Self::Cfgr2];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `SR`.
pub mod sr {
    use super::FieldSpec;
    /// `C1VAL`, bit 0.
    pub const C1VAL: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `C2VAL`, bit 1.
    pub const C2VAL: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `C1IF`, bit 16.
    pub const C1IF: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `C2IF`, bit 17.
    pub const C2IF: &FieldSpec = &super::REGISTERS[0].fields[3];
}

/// The fields of `ICFR`.
pub mod icfr {
    use super::FieldSpec;
    /// `CC1IF`, bit 16.
    pub const CC1IF: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `CC2IF`, bit 17.
    pub const CC2IF: &FieldSpec = &super::REGISTERS[1].fields[1];
}

/// The fields of `OR`.
pub mod or {
    use super::FieldSpec;
    /// `AFOP`, bits 0..=10.
    pub const AFOP: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `OR`, bits 11..=31.
    pub const OR: &FieldSpec = &super::REGISTERS[2].fields[1];
}

/// The fields of `CFGR1`.
pub mod cfgr1 {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `BRGEN`, bit 1.
    pub const BRGEN: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `SCALEN`, bit 2.
    pub const SCALEN: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `POLARITY`, bit 3.
    pub const POLARITY: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `ITEN`, bit 6.
    pub const ITEN: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `HYST`, bits 8..=9.
    pub const HYST: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `PWRMODE`, bits 12..=13.
    pub const PWRMODE: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `INMSEL`, bits 16..=18.
    pub const INMSEL: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `INPSEL`, bit 20.
    pub const INPSEL: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `BLANKING`, bits 24..=27.
    pub const BLANKING: &FieldSpec = &super::REGISTERS[3].fields[9];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[3].fields[10];
}

/// The fields of `CFGR2`.
pub mod cfgr2 {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `BRGEN`, bit 1.
    pub const BRGEN: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `SCALEN`, bit 2.
    pub const SCALEN: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `POLARITY`, bit 3.
    pub const POLARITY: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `WINMODE`, bit 4.
    pub const WINMODE: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `ITEN`, bit 6.
    pub const ITEN: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `HYST`, bits 8..=9.
    pub const HYST: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `PWRMODE`, bits 12..=13.
    pub const PWRMODE: &FieldSpec = &super::REGISTERS[4].fields[7];
    /// `INMSEL`, bits 16..=18.
    pub const INMSEL: &FieldSpec = &super::REGISTERS[4].fields[8];
    /// `INPSEL`, bit 20.
    pub const INPSEL: &FieldSpec = &super::REGISTERS[4].fields[9];
    /// `BLANKING`, bits 24..=27.
    pub const BLANKING: &FieldSpec = &super::REGISTERS[4].fields[10];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[4].fields[11];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 5] = [
    RegisterSpec { name: "SR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "C1VAL", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "C2VAL", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "C1IF", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "C2IF", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ICFR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CC1IF", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2IF", bit: 17, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AFOP", bit: 0, width: 11, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OR", bit: 11, width: 21, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CFGR1", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BRGEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCALEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "POLARITY", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ITEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HYST", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PWRMODE", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "INMSEL", bit: 16, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "INPSEL", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BLANKING", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CFGR2", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BRGEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCALEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "POLARITY", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WINMODE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ITEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HYST", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PWRMODE", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "INMSEL", bit: 16, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "INPSEL", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BLANKING", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];