rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `OTG1_HS_PWRCLK` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `OTG_HS_PCGCR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    OtgHsPcgcr = 0,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 1] = [Self::OtgHsPcgcr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `OTG_HS_PCGCR`.
pub mod otg_hs_pcgcr {
    use super::FieldSpec;
    /// `STPPCLK`, bit 0.
    pub const STPPCLK: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `GATEHCLK`, bit 1.
    pub const GATEHCLK: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `PHYSUSP`, bit 4.
    pub const PHYSUSP: &FieldSpec = &super::REGISTERS[0].fields[2];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 1] = [
    RegisterSpec { name: "OTG_HS_PCGCR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "STPPCLK", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GATEHCLK", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PHYSUSP", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];