rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `HRTIM_Master` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `MCR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Mcr = 0,
    /// `MISR` at offset `0x4`, resets to `0x0000_0000`, read-only.
    Misr = 1,
    /// `MICR` at offset `0x8`, resets to `0x0000_0000`, write-only.
    Micr = 2,
    /// `MDIER4` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Mdier4 = 3,
    /// `MCNTR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Mcntr = 4,
    /// `MPER` at offset `0x14`, resets to `0x0000_FFFF`, read-write.
    Mper = 5,
    /// `MREP` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Mrep = 6,
    /// `MCMP1R` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Mcmp1r = 7,
    /// `MCMP2R` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Mcmp2r = 8,
    /// `MCMP3R` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Mcmp3r = 9,
    /// `MCMP4R` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    Mcmp4r = 10,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 11] = [Self::Mcr, Self::Misr, Self::Micr, Self::Mdier4, Self::Mcntr, Self::Mper, Self::Mrep, Self::Mcmp1r, Self::Mcmp2r, Self::Mcmp3r, Self::Mcmp4r];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `MCR`.
pub mod mcr {
    use super::FieldSpec;
    /// `CK_PSC`, bits 0..=2.
    pub const CK_PSC: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `CONT`, bit 3.
    pub const CONT: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `RETRIG`, bit 4.
    pub const RETRIG: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `HALF`, bit 5.
    pub const HALF: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `SYNC_IN`, bits 8..=9.
    pub const SYNC_IN: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `SYNCRSTM`, bit 10.
    pub const SYNCRSTM: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `SYNCSTRTM`, bit 11.
    pub const SYNCSTRTM: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `SYNC_OUT`, bits 12..=13.
    pub const SYNC_OUT: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `SYNC_SRC`, bits 14..=15.
    pub const SYNC_SRC: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `MCEN`, bit 16.
    pub const MCEN: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `TACEN`, bit 17.
    pub const TACEN: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `TBCEN`, bit 18.
    pub const TBCEN: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `TCCEN`, bit 19.
    pub const TCCEN: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `TDCEN`, bit 20.
    pub const TDCEN: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `TECEN`, bit 21.
    pub const TECEN: &FieldSpec = &super::REGISTERS[0].fields[14];
    /// `DACSYNC`, bits 25..=26.
    pub const DACSYNC: &FieldSpec = &super::REGISTERS[0].fields[15];
    /// `PREEN`, bit 27.
    pub const PREEN: &FieldSpec = &super::REGISTERS[0].fields[16];
    /// `MREPU`, bit 29.
    pub const MREPU: &FieldSpec = &super::REGISTERS[0].fields[17];
    /// `BRSTDMA`, bits 30..=31.
    pub const BRSTDMA: &FieldSpec = &super::REGISTERS[0].fields[18];
}

/// The fields of `MISR`.
pub mod misr {
    use super::FieldSpec;
    /// `MCMP1`, bit 0.
    pub const MCMP1: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `MCMP2`, bit 1.
    pub const MCMP2: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `MCMP3`, bit 2.
    pub const MCMP3: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `MCMP4`, bit 3.
    pub const MCMP4: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `MREP`, bit 4.
    pub const MREP: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `SYNC`, bit 5.
    pub const SYNC: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `MUPD`, bit 6.
    pub const MUPD: &FieldSpec = &super::REGISTERS[1].fields[6];
}

/// The fields of `MICR`.
pub mod micr {
    use super::FieldSpec;
    /// `MCMP1C`, bit 0.
    pub const MCMP1C: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `MCMP2C`, bit 1.
    pub const MCMP2C: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `MCMP3C`, bit 2.
    pub const MCMP3C: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `MCMP4C`, bit 3.
    pub const MCMP4C: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `MREPC`, bit 4.
    pub const MREPC: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `SYNCC`, bit 5.
    pub const SYNCC: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `MUPDC`, bit 6.
    pub const MUPDC: &FieldSpec = &super::REGISTERS[2].fields[6];
}

/// The fields of `MDIER4`.
pub mod mdier4 {
    use super::FieldSpec;
    /// `MCMP1IE`, bit 0.
    pub const MCMP1IE: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `MCMP2IE`, bit 1.
    pub const MCMP2IE: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `MCMP3IE`, bit 2.
    pub const MCMP3IE: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `MCMP4IE`, bit 3.
    pub const MCMP4IE: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `MREPIE`, bit 4.
    pub const MREPIE: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `SYNCIE`, bit 5.
    pub const SYNCIE: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `MUPDIE`, bit 6.
    pub const MUPDIE: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `MCMP1DE`, bit 16.
    pub const MCMP1DE: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `MCMP2DE`, bit 17.
    pub const MCMP2DE: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `MCMP3DE`, bit 18.
    pub const MCMP3DE: &FieldSpec = &super::REGISTERS[3].fields[9];
    /// `MCMP4DE`, bit 19.
    pub const MCMP4DE: &FieldSpec = &super::REGISTERS[3].fields[10];
    /// `MREPDE`, bit 20.
    pub const MREPDE: &FieldSpec = &super::REGISTERS[3].fields[11];
    /// `SYNCDE`, bit 21.
    pub const SYNCDE: &FieldSpec = &super::REGISTERS[3].fields[12];
    /// `MUPDDE`, bit 22.
    pub const MUPDDE: &FieldSpec = &super::REGISTERS[3].fields[13];
}

/// The fields of `MCNTR`.
pub mod mcntr {
    use super::FieldSpec;
    /// `MCNT`, bits 0..=15.
    pub const MCNT: &FieldSpec = &super::REGISTERS[4].fields[0];
}

/// The fields of `MPER`.
pub mod mper {
    use super::FieldSpec;
    /// `MPER`, bits 0..=15.
    pub const MPER: &FieldSpec = &super::REGISTERS[5].fields[0];
}

/// The fields of `MREP`.
pub mod mrep {
    use super::FieldSpec;
    /// `MREP`, bits 0..=7.
    pub const MREP: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `MCMP1R`.
pub mod mcmp1r {
    use super::FieldSpec;
    /// `MCMP1`, bits 0..=15.
    pub const MCMP1: &FieldSpec = &super::REGISTERS[7].fields[0];
}

/// The fields of `MCMP2R`.
pub mod mcmp2r {
    use super::FieldSpec;
    /// `MCMP2`, bits 0..=15.
    pub const MCMP2: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The fields of `MCMP3R`.
pub mod mcmp3r {
    use super::FieldSpec;
    /// `MCMP3`, bits 0..=15.
    pub const MCMP3: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `MCMP4R`.
pub mod mcmp4r {
    use super::FieldSpec;
    /// `MCMP4`, bits 0..=15.
    pub const MCMP4: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 11] = [
    RegisterSpec { name: "MCR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CK_PSC", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CONT", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RETRIG", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HALF", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNC_IN", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCRSTM", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCSTRTM", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNC_OUT", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNC_SRC", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TACEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TBCEN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCCEN", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TDCEN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TECEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DACSYNC", bit: 25, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PREEN", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MREPU", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BRSTDMA", bit: 30, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MISR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MCMP1", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP2", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP3", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP4", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MREP", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNC", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUPD", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MICR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MCMP1C", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP2C", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP3C", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP4C", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MREPC", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCC", bit: 5, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUPDC", bit: 6, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MDIER4", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MCMP1IE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP2IE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP3IE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP4IE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MREPIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUPDIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP1DE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP2DE", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP3DE", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP4DE", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MREPDE", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCDE", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUPDDE", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MCNTR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MCNT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MPER", offset: 0x14, width: Width::W32, reset: 0x0000_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MPER", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MREP", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MREP", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MCMP1R", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MCMP1", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MCMP2R", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MCMP2", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MCMP3R", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MCMP3", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MCMP4R", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MCMP4", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];