rigless 0.3.0

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `DMAMUX2` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `C0CR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    C0cr = 0,
    /// `C1CR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    C1cr = 1,
    /// `C2CR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    C2cr = 2,
    /// `C3CR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    C3cr = 3,
    /// `C4CR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    C4cr = 4,
    /// `C5CR` at offset `0x14`, resets to `0x0000_0000`, read-write.
    C5cr = 5,
    /// `C6CR` at offset `0x18`, resets to `0x0000_0000`, read-write.
    C6cr = 6,
    /// `C7CR` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    C7cr = 7,
    /// `CSR` at offset `0x80`, resets to `0x0000_0000`, read-only.
    Csr = 8,
    /// `CFR` at offset `0x84`, resets to `0x0000_0000`, read-write.
    Cfr = 9,
    /// `RG0CR` at offset `0x100`, resets to `0x0000_0000`, read-write.
    Rg0cr = 10,
    /// `RG1CR` at offset `0x104`, resets to `0x0000_0000`, read-write.
    Rg1cr = 11,
    /// `RG2CR` at offset `0x108`, resets to `0x0000_0000`, read-write.
    Rg2cr = 12,
    /// `RG3CR` at offset `0x10C`, resets to `0x0000_0000`, read-write.
    Rg3cr = 13,
    /// `RG4CR` at offset `0x110`, resets to `0x0000_0000`, read-write.
    Rg4cr = 14,
    /// `RG5CR` at offset `0x114`, resets to `0x0000_0000`, read-write.
    Rg5cr = 15,
    /// `RG6CR` at offset `0x118`, resets to `0x0000_0000`, read-write.
    Rg6cr = 16,
    /// `RG7CR` at offset `0x11C`, resets to `0x0000_0000`, read-write.
    Rg7cr = 17,
    /// `RGSR` at offset `0x140`, resets to `0x0000_0000`, read-only.
    Rgsr = 18,
    /// `RGCFR` at offset `0x144`, resets to `0x0000_0000`, read-only.
    Rgcfr = 19,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 20] = [Self::C0cr, Self::C1cr, Self::C2cr, Self::C3cr, Self::C4cr, Self::C5cr, Self::C6cr, Self::C7cr, Self::Csr, Self::Cfr, Self::Rg0cr, Self::Rg1cr, Self::Rg2cr, Self::Rg3cr, Self::Rg4cr, Self::Rg5cr, Self::Rg6cr, Self::Rg7cr, Self::Rgsr, Self::Rgcfr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `C0CR`.
pub mod c0cr {
    use super::FieldSpec;
    /// `DMAREQ_ID`, bits 0..=4.
    pub const DMAREQ_ID: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `SOIE`, bit 8.
    pub const SOIE: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `EGE`, bit 9.
    pub const EGE: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `SE`, bit 16.
    pub const SE: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `SPOL`, bits 17..=18.
    pub const SPOL: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `NBREQ`, bits 19..=23.
    pub const NBREQ: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `SYNC_ID`, bits 24..=28.
    pub const SYNC_ID: &FieldSpec = &super::REGISTERS[0].fields[6];
}

/// The fields of `C1CR`.
pub mod c1cr {
    use super::FieldSpec;
    /// `DMAREQ_ID`, bits 0..=4.
    pub const DMAREQ_ID: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `SOIE`, bit 8.
    pub const SOIE: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `EGE`, bit 9.
    pub const EGE: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `SE`, bit 16.
    pub const SE: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `SPOL`, bits 17..=18.
    pub const SPOL: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `NBREQ`, bits 19..=23.
    pub const NBREQ: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `SYNC_ID`, bits 24..=28.
    pub const SYNC_ID: &FieldSpec = &super::REGISTERS[1].fields[6];
}

/// The fields of `C2CR`.
pub mod c2cr {
    use super::FieldSpec;
    /// `DMAREQ_ID`, bits 0..=4.
    pub const DMAREQ_ID: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `SOIE`, bit 8.
    pub const SOIE: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `EGE`, bit 9.
    pub const EGE: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `SE`, bit 16.
    pub const SE: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `SPOL`, bits 17..=18.
    pub const SPOL: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `NBREQ`, bits 19..=23.
    pub const NBREQ: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `SYNC_ID`, bits 24..=28.
    pub const SYNC_ID: &FieldSpec = &super::REGISTERS[2].fields[6];
}

/// The fields of `C3CR`.
pub mod c3cr {
    use super::FieldSpec;
    /// `DMAREQ_ID`, bits 0..=4.
    pub const DMAREQ_ID: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `SOIE`, bit 8.
    pub const SOIE: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `EGE`, bit 9.
    pub const EGE: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `SE`, bit 16.
    pub const SE: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `SPOL`, bits 17..=18.
    pub const SPOL: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `NBREQ`, bits 19..=23.
    pub const NBREQ: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `SYNC_ID`, bits 24..=28.
    pub const SYNC_ID: &FieldSpec = &super::REGISTERS[3].fields[6];
}

/// The fields of `C4CR`.
pub mod c4cr {
    use super::FieldSpec;
    /// `DMAREQ_ID`, bits 0..=4.
    pub const DMAREQ_ID: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `SOIE`, bit 8.
    pub const SOIE: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `EGE`, bit 9.
    pub const EGE: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `SE`, bit 16.
    pub const SE: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `SPOL`, bits 17..=18.
    pub const SPOL: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `NBREQ`, bits 19..=23.
    pub const NBREQ: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `SYNC_ID`, bits 24..=28.
    pub const SYNC_ID: &FieldSpec = &super::REGISTERS[4].fields[6];
}

/// The fields of `C5CR`.
pub mod c5cr {
    use super::FieldSpec;
    /// `DMAREQ_ID`, bits 0..=4.
    pub const DMAREQ_ID: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `SOIE`, bit 8.
    pub const SOIE: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `EGE`, bit 9.
    pub const EGE: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `SE`, bit 16.
    pub const SE: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `SPOL`, bits 17..=18.
    pub const SPOL: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `NBREQ`, bits 19..=23.
    pub const NBREQ: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `SYNC_ID`, bits 24..=28.
    pub const SYNC_ID: &FieldSpec = &super::REGISTERS[5].fields[6];
}

/// The fields of `C6CR`.
pub mod c6cr {
    use super::FieldSpec;
    /// `DMAREQ_ID`, bits 0..=4.
    pub const DMAREQ_ID: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `SOIE`, bit 8.
    pub const SOIE: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `EGE`, bit 9.
    pub const EGE: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `SE`, bit 16.
    pub const SE: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `SPOL`, bits 17..=18.
    pub const SPOL: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `NBREQ`, bits 19..=23.
    pub const NBREQ: &FieldSpec = &super::REGISTERS[6].fields[5];
    /// `SYNC_ID`, bits 24..=28.
    pub const SYNC_ID: &FieldSpec = &super::REGISTERS[6].fields[6];
}

/// The fields of `C7CR`.
pub mod c7cr {
    use super::FieldSpec;
    /// `DMAREQ_ID`, bits 0..=4.
    pub const DMAREQ_ID: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `SOIE`, bit 8.
    pub const SOIE: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `EGE`, bit 9.
    pub const EGE: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `SE`, bit 16.
    pub const SE: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `SPOL`, bits 17..=18.
    pub const SPOL: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `NBREQ`, bits 19..=23.
    pub const NBREQ: &FieldSpec = &super::REGISTERS[7].fields[5];
    /// `SYNC_ID`, bits 24..=28.
    pub const SYNC_ID: &FieldSpec = &super::REGISTERS[7].fields[6];
}

/// The fields of `CSR`.
pub mod csr {
    use super::FieldSpec;
    /// `SOF0`, bit 0.
    pub const SOF0: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `SOF1`, bit 1.
    pub const SOF1: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `SOF2`, bit 2.
    pub const SOF2: &FieldSpec = &super::REGISTERS[8].fields[2];
    /// `SOF3`, bit 3.
    pub const SOF3: &FieldSpec = &super::REGISTERS[8].fields[3];
    /// `SOF4`, bit 4.
    pub const SOF4: &FieldSpec = &super::REGISTERS[8].fields[4];
    /// `SOF5`, bit 5.
    pub const SOF5: &FieldSpec = &super::REGISTERS[8].fields[5];
    /// `SOF6`, bit 6.
    pub const SOF6: &FieldSpec = &super::REGISTERS[8].fields[6];
    /// `SOF7`, bit 7.
    pub const SOF7: &FieldSpec = &super::REGISTERS[8].fields[7];
}

/// The fields of `CFR`.
pub mod cfr {
    use super::FieldSpec;
    /// `CSOF0`, bit 0, write-only.
    pub const CSOF0: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `CSOF1`, bit 1, write-only.
    pub const CSOF1: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `CSOF2`, bit 2, write-only.
    pub const CSOF2: &FieldSpec = &super::REGISTERS[9].fields[2];
    /// `CSOF3`, bit 3, write-only.
    pub const CSOF3: &FieldSpec = &super::REGISTERS[9].fields[3];
    /// `CSOF4`, bit 4, write-only.
    pub const CSOF4: &FieldSpec = &super::REGISTERS[9].fields[4];
    /// `CSOF5`, bit 5, write-only.
    pub const CSOF5: &FieldSpec = &super::REGISTERS[9].fields[5];
    /// `CSOF6`, bit 6, write-only.
    pub const CSOF6: &FieldSpec = &super::REGISTERS[9].fields[6];
    /// `CSOF7`, bit 7, write-only.
    pub const CSOF7: &FieldSpec = &super::REGISTERS[9].fields[7];
}

/// The fields of `RG0CR`.
pub mod rg0cr {
    use super::FieldSpec;
    /// `SIG_ID`, bits 0..=4.
    pub const SIG_ID: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `OIE`, bit 8.
    pub const OIE: &FieldSpec = &super::REGISTERS[10].fields[1];
    /// `GE`, bit 16.
    pub const GE: &FieldSpec = &super::REGISTERS[10].fields[2];
    /// `GPOL`, bits 17..=18.
    pub const GPOL: &FieldSpec = &super::REGISTERS[10].fields[3];
    /// `GNBREQ`, bits 19..=23.
    pub const GNBREQ: &FieldSpec = &super::REGISTERS[10].fields[4];
}

/// The fields of `RG1CR`.
pub mod rg1cr {
    use super::FieldSpec;
    /// `SIG_ID`, bits 0..=4.
    pub const SIG_ID: &FieldSpec = &super::REGISTERS[11].fields[0];
    /// `OIE`, bit 8.
    pub const OIE: &FieldSpec = &super::REGISTERS[11].fields[1];
    /// `GE`, bit 16.
    pub const GE: &FieldSpec = &super::REGISTERS[11].fields[2];
    /// `GPOL`, bits 17..=18.
    pub const GPOL: &FieldSpec = &super::REGISTERS[11].fields[3];
    /// `GNBREQ`, bits 19..=23.
    pub const GNBREQ: &FieldSpec = &super::REGISTERS[11].fields[4];
}

/// The fields of `RG2CR`.
pub mod rg2cr {
    use super::FieldSpec;
    /// `SIG_ID`, bits 0..=4.
    pub const SIG_ID: &FieldSpec = &super::REGISTERS[12].fields[0];
    /// `OIE`, bit 8.
    pub const OIE: &FieldSpec = &super::REGISTERS[12].fields[1];
    /// `GE`, bit 16.
    pub const GE: &FieldSpec = &super::REGISTERS[12].fields[2];
    /// `GPOL`, bits 17..=18.
    pub const GPOL: &FieldSpec = &super::REGISTERS[12].fields[3];
    /// `GNBREQ`, bits 19..=23.
    pub const GNBREQ: &FieldSpec = &super::REGISTERS[12].fields[4];
}

/// The fields of `RG3CR`.
pub mod rg3cr {
    use super::FieldSpec;
    /// `SIG_ID`, bits 0..=4.
    pub const SIG_ID: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `OIE`, bit 8.
    pub const OIE: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `GE`, bit 16.
    pub const GE: &FieldSpec = &super::REGISTERS[13].fields[2];
    /// `GPOL`, bits 17..=18.
    pub const GPOL: &FieldSpec = &super::REGISTERS[13].fields[3];
    /// `GNBREQ`, bits 19..=23.
    pub const GNBREQ: &FieldSpec = &super::REGISTERS[13].fields[4];
}

/// The fields of `RG4CR`.
pub mod rg4cr {
    use super::FieldSpec;
    /// `SIG_ID`, bits 0..=4.
    pub const SIG_ID: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `OIE`, bit 8.
    pub const OIE: &FieldSpec = &super::REGISTERS[14].fields[1];
    /// `GE`, bit 16.
    pub const GE: &FieldSpec = &super::REGISTERS[14].fields[2];
    /// `GPOL`, bits 17..=18.
    pub const GPOL: &FieldSpec = &super::REGISTERS[14].fields[3];
    /// `GNBREQ`, bits 19..=23.
    pub const GNBREQ: &FieldSpec = &super::REGISTERS[14].fields[4];
}

/// The fields of `RG5CR`.
pub mod rg5cr {
    use super::FieldSpec;
    /// `SIG_ID`, bits 0..=4.
    pub const SIG_ID: &FieldSpec = &super::REGISTERS[15].fields[0];
    /// `OIE`, bit 8.
    pub const OIE: &FieldSpec = &super::REGISTERS[15].fields[1];
    /// `GE`, bit 16.
    pub const GE: &FieldSpec = &super::REGISTERS[15].fields[2];
    /// `GPOL`, bits 17..=18.
    pub const GPOL: &FieldSpec = &super::REGISTERS[15].fields[3];
    /// `GNBREQ`, bits 19..=23.
    pub const GNBREQ: &FieldSpec = &super::REGISTERS[15].fields[4];
}

/// The fields of `RG6CR`.
pub mod rg6cr {
    use super::FieldSpec;
    /// `SIG_ID`, bits 0..=4.
    pub const SIG_ID: &FieldSpec = &super::REGISTERS[16].fields[0];
    /// `OIE`, bit 8.
    pub const OIE: &FieldSpec = &super::REGISTERS[16].fields[1];
    /// `GE`, bit 16.
    pub const GE: &FieldSpec = &super::REGISTERS[16].fields[2];
    /// `GPOL`, bits 17..=18.
    pub const GPOL: &FieldSpec = &super::REGISTERS[16].fields[3];
    /// `GNBREQ`, bits 19..=23.
    pub const GNBREQ: &FieldSpec = &super::REGISTERS[16].fields[4];
}

/// The fields of `RG7CR`.
pub mod rg7cr {
    use super::FieldSpec;
    /// `SIG_ID`, bits 0..=4.
    pub const SIG_ID: &FieldSpec = &super::REGISTERS[17].fields[0];
    /// `OIE`, bit 8.
    pub const OIE: &FieldSpec = &super::REGISTERS[17].fields[1];
    /// `GE`, bit 16.
    pub const GE: &FieldSpec = &super::REGISTERS[17].fields[2];
    /// `GPOL`, bits 17..=18.
    pub const GPOL: &FieldSpec = &super::REGISTERS[17].fields[3];
    /// `GNBREQ`, bits 19..=23.
    pub const GNBREQ: &FieldSpec = &super::REGISTERS[17].fields[4];
}

/// The fields of `RGSR`.
pub mod rgsr {
    use super::FieldSpec;
    /// `OF0`, bit 0.
    pub const OF0: &FieldSpec = &super::REGISTERS[18].fields[0];
    /// `OF1`, bit 1.
    pub const OF1: &FieldSpec = &super::REGISTERS[18].fields[1];
    /// `OF2`, bit 2.
    pub const OF2: &FieldSpec = &super::REGISTERS[18].fields[2];
    /// `OF3`, bit 3.
    pub const OF3: &FieldSpec = &super::REGISTERS[18].fields[3];
    /// `OF4`, bit 4.
    pub const OF4: &FieldSpec = &super::REGISTERS[18].fields[4];
    /// `OF5`, bit 5.
    pub const OF5: &FieldSpec = &super::REGISTERS[18].fields[5];
    /// `OF6`, bit 6.
    pub const OF6: &FieldSpec = &super::REGISTERS[18].fields[6];
    /// `OF7`, bit 7.
    pub const OF7: &FieldSpec = &super::REGISTERS[18].fields[7];
}

/// The fields of `RGCFR`.
pub mod rgcfr {
    use super::FieldSpec;
    /// `COF0`, bit 0.
    pub const COF0: &FieldSpec = &super::REGISTERS[19].fields[0];
    /// `COF1`, bit 1.
    pub const COF1: &FieldSpec = &super::REGISTERS[19].fields[1];
    /// `COF2`, bit 2.
    pub const COF2: &FieldSpec = &super::REGISTERS[19].fields[2];
    /// `COF3`, bit 3.
    pub const COF3: &FieldSpec = &super::REGISTERS[19].fields[3];
    /// `COF4`, bit 4.
    pub const COF4: &FieldSpec = &super::REGISTERS[19].fields[4];
    /// `COF5`, bit 5.
    pub const COF5: &FieldSpec = &super::REGISTERS[19].fields[5];
    /// `COF6`, bit 6.
    pub const COF6: &FieldSpec = &super::REGISTERS[19].fields[6];
    /// `COF7`, bit 7.
    pub const COF7: &FieldSpec = &super::REGISTERS[19].fields[7];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 20] = [
    RegisterSpec { name: "C0CR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DMAREQ_ID", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EGE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPOL", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NBREQ", bit: 19, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNC_ID", bit: 24, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "C1CR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DMAREQ_ID", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EGE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPOL", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NBREQ", bit: 19, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNC_ID", bit: 24, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "C2CR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DMAREQ_ID", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EGE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPOL", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NBREQ", bit: 19, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNC_ID", bit: 24, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "C3CR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DMAREQ_ID", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EGE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPOL", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NBREQ", bit: 19, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNC_ID", bit: 24, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "C4CR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DMAREQ_ID", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EGE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPOL", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NBREQ", bit: 19, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNC_ID", bit: 24, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "C5CR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DMAREQ_ID", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EGE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPOL", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NBREQ", bit: 19, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNC_ID", bit: 24, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "C6CR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DMAREQ_ID", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EGE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPOL", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NBREQ", bit: 19, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNC_ID", bit: 24, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "C7CR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DMAREQ_ID", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EGE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPOL", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NBREQ", bit: 19, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNC_ID", bit: 24, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CSR", offset: 0x80, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SOF0", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOF1", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOF2", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOF3", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOF4", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOF5", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOF6", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOF7", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CFR", offset: 0x84, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CSOF0", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSOF1", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSOF2", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSOF3", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSOF4", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSOF5", bit: 5, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSOF6", bit: 6, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSOF7", bit: 7, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RG0CR", offset: 0x100, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SIG_ID", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPOL", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GNBREQ", bit: 19, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RG1CR", offset: 0x104, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SIG_ID", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPOL", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GNBREQ", bit: 19, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RG2CR", offset: 0x108, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SIG_ID", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPOL", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GNBREQ", bit: 19, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RG3CR", offset: 0x10C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SIG_ID", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPOL", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GNBREQ", bit: 19, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RG4CR", offset: 0x110, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SIG_ID", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPOL", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GNBREQ", bit: 19, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RG5CR", offset: 0x114, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SIG_ID", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPOL", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GNBREQ", bit: 19, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RG6CR", offset: 0x118, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SIG_ID", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPOL", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GNBREQ", bit: 19, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RG7CR", offset: 0x11C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SIG_ID", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPOL", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GNBREQ", bit: 19, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RGSR", offset: 0x140, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OF0", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OF1", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OF2", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OF3", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OF4", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OF5", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OF6", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OF7", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RGCFR", offset: 0x144, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "COF0", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COF1", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COF2", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COF3", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COF4", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COF5", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COF6", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COF7", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];