rigless 0.3.0

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `Ethernet_MAC` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `MACCR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Maccr = 0,
    /// `MACECR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Macecr = 1,
    /// `MACPFR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Macpfr = 2,
    /// `MACWTR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Macwtr = 3,
    /// `MACHT0R` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Macht0r = 4,
    /// `MACHT1R` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Macht1r = 5,
    /// `MACVTR` at offset `0x50`, resets to `0x0000_0000`, read-write.
    Macvtr = 6,
    /// `MACVHTR` at offset `0x58`, resets to `0x0000_0000`, read-write.
    Macvhtr = 7,
    /// `MACVIR` at offset `0x60`, resets to `0x0000_0000`, read-write.
    Macvir = 8,
    /// `MACIVIR` at offset `0x64`, resets to `0x0000_0000`, read-write.
    Macivir = 9,
    /// `MACQTxFCR` at offset `0x70`, resets to `0x0000_0000`, read-write.
    Macqtxfcr = 10,
    /// `MACRxFCR` at offset `0x90`, resets to `0x0000_0000`, read-write.
    Macrxfcr = 11,
    /// `MACISR` at offset `0xB0`, resets to `0x0000_0000`, read-only.
    Macisr = 12,
    /// `MACIER` at offset `0xB4`, resets to `0x0000_0000`, read-write.
    Macier = 13,
    /// `MACRxTxSR` at offset `0xB8`, resets to `0x0000_0000`, read-only.
    Macrxtxsr = 14,
    /// `MACPCSR` at offset `0xC0`, resets to `0x0000_0000`, read-write.
    Macpcsr = 15,
    /// `MACRWKPFR` at offset `0xC4`, resets to `0x0000_0000`, read-write.
    Macrwkpfr = 16,
    /// `MACLCSR` at offset `0xD0`, resets to `0x0000_0000`, read-write.
    Maclcsr = 17,
    /// `MACLTCR` at offset `0xD4`, resets to `0x03E8_0000`, read-write.
    Macltcr = 18,
    /// `MACLETR` at offset `0xD8`, resets to `0x0000_0000`, read-write.
    Macletr = 19,
    /// `MAC1USTCR` at offset `0xDC`, resets to `0x0000_0000`, read-write.
    Mac1ustcr = 20,
    /// `MACVR` at offset `0x110`, resets to `0x0000_3041`, read-only.
    Macvr = 21,
    /// `MACDR` at offset `0x114`, resets to `0x0000_0000`, read-only.
    Macdr = 22,
    /// `MACHWF1R` at offset `0x120`, resets to `0x1184_1904`, read-only.
    Machwf1r = 23,
    /// `MACHWF2R` at offset `0x124`, resets to `0x4100_0000`, read-only.
    Machwf2r = 24,
    /// `MACMDIOAR` at offset `0x200`, resets to `0x0000_0000`, read-write.
    Macmdioar = 25,
    /// `MACMDIODR` at offset `0x204`, resets to `0x0000_0000`, read-write.
    Macmdiodr = 26,
    /// `MACA0HR` at offset `0x300`, resets to `0x8000_FFFF`, read-write.
    Maca0hr = 27,
    /// `MACA0LR` at offset `0x304`, resets to `0xFFFF_FFFF`, read-write.
    Maca0lr = 28,
    /// `MACA1HR` at offset `0x308`, resets to `0x0000_FFFF`, read-write.
    Maca1hr = 29,
    /// `MACA1LR` at offset `0x30C`, resets to `0xFFFF_FFFF`, read-write.
    Maca1lr = 30,
    /// `MACA2HR` at offset `0x310`, resets to `0x0000_FFFF`, read-write.
    Maca2hr = 31,
    /// `MACA2LR` at offset `0x314`, resets to `0xFFFF_FFFF`, read-write.
    Maca2lr = 32,
    /// `MACA3HR` at offset `0x318`, resets to `0x0000_FFFF`, read-write.
    Maca3hr = 33,
    /// `MACA3LR` at offset `0x31C`, resets to `0xFFFF_FFFF`, read-write.
    Maca3lr = 34,
    /// `MMC_CONTROL` at offset `0x700`, resets to `0x0000_0000`, read-write.
    MmcControl = 35,
    /// `MMC_RX_INTERRUPT` at offset `0x704`, resets to `0x0000_0000`, read-only.
    MmcRxInterrupt = 36,
    /// `MMC_TX_INTERRUPT` at offset `0x708`, resets to `0x0000_0000`, read-only.
    MmcTxInterrupt = 37,
    /// `MMC_RX_INTERRUPT_MASK` at offset `0x70C`, resets to `0x0000_0000`, read-write.
    MmcRxInterruptMask = 38,
    /// `MMC_TX_INTERRUPT_MASK` at offset `0x710`, resets to `0x0000_0000`, read-write.
    MmcTxInterruptMask = 39,
    /// `TX_SINGLE_COLLISION_GOOD_PACKETS` at offset `0x74C`, resets to `0x0000_0000`, read-only.
    TxSingleCollisionGoodPackets = 40,
    /// `TX_MULTIPLE_COLLISION_GOOD_PACKETS` at offset `0x750`, resets to `0x0000_0000`, read-only.
    TxMultipleCollisionGoodPackets = 41,
    /// `TX_PACKET_COUNT_GOOD` at offset `0x768`, resets to `0x0000_0000`, read-only.
    TxPacketCountGood = 42,
    /// `RX_CRC_ERROR_PACKETS` at offset `0x794`, resets to `0x0000_0000`, read-only.
    RxCrcErrorPackets = 43,
    /// `RX_ALIGNMENT_ERROR_PACKETS` at offset `0x798`, resets to `0x0000_0000`, read-only.
    RxAlignmentErrorPackets = 44,
    /// `RX_UNICAST_PACKETS_GOOD` at offset `0x7C4`, resets to `0x0000_0000`, read-only.
    RxUnicastPacketsGood = 45,
    /// `TX_LPI_USEC_CNTR` at offset `0x7EC`, resets to `0x0000_0000`, read-only.
    TxLpiUsecCntr = 46,
    /// `TX_LPI_TRAN_CNTR` at offset `0x7F0`, resets to `0x0000_0000`, read-only.
    TxLpiTranCntr = 47,
    /// `RX_LPI_USEC_CNTR` at offset `0x7F4`, resets to `0x0000_0000`, read-only.
    RxLpiUsecCntr = 48,
    /// `RX_LPI_TRAN_CNTR` at offset `0x7F8`, resets to `0x0000_0000`, read-only.
    RxLpiTranCntr = 49,
    /// `MACL3L4C0R` at offset `0x900`, resets to `0x0000_0000`, read-write.
    Macl3l4c0r = 50,
    /// `MACL4A0R` at offset `0x904`, resets to `0x0000_0000`, read-write.
    Macl4a0r = 51,
    /// `MACL3A00R` at offset `0x910`, resets to `0x0000_0000`, read-write.
    Macl3a00r = 52,
    /// `MACL3A10R` at offset `0x914`, resets to `0x0000_0000`, read-write.
    Macl3a10r = 53,
    /// `MACL3A20` at offset `0x918`, resets to `0x0000_0000`, read-write.
    Macl3a20 = 54,
    /// `MACL3A30` at offset `0x91C`, resets to `0x0000_0000`, read-write.
    Macl3a30 = 55,
    /// `MACL3L4C1R` at offset `0x930`, resets to `0x0000_0000`, read-write.
    Macl3l4c1r = 56,
    /// `MACL4A1R` at offset `0x934`, resets to `0x0000_0000`, read-write.
    Macl4a1r = 57,
    /// `MACL3A01R` at offset `0x940`, resets to `0x0000_0000`, read-write.
    Macl3a01r = 58,
    /// `MACL3A11R` at offset `0x944`, resets to `0x0000_0000`, read-write.
    Macl3a11r = 59,
    /// `MACL3A21R` at offset `0x948`, resets to `0x0000_0000`, read-write.
    Macl3a21r = 60,
    /// `MACL3A31R` at offset `0x94C`, resets to `0x0000_0000`, read-write.
    Macl3a31r = 61,
    /// `MACARPAR` at offset `0xAE0`, resets to `0x0000_0000`, read-write.
    Macarpar = 62,
    /// `MACTSCR` at offset `0xB00`, resets to `0x0000_0200`, read-write.
    Mactscr = 63,
    /// `MACSSIR` at offset `0xB04`, resets to `0x0000_0000`, read-write.
    Macssir = 64,
    /// `MACSTSR` at offset `0xB08`, resets to `0x0000_0000`, read-only.
    Macstsr = 65,
    /// `MACSTNR` at offset `0xB0C`, resets to `0x0000_0000`, read-only.
    Macstnr = 66,
    /// `MACSTSUR` at offset `0xB10`, resets to `0x0000_0000`, read-write.
    Macstsur = 67,
    /// `MACSTNUR` at offset `0xB14`, resets to `0x0000_0000`, read-write.
    Macstnur = 68,
    /// `MACTSAR` at offset `0xB18`, resets to `0x0000_0000`, read-write.
    Mactsar = 69,
    /// `MACTSSR` at offset `0xB20`, resets to `0x0000_0000`, read-only.
    Mactssr = 70,
    /// `MACTxTSSNR` at offset `0xB30`, resets to `0x0000_0000`, read-only.
    Mactxtssnr = 71,
    /// `MACTxTSSSR` at offset `0xB34`, resets to `0x0000_0000`, read-only.
    Mactxtsssr = 72,
    /// `MACACR` at offset `0xB40`, resets to `0x0000_0000`, read-write.
    Macacr = 73,
    /// `MACATSNR` at offset `0xB48`, resets to `0x0000_0000`, read-only.
    Macatsnr = 74,
    /// `MACATSSR` at offset `0xB4C`, resets to `0x0000_0000`, read-only.
    Macatssr = 75,
    /// `MACTSIACR` at offset `0xB50`, resets to `0x0000_0000`, read-write.
    Mactsiacr = 76,
    /// `MACTSEACR` at offset `0xB54`, resets to `0x0000_0000`, read-write.
    Mactseacr = 77,
    /// `MACTSICNR` at offset `0xB58`, resets to `0x0000_0000`, read-write.
    Mactsicnr = 78,
    /// `MACTSECNR` at offset `0xB5C`, resets to `0x0000_0000`, read-write.
    Mactsecnr = 79,
    /// `MACPPSCR` at offset `0xB70`, resets to `0x0000_0000`, read-write.
    Macppscr = 80,
    /// `MACPPSTTSR` at offset `0xB80`, resets to `0x0000_0000`, read-write.
    Macppsttsr = 81,
    /// `MACPPSTTNR` at offset `0xB84`, resets to `0x0000_0000`, read-write.
    Macppsttnr = 82,
    /// `MACPPSIR` at offset `0xB88`, resets to `0x0000_0000`, read-write.
    Macppsir = 83,
    /// `MACPPSWR` at offset `0xB8C`, resets to `0x0000_0000`, read-write.
    Macppswr = 84,
    /// `MACPOCR` at offset `0xBC0`, resets to `0x0000_0000`, read-write.
    Macpocr = 85,
    /// `MACSPI0R` at offset `0xBC4`, resets to `0x0000_0000`, read-write.
    Macspi0r = 86,
    /// `MACSPI1R` at offset `0xBC8`, resets to `0x0000_0000`, read-write.
    Macspi1r = 87,
    /// `MACSPI2R` at offset `0xBCC`, resets to `0x0000_0000`, read-write.
    Macspi2r = 88,
    /// `MACLMIR` at offset `0xBD0`, resets to `0x0000_0000`, read-write.
    Maclmir = 89,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 90] = [Self::Maccr, Self::Macecr, Self::Macpfr, Self::Macwtr, Self::Macht0r, Self::Macht1r, Self::Macvtr, Self::Macvhtr, Self::Macvir, Self::Macivir, Self::Macqtxfcr, Self::Macrxfcr, Self::Macisr, Self::Macier, Self::Macrxtxsr, Self::Macpcsr, Self::Macrwkpfr, Self::Maclcsr, Self::Macltcr, Self::Macletr, Self::Mac1ustcr, Self::Macvr, Self::Macdr, Self::Machwf1r, Self::Machwf2r, Self::Macmdioar, Self::Macmdiodr, Self::Maca0hr, Self::Maca0lr, Self::Maca1hr, Self::Maca1lr, Self::Maca2hr, Self::Maca2lr, Self::Maca3hr, Self::Maca3lr, Self::MmcControl, Self::MmcRxInterrupt, Self::MmcTxInterrupt, Self::MmcRxInterruptMask, Self::MmcTxInterruptMask, Self::TxSingleCollisionGoodPackets, Self::TxMultipleCollisionGoodPackets, Self::TxPacketCountGood, Self::RxCrcErrorPackets, Self::RxAlignmentErrorPackets, Self::RxUnicastPacketsGood, Self::TxLpiUsecCntr, Self::TxLpiTranCntr, Self::RxLpiUsecCntr, Self::RxLpiTranCntr, Self::Macl3l4c0r, Self::Macl4a0r, Self::Macl3a00r, Self::Macl3a10r, Self::Macl3a20, Self::Macl3a30, Self::Macl3l4c1r, Self::Macl4a1r, Self::Macl3a01r, Self::Macl3a11r, Self::Macl3a21r, Self::Macl3a31r, Self::Macarpar, Self::Mactscr, Self::Macssir, Self::Macstsr, Self::Macstnr, Self::Macstsur, Self::Macstnur, Self::Mactsar, Self::Mactssr, Self::Mactxtssnr, Self::Mactxtsssr, Self::Macacr, Self::Macatsnr, Self::Macatssr, Self::Mactsiacr, Self::Mactseacr, Self::Mactsicnr, Self::Mactsecnr, Self::Macppscr, Self::Macppsttsr, Self::Macppsttnr, Self::Macppsir, Self::Macppswr, Self::Macpocr, Self::Macspi0r, Self::Macspi1r, Self::Macspi2r, Self::Maclmir];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `MACCR`.
pub mod maccr {
    use super::FieldSpec;
    /// `RE`, bit 0.
    pub const RE: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `TE`, bit 1.
    pub const TE: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `PRELEN`, bits 2..=3.
    pub const PRELEN: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `DC`, bit 4.
    pub const DC: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `BL`, bits 5..=6.
    pub const BL: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `DR`, bit 8.
    pub const DR: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `DCRS`, bit 9.
    pub const DCRS: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `DO`, bit 10.
    pub const DO: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `ECRSFD`, bit 11.
    pub const ECRSFD: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `LM`, bit 12.
    pub const LM: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `DM`, bit 13.
    pub const DM: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `FES`, bit 14.
    pub const FES: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `JE`, bit 16.
    pub const JE: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `JD`, bit 17.
    pub const JD: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `WD`, bit 19.
    pub const WD: &FieldSpec = &super::REGISTERS[0].fields[14];
    /// `ACS`, bit 20.
    pub const ACS: &FieldSpec = &super::REGISTERS[0].fields[15];
    /// `CST`, bit 21.
    pub const CST: &FieldSpec = &super::REGISTERS[0].fields[16];
    /// `S2KP`, bit 22.
    pub const S2KP: &FieldSpec = &super::REGISTERS[0].fields[17];
    /// `GPSLCE`, bit 23.
    pub const GPSLCE: &FieldSpec = &super::REGISTERS[0].fields[18];
    /// `IPG`, bits 24..=26.
    pub const IPG: &FieldSpec = &super::REGISTERS[0].fields[19];
    /// `IPC`, bit 27.
    pub const IPC: &FieldSpec = &super::REGISTERS[0].fields[20];
    /// `SARC`, bits 28..=30.
    pub const SARC: &FieldSpec = &super::REGISTERS[0].fields[21];
    /// `ARPEN`, bit 31.
    pub const ARPEN: &FieldSpec = &super::REGISTERS[0].fields[22];
}

/// The fields of `MACECR`.
pub mod macecr {
    use super::FieldSpec;
    /// `GPSL`, bits 0..=13.
    pub const GPSL: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `DCRCC`, bit 16.
    pub const DCRCC: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `SPEN`, bit 17.
    pub const SPEN: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `USP`, bit 18.
    pub const USP: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `EIPGEN`, bit 24.
    pub const EIPGEN: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `EIPG`, bits 25..=29.
    pub const EIPG: &FieldSpec = &super::REGISTERS[1].fields[5];
}

/// The fields of `MACPFR`.
pub mod macpfr {
    use super::FieldSpec;
    /// `PR`, bit 0.
    pub const PR: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `HUC`, bit 1.
    pub const HUC: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `HMC`, bit 2.
    pub const HMC: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `DAIF`, bit 3.
    pub const DAIF: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `PM`, bit 4.
    pub const PM: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `DBF`, bit 5.
    pub const DBF: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `PCF`, bits 6..=7.
    pub const PCF: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `SAIF`, bit 8.
    pub const SAIF: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `SAF`, bit 9.
    pub const SAF: &FieldSpec = &super::REGISTERS[2].fields[8];
    /// `HPF`, bit 10.
    pub const HPF: &FieldSpec = &super::REGISTERS[2].fields[9];
    /// `VTFE`, bit 16.
    pub const VTFE: &FieldSpec = &super::REGISTERS[2].fields[10];
    /// `IPFE`, bit 20.
    pub const IPFE: &FieldSpec = &super::REGISTERS[2].fields[11];
    /// `DNTU`, bit 21.
    pub const DNTU: &FieldSpec = &super::REGISTERS[2].fields[12];
    /// `RA`, bit 31.
    pub const RA: &FieldSpec = &super::REGISTERS[2].fields[13];
}

/// The fields of `MACWTR`.
pub mod macwtr {
    use super::FieldSpec;
    /// `WTO`, bits 0..=3.
    pub const WTO: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `PWE`, bit 8.
    pub const PWE: &FieldSpec = &super::REGISTERS[3].fields[1];
}

/// The fields of `MACHT0R`.
pub mod macht0r {
    use super::FieldSpec;
    /// `HT31T0`, bits 0..=31.
    pub const HT31T0: &FieldSpec = &super::REGISTERS[4].fields[0];
}

/// The fields of `MACHT1R`.
pub mod macht1r {
    use super::FieldSpec;
    /// `HT63T32`, bits 0..=31.
    pub const HT63T32: &FieldSpec = &super::REGISTERS[5].fields[0];
}

/// The fields of `MACVTR`.
pub mod macvtr {
    use super::FieldSpec;
    /// `VL`, bits 0..=15.
    pub const VL: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `ETV`, bit 16.
    pub const ETV: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `VTIM`, bit 17.
    pub const VTIM: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `ESVL`, bit 18.
    pub const ESVL: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `ERSVLM`, bit 19.
    pub const ERSVLM: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `DOVLTC`, bit 20.
    pub const DOVLTC: &FieldSpec = &super::REGISTERS[6].fields[5];
    /// `EVLS`, bits 21..=22.
    pub const EVLS: &FieldSpec = &super::REGISTERS[6].fields[6];
    /// `EVLRXS`, bit 24.
    pub const EVLRXS: &FieldSpec = &super::REGISTERS[6].fields[7];
    /// `VTHM`, bit 25.
    pub const VTHM: &FieldSpec = &super::REGISTERS[6].fields[8];
    /// `EDVLP`, bit 26.
    pub const EDVLP: &FieldSpec = &super::REGISTERS[6].fields[9];
    /// `ERIVLT`, bit 27.
    pub const ERIVLT: &FieldSpec = &super::REGISTERS[6].fields[10];
    /// `EIVLS`, bits 28..=29.
    pub const EIVLS: &FieldSpec = &super::REGISTERS[6].fields[11];
    /// `EIVLRXS`, bit 31.
    pub const EIVLRXS: &FieldSpec = &super::REGISTERS[6].fields[12];
}

/// The fields of `MACVHTR`.
pub mod macvhtr {
    use super::FieldSpec;
    /// `VLHT`, bits 0..=15.
    pub const VLHT: &FieldSpec = &super::REGISTERS[7].fields[0];
}

/// The fields of `MACVIR`.
pub mod macvir {
    use super::FieldSpec;
    /// `VLT`, bits 0..=15.
    pub const VLT: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `VLC`, bits 16..=17.
    pub const VLC: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `VLP`, bit 18.
    pub const VLP: &FieldSpec = &super::REGISTERS[8].fields[2];
    /// `CSVL`, bit 19.
    pub const CSVL: &FieldSpec = &super::REGISTERS[8].fields[3];
    /// `VLTI`, bit 20.
    pub const VLTI: &FieldSpec = &super::REGISTERS[8].fields[4];
}

/// The fields of `MACIVIR`.
pub mod macivir {
    use super::FieldSpec;
    /// `VLT`, bits 0..=15.
    pub const VLT: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `VLC`, bits 16..=17.
    pub const VLC: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `VLP`, bit 18.
    pub const VLP: &FieldSpec = &super::REGISTERS[9].fields[2];
    /// `CSVL`, bit 19.
    pub const CSVL: &FieldSpec = &super::REGISTERS[9].fields[3];
    /// `VLTI`, bit 20.
    pub const VLTI: &FieldSpec = &super::REGISTERS[9].fields[4];
}

/// The fields of `MACQTxFCR`.
pub mod macqtxfcr {
    use super::FieldSpec;
    /// `FCB_BPA`, bit 0.
    pub const FCB_BPA: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `TFE`, bit 1.
    pub const TFE: &FieldSpec = &super::REGISTERS[10].fields[1];
    /// `PLT`, bits 4..=6.
    pub const PLT: &FieldSpec = &super::REGISTERS[10].fields[2];
    /// `DZPQ`, bit 7.
    pub const DZPQ: &FieldSpec = &super::REGISTERS[10].fields[3];
    /// `PT`, bits 16..=31.
    pub const PT: &FieldSpec = &super::REGISTERS[10].fields[4];
}

/// The fields of `MACRxFCR`.
pub mod macrxfcr {
    use super::FieldSpec;
    /// `RFE`, bit 0.
    pub const RFE: &FieldSpec = &super::REGISTERS[11].fields[0];
    /// `UP`, bit 1.
    pub const UP: &FieldSpec = &super::REGISTERS[11].fields[1];
}

/// The fields of `MACISR`.
pub mod macisr {
    use super::FieldSpec;
    /// `PHYIS`, bit 3.
    pub const PHYIS: &FieldSpec = &super::REGISTERS[12].fields[0];
    /// `PMTIS`, bit 4.
    pub const PMTIS: &FieldSpec = &super::REGISTERS[12].fields[1];
    /// `LPIIS`, bit 5.
    pub const LPIIS: &FieldSpec = &super::REGISTERS[12].fields[2];
    /// `MMCIS`, bit 8.
    pub const MMCIS: &FieldSpec = &super::REGISTERS[12].fields[3];
    /// `MMCRXIS`, bit 9.
    pub const MMCRXIS: &FieldSpec = &super::REGISTERS[12].fields[4];
    /// `MMCTXIS`, bit 10.
    pub const MMCTXIS: &FieldSpec = &super::REGISTERS[12].fields[5];
    /// `TSIS`, bit 12.
    pub const TSIS: &FieldSpec = &super::REGISTERS[12].fields[6];
    /// `TXSTSIS`, bit 13.
    pub const TXSTSIS: &FieldSpec = &super::REGISTERS[12].fields[7];
    /// `RXSTSIS`, bit 14.
    pub const RXSTSIS: &FieldSpec = &super::REGISTERS[12].fields[8];
}

/// The fields of `MACIER`.
pub mod macier {
    use super::FieldSpec;
    /// `PHYIE`, bit 3.
    pub const PHYIE: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `PMTIE`, bit 4.
    pub const PMTIE: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `LPIIE`, bit 5.
    pub const LPIIE: &FieldSpec = &super::REGISTERS[13].fields[2];
    /// `TSIE`, bit 12.
    pub const TSIE: &FieldSpec = &super::REGISTERS[13].fields[3];
    /// `TXSTSIE`, bit 13.
    pub const TXSTSIE: &FieldSpec = &super::REGISTERS[13].fields[4];
    /// `RXSTSIE`, bit 14.
    pub const RXSTSIE: &FieldSpec = &super::REGISTERS[13].fields[5];
}

/// The fields of `MACRxTxSR`.
pub mod macrxtxsr {
    use super::FieldSpec;
    /// `TJT`, bit 0.
    pub const TJT: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `NCARR`, bit 1.
    pub const NCARR: &FieldSpec = &super::REGISTERS[14].fields[1];
    /// `LCARR`, bit 2.
    pub const LCARR: &FieldSpec = &super::REGISTERS[14].fields[2];
    /// `EXDEF`, bit 3.
    pub const EXDEF: &FieldSpec = &super::REGISTERS[14].fields[3];
    /// `LCOL`, bit 4.
    pub const LCOL: &FieldSpec = &super::REGISTERS[14].fields[4];
    /// `EXCOL`, bit 5.
    pub const EXCOL: &FieldSpec = &super::REGISTERS[14].fields[5];
    /// `RWT`, bit 8.
    pub const RWT: &FieldSpec = &super::REGISTERS[14].fields[6];
}

/// The fields of `MACPCSR`.
pub mod macpcsr {
    use super::FieldSpec;
    /// `PWRDWN`, bit 0.
    pub const PWRDWN: &FieldSpec = &super::REGISTERS[15].fields[0];
    /// `MGKPKTEN`, bit 1.
    pub const MGKPKTEN: &FieldSpec = &super::REGISTERS[15].fields[1];
    /// `RWKPKTEN`, bit 2.
    pub const RWKPKTEN: &FieldSpec = &super::REGISTERS[15].fields[2];
    /// `MGKPRCVD`, bit 5, read-only.
    pub const MGKPRCVD: &FieldSpec = &super::REGISTERS[15].fields[3];
    /// `RWKPRCVD`, bit 6, read-only.
    pub const RWKPRCVD: &FieldSpec = &super::REGISTERS[15].fields[4];
    /// `GLBLUCAST`, bit 9.
    pub const GLBLUCAST: &FieldSpec = &super::REGISTERS[15].fields[5];
    /// `RWKPFE`, bit 10.
    pub const RWKPFE: &FieldSpec = &super::REGISTERS[15].fields[6];
    /// `RWKPTR`, bits 24..=28.
    pub const RWKPTR: &FieldSpec = &super::REGISTERS[15].fields[7];
    /// `RWKFILTRST`, bit 31.
    pub const RWKFILTRST: &FieldSpec = &super::REGISTERS[15].fields[8];
}

/// The fields of `MACRWKPFR`.
pub mod macrwkpfr {
    use super::FieldSpec;
    /// `MACRWKPFR`, bits 0..=31.
    pub const MACRWKPFR: &FieldSpec = &super::REGISTERS[16].fields[0];
}

/// The fields of `MACLCSR`.
pub mod maclcsr {
    use super::FieldSpec;
    /// `TLPIEN`, bit 0, read-only.
    pub const TLPIEN: &FieldSpec = &super::REGISTERS[17].fields[0];
    /// `TLPIEX`, bit 1, read-only.
    pub const TLPIEX: &FieldSpec = &super::REGISTERS[17].fields[1];
    /// `RLPIEN`, bit 2, read-only.
    pub const RLPIEN: &FieldSpec = &super::REGISTERS[17].fields[2];
    /// `RLPIEX`, bit 3, read-only.
    pub const RLPIEX: &FieldSpec = &super::REGISTERS[17].fields[3];
    /// `TLPIST`, bit 8, read-only.
    pub const TLPIST: &FieldSpec = &super::REGISTERS[17].fields[4];
    /// `RLPIST`, bit 9, read-only.
    pub const RLPIST: &FieldSpec = &super::REGISTERS[17].fields[5];
    /// `LPIEN`, bit 16.
    pub const LPIEN: &FieldSpec = &super::REGISTERS[17].fields[6];
    /// `PLS`, bit 17.
    pub const PLS: &FieldSpec = &super::REGISTERS[17].fields[7];
    /// `PLSEN`, bit 18.
    pub const PLSEN: &FieldSpec = &super::REGISTERS[17].fields[8];
    /// `LPITXA`, bit 19.
    pub const LPITXA: &FieldSpec = &super::REGISTERS[17].fields[9];
    /// `LPITE`, bit 20.
    pub const LPITE: &FieldSpec = &super::REGISTERS[17].fields[10];
}

/// The fields of `MACLTCR`.
pub mod macltcr {
    use super::FieldSpec;
    /// `TWT`, bits 0..=15.
    pub const TWT: &FieldSpec = &super::REGISTERS[18].fields[0];
    /// `LST`, bits 16..=25.
    pub const LST: &FieldSpec = &super::REGISTERS[18].fields[1];
}

/// The fields of `MACLETR`.
pub mod macletr {
    use super::FieldSpec;
    /// `LPIET`, bits 0..=16.
    pub const LPIET: &FieldSpec = &super::REGISTERS[19].fields[0];
}

/// The fields of `MAC1USTCR`.
pub mod mac1ustcr {
    use super::FieldSpec;
    /// `TIC_1US_CNTR`, bits 0..=11.
    pub const TIC_1US_CNTR: &FieldSpec = &super::REGISTERS[20].fields[0];
}

/// The fields of `MACVR`.
pub mod macvr {
    use super::FieldSpec;
    /// `SNPSVER`, bits 0..=7.
    pub const SNPSVER: &FieldSpec = &super::REGISTERS[21].fields[0];
    /// `USERVER`, bits 8..=15.
    pub const USERVER: &FieldSpec = &super::REGISTERS[21].fields[1];
}

/// The fields of `MACDR`.
pub mod macdr {
    use super::FieldSpec;
    /// `RPESTS`, bit 0.
    pub const RPESTS: &FieldSpec = &super::REGISTERS[22].fields[0];
    /// `RFCFCSTS`, bits 1..=2.
    pub const RFCFCSTS: &FieldSpec = &super::REGISTERS[22].fields[1];
    /// `TPESTS`, bit 16.
    pub const TPESTS: &FieldSpec = &super::REGISTERS[22].fields[2];
    /// `TFCSTS`, bits 17..=18.
    pub const TFCSTS: &FieldSpec = &super::REGISTERS[22].fields[3];
}

/// The fields of `MACHWF1R`.
pub mod machwf1r {
    use super::FieldSpec;
    /// `RXFIFOSIZE`, bits 0..=4.
    pub const RXFIFOSIZE: &FieldSpec = &super::REGISTERS[23].fields[0];
    /// `TXFIFOSIZE`, bits 6..=10.
    pub const TXFIFOSIZE: &FieldSpec = &super::REGISTERS[23].fields[1];
    /// `OSTEN`, bit 11.
    pub const OSTEN: &FieldSpec = &super::REGISTERS[23].fields[2];
    /// `PTOEN`, bit 12.
    pub const PTOEN: &FieldSpec = &super::REGISTERS[23].fields[3];
    /// `ADVTHWORD`, bit 13.
    pub const ADVTHWORD: &FieldSpec = &super::REGISTERS[23].fields[4];
    /// `ADDR64`, bits 14..=15.
    pub const ADDR64: &FieldSpec = &super::REGISTERS[23].fields[5];
    /// `DCBEN`, bit 16.
    pub const DCBEN: &FieldSpec = &super::REGISTERS[23].fields[6];
    /// `SPHEN`, bit 17.
    pub const SPHEN: &FieldSpec = &super::REGISTERS[23].fields[7];
    /// `TSOEN`, bit 18.
    pub const TSOEN: &FieldSpec = &super::REGISTERS[23].fields[8];
    /// `DBGMEMA`, bit 19.
    pub const DBGMEMA: &FieldSpec = &super::REGISTERS[23].fields[9];
    /// `AVSEL`, bit 20.
    pub const AVSEL: &FieldSpec = &super::REGISTERS[23].fields[10];
    /// `HASHTBLSZ`, bits 24..=25.
    pub const HASHTBLSZ: &FieldSpec = &super::REGISTERS[23].fields[11];
    /// `L3L4FNUM`, bits 27..=30.
    pub const L3L4FNUM: &FieldSpec = &super::REGISTERS[23].fields[12];
}

/// The fields of `MACHWF2R`.
pub mod machwf2r {
    use super::FieldSpec;
    /// `RXQCNT`, bits 0..=3.
    pub const RXQCNT: &FieldSpec = &super::REGISTERS[24].fields[0];
    /// `TXQCNT`, bits 6..=9.
    pub const TXQCNT: &FieldSpec = &super::REGISTERS[24].fields[1];
    /// `RXCHCNT`, bits 12..=15.
    pub const RXCHCNT: &FieldSpec = &super::REGISTERS[24].fields[2];
    /// `TXCHCNT`, bits 18..=21.
    pub const TXCHCNT: &FieldSpec = &super::REGISTERS[24].fields[3];
    /// `PPSOUTNUM`, bits 24..=26.
    pub const PPSOUTNUM: &FieldSpec = &super::REGISTERS[24].fields[4];
    /// `AUXSNAPNUM`, bits 28..=30.
    pub const AUXSNAPNUM: &FieldSpec = &super::REGISTERS[24].fields[5];
}

/// The fields of `MACMDIOAR`.
pub mod macmdioar {
    use super::FieldSpec;
    /// `MB`, bit 0.
    pub const MB: &FieldSpec = &super::REGISTERS[25].fields[0];
    /// `C45E`, bit 1.
    pub const C45E: &FieldSpec = &super::REGISTERS[25].fields[1];
    /// `GOC`, bits 2..=3.
    pub const GOC: &FieldSpec = &super::REGISTERS[25].fields[2];
    /// `SKAP`, bit 4.
    pub const SKAP: &FieldSpec = &super::REGISTERS[25].fields[3];
    /// `CR`, bits 8..=11.
    pub const CR: &FieldSpec = &super::REGISTERS[25].fields[4];
    /// `NTC`, bits 12..=14.
    pub const NTC: &FieldSpec = &super::REGISTERS[25].fields[5];
    /// `RDA`, bits 16..=20.
    pub const RDA: &FieldSpec = &super::REGISTERS[25].fields[6];
    /// `PA`, bits 21..=25.
    pub const PA: &FieldSpec = &super::REGISTERS[25].fields[7];
    /// `BTB`, bit 26.
    pub const BTB: &FieldSpec = &super::REGISTERS[25].fields[8];
    /// `PSE`, bit 27.
    pub const PSE: &FieldSpec = &super::REGISTERS[25].fields[9];
}

/// The fields of `MACMDIODR`.
pub mod macmdiodr {
    use super::FieldSpec;
    /// `MD`, bits 0..=15.
    pub const MD: &FieldSpec = &super::REGISTERS[26].fields[0];
    /// `RA`, bits 16..=31.
    pub const RA: &FieldSpec = &super::REGISTERS[26].fields[1];
}

/// The fields of `MACA0HR`.
pub mod maca0hr {
    use super::FieldSpec;
    /// `ADDRHI`, bits 0..=15.
    pub const ADDRHI: &FieldSpec = &super::REGISTERS[27].fields[0];
    /// `AE`, bit 31, read-only.
    pub const AE: &FieldSpec = &super::REGISTERS[27].fields[1];
}

/// The fields of `MACA0LR`.
pub mod maca0lr {
    use super::FieldSpec;
    /// `ADDRLO`, bits 0..=31.
    pub const ADDRLO: &FieldSpec = &super::REGISTERS[28].fields[0];
}

/// The fields of `MACA1HR`.
pub mod maca1hr {
    use super::FieldSpec;
    /// `ADDRHI`, bits 0..=15.
    pub const ADDRHI: &FieldSpec = &super::REGISTERS[29].fields[0];
    /// `MBC`, bits 24..=29.
    pub const MBC: &FieldSpec = &super::REGISTERS[29].fields[1];
    /// `SA`, bit 30.
    pub const SA: &FieldSpec = &super::REGISTERS[29].fields[2];
    /// `AE`, bit 31.
    pub const AE: &FieldSpec = &super::REGISTERS[29].fields[3];
}

/// The fields of `MACA1LR`.
pub mod maca1lr {
    use super::FieldSpec;
    /// `ADDRLO`, bits 0..=31.
    pub const ADDRLO: &FieldSpec = &super::REGISTERS[30].fields[0];
}

/// The fields of `MACA2HR`.
pub mod maca2hr {
    use super::FieldSpec;
    /// `ADDRHI`, bits 0..=15.
    pub const ADDRHI: &FieldSpec = &super::REGISTERS[31].fields[0];
    /// `MBC`, bits 24..=29.
    pub const MBC: &FieldSpec = &super::REGISTERS[31].fields[1];
    /// `SA`, bit 30.
    pub const SA: &FieldSpec = &super::REGISTERS[31].fields[2];
    /// `AE`, bit 31.
    pub const AE: &FieldSpec = &super::REGISTERS[31].fields[3];
}

/// The fields of `MACA2LR`.
pub mod maca2lr {
    use super::FieldSpec;
    /// `ADDRLO`, bits 0..=31.
    pub const ADDRLO: &FieldSpec = &super::REGISTERS[32].fields[0];
}

/// The fields of `MACA3HR`.
pub mod maca3hr {
    use super::FieldSpec;
    /// `ADDRHI`, bits 0..=15.
    pub const ADDRHI: &FieldSpec = &super::REGISTERS[33].fields[0];
    /// `MBC`, bits 24..=29.
    pub const MBC: &FieldSpec = &super::REGISTERS[33].fields[1];
    /// `SA`, bit 30.
    pub const SA: &FieldSpec = &super::REGISTERS[33].fields[2];
    /// `AE`, bit 31.
    pub const AE: &FieldSpec = &super::REGISTERS[33].fields[3];
}

/// The fields of `MACA3LR`.
pub mod maca3lr {
    use super::FieldSpec;
    /// `ADDRLO`, bits 0..=31.
    pub const ADDRLO: &FieldSpec = &super::REGISTERS[34].fields[0];
}

/// The fields of `MMC_CONTROL`.
pub mod mmc_control {
    use super::FieldSpec;
    /// `CNTRST`, bit 0.
    pub const CNTRST: &FieldSpec = &super::REGISTERS[35].fields[0];
    /// `CNTSTOPRO`, bit 1.
    pub const CNTSTOPRO: &FieldSpec = &super::REGISTERS[35].fields[1];
    /// `RSTONRD`, bit 2.
    pub const RSTONRD: &FieldSpec = &super::REGISTERS[35].fields[2];
    /// `CNTFREEZ`, bit 3.
    pub const CNTFREEZ: &FieldSpec = &super::REGISTERS[35].fields[3];
    /// `CNTPRST`, bit 4.
    pub const CNTPRST: &FieldSpec = &super::REGISTERS[35].fields[4];
    /// `CNTPRSTLVL`, bit 5.
    pub const CNTPRSTLVL: &FieldSpec = &super::REGISTERS[35].fields[5];
    /// `UCDBC`, bit 8.
    pub const UCDBC: &FieldSpec = &super::REGISTERS[35].fields[6];
}

/// The fields of `MMC_RX_INTERRUPT`.
pub mod mmc_rx_interrupt {
    use super::FieldSpec;
    /// `RXCRCERPIS`, bit 5.
    pub const RXCRCERPIS: &FieldSpec = &super::REGISTERS[36].fields[0];
    /// `RXALGNERPIS`, bit 6.
    pub const RXALGNERPIS: &FieldSpec = &super::REGISTERS[36].fields[1];
    /// `RXUCGPIS`, bit 17.
    pub const RXUCGPIS: &FieldSpec = &super::REGISTERS[36].fields[2];
    /// `RXLPIUSCIS`, bit 26.
    pub const RXLPIUSCIS: &FieldSpec = &super::REGISTERS[36].fields[3];
    /// `RXLPITRCIS`, bit 27.
    pub const RXLPITRCIS: &FieldSpec = &super::REGISTERS[36].fields[4];
}

/// The fields of `MMC_TX_INTERRUPT`.
pub mod mmc_tx_interrupt {
    use super::FieldSpec;
    /// `TXSCOLGPIS`, bit 14.
    pub const TXSCOLGPIS: &FieldSpec = &super::REGISTERS[37].fields[0];
    /// `TXMCOLGPIS`, bit 15.
    pub const TXMCOLGPIS: &FieldSpec = &super::REGISTERS[37].fields[1];
    /// `TXGPKTIS`, bit 21.
    pub const TXGPKTIS: &FieldSpec = &super::REGISTERS[37].fields[2];
    /// `TXLPIUSCIS`, bit 26.
    pub const TXLPIUSCIS: &FieldSpec = &super::REGISTERS[37].fields[3];
    /// `TXLPITRCIS`, bit 27.
    pub const TXLPITRCIS: &FieldSpec = &super::REGISTERS[37].fields[4];
}

/// The fields of `MMC_RX_INTERRUPT_MASK`.
pub mod mmc_rx_interrupt_mask {
    use super::FieldSpec;
    /// `RXCRCERPIM`, bit 5.
    pub const RXCRCERPIM: &FieldSpec = &super::REGISTERS[38].fields[0];
    /// `RXALGNERPIM`, bit 6.
    pub const RXALGNERPIM: &FieldSpec = &super::REGISTERS[38].fields[1];
    /// `RXUCGPIM`, bit 17.
    pub const RXUCGPIM: &FieldSpec = &super::REGISTERS[38].fields[2];
    /// `RXLPIUSCIM`, bit 26.
    pub const RXLPIUSCIM: &FieldSpec = &super::REGISTERS[38].fields[3];
    /// `RXLPITRCIM`, bit 27, read-only.
    pub const RXLPITRCIM: &FieldSpec = &super::REGISTERS[38].fields[4];
}

/// The fields of `MMC_TX_INTERRUPT_MASK`.
pub mod mmc_tx_interrupt_mask {
    use super::FieldSpec;
    /// `TXSCOLGPIM`, bit 14.
    pub const TXSCOLGPIM: &FieldSpec = &super::REGISTERS[39].fields[0];
    /// `TXMCOLGPIM`, bit 15.
    pub const TXMCOLGPIM: &FieldSpec = &super::REGISTERS[39].fields[1];
    /// `TXGPKTIM`, bit 21.
    pub const TXGPKTIM: &FieldSpec = &super::REGISTERS[39].fields[2];
    /// `TXLPIUSCIM`, bit 26.
    pub const TXLPIUSCIM: &FieldSpec = &super::REGISTERS[39].fields[3];
    /// `TXLPITRCIM`, bit 27, read-only.
    pub const TXLPITRCIM: &FieldSpec = &super::REGISTERS[39].fields[4];
}

/// The fields of `TX_SINGLE_COLLISION_GOOD_PACKETS`.
pub mod tx_single_collision_good_packets {
    use super::FieldSpec;
    /// `TXSNGLCOLG`, bits 0..=31.
    pub const TXSNGLCOLG: &FieldSpec = &super::REGISTERS[40].fields[0];
}

/// The fields of `TX_MULTIPLE_COLLISION_GOOD_PACKETS`.
pub mod tx_multiple_collision_good_packets {
    use super::FieldSpec;
    /// `TXMULTCOLG`, bits 0..=31.
    pub const TXMULTCOLG: &FieldSpec = &super::REGISTERS[41].fields[0];
}

/// The fields of `TX_PACKET_COUNT_GOOD`.
pub mod tx_packet_count_good {
    use super::FieldSpec;
    /// `TXPKTG`, bits 0..=31.
    pub const TXPKTG: &FieldSpec = &super::REGISTERS[42].fields[0];
}

/// The fields of `RX_CRC_ERROR_PACKETS`.
pub mod rx_crc_error_packets {
    use super::FieldSpec;
    /// `RXCRCERR`, bits 0..=31.
    pub const RXCRCERR: &FieldSpec = &super::REGISTERS[43].fields[0];
}

/// The fields of `RX_ALIGNMENT_ERROR_PACKETS`.
pub mod rx_alignment_error_packets {
    use super::FieldSpec;
    /// `RXALGNERR`, bits 0..=31.
    pub const RXALGNERR: &FieldSpec = &super::REGISTERS[44].fields[0];
}

/// The fields of `RX_UNICAST_PACKETS_GOOD`.
pub mod rx_unicast_packets_good {
    use super::FieldSpec;
    /// `RXUCASTG`, bits 0..=31.
    pub const RXUCASTG: &FieldSpec = &super::REGISTERS[45].fields[0];
}

/// The fields of `TX_LPI_USEC_CNTR`.
pub mod tx_lpi_usec_cntr {
    use super::FieldSpec;
    /// `TXLPIUSC`, bits 0..=31.
    pub const TXLPIUSC: &FieldSpec = &super::REGISTERS[46].fields[0];
}

/// The fields of `TX_LPI_TRAN_CNTR`.
pub mod tx_lpi_tran_cntr {
    use super::FieldSpec;
    /// `TXLPITRC`, bits 0..=31.
    pub const TXLPITRC: &FieldSpec = &super::REGISTERS[47].fields[0];
}

/// The fields of `RX_LPI_USEC_CNTR`.
pub mod rx_lpi_usec_cntr {
    use super::FieldSpec;
    /// `RXLPIUSC`, bits 0..=31.
    pub const RXLPIUSC: &FieldSpec = &super::REGISTERS[48].fields[0];
}

/// The fields of `RX_LPI_TRAN_CNTR`.
pub mod rx_lpi_tran_cntr {
    use super::FieldSpec;
    /// `RXLPITRC`, bits 0..=31.
    pub const RXLPITRC: &FieldSpec = &super::REGISTERS[49].fields[0];
}

/// The fields of `MACL3L4C0R`.
pub mod macl3l4c0r {
    use super::FieldSpec;
    /// `L3PEN0`, bit 0.
    pub const L3PEN0: &FieldSpec = &super::REGISTERS[50].fields[0];
    /// `L3SAM0`, bit 2.
    pub const L3SAM0: &FieldSpec = &super::REGISTERS[50].fields[1];
    /// `L3SAIM0`, bit 3.
    pub const L3SAIM0: &FieldSpec = &super::REGISTERS[50].fields[2];
    /// `L3DAM0`, bit 4.
    pub const L3DAM0: &FieldSpec = &super::REGISTERS[50].fields[3];
    /// `L3DAIM0`, bit 5.
    pub const L3DAIM0: &FieldSpec = &super::REGISTERS[50].fields[4];
    /// `L3HSBM0`, bits 6..=10.
    pub const L3HSBM0: &FieldSpec = &super::REGISTERS[50].fields[5];
    /// `L3HDBM0`, bits 11..=15.
    pub const L3HDBM0: &FieldSpec = &super::REGISTERS[50].fields[6];
    /// `L4PEN0`, bit 16.
    pub const L4PEN0: &FieldSpec = &super::REGISTERS[50].fields[7];
    /// `L4SPM0`, bit 18.
    pub const L4SPM0: &FieldSpec = &super::REGISTERS[50].fields[8];
    /// `L4SPIM0`, bit 19.
    pub const L4SPIM0: &FieldSpec = &super::REGISTERS[50].fields[9];
    /// `L4DPM0`, bit 20.
    pub const L4DPM0: &FieldSpec = &super::REGISTERS[50].fields[10];
    /// `L4DPIM0`, bit 21.
    pub const L4DPIM0: &FieldSpec = &super::REGISTERS[50].fields[11];
}

/// The fields of `MACL4A0R`.
pub mod macl4a0r {
    use super::FieldSpec;
    /// `L4SP0`, bits 0..=15.
    pub const L4SP0: &FieldSpec = &super::REGISTERS[51].fields[0];
    /// `L4DP0`, bits 16..=31.
    pub const L4DP0: &FieldSpec = &super::REGISTERS[51].fields[1];
}

/// The fields of `MACL3A00R`.
pub mod macl3a00r {
    use super::FieldSpec;
    /// `L3A00`, bits 0..=31.
    pub const L3A00: &FieldSpec = &super::REGISTERS[52].fields[0];
}

/// The fields of `MACL3A10R`.
pub mod macl3a10r {
    use super::FieldSpec;
    /// `L3A10`, bits 0..=31.
    pub const L3A10: &FieldSpec = &super::REGISTERS[53].fields[0];
}

/// The fields of `MACL3A20`.
pub mod macl3a20 {
    use super::FieldSpec;
    /// `L3A20`, bits 0..=31.
    pub const L3A20: &FieldSpec = &super::REGISTERS[54].fields[0];
}

/// The fields of `MACL3A30`.
pub mod macl3a30 {
    use super::FieldSpec;
    /// `L3A30`, bits 0..=31.
    pub const L3A30: &FieldSpec = &super::REGISTERS[55].fields[0];
}

/// The fields of `MACL3L4C1R`.
pub mod macl3l4c1r {
    use super::FieldSpec;
    /// `L3PEN1`, bit 0.
    pub const L3PEN1: &FieldSpec = &super::REGISTERS[56].fields[0];
    /// `L3SAM1`, bit 2.
    pub const L3SAM1: &FieldSpec = &super::REGISTERS[56].fields[1];
    /// `L3SAIM1`, bit 3.
    pub const L3SAIM1: &FieldSpec = &super::REGISTERS[56].fields[2];
    /// `L3DAM1`, bit 4.
    pub const L3DAM1: &FieldSpec = &super::REGISTERS[56].fields[3];
    /// `L3DAIM1`, bit 5.
    pub const L3DAIM1: &FieldSpec = &super::REGISTERS[56].fields[4];
    /// `L3HSBM1`, bits 6..=10.
    pub const L3HSBM1: &FieldSpec = &super::REGISTERS[56].fields[5];
    /// `L3HDBM1`, bits 11..=15.
    pub const L3HDBM1: &FieldSpec = &super::REGISTERS[56].fields[6];
    /// `L4PEN1`, bit 16.
    pub const L4PEN1: &FieldSpec = &super::REGISTERS[56].fields[7];
    /// `L4SPM1`, bit 18.
    pub const L4SPM1: &FieldSpec = &super::REGISTERS[56].fields[8];
    /// `L4SPIM1`, bit 19.
    pub const L4SPIM1: &FieldSpec = &super::REGISTERS[56].fields[9];
    /// `L4DPM1`, bit 20.
    pub const L4DPM1: &FieldSpec = &super::REGISTERS[56].fields[10];
    /// `L4DPIM1`, bit 21.
    pub const L4DPIM1: &FieldSpec = &super::REGISTERS[56].fields[11];
}

/// The fields of `MACL4A1R`.
pub mod macl4a1r {
    use super::FieldSpec;
    /// `L4SP1`, bits 0..=15.
    pub const L4SP1: &FieldSpec = &super::REGISTERS[57].fields[0];
    /// `L4DP1`, bits 16..=31.
    pub const L4DP1: &FieldSpec = &super::REGISTERS[57].fields[1];
}

/// The fields of `MACL3A01R`.
pub mod macl3a01r {
    use super::FieldSpec;
    /// `L3A01`, bits 0..=31.
    pub const L3A01: &FieldSpec = &super::REGISTERS[58].fields[0];
}

/// The fields of `MACL3A11R`.
pub mod macl3a11r {
    use super::FieldSpec;
    /// `L3A11`, bits 0..=31.
    pub const L3A11: &FieldSpec = &super::REGISTERS[59].fields[0];
}

/// The fields of `MACL3A21R`.
pub mod macl3a21r {
    use super::FieldSpec;
    /// `L3A21`, bits 0..=31.
    pub const L3A21: &FieldSpec = &super::REGISTERS[60].fields[0];
}

/// The fields of `MACL3A31R`.
pub mod macl3a31r {
    use super::FieldSpec;
    /// `L3A31`, bits 0..=31.
    pub const L3A31: &FieldSpec = &super::REGISTERS[61].fields[0];
}

/// The fields of `MACARPAR`.
pub mod macarpar {
    use super::FieldSpec;
    /// `ARPPA`, bits 0..=31.
    pub const ARPPA: &FieldSpec = &super::REGISTERS[62].fields[0];
}

/// The fields of `MACTSCR`.
pub mod mactscr {
    use super::FieldSpec;
    /// `TSENA`, bit 0.
    pub const TSENA: &FieldSpec = &super::REGISTERS[63].fields[0];
    /// `TSCFUPDT`, bit 1.
    pub const TSCFUPDT: &FieldSpec = &super::REGISTERS[63].fields[1];
    /// `TSINIT`, bit 2.
    pub const TSINIT: &FieldSpec = &super::REGISTERS[63].fields[2];
    /// `TSUPDT`, bit 3.
    pub const TSUPDT: &FieldSpec = &super::REGISTERS[63].fields[3];
    /// `TSADDREG`, bit 5.
    pub const TSADDREG: &FieldSpec = &super::REGISTERS[63].fields[4];
    /// `TSENALL`, bit 8.
    pub const TSENALL: &FieldSpec = &super::REGISTERS[63].fields[5];
    /// `TSCTRLSSR`, bit 9.
    pub const TSCTRLSSR: &FieldSpec = &super::REGISTERS[63].fields[6];
    /// `TSVER2ENA`, bit 10.
    pub const TSVER2ENA: &FieldSpec = &super::REGISTERS[63].fields[7];
    /// `TSIPENA`, bit 11.
    pub const TSIPENA: &FieldSpec = &super::REGISTERS[63].fields[8];
    /// `TSIPV6ENA`, bit 12.
    pub const TSIPV6ENA: &FieldSpec = &super::REGISTERS[63].fields[9];
    /// `TSIPV4ENA`, bit 13.
    pub const TSIPV4ENA: &FieldSpec = &super::REGISTERS[63].fields[10];
    /// `TSEVNTENA`, bit 14.
    pub const TSEVNTENA: &FieldSpec = &super::REGISTERS[63].fields[11];
    /// `TSMSTRENA`, bit 15.
    pub const TSMSTRENA: &FieldSpec = &super::REGISTERS[63].fields[12];
    /// `SNAPTYPSEL`, bits 16..=17.
    pub const SNAPTYPSEL: &FieldSpec = &super::REGISTERS[63].fields[13];
    /// `TSENMACADDR`, bit 18.
    pub const TSENMACADDR: &FieldSpec = &super::REGISTERS[63].fields[14];
    /// `CSC`, bit 19, read-only.
    pub const CSC: &FieldSpec = &super::REGISTERS[63].fields[15];
    /// `TXTSSTSM`, bit 24.
    pub const TXTSSTSM: &FieldSpec = &super::REGISTERS[63].fields[16];
}

/// The fields of `MACSSIR`.
pub mod macssir {
    use super::FieldSpec;
    /// `SNSINC`, bits 8..=15.
    pub const SNSINC: &FieldSpec = &super::REGISTERS[64].fields[0];
    /// `SSINC`, bits 16..=23.
    pub const SSINC: &FieldSpec = &super::REGISTERS[64].fields[1];
}

/// The fields of `MACSTSR`.
pub mod macstsr {
    use super::FieldSpec;
    /// `TSS`, bits 0..=31.
    pub const TSS: &FieldSpec = &super::REGISTERS[65].fields[0];
}

/// The fields of `MACSTNR`.
pub mod macstnr {
    use super::FieldSpec;
    /// `TSSS`, bits 0..=30.
    pub const TSSS: &FieldSpec = &super::REGISTERS[66].fields[0];
}

/// The fields of `MACSTSUR`.
pub mod macstsur {
    use super::FieldSpec;
    /// `TSS`, bits 0..=31.
    pub const TSS: &FieldSpec = &super::REGISTERS[67].fields[0];
}

/// The fields of `MACSTNUR`.
pub mod macstnur {
    use super::FieldSpec;
    /// `TSSS`, bits 0..=30.
    pub const TSSS: &FieldSpec = &super::REGISTERS[68].fields[0];
    /// `ADDSUB`, bit 31.
    pub const ADDSUB: &FieldSpec = &super::REGISTERS[68].fields[1];
}

/// The fields of `MACTSAR`.
pub mod mactsar {
    use super::FieldSpec;
    /// `TSAR`, bits 0..=31.
    pub const TSAR: &FieldSpec = &super::REGISTERS[69].fields[0];
}

/// The fields of `MACTSSR`.
pub mod mactssr {
    use super::FieldSpec;
    /// `TSSOVF`, bit 0.
    pub const TSSOVF: &FieldSpec = &super::REGISTERS[70].fields[0];
    /// `TSTARGT0`, bit 1.
    pub const TSTARGT0: &FieldSpec = &super::REGISTERS[70].fields[1];
    /// `AUXTSTRIG`, bit 2.
    pub const AUXTSTRIG: &FieldSpec = &super::REGISTERS[70].fields[2];
    /// `TSTRGTERR0`, bit 3.
    pub const TSTRGTERR0: &FieldSpec = &super::REGISTERS[70].fields[3];
    /// `TXTSSIS`, bit 15.
    pub const TXTSSIS: &FieldSpec = &super::REGISTERS[70].fields[4];
    /// `ATSSTN`, bits 16..=19.
    pub const ATSSTN: &FieldSpec = &super::REGISTERS[70].fields[5];
    /// `ATSSTM`, bit 24.
    pub const ATSSTM: &FieldSpec = &super::REGISTERS[70].fields[6];
    /// `ATSNS`, bits 25..=29.
    pub const ATSNS: &FieldSpec = &super::REGISTERS[70].fields[7];
}

/// The fields of `MACTxTSSNR`.
pub mod mactxtssnr {
    use super::FieldSpec;
    /// `TXTSSLO`, bits 0..=30.
    pub const TXTSSLO: &FieldSpec = &super::REGISTERS[71].fields[0];
    /// `TXTSSMIS`, bit 31.
    pub const TXTSSMIS: &FieldSpec = &super::REGISTERS[71].fields[1];
}

/// The fields of `MACTxTSSSR`.
pub mod mactxtsssr {
    use super::FieldSpec;
    /// `TXTSSHI`, bits 0..=31.
    pub const TXTSSHI: &FieldSpec = &super::REGISTERS[72].fields[0];
}

/// The fields of `MACACR`.
pub mod macacr {
    use super::FieldSpec;
    /// `ATSFC`, bit 0.
    pub const ATSFC: &FieldSpec = &super::REGISTERS[73].fields[0];
    /// `ATSEN0`, bit 4.
    pub const ATSEN0: &FieldSpec = &super::REGISTERS[73].fields[1];
    /// `ATSEN1`, bit 5.
    pub const ATSEN1: &FieldSpec = &super::REGISTERS[73].fields[2];
    /// `ATSEN2`, bit 6.
    pub const ATSEN2: &FieldSpec = &super::REGISTERS[73].fields[3];
    /// `ATSEN3`, bit 7.
    pub const ATSEN3: &FieldSpec = &super::REGISTERS[73].fields[4];
}

/// The fields of `MACATSNR`.
pub mod macatsnr {
    use super::FieldSpec;
    /// `AUXTSLO`, bits 0..=30.
    pub const AUXTSLO: &FieldSpec = &super::REGISTERS[74].fields[0];
}

/// The fields of `MACATSSR`.
pub mod macatssr {
    use super::FieldSpec;
    /// `AUXTSHI`, bits 0..=31.
    pub const AUXTSHI: &FieldSpec = &super::REGISTERS[75].fields[0];
}

/// The fields of `MACTSIACR`.
pub mod mactsiacr {
    use super::FieldSpec;
    /// `OSTIAC`, bits 0..=31.
    pub const OSTIAC: &FieldSpec = &super::REGISTERS[76].fields[0];
}

/// The fields of `MACTSEACR`.
pub mod mactseacr {
    use super::FieldSpec;
    /// `OSTEAC`, bits 0..=31.
    pub const OSTEAC: &FieldSpec = &super::REGISTERS[77].fields[0];
}

/// The fields of `MACTSICNR`.
pub mod mactsicnr {
    use super::FieldSpec;
    /// `TSIC`, bits 0..=31.
    pub const TSIC: &FieldSpec = &super::REGISTERS[78].fields[0];
}

/// The fields of `MACTSECNR`.
pub mod mactsecnr {
    use super::FieldSpec;
    /// `TSEC`, bits 0..=31.
    pub const TSEC: &FieldSpec = &super::REGISTERS[79].fields[0];
}

/// The fields of `MACPPSCR`.
pub mod macppscr {
    use super::FieldSpec;
    /// `PPSCTRL`, bits 0..=3.
    pub const PPSCTRL: &FieldSpec = &super::REGISTERS[80].fields[0];
    /// `PPSEN0`, bit 4.
    pub const PPSEN0: &FieldSpec = &super::REGISTERS[80].fields[1];
    /// `TRGTMODSEL0`, bits 5..=6.
    pub const TRGTMODSEL0: &FieldSpec = &super::REGISTERS[80].fields[2];
}

/// The fields of `MACPPSTTSR`.
pub mod macppsttsr {
    use super::FieldSpec;
    /// `TSTRH0`, bits 0..=30.
    pub const TSTRH0: &FieldSpec = &super::REGISTERS[81].fields[0];
}

/// The fields of `MACPPSTTNR`.
pub mod macppsttnr {
    use super::FieldSpec;
    /// `TTSL0`, bits 0..=30.
    pub const TTSL0: &FieldSpec = &super::REGISTERS[82].fields[0];
    /// `TRGTBUSY0`, bit 31.
    pub const TRGTBUSY0: &FieldSpec = &super::REGISTERS[82].fields[1];
}

/// The fields of `MACPPSIR`.
pub mod macppsir {
    use super::FieldSpec;
    /// `PPSINT0`, bits 0..=31.
    pub const PPSINT0: &FieldSpec = &super::REGISTERS[83].fields[0];
}

/// The fields of `MACPPSWR`.
pub mod macppswr {
    use super::FieldSpec;
    /// `PPSWIDTH0`, bits 0..=31.
    pub const PPSWIDTH0: &FieldSpec = &super::REGISTERS[84].fields[0];
}

/// The fields of `MACPOCR`.
pub mod macpocr {
    use super::FieldSpec;
    /// `PTOEN`, bit 0.
    pub const PTOEN: &FieldSpec = &super::REGISTERS[85].fields[0];
    /// `ASYNCEN`, bit 1.
    pub const ASYNCEN: &FieldSpec = &super::REGISTERS[85].fields[1];
    /// `APDREQEN`, bit 2.
    pub const APDREQEN: &FieldSpec = &super::REGISTERS[85].fields[2];
    /// `ASYNCTRIG`, bit 4.
    pub const ASYNCTRIG: &FieldSpec = &super::REGISTERS[85].fields[3];
    /// `APDREQTRIG`, bit 5.
    pub const APDREQTRIG: &FieldSpec = &super::REGISTERS[85].fields[4];
    /// `DRRDIS`, bit 6.
    pub const DRRDIS: &FieldSpec = &super::REGISTERS[85].fields[5];
    /// `DN`, bits 8..=15.
    pub const DN: &FieldSpec = &super::REGISTERS[85].fields[6];
}

/// The fields of `MACSPI0R`.
pub mod macspi0r {
    use super::FieldSpec;
    /// `SPI0`, bits 0..=31.
    pub const SPI0: &FieldSpec = &super::REGISTERS[86].fields[0];
}

/// The fields of `MACSPI1R`.
pub mod macspi1r {
    use super::FieldSpec;
    /// `SPI1`, bits 0..=31.
    pub const SPI1: &FieldSpec = &super::REGISTERS[87].fields[0];
}

/// The fields of `MACSPI2R`.
pub mod macspi2r {
    use super::FieldSpec;
    /// `SPI2`, bits 0..=15.
    pub const SPI2: &FieldSpec = &super::REGISTERS[88].fields[0];
}

/// The fields of `MACLMIR`.
pub mod maclmir {
    use super::FieldSpec;
    /// `LSI`, bits 0..=7.
    pub const LSI: &FieldSpec = &super::REGISTERS[89].fields[0];
    /// `DRSYNCR`, bits 8..=10.
    pub const DRSYNCR: &FieldSpec = &super::REGISTERS[89].fields[1];
    /// `LMPDRI`, bits 24..=31.
    pub const LMPDRI: &FieldSpec = &super::REGISTERS[89].fields[2];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 90] = [
    RegisterSpec { name: "MACCR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PRELEN", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DC", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BL", bit: 5, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DR", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DCRS", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DO", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ECRSFD", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LM", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DM", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FES", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JD", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WD", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACS", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CST", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "S2KP", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPSLCE", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IPG", bit: 24, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IPC", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SARC", bit: 28, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARPEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACECR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "GPSL", bit: 0, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DCRCC", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USP", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EIPGEN", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EIPG", bit: 25, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACPFR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PR", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HUC", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HMC", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DAIF", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PM", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBF", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCF", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SAIF", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SAF", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HPF", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VTFE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IPFE", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DNTU", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RA", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACWTR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WTO", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PWE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACHT0R", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HT31T0", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACHT1R", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HT63T32", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACVTR", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "VL", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ETV", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VTIM", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ESVL", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ERSVLM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DOVLTC", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EVLS", bit: 21, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EVLRXS", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VTHM", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EDVLP", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ERIVLT", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EIVLS", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EIVLRXS", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACVHTR", offset: 0x58, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "VLHT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACVIR", offset: 0x60, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "VLT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VLC", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VLP", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSVL", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VLTI", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACIVIR", offset: 0x64, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "VLT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VLC", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VLP", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSVL", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VLTI", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACQTxFCR", offset: 0x70, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FCB_BPA", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TFE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLT", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DZPQ", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PT", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACRxFCR", offset: 0x90, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RFE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UP", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACISR", offset: 0xB0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PHYIS", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PMTIS", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LPIIS", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MMCIS", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MMCRXIS", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MMCTXIS", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSIS", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXSTSIS", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXSTSIS", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACIER", offset: 0xB4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PHYIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PMTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LPIIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSIE", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXSTSIE", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXSTSIE", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACRxTxSR", offset: 0xB8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TJT", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NCARR", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCARR", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXDEF", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCOL", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXCOL", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWT", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACPCSR", offset: 0xC0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PWRDWN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MGKPKTEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWKPKTEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MGKPRCVD", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWKPRCVD", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GLBLUCAST", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWKPFE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWKPTR", bit: 24, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWKFILTRST", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACRWKPFR", offset: 0xC4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MACRWKPFR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACLCSR", offset: 0xD0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TLPIEN", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TLPIEX", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RLPIEN", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RLPIEX", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TLPIST", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RLPIST", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LPIEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLSEN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LPITXA", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LPITE", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACLTCR", offset: 0xD4, width: Width::W32, reset: 0x03E8_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TWT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LST", bit: 16, width: 10, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACLETR", offset: 0xD8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LPIET", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MAC1USTCR", offset: 0xDC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TIC_1US_CNTR", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACVR", offset: 0x110, width: Width::W32, reset: 0x0000_3041, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SNPSVER", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USERVER", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACDR", offset: 0x114, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RPESTS", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RFCFCSTS", bit: 1, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TPESTS", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TFCSTS", bit: 17, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACHWF1R", offset: 0x120, width: Width::W32, reset: 0x1184_1904, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXFIFOSIZE", bit: 0, width: 5, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFIFOSIZE", bit: 6, width: 5, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSTEN", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PTOEN", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADVTHWORD", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADDR64", bit: 14, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DCBEN", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPHEN", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSOEN", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBGMEMA", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AVSEL", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HASHTBLSZ", bit: 24, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L3L4FNUM", bit: 27, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACHWF2R", offset: 0x124, width: Width::W32, reset: 0x4100_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXQCNT", bit: 0, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXQCNT", bit: 6, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXCHCNT", bit: 12, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXCHCNT", bit: 18, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PPSOUTNUM", bit: 24, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AUXSNAPNUM", bit: 28, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACMDIOAR", offset: 0x200, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MB", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "C45E", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GOC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SKAP", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CR", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NTC", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RDA", bit: 16, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PA", bit: 21, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BTB", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSE", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACMDIODR", offset: 0x204, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MD", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RA", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACA0HR", offset: 0x300, width: Width::W32, reset: 0x8000_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDRHI", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AE", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACA0LR", offset: 0x304, width: Width::W32, reset: 0xFFFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDRLO", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACA1HR", offset: 0x308, width: Width::W32, reset: 0x0000_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDRHI", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MBC", bit: 24, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SA", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AE", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACA1LR", offset: 0x30C, width: Width::W32, reset: 0xFFFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDRLO", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACA2HR", offset: 0x310, width: Width::W32, reset: 0x0000_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDRHI", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MBC", bit: 24, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SA", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AE", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACA2LR", offset: 0x314, width: Width::W32, reset: 0xFFFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDRLO", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACA3HR", offset: 0x318, width: Width::W32, reset: 0x0000_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDRHI", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MBC", bit: 24, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SA", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AE", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACA3LR", offset: 0x31C, width: Width::W32, reset: 0xFFFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDRLO", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MMC_CONTROL", offset: 0x700, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CNTRST", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNTSTOPRO", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSTONRD", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNTFREEZ", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNTPRST", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNTPRSTLVL", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UCDBC", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MMC_RX_INTERRUPT", offset: 0x704, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXCRCERPIS", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXALGNERPIS", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXUCGPIS", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXLPIUSCIS", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXLPITRCIS", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MMC_TX_INTERRUPT", offset: 0x708, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TXSCOLGPIS", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXMCOLGPIS", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXGPKTIS", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXLPIUSCIS", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXLPITRCIS", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MMC_RX_INTERRUPT_MASK", offset: 0x70C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXCRCERPIM", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXALGNERPIM", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXUCGPIM", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXLPIUSCIM", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXLPITRCIM", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MMC_TX_INTERRUPT_MASK", offset: 0x710, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TXSCOLGPIM", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXMCOLGPIM", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXGPKTIM", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXLPIUSCIM", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXLPITRCIM", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TX_SINGLE_COLLISION_GOOD_PACKETS", offset: 0x74C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TXSNGLCOLG", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TX_MULTIPLE_COLLISION_GOOD_PACKETS", offset: 0x750, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TXMULTCOLG", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TX_PACKET_COUNT_GOOD", offset: 0x768, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TXPKTG", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RX_CRC_ERROR_PACKETS", offset: 0x794, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXCRCERR", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RX_ALIGNMENT_ERROR_PACKETS", offset: 0x798, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXALGNERR", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RX_UNICAST_PACKETS_GOOD", offset: 0x7C4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXUCASTG", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TX_LPI_USEC_CNTR", offset: 0x7EC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TXLPIUSC", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TX_LPI_TRAN_CNTR", offset: 0x7F0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TXLPITRC", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RX_LPI_USEC_CNTR", offset: 0x7F4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXLPIUSC", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RX_LPI_TRAN_CNTR", offset: 0x7F8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXLPITRC", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACL3L4C0R", offset: 0x900, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "L3PEN0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L3SAM0", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L3SAIM0", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L3DAM0", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L3DAIM0", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L3HSBM0", bit: 6, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L3HDBM0", bit: 11, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L4PEN0", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L4SPM0", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L4SPIM0", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L4DPM0", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L4DPIM0", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACL4A0R", offset: 0x904, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "L4SP0", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L4DP0", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACL3A00R", offset: 0x910, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "L3A00", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACL3A10R", offset: 0x914, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "L3A10", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACL3A20", offset: 0x918, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "L3A20", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACL3A30", offset: 0x91C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "L3A30", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACL3L4C1R", offset: 0x930, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "L3PEN1", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L3SAM1", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L3SAIM1", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L3DAM1", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L3DAIM1", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L3HSBM1", bit: 6, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L3HDBM1", bit: 11, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L4PEN1", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L4SPM1", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L4SPIM1", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L4DPM1", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L4DPIM1", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACL4A1R", offset: 0x934, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "L4SP1", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L4DP1", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACL3A01R", offset: 0x940, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "L3A01", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACL3A11R", offset: 0x944, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "L3A11", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACL3A21R", offset: 0x948, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "L3A21", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACL3A31R", offset: 0x94C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "L3A31", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACARPAR", offset: 0xAE0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ARPPA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACTSCR", offset: 0xB00, width: Width::W32, reset: 0x0000_0200, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TSENA", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSCFUPDT", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSINIT", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSUPDT", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSADDREG", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSENALL", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSCTRLSSR", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSVER2ENA", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSIPENA", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSIPV6ENA", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSIPV4ENA", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSEVNTENA", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSMSTRENA", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SNAPTYPSEL", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSENMACADDR", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSC", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXTSSTSM", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACSSIR", offset: 0xB04, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SNSINC", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SSINC", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACSTSR", offset: 0xB08, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TSS", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACSTNR", offset: 0xB0C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TSSS", bit: 0, width: 31, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACSTSUR", offset: 0xB10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TSS", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACSTNUR", offset: 0xB14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TSSS", bit: 0, width: 31, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADDSUB", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACTSAR", offset: 0xB18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TSAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACTSSR", offset: 0xB20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TSSOVF", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSTARGT0", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AUXTSTRIG", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSTRGTERR0", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXTSSIS", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ATSSTN", bit: 16, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ATSSTM", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ATSNS", bit: 25, width: 5, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACTxTSSNR", offset: 0xB30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TXTSSLO", bit: 0, width: 31, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXTSSMIS", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACTxTSSSR", offset: 0xB34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TXTSSHI", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACACR", offset: 0xB40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ATSFC", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ATSEN0", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ATSEN1", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ATSEN2", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ATSEN3", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACATSNR", offset: 0xB48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AUXTSLO", bit: 0, width: 31, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACATSSR", offset: 0xB4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AUXTSHI", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACTSIACR", offset: 0xB50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OSTIAC", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACTSEACR", offset: 0xB54, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OSTEAC", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACTSICNR", offset: 0xB58, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TSIC", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACTSECNR", offset: 0xB5C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TSEC", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACPPSCR", offset: 0xB70, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PPSCTRL", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PPSEN0", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRGTMODSEL0", bit: 5, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACPPSTTSR", offset: 0xB80, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TSTRH0", bit: 0, width: 31, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACPPSTTNR", offset: 0xB84, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TTSL0", bit: 0, width: 31, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRGTBUSY0", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACPPSIR", offset: 0xB88, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PPSINT0", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACPPSWR", offset: 0xB8C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PPSWIDTH0", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACPOCR", offset: 0xBC0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PTOEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ASYNCEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "APDREQEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ASYNCTRIG", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "APDREQTRIG", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DRRDIS", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DN", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACSPI0R", offset: 0xBC4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SPI0", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACSPI1R", offset: 0xBC8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SPI1", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACSPI2R", offset: 0xBCC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SPI2", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACLMIR", offset: 0xBD0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LSI", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DRSYNCR", bit: 8, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LMPDRI", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];