rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `LPTIM3` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `ISR` at offset `0x0`, resets to `0x0000_0000`, read-only.
    Isr = 0,
    /// `ICR` at offset `0x4`, resets to `0x0000_0000`, write-only.
    Icr = 1,
    /// `IER` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Ier = 2,
    /// `CFGR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Cfgr = 3,
    /// `CR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Cr = 4,
    /// `CMP` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Cmp = 5,
    /// `ARR` at offset `0x18`, resets to `0x0000_0001`, read-write.
    Arr = 6,
    /// `CNT` at offset `0x1C`, resets to `0x0000_0000`, read-only.
    Cnt = 7,
    /// `CFGR2` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Cfgr2 = 8,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 9] = [Self::Isr, Self::Icr, Self::Ier, Self::Cfgr, Self::Cr, Self::Cmp, Self::Arr, Self::Cnt, Self::Cfgr2];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `ISR`.
pub mod isr {
    use super::FieldSpec;
    /// `CMPM`, bit 0.
    pub const CMPM: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `ARRM`, bit 1.
    pub const ARRM: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `EXTTRIG`, bit 2.
    pub const EXTTRIG: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `CMPOK`, bit 3.
    pub const CMPOK: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `ARROK`, bit 4.
    pub const ARROK: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `UP`, bit 5.
    pub const UP: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `DOWN`, bit 6.
    pub const DOWN: &FieldSpec = &super::REGISTERS[0].fields[6];
}

/// The fields of `ICR`.
pub mod icr {
    use super::FieldSpec;
    /// `CMPMCF`, bit 0.
    pub const CMPMCF: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `ARRMCF`, bit 1.
    pub const ARRMCF: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `EXTTRIGCF`, bit 2.
    pub const EXTTRIGCF: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `CMPOKCF`, bit 3.
    pub const CMPOKCF: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `ARROKCF`, bit 4.
    pub const ARROKCF: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `UPCF`, bit 5.
    pub const UPCF: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `DOWNCF`, bit 6.
    pub const DOWNCF: &FieldSpec = &super::REGISTERS[1].fields[6];
}

/// The fields of `IER`.
pub mod ier {
    use super::FieldSpec;
    /// `CMPMIE`, bit 0.
    pub const CMPMIE: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `ARRMIE`, bit 1.
    pub const ARRMIE: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `EXTTRIGIE`, bit 2.
    pub const EXTTRIGIE: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `CMPOKIE`, bit 3.
    pub const CMPOKIE: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `ARROKIE`, bit 4.
    pub const ARROKIE: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `UPIE`, bit 5.
    pub const UPIE: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `DOWNIE`, bit 6.
    pub const DOWNIE: &FieldSpec = &super::REGISTERS[2].fields[6];
}

/// The fields of `CFGR`.
pub mod cfgr {
    use super::FieldSpec;
    /// `CKSEL`, bit 0.
    pub const CKSEL: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `CKPOL`, bits 1..=2.
    pub const CKPOL: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `CKFLT`, bits 3..=4.
    pub const CKFLT: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `TRGFLT`, bits 6..=7.
    pub const TRGFLT: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `PRESC`, bits 9..=11.
    pub const PRESC: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `TRIGSEL`, bits 13..=15.
    pub const TRIGSEL: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `TRIGEN`, bits 17..=18.
    pub const TRIGEN: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `TIMOUT`, bit 19.
    pub const TIMOUT: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `WAVE`, bit 20.
    pub const WAVE: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `WAVPOL`, bit 21.
    pub const WAVPOL: &FieldSpec = &super::REGISTERS[3].fields[9];
    /// `PRELOAD`, bit 22.
    pub const PRELOAD: &FieldSpec = &super::REGISTERS[3].fields[10];
    /// `COUNTMODE`, bit 23.
    pub const COUNTMODE: &FieldSpec = &super::REGISTERS[3].fields[11];
    /// `ENC`, bit 24.
    pub const ENC: &FieldSpec = &super::REGISTERS[3].fields[12];
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `ENABLE`, bit 0.
    pub const ENABLE: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `SNGSTRT`, bit 1.
    pub const SNGSTRT: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `CNTSTRT`, bit 2.
    pub const CNTSTRT: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `COUNTRST`, bit 3.
    pub const COUNTRST: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `RSTARE`, bit 4.
    pub const RSTARE: &FieldSpec = &super::REGISTERS[4].fields[4];
}

/// The fields of `CMP`.
pub mod cmp {
    use super::FieldSpec;
    /// `CMP`, bits 0..=15.
    pub const CMP: &FieldSpec = &super::REGISTERS[5].fields[0];
}

/// The fields of `ARR`.
pub mod arr {
    use super::FieldSpec;
    /// `ARR`, bits 0..=15.
    pub const ARR: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `CNT`.
pub mod cnt {
    use super::FieldSpec;
    /// `CNT`, bits 0..=15.
    pub const CNT: &FieldSpec = &super::REGISTERS[7].fields[0];
}

/// The fields of `CFGR2`.
pub mod cfgr2 {
    use super::FieldSpec;
    /// `IN1SEL`, bits 0..=1.
    pub const IN1SEL: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 9] = [
    RegisterSpec { name: "ISR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CMPM", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARRM", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTTRIG", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMPOK", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARROK", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UP", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DOWN", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ICR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CMPMCF", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARRMCF", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTTRIGCF", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMPOKCF", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARROKCF", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UPCF", bit: 5, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DOWNCF", bit: 6, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IER", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CMPMIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARRMIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTTRIGIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMPOKIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARROKIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UPIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DOWNIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CFGR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CKSEL", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKPOL", bit: 1, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKFLT", bit: 3, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRGFLT", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PRESC", bit: 9, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRIGSEL", bit: 13, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRIGEN", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMOUT", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAVE", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAVPOL", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PRELOAD", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COUNTMODE", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ENC", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ENABLE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SNGSTRT", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNTSTRT", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COUNTRST", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSTARE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CMP", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CMP", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ARR", offset: 0x18, width: Width::W32, reset: 0x0000_0001, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ARR", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CNT", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CNT", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CFGR2", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IN1SEL", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];