// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `LTDC` and the instances derived from it.
use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};
/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
/// `SSCR` at offset `0x8`, resets to `0x0000_0000`, read-write.
Sscr = 0,
/// `BPCR` at offset `0xC`, resets to `0x0000_0000`, read-write.
Bpcr = 1,
/// `AWCR` at offset `0x10`, resets to `0x0000_0000`, read-write.
Awcr = 2,
/// `TWCR` at offset `0x14`, resets to `0x0000_0000`, read-write.
Twcr = 3,
/// `GCR` at offset `0x18`, resets to `0x0000_2220`, read-write.
Gcr = 4,
/// `SRCR` at offset `0x24`, resets to `0x0000_0000`, read-write.
Srcr = 5,
/// `BCCR` at offset `0x2C`, resets to `0x0000_0000`, read-write.
Bccr = 6,
/// `IER` at offset `0x34`, resets to `0x0000_0000`, read-write.
Ier = 7,
/// `ISR` at offset `0x38`, resets to `0x0000_0000`, read-only.
Isr = 8,
/// `ICR` at offset `0x3C`, resets to `0x0000_0000`, write-only.
Icr = 9,
/// `LIPCR` at offset `0x40`, resets to `0x0000_0000`, read-write.
Lipcr = 10,
/// `CPSR` at offset `0x44`, resets to `0x0000_0000`, read-only.
Cpsr = 11,
/// `CDSR` at offset `0x48`, resets to `0x0000_000F`, read-only.
Cdsr = 12,
/// `L1CR` at offset `0x84`, resets to `0x0000_0000`, read-write.
L1cr = 13,
/// `L1WHPCR` at offset `0x88`, resets to `0x0000_0000`, read-write.
L1whpcr = 14,
/// `L1WVPCR` at offset `0x8C`, resets to `0x0000_0000`, read-write.
L1wvpcr = 15,
/// `L1CKCR` at offset `0x90`, resets to `0x0000_0000`, read-write.
L1ckcr = 16,
/// `L1PFCR` at offset `0x94`, resets to `0x0000_0000`, read-write.
L1pfcr = 17,
/// `L1CACR` at offset `0x98`, resets to `0x0000_0000`, read-write.
L1cacr = 18,
/// `L1DCCR` at offset `0x9C`, resets to `0x0000_0000`, read-write.
L1dccr = 19,
/// `L1BFCR` at offset `0xA0`, resets to `0x0000_0607`, read-write.
L1bfcr = 20,
/// `L1CFBAR` at offset `0xAC`, resets to `0x0000_0000`, read-write.
L1cfbar = 21,
/// `L1CFBLR` at offset `0xB0`, resets to `0x0000_0000`, read-write.
L1cfblr = 22,
/// `L1CFBLNR` at offset `0xB4`, resets to `0x0000_0000`, read-write.
L1cfblnr = 23,
/// `L1CLUTWR` at offset `0xC4`, resets to `0x0000_0000`, write-only.
L1clutwr = 24,
/// `L2CR` at offset `0x104`, resets to `0x0000_0000`, read-write.
L2cr = 25,
/// `L2WHPCR` at offset `0x108`, resets to `0x0000_0000`, read-write.
L2whpcr = 26,
/// `L2WVPCR` at offset `0x10C`, resets to `0x0000_0000`, read-write.
L2wvpcr = 27,
/// `L2CKCR` at offset `0x110`, resets to `0x0000_0000`, read-write.
L2ckcr = 28,
/// `L2PFCR` at offset `0x114`, resets to `0x0000_0000`, read-write.
L2pfcr = 29,
/// `L2CACR` at offset `0x118`, resets to `0x0000_0000`, read-write.
L2cacr = 30,
/// `L2DCCR` at offset `0x11C`, resets to `0x0000_0000`, read-write.
L2dccr = 31,
/// `L2BFCR` at offset `0x120`, resets to `0x0000_0607`, read-write.
L2bfcr = 32,
/// `L2CFBAR` at offset `0x12C`, resets to `0x0000_0000`, read-write.
L2cfbar = 33,
/// `L2CFBLR` at offset `0x130`, resets to `0x0000_0000`, read-write.
L2cfblr = 34,
/// `L2CFBLNR` at offset `0x134`, resets to `0x0000_0000`, read-write.
L2cfblnr = 35,
/// `L2CLUTWR` at offset `0x144`, resets to `0x0000_0000`, write-only.
L2clutwr = 36,
}
impl Register {
/// Every register, in table order.
pub const ALL: [Self; 37] = [Self::Sscr, Self::Bpcr, Self::Awcr, Self::Twcr, Self::Gcr, Self::Srcr, Self::Bccr, Self::Ier, Self::Isr, Self::Icr, Self::Lipcr, Self::Cpsr, Self::Cdsr, Self::L1cr, Self::L1whpcr, Self::L1wvpcr, Self::L1ckcr, Self::L1pfcr, Self::L1cacr, Self::L1dccr, Self::L1bfcr, Self::L1cfbar, Self::L1cfblr, Self::L1cfblnr, Self::L1clutwr, Self::L2cr, Self::L2whpcr, Self::L2wvpcr, Self::L2ckcr, Self::L2pfcr, Self::L2cacr, Self::L2dccr, Self::L2bfcr, Self::L2cfbar, Self::L2cfblr, Self::L2cfblnr, Self::L2clutwr];
}
impl Layout for Register {
const REGISTERS: &'static [RegisterSpec] = ®ISTERS;
fn from_index(index: usize) -> Option<Self> {
Self::ALL.get(index).copied()
}
fn index(self) -> usize {
self as usize
}
}
/// The fields of `SSCR`.
pub mod sscr {
use super::FieldSpec;
/// `VSH`, bits 0..=10.
pub const VSH: &FieldSpec = &super::REGISTERS[0].fields[0];
/// `HSW`, bits 16..=25.
pub const HSW: &FieldSpec = &super::REGISTERS[0].fields[1];
}
/// The fields of `BPCR`.
pub mod bpcr {
use super::FieldSpec;
/// `AVBP`, bits 0..=10.
pub const AVBP: &FieldSpec = &super::REGISTERS[1].fields[0];
/// `AHBP`, bits 16..=27.
pub const AHBP: &FieldSpec = &super::REGISTERS[1].fields[1];
}
/// The fields of `AWCR`.
pub mod awcr {
use super::FieldSpec;
/// `AAH`, bits 0..=10.
pub const AAH: &FieldSpec = &super::REGISTERS[2].fields[0];
/// `AAV`, bits 16..=27.
pub const AAV: &FieldSpec = &super::REGISTERS[2].fields[1];
}
/// The fields of `TWCR`.
pub mod twcr {
use super::FieldSpec;
/// `TOTALH`, bits 0..=10.
pub const TOTALH: &FieldSpec = &super::REGISTERS[3].fields[0];
/// `TOTALW`, bits 16..=27.
pub const TOTALW: &FieldSpec = &super::REGISTERS[3].fields[1];
}
/// The fields of `GCR`.
pub mod gcr {
use super::FieldSpec;
/// `LTDCEN`, bit 0.
pub const LTDCEN: &FieldSpec = &super::REGISTERS[4].fields[0];
/// `DBW`, bits 4..=6, read-only.
pub const DBW: &FieldSpec = &super::REGISTERS[4].fields[1];
/// `DGW`, bits 8..=10, read-only.
pub const DGW: &FieldSpec = &super::REGISTERS[4].fields[2];
/// `DRW`, bits 12..=14, read-only.
pub const DRW: &FieldSpec = &super::REGISTERS[4].fields[3];
/// `DEN`, bit 16.
pub const DEN: &FieldSpec = &super::REGISTERS[4].fields[4];
/// `PCPOL`, bit 28.
pub const PCPOL: &FieldSpec = &super::REGISTERS[4].fields[5];
/// `DEPOL`, bit 29.
pub const DEPOL: &FieldSpec = &super::REGISTERS[4].fields[6];
/// `VSPOL`, bit 30.
pub const VSPOL: &FieldSpec = &super::REGISTERS[4].fields[7];
/// `HSPOL`, bit 31.
pub const HSPOL: &FieldSpec = &super::REGISTERS[4].fields[8];
}
/// The fields of `SRCR`.
pub mod srcr {
use super::FieldSpec;
/// `IMR`, bit 0.
pub const IMR: &FieldSpec = &super::REGISTERS[5].fields[0];
/// `VBR`, bit 1.
pub const VBR: &FieldSpec = &super::REGISTERS[5].fields[1];
}
/// The fields of `BCCR`.
pub mod bccr {
use super::FieldSpec;
/// `BCBLUE`, bits 0..=7.
pub const BCBLUE: &FieldSpec = &super::REGISTERS[6].fields[0];
/// `BCGREEN`, bits 8..=15.
pub const BCGREEN: &FieldSpec = &super::REGISTERS[6].fields[1];
/// `BCRED`, bits 16..=23.
pub const BCRED: &FieldSpec = &super::REGISTERS[6].fields[2];
}
/// The fields of `IER`.
pub mod ier {
use super::FieldSpec;
/// `LIE`, bit 0.
pub const LIE: &FieldSpec = &super::REGISTERS[7].fields[0];
/// `FUIE`, bit 1.
pub const FUIE: &FieldSpec = &super::REGISTERS[7].fields[1];
/// `TERRIE`, bit 2.
pub const TERRIE: &FieldSpec = &super::REGISTERS[7].fields[2];
/// `RRIE`, bit 3.
pub const RRIE: &FieldSpec = &super::REGISTERS[7].fields[3];
}
/// The fields of `ISR`.
pub mod isr {
use super::FieldSpec;
/// `LIF`, bit 0.
pub const LIF: &FieldSpec = &super::REGISTERS[8].fields[0];
/// `FUIF`, bit 1.
pub const FUIF: &FieldSpec = &super::REGISTERS[8].fields[1];
/// `TERRIF`, bit 2.
pub const TERRIF: &FieldSpec = &super::REGISTERS[8].fields[2];
/// `RRIF`, bit 3.
pub const RRIF: &FieldSpec = &super::REGISTERS[8].fields[3];
}
/// The fields of `ICR`.
pub mod icr {
use super::FieldSpec;
/// `CLIF`, bit 0.
pub const CLIF: &FieldSpec = &super::REGISTERS[9].fields[0];
/// `CFUIF`, bit 1.
pub const CFUIF: &FieldSpec = &super::REGISTERS[9].fields[1];
/// `CTERRIF`, bit 2.
pub const CTERRIF: &FieldSpec = &super::REGISTERS[9].fields[2];
/// `CRRIF`, bit 3.
pub const CRRIF: &FieldSpec = &super::REGISTERS[9].fields[3];
}
/// The fields of `LIPCR`.
pub mod lipcr {
use super::FieldSpec;
/// `LIPOS`, bits 0..=10.
pub const LIPOS: &FieldSpec = &super::REGISTERS[10].fields[0];
}
/// The fields of `CPSR`.
pub mod cpsr {
use super::FieldSpec;
/// `CYPOS`, bits 0..=15.
pub const CYPOS: &FieldSpec = &super::REGISTERS[11].fields[0];
/// `CXPOS`, bits 16..=31.
pub const CXPOS: &FieldSpec = &super::REGISTERS[11].fields[1];
}
/// The fields of `CDSR`.
pub mod cdsr {
use super::FieldSpec;
/// `VDES`, bit 0.
pub const VDES: &FieldSpec = &super::REGISTERS[12].fields[0];
/// `HDES`, bit 1.
pub const HDES: &FieldSpec = &super::REGISTERS[12].fields[1];
/// `VSYNCS`, bit 2.
pub const VSYNCS: &FieldSpec = &super::REGISTERS[12].fields[2];
/// `HSYNCS`, bit 3.
pub const HSYNCS: &FieldSpec = &super::REGISTERS[12].fields[3];
}
/// The fields of `L1CR`.
pub mod l1cr {
use super::FieldSpec;
/// `LEN`, bit 0.
pub const LEN: &FieldSpec = &super::REGISTERS[13].fields[0];
/// `COLKEN`, bit 1.
pub const COLKEN: &FieldSpec = &super::REGISTERS[13].fields[1];
/// `CLUTEN`, bit 4.
pub const CLUTEN: &FieldSpec = &super::REGISTERS[13].fields[2];
}
/// The fields of `L1WHPCR`.
pub mod l1whpcr {
use super::FieldSpec;
/// `WHSTPOS`, bits 0..=11.
pub const WHSTPOS: &FieldSpec = &super::REGISTERS[14].fields[0];
/// `WHSPPOS`, bits 16..=27.
pub const WHSPPOS: &FieldSpec = &super::REGISTERS[14].fields[1];
}
/// The fields of `L1WVPCR`.
pub mod l1wvpcr {
use super::FieldSpec;
/// `WVSTPOS`, bits 0..=10.
pub const WVSTPOS: &FieldSpec = &super::REGISTERS[15].fields[0];
/// `WVSPPOS`, bits 16..=26.
pub const WVSPPOS: &FieldSpec = &super::REGISTERS[15].fields[1];
}
/// The fields of `L1CKCR`.
pub mod l1ckcr {
use super::FieldSpec;
/// `CKBLUE`, bits 0..=7.
pub const CKBLUE: &FieldSpec = &super::REGISTERS[16].fields[0];
/// `CKGREEN`, bits 8..=15.
pub const CKGREEN: &FieldSpec = &super::REGISTERS[16].fields[1];
/// `CKRED`, bits 16..=23.
pub const CKRED: &FieldSpec = &super::REGISTERS[16].fields[2];
}
/// The fields of `L1PFCR`.
pub mod l1pfcr {
use super::FieldSpec;
/// `PF`, bits 0..=2.
pub const PF: &FieldSpec = &super::REGISTERS[17].fields[0];
}
/// The fields of `L1CACR`.
pub mod l1cacr {
use super::FieldSpec;
/// `CONSTA`, bits 0..=7.
pub const CONSTA: &FieldSpec = &super::REGISTERS[18].fields[0];
}
/// The fields of `L1DCCR`.
pub mod l1dccr {
use super::FieldSpec;
/// `DCBLUE`, bits 0..=7.
pub const DCBLUE: &FieldSpec = &super::REGISTERS[19].fields[0];
/// `DCGREEN`, bits 8..=15.
pub const DCGREEN: &FieldSpec = &super::REGISTERS[19].fields[1];
/// `DCRED`, bits 16..=23.
pub const DCRED: &FieldSpec = &super::REGISTERS[19].fields[2];
/// `DCALPHA`, bits 24..=31.
pub const DCALPHA: &FieldSpec = &super::REGISTERS[19].fields[3];
}
/// The fields of `L1BFCR`.
pub mod l1bfcr {
use super::FieldSpec;
/// `BF2`, bits 0..=2.
pub const BF2: &FieldSpec = &super::REGISTERS[20].fields[0];
/// `BF1`, bits 8..=10.
pub const BF1: &FieldSpec = &super::REGISTERS[20].fields[1];
}
/// The fields of `L1CFBAR`.
pub mod l1cfbar {
use super::FieldSpec;
/// `CFBADD`, bits 0..=31.
pub const CFBADD: &FieldSpec = &super::REGISTERS[21].fields[0];
}
/// The fields of `L1CFBLR`.
pub mod l1cfblr {
use super::FieldSpec;
/// `CFBLL`, bits 0..=12.
pub const CFBLL: &FieldSpec = &super::REGISTERS[22].fields[0];
/// `CFBP`, bits 16..=28.
pub const CFBP: &FieldSpec = &super::REGISTERS[22].fields[1];
}
/// The fields of `L1CFBLNR`.
pub mod l1cfblnr {
use super::FieldSpec;
/// `CFBLNBR`, bits 0..=10.
pub const CFBLNBR: &FieldSpec = &super::REGISTERS[23].fields[0];
}
/// The fields of `L1CLUTWR`.
pub mod l1clutwr {
use super::FieldSpec;
/// `BLUE`, bits 0..=7.
pub const BLUE: &FieldSpec = &super::REGISTERS[24].fields[0];
/// `GREEN`, bits 8..=15.
pub const GREEN: &FieldSpec = &super::REGISTERS[24].fields[1];
/// `RED`, bits 16..=23.
pub const RED: &FieldSpec = &super::REGISTERS[24].fields[2];
/// `CLUTADD`, bits 24..=31.
pub const CLUTADD: &FieldSpec = &super::REGISTERS[24].fields[3];
}
/// The fields of `L2CR`.
pub mod l2cr {
use super::FieldSpec;
/// `LEN`, bit 0.
pub const LEN: &FieldSpec = &super::REGISTERS[25].fields[0];
/// `COLKEN`, bit 1.
pub const COLKEN: &FieldSpec = &super::REGISTERS[25].fields[1];
/// `CLUTEN`, bit 4.
pub const CLUTEN: &FieldSpec = &super::REGISTERS[25].fields[2];
}
/// The fields of `L2WHPCR`.
pub mod l2whpcr {
use super::FieldSpec;
/// `WHSTPOS`, bits 0..=11.
pub const WHSTPOS: &FieldSpec = &super::REGISTERS[26].fields[0];
/// `WHSPPOS`, bits 16..=27.
pub const WHSPPOS: &FieldSpec = &super::REGISTERS[26].fields[1];
}
/// The fields of `L2WVPCR`.
pub mod l2wvpcr {
use super::FieldSpec;
/// `WVSTPOS`, bits 0..=10.
pub const WVSTPOS: &FieldSpec = &super::REGISTERS[27].fields[0];
/// `WVSPPOS`, bits 16..=26.
pub const WVSPPOS: &FieldSpec = &super::REGISTERS[27].fields[1];
}
/// The fields of `L2CKCR`.
pub mod l2ckcr {
use super::FieldSpec;
/// `CKBLUE`, bits 0..=7.
pub const CKBLUE: &FieldSpec = &super::REGISTERS[28].fields[0];
/// `CKGREEN`, bits 8..=15.
pub const CKGREEN: &FieldSpec = &super::REGISTERS[28].fields[1];
/// `CKRED`, bits 16..=23.
pub const CKRED: &FieldSpec = &super::REGISTERS[28].fields[2];
}
/// The fields of `L2PFCR`.
pub mod l2pfcr {
use super::FieldSpec;
/// `PF`, bits 0..=2.
pub const PF: &FieldSpec = &super::REGISTERS[29].fields[0];
}
/// The fields of `L2CACR`.
pub mod l2cacr {
use super::FieldSpec;
/// `CONSTA`, bits 0..=7.
pub const CONSTA: &FieldSpec = &super::REGISTERS[30].fields[0];
}
/// The fields of `L2DCCR`.
pub mod l2dccr {
use super::FieldSpec;
/// `DCBLUE`, bits 0..=7.
pub const DCBLUE: &FieldSpec = &super::REGISTERS[31].fields[0];
/// `DCGREEN`, bits 8..=15.
pub const DCGREEN: &FieldSpec = &super::REGISTERS[31].fields[1];
/// `DCRED`, bits 16..=23.
pub const DCRED: &FieldSpec = &super::REGISTERS[31].fields[2];
/// `DCALPHA`, bits 24..=31.
pub const DCALPHA: &FieldSpec = &super::REGISTERS[31].fields[3];
}
/// The fields of `L2BFCR`.
pub mod l2bfcr {
use super::FieldSpec;
/// `BF2`, bits 0..=2.
pub const BF2: &FieldSpec = &super::REGISTERS[32].fields[0];
/// `BF1`, bits 8..=10.
pub const BF1: &FieldSpec = &super::REGISTERS[32].fields[1];
}
/// The fields of `L2CFBAR`.
pub mod l2cfbar {
use super::FieldSpec;
/// `CFBADD`, bits 0..=31.
pub const CFBADD: &FieldSpec = &super::REGISTERS[33].fields[0];
}
/// The fields of `L2CFBLR`.
pub mod l2cfblr {
use super::FieldSpec;
/// `CFBLL`, bits 0..=12.
pub const CFBLL: &FieldSpec = &super::REGISTERS[34].fields[0];
/// `CFBP`, bits 16..=28.
pub const CFBP: &FieldSpec = &super::REGISTERS[34].fields[1];
}
/// The fields of `L2CFBLNR`.
pub mod l2cfblnr {
use super::FieldSpec;
/// `CFBLNBR`, bits 0..=10.
pub const CFBLNBR: &FieldSpec = &super::REGISTERS[35].fields[0];
}
/// The fields of `L2CLUTWR`.
pub mod l2clutwr {
use super::FieldSpec;
/// `BLUE`, bits 0..=7.
pub const BLUE: &FieldSpec = &super::REGISTERS[36].fields[0];
/// `GREEN`, bits 8..=15.
pub const GREEN: &FieldSpec = &super::REGISTERS[36].fields[1];
/// `RED`, bits 16..=23.
pub const RED: &FieldSpec = &super::REGISTERS[36].fields[2];
/// `CLUTADD`, bits 24..=31.
pub const CLUTADD: &FieldSpec = &super::REGISTERS[36].fields[3];
}
/// The register table.
pub static REGISTERS: [RegisterSpec; 37] = [
RegisterSpec { name: "SSCR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "VSH", bit: 0, width: 11, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSW", bit: 16, width: 10, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BPCR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "AVBP", bit: 0, width: 11, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "AHBP", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AWCR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "AAH", bit: 0, width: 11, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "AAV", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "TWCR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TOTALH", bit: 0, width: 11, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TOTALW", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "GCR", offset: 0x18, width: Width::W32, reset: 0x0000_2220, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LTDCEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBW", bit: 4, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DGW", bit: 8, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DRW", bit: 12, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PCPOL", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DEPOL", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "VSPOL", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSPOL", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "SRCR", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "IMR", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "VBR", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BCCR", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BCBLUE", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BCGREEN", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BCRED", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "IER", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FUIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TERRIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RRIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "ISR", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LIF", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FUIF", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TERRIF", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RRIF", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "ICR", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CLIF", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CFUIF", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTERRIF", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRRIF", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "LIPCR", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LIPOS", bit: 0, width: 11, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CPSR", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CYPOS", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CXPOS", bit: 16, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CDSR", offset: 0x48, width: Width::W32, reset: 0x0000_000F, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "VDES", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HDES", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "VSYNCS", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSYNCS", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L1CR", offset: 0x84, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "COLKEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLUTEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L1WHPCR", offset: 0x88, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "WHSTPOS", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WHSPPOS", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L1WVPCR", offset: 0x8C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "WVSTPOS", bit: 0, width: 11, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WVSPPOS", bit: 16, width: 11, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L1CKCR", offset: 0x90, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CKBLUE", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CKGREEN", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CKRED", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L1PFCR", offset: 0x94, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "PF", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L1CACR", offset: 0x98, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CONSTA", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L1DCCR", offset: 0x9C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DCBLUE", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DCGREEN", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DCRED", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DCALPHA", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L1BFCR", offset: 0xA0, width: Width::W32, reset: 0x0000_0607, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BF2", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BF1", bit: 8, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L1CFBAR", offset: 0xAC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CFBADD", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L1CFBLR", offset: 0xB0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CFBLL", bit: 0, width: 13, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CFBP", bit: 16, width: 13, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L1CFBLNR", offset: 0xB4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CFBLNBR", bit: 0, width: 11, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L1CLUTWR", offset: 0xC4, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BLUE", bit: 0, width: 8, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GREEN", bit: 8, width: 8, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RED", bit: 16, width: 8, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLUTADD", bit: 24, width: 8, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L2CR", offset: 0x104, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "COLKEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLUTEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L2WHPCR", offset: 0x108, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "WHSTPOS", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WHSPPOS", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L2WVPCR", offset: 0x10C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "WVSTPOS", bit: 0, width: 11, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WVSPPOS", bit: 16, width: 11, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L2CKCR", offset: 0x110, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CKBLUE", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CKGREEN", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CKRED", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L2PFCR", offset: 0x114, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "PF", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L2CACR", offset: 0x118, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CONSTA", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L2DCCR", offset: 0x11C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DCBLUE", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DCGREEN", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DCRED", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DCALPHA", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L2BFCR", offset: 0x120, width: Width::W32, reset: 0x0000_0607, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BF2", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BF1", bit: 8, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L2CFBAR", offset: 0x12C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CFBADD", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L2CFBLR", offset: 0x130, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CFBLL", bit: 0, width: 13, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CFBP", bit: 16, width: 13, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L2CFBLNR", offset: 0x134, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CFBLNBR", bit: 0, width: 11, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "L2CLUTWR", offset: 0x144, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BLUE", bit: 0, width: 8, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GREEN", bit: 8, width: 8, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RED", bit: 16, width: 8, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLUTADD", bit: 24, width: 8, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
];