rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `CEC` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr = 0,
    /// `CFGR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Cfgr = 1,
    /// `TXDR` at offset `0x8`, resets to `0x0000_0000`, write-only.
    Txdr = 2,
    /// `RXDR` at offset `0xC`, resets to `0x0000_0000`, read-only.
    Rxdr = 3,
    /// `ISR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Isr = 4,
    /// `IER` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Ier = 5,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 6] = [Self::Cr, Self::Cfgr, Self::Txdr, Self::Rxdr, Self::Isr, Self::Ier];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `CECEN`, bit 0.
    pub const CECEN: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `TXSOM`, bit 1.
    pub const TXSOM: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `TXEOM`, bit 2.
    pub const TXEOM: &FieldSpec = &super::REGISTERS[0].fields[2];
}

/// The fields of `CFGR`.
pub mod cfgr {
    use super::FieldSpec;
    /// `SFT`, bits 0..=2.
    pub const SFT: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `RXTOL`, bit 3.
    pub const RXTOL: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `BRESTP`, bit 4.
    pub const BRESTP: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `BREGEN`, bit 5.
    pub const BREGEN: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `LBPEGEN`, bit 6.
    pub const LBPEGEN: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `BRDNOGEN`, bit 7.
    pub const BRDNOGEN: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `SFTOPT`, bit 8.
    pub const SFTOPT: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `OAR`, bits 16..=30.
    pub const OAR: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `LSTN`, bit 31.
    pub const LSTN: &FieldSpec = &super::REGISTERS[1].fields[8];
}

/// The fields of `TXDR`.
pub mod txdr {
    use super::FieldSpec;
    /// `TXD`, bits 0..=7.
    pub const TXD: &FieldSpec = &super::REGISTERS[2].fields[0];
}

/// The fields of `RXDR`.
pub mod rxdr {
    use super::FieldSpec;
    /// `RXD`, bits 0..=7.
    pub const RXD: &FieldSpec = &super::REGISTERS[3].fields[0];
}

/// The fields of `ISR`.
pub mod isr {
    use super::FieldSpec;
    /// `RXBR`, bit 0.
    pub const RXBR: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `RXEND`, bit 1.
    pub const RXEND: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `RXOVR`, bit 2.
    pub const RXOVR: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `BRE`, bit 3.
    pub const BRE: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `SBPE`, bit 4.
    pub const SBPE: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `LBPE`, bit 5.
    pub const LBPE: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `RXACKE`, bit 6.
    pub const RXACKE: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `ARBLST`, bit 7.
    pub const ARBLST: &FieldSpec = &super::REGISTERS[4].fields[7];
    /// `TXBR`, bit 8.
    pub const TXBR: &FieldSpec = &super::REGISTERS[4].fields[8];
    /// `TXEND`, bit 9.
    pub const TXEND: &FieldSpec = &super::REGISTERS[4].fields[9];
    /// `TXUDR`, bit 10.
    pub const TXUDR: &FieldSpec = &super::REGISTERS[4].fields[10];
    /// `TXERR`, bit 11.
    pub const TXERR: &FieldSpec = &super::REGISTERS[4].fields[11];
    /// `TXACKE`, bit 12.
    pub const TXACKE: &FieldSpec = &super::REGISTERS[4].fields[12];
}

/// The fields of `IER`.
pub mod ier {
    use super::FieldSpec;
    /// `RXBRIE`, bit 0.
    pub const RXBRIE: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `RXENDIE`, bit 1.
    pub const RXENDIE: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `RXOVRIE`, bit 2.
    pub const RXOVRIE: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `BREIE`, bit 3.
    pub const BREIE: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `SBPEIE`, bit 4.
    pub const SBPEIE: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `LBPEIE`, bit 5.
    pub const LBPEIE: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `RXACKIE`, bit 6.
    pub const RXACKIE: &FieldSpec = &super::REGISTERS[5].fields[6];
    /// `ARBLSTIE`, bit 7.
    pub const ARBLSTIE: &FieldSpec = &super::REGISTERS[5].fields[7];
    /// `TXBRIE`, bit 8.
    pub const TXBRIE: &FieldSpec = &super::REGISTERS[5].fields[8];
    /// `TXENDIE`, bit 9.
    pub const TXENDIE: &FieldSpec = &super::REGISTERS[5].fields[9];
    /// `TXUDRIE`, bit 10.
    pub const TXUDRIE: &FieldSpec = &super::REGISTERS[5].fields[10];
    /// `TXERRIE`, bit 11.
    pub const TXERRIE: &FieldSpec = &super::REGISTERS[5].fields[11];
    /// `TXACKIE`, bit 12.
    pub const TXACKIE: &FieldSpec = &super::REGISTERS[5].fields[12];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 6] = [
    RegisterSpec { name: "CR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CECEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXSOM", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXEOM", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CFGR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SFT", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXTOL", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BRESTP", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BREGEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LBPEGEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BRDNOGEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SFTOPT", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OAR", bit: 16, width: 15, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSTN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TXDR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TXD", bit: 0, width: 8, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RXDR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXD", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ISR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXBR", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXEND", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXOVR", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BRE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SBPE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LBPE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXACKE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARBLST", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXBR", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXEND", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXUDR", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXERR", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXACKE", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IER", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXBRIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXENDIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXOVRIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BREIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SBPEIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LBPEIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXACKIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARBLSTIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXBRIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXENDIE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXUDRIE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXERRIE", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXACKIE", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];