rigless 0.3.0

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `BDMA` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `BDMA_ISR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    BdmaIsr = 0,
    /// `BDMA_IFCR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    BdmaIfcr = 1,
    /// `BDMA_CCR0` at offset `0x8`, resets to `0x0000_0000`, read-write.
    BdmaCcr0 = 2,
    /// `BDMA_CNDTR0` at offset `0xC`, resets to `0x0000_0000`, read-write.
    BdmaCndtr0 = 3,
    /// `BDMA_CPAR0` at offset `0x10`, resets to `0x0000_0000`, read-write.
    BdmaCpar0 = 4,
    /// `BDMA_CM0AR0` at offset `0x14`, resets to `0x0000_0000`, read-write.
    BdmaCm0ar0 = 5,
    /// `BDMA_CM1AR0` at offset `0x18`, resets to `0x0000_0000`, read-write.
    BdmaCm1ar0 = 6,
    /// `BDMA_CCR1` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    BdmaCcr1 = 7,
    /// `BDMA_CNDTR1` at offset `0x20`, resets to `0x0000_0000`, read-write.
    BdmaCndtr1 = 8,
    /// `BDMA_CPAR1` at offset `0x24`, resets to `0x0000_0000`, read-write.
    BdmaCpar1 = 9,
    /// `BDMA_CM0AR1` at offset `0x28`, resets to `0x0000_0000`, read-write.
    BdmaCm0ar1 = 10,
    /// `BDMA_CM1AR1` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    BdmaCm1ar1 = 11,
    /// `BDMA_CCR2` at offset `0x30`, resets to `0x0000_0000`, read-write.
    BdmaCcr2 = 12,
    /// `BDMA_CNDTR2` at offset `0x34`, resets to `0x0000_0000`, read-write.
    BdmaCndtr2 = 13,
    /// `BDMA_CPAR2` at offset `0x38`, resets to `0x0000_0000`, read-write.
    BdmaCpar2 = 14,
    /// `BDMA_CM0AR2` at offset `0x3C`, resets to `0x0000_0000`, read-write.
    BdmaCm0ar2 = 15,
    /// `BDMA_CM1AR2` at offset `0x40`, resets to `0x0000_0000`, read-write.
    BdmaCm1ar2 = 16,
    /// `BDMA_CCR3` at offset `0x44`, resets to `0x0000_0000`, read-write.
    BdmaCcr3 = 17,
    /// `BDMA_CNDTR3` at offset `0x48`, resets to `0x0000_0000`, read-write.
    BdmaCndtr3 = 18,
    /// `BDMA_CPAR3` at offset `0x4C`, resets to `0x0000_0000`, read-write.
    BdmaCpar3 = 19,
    /// `BDMA_CM0AR3` at offset `0x50`, resets to `0x0000_0000`, read-write.
    BdmaCm0ar3 = 20,
    /// `BDMA_CM1AR3` at offset `0x54`, resets to `0x0000_0000`, read-write.
    BdmaCm1ar3 = 21,
    /// `BDMA_CCR4` at offset `0x58`, resets to `0x0000_0000`, read-write.
    BdmaCcr4 = 22,
    /// `BDMA_CNDTR4` at offset `0x5C`, resets to `0x0000_0000`, read-write.
    BdmaCndtr4 = 23,
    /// `BDMA_CPAR4` at offset `0x60`, resets to `0x0000_0000`, read-write.
    BdmaCpar4 = 24,
    /// `BDMA_CM0AR4` at offset `0x64`, resets to `0x0000_0000`, read-write.
    BdmaCm0ar4 = 25,
    /// `BDMA_CM1AR4` at offset `0x68`, resets to `0x0000_0000`, read-write.
    BdmaCm1ar4 = 26,
    /// `BDMA_CCR5` at offset `0x6C`, resets to `0x0000_0000`, read-write.
    BdmaCcr5 = 27,
    /// `BDMA_CNDTR5` at offset `0x70`, resets to `0x0000_0000`, read-write.
    BdmaCndtr5 = 28,
    /// `BDMA_CPAR5` at offset `0x74`, resets to `0x0000_0000`, read-write.
    BdmaCpar5 = 29,
    /// `BDMA_CM0AR5` at offset `0x78`, resets to `0x0000_0000`, read-write.
    BdmaCm0ar5 = 30,
    /// `BDMA_CM1AR5` at offset `0x7C`, resets to `0x0000_0000`, read-write.
    BdmaCm1ar5 = 31,
    /// `BDMA_CCR6` at offset `0x80`, resets to `0x0000_0000`, read-write.
    BdmaCcr6 = 32,
    /// `BDMA_CNDTR6` at offset `0x84`, resets to `0x0000_0000`, read-write.
    BdmaCndtr6 = 33,
    /// `BDMA_CPAR6` at offset `0x88`, resets to `0x0000_0000`, read-write.
    BdmaCpar6 = 34,
    /// `BDMA_CM0AR6` at offset `0x8C`, resets to `0x0000_0000`, read-write.
    BdmaCm0ar6 = 35,
    /// `BDMA_CM1AR6` at offset `0x90`, resets to `0x0000_0000`, read-write.
    BdmaCm1ar6 = 36,
    /// `BDMA_CCR7` at offset `0x94`, resets to `0x0000_0000`, read-write.
    BdmaCcr7 = 37,
    /// `BDMA_CNDTR7` at offset `0x98`, resets to `0x0000_0000`, read-write.
    BdmaCndtr7 = 38,
    /// `BDMA_CPAR7` at offset `0x9C`, resets to `0x0000_0000`, read-write.
    BdmaCpar7 = 39,
    /// `BDMA_CM0AR7` at offset `0xA0`, resets to `0x0000_0000`, read-write.
    BdmaCm0ar7 = 40,
    /// `BDMA_CM1AR7` at offset `0xA4`, resets to `0x0000_0000`, read-write.
    BdmaCm1ar7 = 41,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 42] = [Self::BdmaIsr, Self::BdmaIfcr, Self::BdmaCcr0, Self::BdmaCndtr0, Self::BdmaCpar0, Self::BdmaCm0ar0, Self::BdmaCm1ar0, Self::BdmaCcr1, Self::BdmaCndtr1, Self::BdmaCpar1, Self::BdmaCm0ar1, Self::BdmaCm1ar1, Self::BdmaCcr2, Self::BdmaCndtr2, Self::BdmaCpar2, Self::BdmaCm0ar2, Self::BdmaCm1ar2, Self::BdmaCcr3, Self::BdmaCndtr3, Self::BdmaCpar3, Self::BdmaCm0ar3, Self::BdmaCm1ar3, Self::BdmaCcr4, Self::BdmaCndtr4, Self::BdmaCpar4, Self::BdmaCm0ar4, Self::BdmaCm1ar4, Self::BdmaCcr5, Self::BdmaCndtr5, Self::BdmaCpar5, Self::BdmaCm0ar5, Self::BdmaCm1ar5, Self::BdmaCcr6, Self::BdmaCndtr6, Self::BdmaCpar6, Self::BdmaCm0ar6, Self::BdmaCm1ar6, Self::BdmaCcr7, Self::BdmaCndtr7, Self::BdmaCpar7, Self::BdmaCm0ar7, Self::BdmaCm1ar7];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `BDMA_ISR`.
pub mod bdma_isr {
    use super::FieldSpec;
    /// `GIF0`, bit 0, read-only.
    pub const GIF0: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `TCIF0`, bit 1, read-only.
    pub const TCIF0: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `HTIF0`, bit 2, read-only.
    pub const HTIF0: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `TEIF0`, bit 3, read-only.
    pub const TEIF0: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `GIF1`, bit 4, read-only.
    pub const GIF1: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `TCIF1`, bit 5, read-only.
    pub const TCIF1: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `HTIF1`, bit 6, read-only.
    pub const HTIF1: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `TEIF1`, bit 7, read-only.
    pub const TEIF1: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `GIF2`, bit 8, read-only.
    pub const GIF2: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `TCIF2`, bit 9, read-only.
    pub const TCIF2: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `HTIF2`, bit 10, read-only.
    pub const HTIF2: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `TEIF2`, bit 11, read-only.
    pub const TEIF2: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `GIF3`, bit 12, read-only.
    pub const GIF3: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `TCIF3`, bit 13, read-only.
    pub const TCIF3: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `HTIF3`, bit 14, read-only.
    pub const HTIF3: &FieldSpec = &super::REGISTERS[0].fields[14];
    /// `TEIF3`, bit 15, read-only.
    pub const TEIF3: &FieldSpec = &super::REGISTERS[0].fields[15];
    /// `GIF4`, bit 16, read-only.
    pub const GIF4: &FieldSpec = &super::REGISTERS[0].fields[16];
    /// `TCIF4`, bit 17, read-only.
    pub const TCIF4: &FieldSpec = &super::REGISTERS[0].fields[17];
    /// `HTIF4`, bit 18, read-only.
    pub const HTIF4: &FieldSpec = &super::REGISTERS[0].fields[18];
    /// `TEIF4`, bit 19, read-only.
    pub const TEIF4: &FieldSpec = &super::REGISTERS[0].fields[19];
    /// `GIF5`, bit 20, read-only.
    pub const GIF5: &FieldSpec = &super::REGISTERS[0].fields[20];
    /// `TCIF5`, bit 21, read-only.
    pub const TCIF5: &FieldSpec = &super::REGISTERS[0].fields[21];
    /// `HTIF5`, bit 22, read-only.
    pub const HTIF5: &FieldSpec = &super::REGISTERS[0].fields[22];
    /// `TEIF5`, bit 23, read-only.
    pub const TEIF5: &FieldSpec = &super::REGISTERS[0].fields[23];
    /// `GIF6`, bit 24, read-only.
    pub const GIF6: &FieldSpec = &super::REGISTERS[0].fields[24];
    /// `TCIF6`, bit 25, read-only.
    pub const TCIF6: &FieldSpec = &super::REGISTERS[0].fields[25];
    /// `HTIF6`, bit 26, read-only.
    pub const HTIF6: &FieldSpec = &super::REGISTERS[0].fields[26];
    /// `TEIF6`, bit 27, read-only.
    pub const TEIF6: &FieldSpec = &super::REGISTERS[0].fields[27];
    /// `GIF7`, bit 28, read-only.
    pub const GIF7: &FieldSpec = &super::REGISTERS[0].fields[28];
    /// `TCIF7`, bit 29, read-only.
    pub const TCIF7: &FieldSpec = &super::REGISTERS[0].fields[29];
    /// `HTIF7`, bit 30, read-only.
    pub const HTIF7: &FieldSpec = &super::REGISTERS[0].fields[30];
    /// `TEIF7`, bit 31, read-only.
    pub const TEIF7: &FieldSpec = &super::REGISTERS[0].fields[31];
}

/// The fields of `BDMA_IFCR`.
pub mod bdma_ifcr {
    use super::FieldSpec;
    /// `CGIF0`, bit 0, write-only.
    pub const CGIF0: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `CTCIF0`, bit 1, write-only.
    pub const CTCIF0: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `CHTIF0`, bit 2, write-only.
    pub const CHTIF0: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `CTEIF0`, bit 3, write-only.
    pub const CTEIF0: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `CGIF1`, bit 4, write-only.
    pub const CGIF1: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `CTCIF1`, bit 5, write-only.
    pub const CTCIF1: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `CHTIF1`, bit 6, write-only.
    pub const CHTIF1: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `CTEIF1`, bit 7, write-only.
    pub const CTEIF1: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `CGIF2`, bit 8, write-only.
    pub const CGIF2: &FieldSpec = &super::REGISTERS[1].fields[8];
    /// `CTCIF2`, bit 9, write-only.
    pub const CTCIF2: &FieldSpec = &super::REGISTERS[1].fields[9];
    /// `CHTIF2`, bit 10, write-only.
    pub const CHTIF2: &FieldSpec = &super::REGISTERS[1].fields[10];
    /// `CTEIF2`, bit 11, write-only.
    pub const CTEIF2: &FieldSpec = &super::REGISTERS[1].fields[11];
    /// `CGIF3`, bit 12, write-only.
    pub const CGIF3: &FieldSpec = &super::REGISTERS[1].fields[12];
    /// `CTCIF3`, bit 13, write-only.
    pub const CTCIF3: &FieldSpec = &super::REGISTERS[1].fields[13];
    /// `CHTIF3`, bit 14, write-only.
    pub const CHTIF3: &FieldSpec = &super::REGISTERS[1].fields[14];
    /// `CTEIF3`, bit 15, write-only.
    pub const CTEIF3: &FieldSpec = &super::REGISTERS[1].fields[15];
    /// `CGIF4`, bit 16, write-only.
    pub const CGIF4: &FieldSpec = &super::REGISTERS[1].fields[16];
    /// `CTCIF4`, bit 17, write-only.
    pub const CTCIF4: &FieldSpec = &super::REGISTERS[1].fields[17];
    /// `CHTIF4`, bit 18, write-only.
    pub const CHTIF4: &FieldSpec = &super::REGISTERS[1].fields[18];
    /// `CTEIF4`, bit 19, write-only.
    pub const CTEIF4: &FieldSpec = &super::REGISTERS[1].fields[19];
    /// `CGIF5`, bit 20, write-only.
    pub const CGIF5: &FieldSpec = &super::REGISTERS[1].fields[20];
    /// `CTCIF5`, bit 21, write-only.
    pub const CTCIF5: &FieldSpec = &super::REGISTERS[1].fields[21];
    /// `CHTIF5`, bit 22, write-only.
    pub const CHTIF5: &FieldSpec = &super::REGISTERS[1].fields[22];
    /// `CTEIF5`, bit 23, write-only.
    pub const CTEIF5: &FieldSpec = &super::REGISTERS[1].fields[23];
    /// `CGIF6`, bit 24, write-only.
    pub const CGIF6: &FieldSpec = &super::REGISTERS[1].fields[24];
    /// `CTCIF6`, bit 25, write-only.
    pub const CTCIF6: &FieldSpec = &super::REGISTERS[1].fields[25];
    /// `CHTIF6`, bit 26, write-only.
    pub const CHTIF6: &FieldSpec = &super::REGISTERS[1].fields[26];
    /// `CTEIF6`, bit 27, write-only.
    pub const CTEIF6: &FieldSpec = &super::REGISTERS[1].fields[27];
    /// `CGIF7`, bit 28, write-only.
    pub const CGIF7: &FieldSpec = &super::REGISTERS[1].fields[28];
    /// `CTCIF7`, bit 29, write-only.
    pub const CTCIF7: &FieldSpec = &super::REGISTERS[1].fields[29];
    /// `CHTIF7`, bit 30, write-only.
    pub const CHTIF7: &FieldSpec = &super::REGISTERS[1].fields[30];
    /// `CTEIF7`, bit 31, write-only.
    pub const CTEIF7: &FieldSpec = &super::REGISTERS[1].fields[31];
}

/// The fields of `BDMA_CCR0`.
pub mod bdma_ccr0 {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `TCIE`, bit 1.
    pub const TCIE: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `HTIE`, bit 2.
    pub const HTIE: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `TEIE`, bit 3.
    pub const TEIE: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `DIR`, bit 4.
    pub const DIR: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `CIRC`, bit 5.
    pub const CIRC: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `PINC`, bit 6.
    pub const PINC: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `MINC`, bit 7.
    pub const MINC: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `PSIZE`, bits 8..=9.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[2].fields[8];
    /// `MSIZE`, bits 10..=11.
    pub const MSIZE: &FieldSpec = &super::REGISTERS[2].fields[9];
    /// `PL`, bits 12..=13.
    pub const PL: &FieldSpec = &super::REGISTERS[2].fields[10];
    /// `MEM2MEM`, bit 14.
    pub const MEM2MEM: &FieldSpec = &super::REGISTERS[2].fields[11];
    /// `DBM`, bit 15.
    pub const DBM: &FieldSpec = &super::REGISTERS[2].fields[12];
    /// `CT`, bit 16.
    pub const CT: &FieldSpec = &super::REGISTERS[2].fields[13];
}

/// The fields of `BDMA_CNDTR0`.
pub mod bdma_cndtr0 {
    use super::FieldSpec;
    /// `NDT`, bits 0..=15.
    pub const NDT: &FieldSpec = &super::REGISTERS[3].fields[0];
}

/// The fields of `BDMA_CPAR0`.
pub mod bdma_cpar0 {
    use super::FieldSpec;
    /// `PA`, bits 0..=31.
    pub const PA: &FieldSpec = &super::REGISTERS[4].fields[0];
}

/// The fields of `BDMA_CM0AR0`.
pub mod bdma_cm0ar0 {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[5].fields[0];
}

/// The fields of `BDMA_CM1AR0`.
pub mod bdma_cm1ar0 {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `BDMA_CCR1`.
pub mod bdma_ccr1 {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `TCIE`, bit 1.
    pub const TCIE: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `HTIE`, bit 2.
    pub const HTIE: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `TEIE`, bit 3.
    pub const TEIE: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `DIR`, bit 4.
    pub const DIR: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `CIRC`, bit 5.
    pub const CIRC: &FieldSpec = &super::REGISTERS[7].fields[5];
    /// `PINC`, bit 6.
    pub const PINC: &FieldSpec = &super::REGISTERS[7].fields[6];
    /// `MINC`, bit 7.
    pub const MINC: &FieldSpec = &super::REGISTERS[7].fields[7];
    /// `PSIZE`, bits 8..=9.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[7].fields[8];
    /// `MSIZE`, bits 10..=11.
    pub const MSIZE: &FieldSpec = &super::REGISTERS[7].fields[9];
    /// `PL`, bits 12..=13.
    pub const PL: &FieldSpec = &super::REGISTERS[7].fields[10];
    /// `MEM2MEM`, bit 14.
    pub const MEM2MEM: &FieldSpec = &super::REGISTERS[7].fields[11];
    /// `DBM`, bit 15.
    pub const DBM: &FieldSpec = &super::REGISTERS[7].fields[12];
    /// `CT`, bit 16.
    pub const CT: &FieldSpec = &super::REGISTERS[7].fields[13];
}

/// The fields of `BDMA_CNDTR1`.
pub mod bdma_cndtr1 {
    use super::FieldSpec;
    /// `NDT`, bits 0..=15.
    pub const NDT: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The fields of `BDMA_CPAR1`.
pub mod bdma_cpar1 {
    use super::FieldSpec;
    /// `PA`, bits 0..=31.
    pub const PA: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `BDMA_CM0AR1`.
pub mod bdma_cm0ar1 {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The fields of `BDMA_CM1AR1`.
pub mod bdma_cm1ar1 {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The fields of `BDMA_CCR2`.
pub mod bdma_ccr2 {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[12].fields[0];
    /// `TCIE`, bit 1.
    pub const TCIE: &FieldSpec = &super::REGISTERS[12].fields[1];
    /// `HTIE`, bit 2.
    pub const HTIE: &FieldSpec = &super::REGISTERS[12].fields[2];
    /// `TEIE`, bit 3.
    pub const TEIE: &FieldSpec = &super::REGISTERS[12].fields[3];
    /// `DIR`, bit 4.
    pub const DIR: &FieldSpec = &super::REGISTERS[12].fields[4];
    /// `CIRC`, bit 5.
    pub const CIRC: &FieldSpec = &super::REGISTERS[12].fields[5];
    /// `PINC`, bit 6.
    pub const PINC: &FieldSpec = &super::REGISTERS[12].fields[6];
    /// `MINC`, bit 7.
    pub const MINC: &FieldSpec = &super::REGISTERS[12].fields[7];
    /// `PSIZE`, bits 8..=9.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[12].fields[8];
    /// `MSIZE`, bits 10..=11.
    pub const MSIZE: &FieldSpec = &super::REGISTERS[12].fields[9];
    /// `PL`, bits 12..=13.
    pub const PL: &FieldSpec = &super::REGISTERS[12].fields[10];
    /// `MEM2MEM`, bit 14.
    pub const MEM2MEM: &FieldSpec = &super::REGISTERS[12].fields[11];
    /// `DBM`, bit 15.
    pub const DBM: &FieldSpec = &super::REGISTERS[12].fields[12];
    /// `CT`, bit 16.
    pub const CT: &FieldSpec = &super::REGISTERS[12].fields[13];
}

/// The fields of `BDMA_CNDTR2`.
pub mod bdma_cndtr2 {
    use super::FieldSpec;
    /// `NDT`, bits 0..=15.
    pub const NDT: &FieldSpec = &super::REGISTERS[13].fields[0];
}

/// The fields of `BDMA_CPAR2`.
pub mod bdma_cpar2 {
    use super::FieldSpec;
    /// `PA`, bits 0..=31.
    pub const PA: &FieldSpec = &super::REGISTERS[14].fields[0];
}

/// The fields of `BDMA_CM0AR2`.
pub mod bdma_cm0ar2 {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[15].fields[0];
}

/// The fields of `BDMA_CM1AR2`.
pub mod bdma_cm1ar2 {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[16].fields[0];
}

/// The fields of `BDMA_CCR3`.
pub mod bdma_ccr3 {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[17].fields[0];
    /// `TCIE`, bit 1.
    pub const TCIE: &FieldSpec = &super::REGISTERS[17].fields[1];
    /// `HTIE`, bit 2.
    pub const HTIE: &FieldSpec = &super::REGISTERS[17].fields[2];
    /// `TEIE`, bit 3.
    pub const TEIE: &FieldSpec = &super::REGISTERS[17].fields[3];
    /// `DIR`, bit 4.
    pub const DIR: &FieldSpec = &super::REGISTERS[17].fields[4];
    /// `CIRC`, bit 5.
    pub const CIRC: &FieldSpec = &super::REGISTERS[17].fields[5];
    /// `PINC`, bit 6.
    pub const PINC: &FieldSpec = &super::REGISTERS[17].fields[6];
    /// `MINC`, bit 7.
    pub const MINC: &FieldSpec = &super::REGISTERS[17].fields[7];
    /// `PSIZE`, bits 8..=9.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[17].fields[8];
    /// `MSIZE`, bits 10..=11.
    pub const MSIZE: &FieldSpec = &super::REGISTERS[17].fields[9];
    /// `PL`, bits 12..=13.
    pub const PL: &FieldSpec = &super::REGISTERS[17].fields[10];
    /// `MEM2MEM`, bit 14.
    pub const MEM2MEM: &FieldSpec = &super::REGISTERS[17].fields[11];
    /// `DBM`, bit 15.
    pub const DBM: &FieldSpec = &super::REGISTERS[17].fields[12];
    /// `CT`, bit 16.
    pub const CT: &FieldSpec = &super::REGISTERS[17].fields[13];
}

/// The fields of `BDMA_CNDTR3`.
pub mod bdma_cndtr3 {
    use super::FieldSpec;
    /// `NDT`, bits 0..=15.
    pub const NDT: &FieldSpec = &super::REGISTERS[18].fields[0];
}

/// The fields of `BDMA_CPAR3`.
pub mod bdma_cpar3 {
    use super::FieldSpec;
    /// `PA`, bits 0..=31.
    pub const PA: &FieldSpec = &super::REGISTERS[19].fields[0];
}

/// The fields of `BDMA_CM0AR3`.
pub mod bdma_cm0ar3 {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[20].fields[0];
}

/// The fields of `BDMA_CM1AR3`.
pub mod bdma_cm1ar3 {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[21].fields[0];
}

/// The fields of `BDMA_CCR4`.
pub mod bdma_ccr4 {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[22].fields[0];
    /// `TCIE`, bit 1.
    pub const TCIE: &FieldSpec = &super::REGISTERS[22].fields[1];
    /// `HTIE`, bit 2.
    pub const HTIE: &FieldSpec = &super::REGISTERS[22].fields[2];
    /// `TEIE`, bit 3.
    pub const TEIE: &FieldSpec = &super::REGISTERS[22].fields[3];
    /// `DIR`, bit 4.
    pub const DIR: &FieldSpec = &super::REGISTERS[22].fields[4];
    /// `CIRC`, bit 5.
    pub const CIRC: &FieldSpec = &super::REGISTERS[22].fields[5];
    /// `PINC`, bit 6.
    pub const PINC: &FieldSpec = &super::REGISTERS[22].fields[6];
    /// `MINC`, bit 7.
    pub const MINC: &FieldSpec = &super::REGISTERS[22].fields[7];
    /// `PSIZE`, bits 8..=9.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[22].fields[8];
    /// `MSIZE`, bits 10..=11.
    pub const MSIZE: &FieldSpec = &super::REGISTERS[22].fields[9];
    /// `PL`, bits 12..=13.
    pub const PL: &FieldSpec = &super::REGISTERS[22].fields[10];
    /// `MEM2MEM`, bit 14.
    pub const MEM2MEM: &FieldSpec = &super::REGISTERS[22].fields[11];
    /// `DBM`, bit 15.
    pub const DBM: &FieldSpec = &super::REGISTERS[22].fields[12];
    /// `CT`, bit 16.
    pub const CT: &FieldSpec = &super::REGISTERS[22].fields[13];
}

/// The fields of `BDMA_CNDTR4`.
pub mod bdma_cndtr4 {
    use super::FieldSpec;
    /// `NDT`, bits 0..=15.
    pub const NDT: &FieldSpec = &super::REGISTERS[23].fields[0];
}

/// The fields of `BDMA_CPAR4`.
pub mod bdma_cpar4 {
    use super::FieldSpec;
    /// `PA`, bits 0..=31.
    pub const PA: &FieldSpec = &super::REGISTERS[24].fields[0];
}

/// The fields of `BDMA_CM0AR4`.
pub mod bdma_cm0ar4 {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[25].fields[0];
}

/// The fields of `BDMA_CM1AR4`.
pub mod bdma_cm1ar4 {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[26].fields[0];
}

/// The fields of `BDMA_CCR5`.
pub mod bdma_ccr5 {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[27].fields[0];
    /// `TCIE`, bit 1.
    pub const TCIE: &FieldSpec = &super::REGISTERS[27].fields[1];
    /// `HTIE`, bit 2.
    pub const HTIE: &FieldSpec = &super::REGISTERS[27].fields[2];
    /// `TEIE`, bit 3.
    pub const TEIE: &FieldSpec = &super::REGISTERS[27].fields[3];
    /// `DIR`, bit 4.
    pub const DIR: &FieldSpec = &super::REGISTERS[27].fields[4];
    /// `CIRC`, bit 5.
    pub const CIRC: &FieldSpec = &super::REGISTERS[27].fields[5];
    /// `PINC`, bit 6.
    pub const PINC: &FieldSpec = &super::REGISTERS[27].fields[6];
    /// `MINC`, bit 7.
    pub const MINC: &FieldSpec = &super::REGISTERS[27].fields[7];
    /// `PSIZE`, bits 8..=9.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[27].fields[8];
    /// `MSIZE`, bits 10..=11.
    pub const MSIZE: &FieldSpec = &super::REGISTERS[27].fields[9];
    /// `PL`, bits 12..=13.
    pub const PL: &FieldSpec = &super::REGISTERS[27].fields[10];
    /// `MEM2MEM`, bit 14.
    pub const MEM2MEM: &FieldSpec = &super::REGISTERS[27].fields[11];
    /// `DBM`, bit 15.
    pub const DBM: &FieldSpec = &super::REGISTERS[27].fields[12];
    /// `CT`, bit 16.
    pub const CT: &FieldSpec = &super::REGISTERS[27].fields[13];
}

/// The fields of `BDMA_CNDTR5`.
pub mod bdma_cndtr5 {
    use super::FieldSpec;
    /// `NDT`, bits 0..=15.
    pub const NDT: &FieldSpec = &super::REGISTERS[28].fields[0];
}

/// The fields of `BDMA_CPAR5`.
pub mod bdma_cpar5 {
    use super::FieldSpec;
    /// `PA`, bits 0..=31.
    pub const PA: &FieldSpec = &super::REGISTERS[29].fields[0];
}

/// The fields of `BDMA_CM0AR5`.
pub mod bdma_cm0ar5 {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[30].fields[0];
}

/// The fields of `BDMA_CM1AR5`.
pub mod bdma_cm1ar5 {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[31].fields[0];
}

/// The fields of `BDMA_CCR6`.
pub mod bdma_ccr6 {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[32].fields[0];
    /// `TCIE`, bit 1.
    pub const TCIE: &FieldSpec = &super::REGISTERS[32].fields[1];
    /// `HTIE`, bit 2.
    pub const HTIE: &FieldSpec = &super::REGISTERS[32].fields[2];
    /// `TEIE`, bit 3.
    pub const TEIE: &FieldSpec = &super::REGISTERS[32].fields[3];
    /// `DIR`, bit 4.
    pub const DIR: &FieldSpec = &super::REGISTERS[32].fields[4];
    /// `CIRC`, bit 5.
    pub const CIRC: &FieldSpec = &super::REGISTERS[32].fields[5];
    /// `PINC`, bit 6.
    pub const PINC: &FieldSpec = &super::REGISTERS[32].fields[6];
    /// `MINC`, bit 7.
    pub const MINC: &FieldSpec = &super::REGISTERS[32].fields[7];
    /// `PSIZE`, bits 8..=9.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[32].fields[8];
    /// `MSIZE`, bits 10..=11.
    pub const MSIZE: &FieldSpec = &super::REGISTERS[32].fields[9];
    /// `PL`, bits 12..=13.
    pub const PL: &FieldSpec = &super::REGISTERS[32].fields[10];
    /// `MEM2MEM`, bit 14.
    pub const MEM2MEM: &FieldSpec = &super::REGISTERS[32].fields[11];
    /// `DBM`, bit 15.
    pub const DBM: &FieldSpec = &super::REGISTERS[32].fields[12];
    /// `CT`, bit 16.
    pub const CT: &FieldSpec = &super::REGISTERS[32].fields[13];
}

/// The fields of `BDMA_CNDTR6`.
pub mod bdma_cndtr6 {
    use super::FieldSpec;
    /// `NDT`, bits 0..=15.
    pub const NDT: &FieldSpec = &super::REGISTERS[33].fields[0];
}

/// The fields of `BDMA_CPAR6`.
pub mod bdma_cpar6 {
    use super::FieldSpec;
    /// `PA`, bits 0..=31.
    pub const PA: &FieldSpec = &super::REGISTERS[34].fields[0];
}

/// The fields of `BDMA_CM0AR6`.
pub mod bdma_cm0ar6 {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[35].fields[0];
}

/// The fields of `BDMA_CM1AR6`.
pub mod bdma_cm1ar6 {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[36].fields[0];
}

/// The fields of `BDMA_CCR7`.
pub mod bdma_ccr7 {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[37].fields[0];
    /// `TCIE`, bit 1.
    pub const TCIE: &FieldSpec = &super::REGISTERS[37].fields[1];
    /// `HTIE`, bit 2.
    pub const HTIE: &FieldSpec = &super::REGISTERS[37].fields[2];
    /// `TEIE`, bit 3.
    pub const TEIE: &FieldSpec = &super::REGISTERS[37].fields[3];
    /// `DIR`, bit 4.
    pub const DIR: &FieldSpec = &super::REGISTERS[37].fields[4];
    /// `CIRC`, bit 5.
    pub const CIRC: &FieldSpec = &super::REGISTERS[37].fields[5];
    /// `PINC`, bit 6.
    pub const PINC: &FieldSpec = &super::REGISTERS[37].fields[6];
    /// `MINC`, bit 7.
    pub const MINC: &FieldSpec = &super::REGISTERS[37].fields[7];
    /// `PSIZE`, bits 8..=9.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[37].fields[8];
    /// `MSIZE`, bits 10..=11.
    pub const MSIZE: &FieldSpec = &super::REGISTERS[37].fields[9];
    /// `PL`, bits 12..=13.
    pub const PL: &FieldSpec = &super::REGISTERS[37].fields[10];
    /// `MEM2MEM`, bit 14.
    pub const MEM2MEM: &FieldSpec = &super::REGISTERS[37].fields[11];
    /// `DBM`, bit 15.
    pub const DBM: &FieldSpec = &super::REGISTERS[37].fields[12];
    /// `CT`, bit 16.
    pub const CT: &FieldSpec = &super::REGISTERS[37].fields[13];
}

/// The fields of `BDMA_CNDTR7`.
pub mod bdma_cndtr7 {
    use super::FieldSpec;
    /// `NDT`, bits 0..=15.
    pub const NDT: &FieldSpec = &super::REGISTERS[38].fields[0];
}

/// The fields of `BDMA_CPAR7`.
pub mod bdma_cpar7 {
    use super::FieldSpec;
    /// `PA`, bits 0..=31.
    pub const PA: &FieldSpec = &super::REGISTERS[39].fields[0];
}

/// The fields of `BDMA_CM0AR7`.
pub mod bdma_cm0ar7 {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[40].fields[0];
}

/// The fields of `BDMA_CM1AR7`.
pub mod bdma_cm1ar7 {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[41].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 42] = [
    RegisterSpec { name: "BDMA_ISR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "GIF0", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF0", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIF0", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIF0", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GIF1", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF1", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIF1", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIF1", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GIF2", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF2", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIF2", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIF2", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GIF3", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF3", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIF3", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIF3", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GIF4", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF4", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIF4", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIF4", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GIF5", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF5", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIF5", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIF5", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GIF6", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF6", bit: 25, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIF6", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIF6", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GIF7", bit: 28, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF7", bit: 29, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIF7", bit: 30, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIF7", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_IFCR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CGIF0", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF0", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHTIF0", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTEIF0", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CGIF1", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF1", bit: 5, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHTIF1", bit: 6, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTEIF1", bit: 7, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CGIF2", bit: 8, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF2", bit: 9, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHTIF2", bit: 10, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTEIF2", bit: 11, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CGIF3", bit: 12, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF3", bit: 13, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHTIF3", bit: 14, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTEIF3", bit: 15, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CGIF4", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF4", bit: 17, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHTIF4", bit: 18, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTEIF4", bit: 19, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CGIF5", bit: 20, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF5", bit: 21, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHTIF5", bit: 22, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTEIF5", bit: 23, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CGIF6", bit: 24, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF6", bit: 25, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHTIF6", bit: 26, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTEIF6", bit: 27, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CGIF7", bit: 28, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF7", bit: 29, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHTIF7", bit: 30, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTEIF7", bit: 31, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CCR0", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CIRC", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINC", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MINC", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSIZE", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEM2MEM", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBM", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CT", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CNDTR0", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NDT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CPAR0", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CM0AR0", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CM1AR0", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CCR1", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CIRC", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINC", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MINC", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSIZE", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEM2MEM", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBM", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CT", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CNDTR1", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NDT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CPAR1", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CM0AR1", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CM1AR1", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CCR2", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CIRC", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINC", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MINC", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSIZE", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEM2MEM", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBM", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CT", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CNDTR2", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NDT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CPAR2", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CM0AR2", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CM1AR2", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CCR3", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CIRC", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINC", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MINC", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSIZE", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEM2MEM", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBM", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CT", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CNDTR3", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NDT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CPAR3", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CM0AR3", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CM1AR3", offset: 0x54, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CCR4", offset: 0x58, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CIRC", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINC", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MINC", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSIZE", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEM2MEM", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBM", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CT", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CNDTR4", offset: 0x5C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NDT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CPAR4", offset: 0x60, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CM0AR4", offset: 0x64, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CM1AR4", offset: 0x68, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CCR5", offset: 0x6C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CIRC", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINC", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MINC", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSIZE", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEM2MEM", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBM", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CT", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CNDTR5", offset: 0x70, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NDT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CPAR5", offset: 0x74, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CM0AR5", offset: 0x78, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CM1AR5", offset: 0x7C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CCR6", offset: 0x80, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CIRC", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINC", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MINC", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSIZE", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEM2MEM", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBM", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CT", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CNDTR6", offset: 0x84, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NDT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CPAR6", offset: 0x88, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CM0AR6", offset: 0x8C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CM1AR6", offset: 0x90, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CCR7", offset: 0x94, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CIRC", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINC", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MINC", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSIZE", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEM2MEM", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBM", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CT", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CNDTR7", offset: 0x98, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NDT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CPAR7", offset: 0x9C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CM0AR7", offset: 0xA0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMA_CM1AR7", offset: 0xA4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];