// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `MDMA` and the instances derived from it.
use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};
/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
/// `MDMA_GISR0` at offset `0x0`, resets to `0x0000_0000`, read-only.
MdmaGisr0 = 0,
/// `MDMA_C0ISR` at offset `0x40`, resets to `0x0000_0000`, read-only.
MdmaC0isr = 1,
/// `MDMA_C0IFCR` at offset `0x44`, resets to `0x0000_0000`, write-only.
MdmaC0ifcr = 2,
/// `MDMA_C0ESR` at offset `0x48`, resets to `0x0000_0000`, read-only.
MdmaC0esr = 3,
/// `MDMA_C0CR` at offset `0x4C`, resets to `0x0000_0000`, read-write.
MdmaC0cr = 4,
/// `MDMA_C0TCR` at offset `0x50`, resets to `0x0000_0000`, read-write.
MdmaC0tcr = 5,
/// `MDMA_C0BNDTR` at offset `0x54`, resets to `0x0000_0000`, read-write.
MdmaC0bndtr = 6,
/// `MDMA_C0SAR` at offset `0x58`, resets to `0x0000_0000`, read-write.
MdmaC0sar = 7,
/// `MDMA_C0DAR` at offset `0x5C`, resets to `0x0000_0000`, read-write.
MdmaC0dar = 8,
/// `MDMA_C0BRUR` at offset `0x60`, resets to `0x0000_0000`, read-write.
MdmaC0brur = 9,
/// `MDMA_C0LAR` at offset `0x64`, resets to `0x0000_0000`, read-write.
MdmaC0lar = 10,
/// `MDMA_C0TBR` at offset `0x68`, resets to `0x0000_0000`, read-write.
MdmaC0tbr = 11,
/// `MDMA_C0MAR` at offset `0x70`, resets to `0x0000_0000`, read-write.
MdmaC0mar = 12,
/// `MDMA_C0MDR` at offset `0x74`, resets to `0x0000_0000`, read-write.
MdmaC0mdr = 13,
/// `MDMA_C1ISR` at offset `0x80`, resets to `0x0000_0000`, read-only.
MdmaC1isr = 14,
/// `MDMA_C1IFCR` at offset `0x84`, resets to `0x0000_0000`, write-only.
MdmaC1ifcr = 15,
/// `MDMA_C1ESR` at offset `0x88`, resets to `0x0000_0000`, read-only.
MdmaC1esr = 16,
/// `MDMA_C1CR` at offset `0x8C`, resets to `0x0000_0000`, read-write.
MdmaC1cr = 17,
/// `MDMA_C1TCR` at offset `0x90`, resets to `0x0000_0000`, read-write.
MdmaC1tcr = 18,
/// `MDMA_C1BNDTR` at offset `0x94`, resets to `0x0000_0000`, read-write.
MdmaC1bndtr = 19,
/// `MDMA_C1SAR` at offset `0x98`, resets to `0x0000_0000`, read-write.
MdmaC1sar = 20,
/// `MDMA_C1DAR` at offset `0x9C`, resets to `0x0000_0000`, read-write.
MdmaC1dar = 21,
/// `MDMA_C1BRUR` at offset `0xA0`, resets to `0x0000_0000`, read-write.
MdmaC1brur = 22,
/// `MDMA_C1LAR` at offset `0xA4`, resets to `0x0000_0000`, read-write.
MdmaC1lar = 23,
/// `MDMA_C1TBR` at offset `0xA8`, resets to `0x0000_0000`, read-write.
MdmaC1tbr = 24,
/// `MDMA_C1MAR` at offset `0xB0`, resets to `0x0000_0000`, read-write.
MdmaC1mar = 25,
/// `MDMA_C1MDR` at offset `0xB4`, resets to `0x0000_0000`, read-write.
MdmaC1mdr = 26,
/// `MDMA_C2ISR` at offset `0xC0`, resets to `0x0000_0000`, read-only.
MdmaC2isr = 27,
/// `MDMA_C2IFCR` at offset `0xC4`, resets to `0x0000_0000`, write-only.
MdmaC2ifcr = 28,
/// `MDMA_C2ESR` at offset `0xC8`, resets to `0x0000_0000`, read-only.
MdmaC2esr = 29,
/// `MDMA_C2CR` at offset `0xCC`, resets to `0x0000_0000`, read-write.
MdmaC2cr = 30,
/// `MDMA_C2TCR` at offset `0xD0`, resets to `0x0000_0000`, read-write.
MdmaC2tcr = 31,
/// `MDMA_C2BNDTR` at offset `0xD4`, resets to `0x0000_0000`, read-write.
MdmaC2bndtr = 32,
/// `MDMA_C2SAR` at offset `0xD8`, resets to `0x0000_0000`, read-write.
MdmaC2sar = 33,
/// `MDMA_C2DAR` at offset `0xDC`, resets to `0x0000_0000`, read-write.
MdmaC2dar = 34,
/// `MDMA_C2BRUR` at offset `0xE0`, resets to `0x0000_0000`, read-write.
MdmaC2brur = 35,
/// `MDMA_C2LAR` at offset `0xE4`, resets to `0x0000_0000`, read-write.
MdmaC2lar = 36,
/// `MDMA_C2TBR` at offset `0xE8`, resets to `0x0000_0000`, read-write.
MdmaC2tbr = 37,
/// `MDMA_C2MAR` at offset `0xF0`, resets to `0x0000_0000`, read-write.
MdmaC2mar = 38,
/// `MDMA_C2MDR` at offset `0xF4`, resets to `0x0000_0000`, read-write.
MdmaC2mdr = 39,
/// `MDMA_C3ISR` at offset `0x100`, resets to `0x0000_0000`, read-only.
MdmaC3isr = 40,
/// `MDMA_C3IFCR` at offset `0x104`, resets to `0x0000_0000`, write-only.
MdmaC3ifcr = 41,
/// `MDMA_C3ESR` at offset `0x108`, resets to `0x0000_0000`, read-only.
MdmaC3esr = 42,
/// `MDMA_C3CR` at offset `0x10C`, resets to `0x0000_0000`, read-write.
MdmaC3cr = 43,
/// `MDMA_C3TCR` at offset `0x110`, resets to `0x0000_0000`, read-write.
MdmaC3tcr = 44,
/// `MDMA_C3BNDTR` at offset `0x114`, resets to `0x0000_0000`, read-write.
MdmaC3bndtr = 45,
/// `MDMA_C3SAR` at offset `0x118`, resets to `0x0000_0000`, read-write.
MdmaC3sar = 46,
/// `MDMA_C3DAR` at offset `0x11C`, resets to `0x0000_0000`, read-write.
MdmaC3dar = 47,
/// `MDMA_C3BRUR` at offset `0x120`, resets to `0x0000_0000`, read-write.
MdmaC3brur = 48,
/// `MDMA_C3LAR` at offset `0x124`, resets to `0x0000_0000`, read-write.
MdmaC3lar = 49,
/// `MDMA_C3TBR` at offset `0x128`, resets to `0x0000_0000`, read-write.
MdmaC3tbr = 50,
/// `MDMA_C3MAR` at offset `0x130`, resets to `0x0000_0000`, read-write.
MdmaC3mar = 51,
/// `MDMA_C3MDR` at offset `0x134`, resets to `0x0000_0000`, read-write.
MdmaC3mdr = 52,
/// `MDMA_C4ISR` at offset `0x140`, resets to `0x0000_0000`, read-only.
MdmaC4isr = 53,
/// `MDMA_C4IFCR` at offset `0x144`, resets to `0x0000_0000`, write-only.
MdmaC4ifcr = 54,
/// `MDMA_C4ESR` at offset `0x148`, resets to `0x0000_0000`, read-only.
MdmaC4esr = 55,
/// `MDMA_C4CR` at offset `0x14C`, resets to `0x0000_0000`, read-write.
MdmaC4cr = 56,
/// `MDMA_C4TCR` at offset `0x150`, resets to `0x0000_0000`, read-write.
MdmaC4tcr = 57,
/// `MDMA_C4BNDTR` at offset `0x154`, resets to `0x0000_0000`, read-write.
MdmaC4bndtr = 58,
/// `MDMA_C4SAR` at offset `0x158`, resets to `0x0000_0000`, read-write.
MdmaC4sar = 59,
/// `MDMA_C4DAR` at offset `0x15C`, resets to `0x0000_0000`, read-write.
MdmaC4dar = 60,
/// `MDMA_C4BRUR` at offset `0x160`, resets to `0x0000_0000`, read-write.
MdmaC4brur = 61,
/// `MDMA_C4LAR` at offset `0x164`, resets to `0x0000_0000`, read-write.
MdmaC4lar = 62,
/// `MDMA_C4TBR` at offset `0x168`, resets to `0x0000_0000`, read-write.
MdmaC4tbr = 63,
/// `MDMA_C4MAR` at offset `0x170`, resets to `0x0000_0000`, read-write.
MdmaC4mar = 64,
/// `MDMA_C4MDR` at offset `0x174`, resets to `0x0000_0000`, read-write.
MdmaC4mdr = 65,
/// `MDMA_C5ISR` at offset `0x180`, resets to `0x0000_0000`, read-only.
MdmaC5isr = 66,
/// `MDMA_C5IFCR` at offset `0x184`, resets to `0x0000_0000`, write-only.
MdmaC5ifcr = 67,
/// `MDMA_C5ESR` at offset `0x188`, resets to `0x0000_0000`, read-only.
MdmaC5esr = 68,
/// `MDMA_C5CR` at offset `0x18C`, resets to `0x0000_0000`, read-write.
MdmaC5cr = 69,
/// `MDMA_C5TCR` at offset `0x190`, resets to `0x0000_0000`, read-write.
MdmaC5tcr = 70,
/// `MDMA_C5BNDTR` at offset `0x194`, resets to `0x0000_0000`, read-write.
MdmaC5bndtr = 71,
/// `MDMA_C5SAR` at offset `0x198`, resets to `0x0000_0000`, read-write.
MdmaC5sar = 72,
/// `MDMA_C5DAR` at offset `0x19C`, resets to `0x0000_0000`, read-write.
MdmaC5dar = 73,
/// `MDMA_C5BRUR` at offset `0x1A0`, resets to `0x0000_0000`, read-write.
MdmaC5brur = 74,
/// `MDMA_C5LAR` at offset `0x1A4`, resets to `0x0000_0000`, read-write.
MdmaC5lar = 75,
/// `MDMA_C5TBR` at offset `0x1A8`, resets to `0x0000_0000`, read-write.
MdmaC5tbr = 76,
/// `MDMA_C5MAR` at offset `0x1B0`, resets to `0x0000_0000`, read-write.
MdmaC5mar = 77,
/// `MDMA_C5MDR` at offset `0x1B4`, resets to `0x0000_0000`, read-write.
MdmaC5mdr = 78,
/// `MDMA_C6ISR` at offset `0x1C0`, resets to `0x0000_0000`, read-only.
MdmaC6isr = 79,
/// `MDMA_C6IFCR` at offset `0x1C4`, resets to `0x0000_0000`, write-only.
MdmaC6ifcr = 80,
/// `MDMA_C6ESR` at offset `0x1C8`, resets to `0x0000_0000`, read-only.
MdmaC6esr = 81,
/// `MDMA_C6CR` at offset `0x1CC`, resets to `0x0000_0000`, read-write.
MdmaC6cr = 82,
/// `MDMA_C6TCR` at offset `0x1D0`, resets to `0x0000_0000`, read-write.
MdmaC6tcr = 83,
/// `MDMA_C6BNDTR` at offset `0x1D4`, resets to `0x0000_0000`, read-write.
MdmaC6bndtr = 84,
/// `MDMA_C6SAR` at offset `0x1D8`, resets to `0x0000_0000`, read-write.
MdmaC6sar = 85,
/// `MDMA_C6DAR` at offset `0x1DC`, resets to `0x0000_0000`, read-write.
MdmaC6dar = 86,
/// `MDMA_C6BRUR` at offset `0x1E0`, resets to `0x0000_0000`, read-write.
MdmaC6brur = 87,
/// `MDMA_C6LAR` at offset `0x1E4`, resets to `0x0000_0000`, read-write.
MdmaC6lar = 88,
/// `MDMA_C6TBR` at offset `0x1E8`, resets to `0x0000_0000`, read-write.
MdmaC6tbr = 89,
/// `MDMA_C6MAR` at offset `0x1F0`, resets to `0x0000_0000`, read-write.
MdmaC6mar = 90,
/// `MDMA_C6MDR` at offset `0x1F4`, resets to `0x0000_0000`, read-write.
MdmaC6mdr = 91,
/// `MDMA_C7ISR` at offset `0x200`, resets to `0x0000_0000`, read-only.
MdmaC7isr = 92,
/// `MDMA_C7IFCR` at offset `0x204`, resets to `0x0000_0000`, write-only.
MdmaC7ifcr = 93,
/// `MDMA_C7ESR` at offset `0x208`, resets to `0x0000_0000`, read-only.
MdmaC7esr = 94,
/// `MDMA_C7CR` at offset `0x20C`, resets to `0x0000_0000`, read-write.
MdmaC7cr = 95,
/// `MDMA_C7TCR` at offset `0x210`, resets to `0x0000_0000`, read-write.
MdmaC7tcr = 96,
/// `MDMA_C7BNDTR` at offset `0x214`, resets to `0x0000_0000`, read-write.
MdmaC7bndtr = 97,
/// `MDMA_C7SAR` at offset `0x218`, resets to `0x0000_0000`, read-write.
MdmaC7sar = 98,
/// `MDMA_C7DAR` at offset `0x21C`, resets to `0x0000_0000`, read-write.
MdmaC7dar = 99,
/// `MDMA_C7BRUR` at offset `0x220`, resets to `0x0000_0000`, read-write.
MdmaC7brur = 100,
/// `MDMA_C7LAR` at offset `0x224`, resets to `0x0000_0000`, read-write.
MdmaC7lar = 101,
/// `MDMA_C7TBR` at offset `0x228`, resets to `0x0000_0000`, read-write.
MdmaC7tbr = 102,
/// `MDMA_C7MAR` at offset `0x230`, resets to `0x0000_0000`, read-write.
MdmaC7mar = 103,
/// `MDMA_C7MDR` at offset `0x234`, resets to `0x0000_0000`, read-write.
MdmaC7mdr = 104,
/// `MDMA_C8ISR` at offset `0x240`, resets to `0x0000_0000`, read-only.
MdmaC8isr = 105,
/// `MDMA_C8IFCR` at offset `0x244`, resets to `0x0000_0000`, write-only.
MdmaC8ifcr = 106,
/// `MDMA_C8ESR` at offset `0x248`, resets to `0x0000_0000`, read-only.
MdmaC8esr = 107,
/// `MDMA_C8CR` at offset `0x24C`, resets to `0x0000_0000`, read-write.
MdmaC8cr = 108,
/// `MDMA_C8TCR` at offset `0x250`, resets to `0x0000_0000`, read-write.
MdmaC8tcr = 109,
/// `MDMA_C8BNDTR` at offset `0x254`, resets to `0x0000_0000`, read-write.
MdmaC8bndtr = 110,
/// `MDMA_C8SAR` at offset `0x258`, resets to `0x0000_0000`, read-write.
MdmaC8sar = 111,
/// `MDMA_C8DAR` at offset `0x25C`, resets to `0x0000_0000`, read-write.
MdmaC8dar = 112,
/// `MDMA_C8BRUR` at offset `0x260`, resets to `0x0000_0000`, read-write.
MdmaC8brur = 113,
/// `MDMA_C8LAR` at offset `0x264`, resets to `0x0000_0000`, read-write.
MdmaC8lar = 114,
/// `MDMA_C8TBR` at offset `0x268`, resets to `0x0000_0000`, read-write.
MdmaC8tbr = 115,
/// `MDMA_C8MAR` at offset `0x270`, resets to `0x0000_0000`, read-write.
MdmaC8mar = 116,
/// `MDMA_C8MDR` at offset `0x274`, resets to `0x0000_0000`, read-write.
MdmaC8mdr = 117,
/// `MDMA_C9ISR` at offset `0x280`, resets to `0x0000_0000`, read-only.
MdmaC9isr = 118,
/// `MDMA_C9IFCR` at offset `0x284`, resets to `0x0000_0000`, write-only.
MdmaC9ifcr = 119,
/// `MDMA_C9ESR` at offset `0x288`, resets to `0x0000_0000`, read-only.
MdmaC9esr = 120,
/// `MDMA_C9CR` at offset `0x28C`, resets to `0x0000_0000`, read-write.
MdmaC9cr = 121,
/// `MDMA_C9TCR` at offset `0x290`, resets to `0x0000_0000`, read-write.
MdmaC9tcr = 122,
/// `MDMA_C9BNDTR` at offset `0x294`, resets to `0x0000_0000`, read-write.
MdmaC9bndtr = 123,
/// `MDMA_C9SAR` at offset `0x298`, resets to `0x0000_0000`, read-write.
MdmaC9sar = 124,
/// `MDMA_C9DAR` at offset `0x29C`, resets to `0x0000_0000`, read-write.
MdmaC9dar = 125,
/// `MDMA_C9BRUR` at offset `0x2A0`, resets to `0x0000_0000`, read-write.
MdmaC9brur = 126,
/// `MDMA_C9LAR` at offset `0x2A4`, resets to `0x0000_0000`, read-write.
MdmaC9lar = 127,
/// `MDMA_C9TBR` at offset `0x2A8`, resets to `0x0000_0000`, read-write.
MdmaC9tbr = 128,
/// `MDMA_C9MAR` at offset `0x2B0`, resets to `0x0000_0000`, read-write.
MdmaC9mar = 129,
/// `MDMA_C9MDR` at offset `0x2B4`, resets to `0x0000_0000`, read-write.
MdmaC9mdr = 130,
/// `MDMA_C10ISR` at offset `0x2C0`, resets to `0x0000_0000`, read-only.
MdmaC10isr = 131,
/// `MDMA_C10IFCR` at offset `0x2C4`, resets to `0x0000_0000`, write-only.
MdmaC10ifcr = 132,
/// `MDMA_C10ESR` at offset `0x2C8`, resets to `0x0000_0000`, read-only.
MdmaC10esr = 133,
/// `MDMA_C10CR` at offset `0x2CC`, resets to `0x0000_0000`, read-write.
MdmaC10cr = 134,
/// `MDMA_C10TCR` at offset `0x2D0`, resets to `0x0000_0000`, read-write.
MdmaC10tcr = 135,
/// `MDMA_C10BNDTR` at offset `0x2D4`, resets to `0x0000_0000`, read-write.
MdmaC10bndtr = 136,
/// `MDMA_C10SAR` at offset `0x2D8`, resets to `0x0000_0000`, read-write.
MdmaC10sar = 137,
/// `MDMA_C10DAR` at offset `0x2DC`, resets to `0x0000_0000`, read-write.
MdmaC10dar = 138,
/// `MDMA_C10BRUR` at offset `0x2E0`, resets to `0x0000_0000`, read-write.
MdmaC10brur = 139,
/// `MDMA_C10LAR` at offset `0x2E4`, resets to `0x0000_0000`, read-write.
MdmaC10lar = 140,
/// `MDMA_C10TBR` at offset `0x2E8`, resets to `0x0000_0000`, read-write.
MdmaC10tbr = 141,
/// `MDMA_C10MAR` at offset `0x2F0`, resets to `0x0000_0000`, read-write.
MdmaC10mar = 142,
/// `MDMA_C10MDR` at offset `0x2F4`, resets to `0x0000_0000`, read-write.
MdmaC10mdr = 143,
/// `MDMA_C11ISR` at offset `0x300`, resets to `0x0000_0000`, read-only.
MdmaC11isr = 144,
/// `MDMA_C11IFCR` at offset `0x304`, resets to `0x0000_0000`, write-only.
MdmaC11ifcr = 145,
/// `MDMA_C11ESR` at offset `0x308`, resets to `0x0000_0000`, read-only.
MdmaC11esr = 146,
/// `MDMA_C11CR` at offset `0x30C`, resets to `0x0000_0000`, read-write.
MdmaC11cr = 147,
/// `MDMA_C11TCR` at offset `0x310`, resets to `0x0000_0000`, read-write.
MdmaC11tcr = 148,
/// `MDMA_C11BNDTR` at offset `0x314`, resets to `0x0000_0000`, read-write.
MdmaC11bndtr = 149,
/// `MDMA_C11SAR` at offset `0x318`, resets to `0x0000_0000`, read-write.
MdmaC11sar = 150,
/// `MDMA_C11DAR` at offset `0x31C`, resets to `0x0000_0000`, read-write.
MdmaC11dar = 151,
/// `MDMA_C11BRUR` at offset `0x320`, resets to `0x0000_0000`, read-write.
MdmaC11brur = 152,
/// `MDMA_C11LAR` at offset `0x324`, resets to `0x0000_0000`, read-write.
MdmaC11lar = 153,
/// `MDMA_C11TBR` at offset `0x328`, resets to `0x0000_0000`, read-write.
MdmaC11tbr = 154,
/// `MDMA_C11MAR` at offset `0x330`, resets to `0x0000_0000`, read-write.
MdmaC11mar = 155,
/// `MDMA_C11MDR` at offset `0x334`, resets to `0x0000_0000`, read-write.
MdmaC11mdr = 156,
/// `MDMA_C12ISR` at offset `0x340`, resets to `0x0000_0000`, read-only.
MdmaC12isr = 157,
/// `MDMA_C12IFCR` at offset `0x344`, resets to `0x0000_0000`, write-only.
MdmaC12ifcr = 158,
/// `MDMA_C12ESR` at offset `0x348`, resets to `0x0000_0000`, read-only.
MdmaC12esr = 159,
/// `MDMA_C12CR` at offset `0x34C`, resets to `0x0000_0000`, read-write.
MdmaC12cr = 160,
/// `MDMA_C12TCR` at offset `0x350`, resets to `0x0000_0000`, read-write.
MdmaC12tcr = 161,
/// `MDMA_C12BNDTR` at offset `0x354`, resets to `0x0000_0000`, read-write.
MdmaC12bndtr = 162,
/// `MDMA_C12SAR` at offset `0x358`, resets to `0x0000_0000`, read-write.
MdmaC12sar = 163,
/// `MDMA_C12DAR` at offset `0x35C`, resets to `0x0000_0000`, read-write.
MdmaC12dar = 164,
/// `MDMA_C12BRUR` at offset `0x360`, resets to `0x0000_0000`, read-write.
MdmaC12brur = 165,
/// `MDMA_C12LAR` at offset `0x364`, resets to `0x0000_0000`, read-write.
MdmaC12lar = 166,
/// `MDMA_C12TBR` at offset `0x368`, resets to `0x0000_0000`, read-write.
MdmaC12tbr = 167,
/// `MDMA_C12MAR` at offset `0x370`, resets to `0x0000_0000`, read-write.
MdmaC12mar = 168,
/// `MDMA_C12MDR` at offset `0x374`, resets to `0x0000_0000`, read-write.
MdmaC12mdr = 169,
/// `MDMA_C13ISR` at offset `0x380`, resets to `0x0000_0000`, read-only.
MdmaC13isr = 170,
/// `MDMA_C13IFCR` at offset `0x384`, resets to `0x0000_0000`, write-only.
MdmaC13ifcr = 171,
/// `MDMA_C13ESR` at offset `0x388`, resets to `0x0000_0000`, read-only.
MdmaC13esr = 172,
/// `MDMA_C13CR` at offset `0x38C`, resets to `0x0000_0000`, read-write.
MdmaC13cr = 173,
/// `MDMA_C13TCR` at offset `0x390`, resets to `0x0000_0000`, read-write.
MdmaC13tcr = 174,
/// `MDMA_C13BNDTR` at offset `0x394`, resets to `0x0000_0000`, read-write.
MdmaC13bndtr = 175,
/// `MDMA_C13SAR` at offset `0x398`, resets to `0x0000_0000`, read-write.
MdmaC13sar = 176,
/// `MDMA_C13DAR` at offset `0x39C`, resets to `0x0000_0000`, read-write.
MdmaC13dar = 177,
/// `MDMA_C13BRUR` at offset `0x3A0`, resets to `0x0000_0000`, read-write.
MdmaC13brur = 178,
/// `MDMA_C13LAR` at offset `0x3A4`, resets to `0x0000_0000`, read-write.
MdmaC13lar = 179,
/// `MDMA_C13TBR` at offset `0x3A8`, resets to `0x0000_0000`, read-write.
MdmaC13tbr = 180,
/// `MDMA_C13MAR` at offset `0x3B0`, resets to `0x0000_0000`, read-write.
MdmaC13mar = 181,
/// `MDMA_C13MDR` at offset `0x3B4`, resets to `0x0000_0000`, read-write.
MdmaC13mdr = 182,
/// `MDMA_C14ISR` at offset `0x3C0`, resets to `0x0000_0000`, read-only.
MdmaC14isr = 183,
/// `MDMA_C14IFCR` at offset `0x3C4`, resets to `0x0000_0000`, write-only.
MdmaC14ifcr = 184,
/// `MDMA_C14ESR` at offset `0x3C8`, resets to `0x0000_0000`, read-only.
MdmaC14esr = 185,
/// `MDMA_C14CR` at offset `0x3CC`, resets to `0x0000_0000`, read-write.
MdmaC14cr = 186,
/// `MDMA_C14TCR` at offset `0x3D0`, resets to `0x0000_0000`, read-write.
MdmaC14tcr = 187,
/// `MDMA_C14BNDTR` at offset `0x3D4`, resets to `0x0000_0000`, read-write.
MdmaC14bndtr = 188,
/// `MDMA_C14SAR` at offset `0x3D8`, resets to `0x0000_0000`, read-write.
MdmaC14sar = 189,
/// `MDMA_C14DAR` at offset `0x3DC`, resets to `0x0000_0000`, read-write.
MdmaC14dar = 190,
/// `MDMA_C14BRUR` at offset `0x3E0`, resets to `0x0000_0000`, read-write.
MdmaC14brur = 191,
/// `MDMA_C14LAR` at offset `0x3E4`, resets to `0x0000_0000`, read-write.
MdmaC14lar = 192,
/// `MDMA_C14TBR` at offset `0x3E8`, resets to `0x0000_0000`, read-write.
MdmaC14tbr = 193,
/// `MDMA_C14MAR` at offset `0x3F0`, resets to `0x0000_0000`, read-write.
MdmaC14mar = 194,
/// `MDMA_C14MDR` at offset `0x3F4`, resets to `0x0000_0000`, read-write.
MdmaC14mdr = 195,
/// `MDMA_C15ISR` at offset `0x400`, resets to `0x0000_0000`, read-only.
MdmaC15isr = 196,
/// `MDMA_C15IFCR` at offset `0x404`, resets to `0x0000_0000`, write-only.
MdmaC15ifcr = 197,
/// `MDMA_C15ESR` at offset `0x408`, resets to `0x0000_0000`, read-only.
MdmaC15esr = 198,
/// `MDMA_C15CR` at offset `0x40C`, resets to `0x0000_0000`, read-write.
MdmaC15cr = 199,
/// `MDMA_C15TCR` at offset `0x410`, resets to `0x0000_0000`, read-write.
MdmaC15tcr = 200,
/// `MDMA_C15BNDTR` at offset `0x414`, resets to `0x0000_0000`, read-write.
MdmaC15bndtr = 201,
/// `MDMA_C15SAR` at offset `0x418`, resets to `0x0000_0000`, read-write.
MdmaC15sar = 202,
/// `MDMA_C15DAR` at offset `0x41C`, resets to `0x0000_0000`, read-write.
MdmaC15dar = 203,
/// `MDMA_C15BRUR` at offset `0x420`, resets to `0x0000_0000`, read-write.
MdmaC15brur = 204,
/// `MDMA_C15LAR` at offset `0x424`, resets to `0x0000_0000`, read-write.
MdmaC15lar = 205,
/// `MDMA_C15TBR` at offset `0x428`, resets to `0x0000_0000`, read-write.
MdmaC15tbr = 206,
/// `MDMA_C15MAR` at offset `0x430`, resets to `0x0000_0000`, read-write.
MdmaC15mar = 207,
/// `MDMA_C15MDR` at offset `0x434`, resets to `0x0000_0000`, read-write.
MdmaC15mdr = 208,
}
impl Register {
/// Every register, in table order.
pub const ALL: [Self; 209] = [Self::MdmaGisr0, Self::MdmaC0isr, Self::MdmaC0ifcr, Self::MdmaC0esr, Self::MdmaC0cr, Self::MdmaC0tcr, Self::MdmaC0bndtr, Self::MdmaC0sar, Self::MdmaC0dar, Self::MdmaC0brur, Self::MdmaC0lar, Self::MdmaC0tbr, Self::MdmaC0mar, Self::MdmaC0mdr, Self::MdmaC1isr, Self::MdmaC1ifcr, Self::MdmaC1esr, Self::MdmaC1cr, Self::MdmaC1tcr, Self::MdmaC1bndtr, Self::MdmaC1sar, Self::MdmaC1dar, Self::MdmaC1brur, Self::MdmaC1lar, Self::MdmaC1tbr, Self::MdmaC1mar, Self::MdmaC1mdr, Self::MdmaC2isr, Self::MdmaC2ifcr, Self::MdmaC2esr, Self::MdmaC2cr, Self::MdmaC2tcr, Self::MdmaC2bndtr, Self::MdmaC2sar, Self::MdmaC2dar, Self::MdmaC2brur, Self::MdmaC2lar, Self::MdmaC2tbr, Self::MdmaC2mar, Self::MdmaC2mdr, Self::MdmaC3isr, Self::MdmaC3ifcr, Self::MdmaC3esr, Self::MdmaC3cr, Self::MdmaC3tcr, Self::MdmaC3bndtr, Self::MdmaC3sar, Self::MdmaC3dar, Self::MdmaC3brur, Self::MdmaC3lar, Self::MdmaC3tbr, Self::MdmaC3mar, Self::MdmaC3mdr, Self::MdmaC4isr, Self::MdmaC4ifcr, Self::MdmaC4esr, Self::MdmaC4cr, Self::MdmaC4tcr, Self::MdmaC4bndtr, Self::MdmaC4sar, Self::MdmaC4dar, Self::MdmaC4brur, Self::MdmaC4lar, Self::MdmaC4tbr, Self::MdmaC4mar, Self::MdmaC4mdr, Self::MdmaC5isr, Self::MdmaC5ifcr, Self::MdmaC5esr, Self::MdmaC5cr, Self::MdmaC5tcr, Self::MdmaC5bndtr, Self::MdmaC5sar, Self::MdmaC5dar, Self::MdmaC5brur, Self::MdmaC5lar, Self::MdmaC5tbr, Self::MdmaC5mar, Self::MdmaC5mdr, Self::MdmaC6isr, Self::MdmaC6ifcr, Self::MdmaC6esr, Self::MdmaC6cr, Self::MdmaC6tcr, Self::MdmaC6bndtr, Self::MdmaC6sar, Self::MdmaC6dar, Self::MdmaC6brur, Self::MdmaC6lar, Self::MdmaC6tbr, Self::MdmaC6mar, Self::MdmaC6mdr, Self::MdmaC7isr, Self::MdmaC7ifcr, Self::MdmaC7esr, Self::MdmaC7cr, Self::MdmaC7tcr, Self::MdmaC7bndtr, Self::MdmaC7sar, Self::MdmaC7dar, Self::MdmaC7brur, Self::MdmaC7lar, Self::MdmaC7tbr, Self::MdmaC7mar, Self::MdmaC7mdr, Self::MdmaC8isr, Self::MdmaC8ifcr, Self::MdmaC8esr, Self::MdmaC8cr, Self::MdmaC8tcr, Self::MdmaC8bndtr, Self::MdmaC8sar, Self::MdmaC8dar, Self::MdmaC8brur, Self::MdmaC8lar, Self::MdmaC8tbr, Self::MdmaC8mar, Self::MdmaC8mdr, Self::MdmaC9isr, Self::MdmaC9ifcr, Self::MdmaC9esr, Self::MdmaC9cr, Self::MdmaC9tcr, Self::MdmaC9bndtr, Self::MdmaC9sar, Self::MdmaC9dar, Self::MdmaC9brur, Self::MdmaC9lar, Self::MdmaC9tbr, Self::MdmaC9mar, Self::MdmaC9mdr, Self::MdmaC10isr, Self::MdmaC10ifcr, Self::MdmaC10esr, Self::MdmaC10cr, Self::MdmaC10tcr, Self::MdmaC10bndtr, Self::MdmaC10sar, Self::MdmaC10dar, Self::MdmaC10brur, Self::MdmaC10lar, Self::MdmaC10tbr, Self::MdmaC10mar, Self::MdmaC10mdr, Self::MdmaC11isr, Self::MdmaC11ifcr, Self::MdmaC11esr, Self::MdmaC11cr, Self::MdmaC11tcr, Self::MdmaC11bndtr, Self::MdmaC11sar, Self::MdmaC11dar, Self::MdmaC11brur, Self::MdmaC11lar, Self::MdmaC11tbr, Self::MdmaC11mar, Self::MdmaC11mdr, Self::MdmaC12isr, Self::MdmaC12ifcr, Self::MdmaC12esr, Self::MdmaC12cr, Self::MdmaC12tcr, Self::MdmaC12bndtr, Self::MdmaC12sar, Self::MdmaC12dar, Self::MdmaC12brur, Self::MdmaC12lar, Self::MdmaC12tbr, Self::MdmaC12mar, Self::MdmaC12mdr, Self::MdmaC13isr, Self::MdmaC13ifcr, Self::MdmaC13esr, Self::MdmaC13cr, Self::MdmaC13tcr, Self::MdmaC13bndtr, Self::MdmaC13sar, Self::MdmaC13dar, Self::MdmaC13brur, Self::MdmaC13lar, Self::MdmaC13tbr, Self::MdmaC13mar, Self::MdmaC13mdr, Self::MdmaC14isr, Self::MdmaC14ifcr, Self::MdmaC14esr, Self::MdmaC14cr, Self::MdmaC14tcr, Self::MdmaC14bndtr, Self::MdmaC14sar, Self::MdmaC14dar, Self::MdmaC14brur, Self::MdmaC14lar, Self::MdmaC14tbr, Self::MdmaC14mar, Self::MdmaC14mdr, Self::MdmaC15isr, Self::MdmaC15ifcr, Self::MdmaC15esr, Self::MdmaC15cr, Self::MdmaC15tcr, Self::MdmaC15bndtr, Self::MdmaC15sar, Self::MdmaC15dar, Self::MdmaC15brur, Self::MdmaC15lar, Self::MdmaC15tbr, Self::MdmaC15mar, Self::MdmaC15mdr];
}
impl Layout for Register {
const REGISTERS: &'static [RegisterSpec] = ®ISTERS;
fn from_index(index: usize) -> Option<Self> {
Self::ALL.get(index).copied()
}
fn index(self) -> usize {
self as usize
}
}
/// The fields of `MDMA_GISR0`.
pub mod mdma_gisr0 {
use super::FieldSpec;
/// `GIF0`, bit 0.
pub const GIF0: &FieldSpec = &super::REGISTERS[0].fields[0];
/// `GIF1`, bit 1.
pub const GIF1: &FieldSpec = &super::REGISTERS[0].fields[1];
/// `GIF2`, bit 2.
pub const GIF2: &FieldSpec = &super::REGISTERS[0].fields[2];
/// `GIF3`, bit 3.
pub const GIF3: &FieldSpec = &super::REGISTERS[0].fields[3];
/// `GIF4`, bit 4.
pub const GIF4: &FieldSpec = &super::REGISTERS[0].fields[4];
/// `GIF5`, bit 5.
pub const GIF5: &FieldSpec = &super::REGISTERS[0].fields[5];
/// `GIF6`, bit 6.
pub const GIF6: &FieldSpec = &super::REGISTERS[0].fields[6];
/// `GIF7`, bit 7.
pub const GIF7: &FieldSpec = &super::REGISTERS[0].fields[7];
/// `GIF8`, bit 8.
pub const GIF8: &FieldSpec = &super::REGISTERS[0].fields[8];
/// `GIF9`, bit 9.
pub const GIF9: &FieldSpec = &super::REGISTERS[0].fields[9];
/// `GIF10`, bit 10.
pub const GIF10: &FieldSpec = &super::REGISTERS[0].fields[10];
/// `GIF11`, bit 11.
pub const GIF11: &FieldSpec = &super::REGISTERS[0].fields[11];
/// `GIF12`, bit 12.
pub const GIF12: &FieldSpec = &super::REGISTERS[0].fields[12];
/// `GIF13`, bit 13.
pub const GIF13: &FieldSpec = &super::REGISTERS[0].fields[13];
/// `GIF14`, bit 14.
pub const GIF14: &FieldSpec = &super::REGISTERS[0].fields[14];
/// `GIF15`, bit 15.
pub const GIF15: &FieldSpec = &super::REGISTERS[0].fields[15];
}
/// The fields of `MDMA_C0ISR`.
pub mod mdma_c0isr {
use super::FieldSpec;
/// `TEIF0`, bit 0.
pub const TEIF0: &FieldSpec = &super::REGISTERS[1].fields[0];
/// `CTCIF0`, bit 1.
pub const CTCIF0: &FieldSpec = &super::REGISTERS[1].fields[1];
/// `BRTIF0`, bit 2.
pub const BRTIF0: &FieldSpec = &super::REGISTERS[1].fields[2];
/// `BTIF0`, bit 3.
pub const BTIF0: &FieldSpec = &super::REGISTERS[1].fields[3];
/// `TCIF0`, bit 4.
pub const TCIF0: &FieldSpec = &super::REGISTERS[1].fields[4];
/// `CRQA0`, bit 16.
pub const CRQA0: &FieldSpec = &super::REGISTERS[1].fields[5];
}
/// The fields of `MDMA_C0IFCR`.
pub mod mdma_c0ifcr {
use super::FieldSpec;
/// `CTEIF0`, bit 0.
pub const CTEIF0: &FieldSpec = &super::REGISTERS[2].fields[0];
/// `CCTCIF0`, bit 1.
pub const CCTCIF0: &FieldSpec = &super::REGISTERS[2].fields[1];
/// `CBRTIF0`, bit 2.
pub const CBRTIF0: &FieldSpec = &super::REGISTERS[2].fields[2];
/// `CBTIF0`, bit 3.
pub const CBTIF0: &FieldSpec = &super::REGISTERS[2].fields[3];
/// `CLTCIF0`, bit 4.
pub const CLTCIF0: &FieldSpec = &super::REGISTERS[2].fields[4];
}
/// The fields of `MDMA_C0ESR`.
pub mod mdma_c0esr {
use super::FieldSpec;
/// `TEA`, bits 0..=6.
pub const TEA: &FieldSpec = &super::REGISTERS[3].fields[0];
/// `TED`, bit 7.
pub const TED: &FieldSpec = &super::REGISTERS[3].fields[1];
/// `TELD`, bit 8.
pub const TELD: &FieldSpec = &super::REGISTERS[3].fields[2];
/// `TEMD`, bit 9.
pub const TEMD: &FieldSpec = &super::REGISTERS[3].fields[3];
/// `ASE`, bit 10.
pub const ASE: &FieldSpec = &super::REGISTERS[3].fields[4];
/// `BSE`, bit 11.
pub const BSE: &FieldSpec = &super::REGISTERS[3].fields[5];
}
/// The fields of `MDMA_C0CR`.
pub mod mdma_c0cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[4].fields[0];
/// `TEIE`, bit 1.
pub const TEIE: &FieldSpec = &super::REGISTERS[4].fields[1];
/// `CTCIE`, bit 2.
pub const CTCIE: &FieldSpec = &super::REGISTERS[4].fields[2];
/// `BRTIE`, bit 3.
pub const BRTIE: &FieldSpec = &super::REGISTERS[4].fields[3];
/// `BTIE`, bit 4.
pub const BTIE: &FieldSpec = &super::REGISTERS[4].fields[4];
/// `TCIE`, bit 5.
pub const TCIE: &FieldSpec = &super::REGISTERS[4].fields[5];
/// `PL`, bits 6..=7.
pub const PL: &FieldSpec = &super::REGISTERS[4].fields[6];
/// `BEX`, bit 12.
pub const BEX: &FieldSpec = &super::REGISTERS[4].fields[7];
/// `HEX`, bit 13.
pub const HEX: &FieldSpec = &super::REGISTERS[4].fields[8];
/// `WEX`, bit 14.
pub const WEX: &FieldSpec = &super::REGISTERS[4].fields[9];
/// `SWRQ`, bit 16, write-only.
pub const SWRQ: &FieldSpec = &super::REGISTERS[4].fields[10];
}
/// The fields of `MDMA_C0TCR`.
pub mod mdma_c0tcr {
use super::FieldSpec;
/// `SINC`, bits 0..=1.
pub const SINC: &FieldSpec = &super::REGISTERS[5].fields[0];
/// `DINC`, bits 2..=3.
pub const DINC: &FieldSpec = &super::REGISTERS[5].fields[1];
/// `SSIZE`, bits 4..=5.
pub const SSIZE: &FieldSpec = &super::REGISTERS[5].fields[2];
/// `DSIZE`, bits 6..=7.
pub const DSIZE: &FieldSpec = &super::REGISTERS[5].fields[3];
/// `SINCOS`, bits 8..=9.
pub const SINCOS: &FieldSpec = &super::REGISTERS[5].fields[4];
/// `DINCOS`, bits 10..=11.
pub const DINCOS: &FieldSpec = &super::REGISTERS[5].fields[5];
/// `SBURST`, bits 12..=14.
pub const SBURST: &FieldSpec = &super::REGISTERS[5].fields[6];
/// `DBURST`, bits 15..=17.
pub const DBURST: &FieldSpec = &super::REGISTERS[5].fields[7];
/// `TLEN`, bits 18..=24.
pub const TLEN: &FieldSpec = &super::REGISTERS[5].fields[8];
/// `PKE`, bit 25.
pub const PKE: &FieldSpec = &super::REGISTERS[5].fields[9];
/// `PAM`, bits 26..=27.
pub const PAM: &FieldSpec = &super::REGISTERS[5].fields[10];
/// `TRGM`, bits 28..=29.
pub const TRGM: &FieldSpec = &super::REGISTERS[5].fields[11];
/// `SWRM`, bit 30.
pub const SWRM: &FieldSpec = &super::REGISTERS[5].fields[12];
/// `BWM`, bit 31.
pub const BWM: &FieldSpec = &super::REGISTERS[5].fields[13];
}
/// The fields of `MDMA_C0BNDTR`.
pub mod mdma_c0bndtr {
use super::FieldSpec;
/// `BNDT`, bits 0..=16.
pub const BNDT: &FieldSpec = &super::REGISTERS[6].fields[0];
/// `BRSUM`, bit 18.
pub const BRSUM: &FieldSpec = &super::REGISTERS[6].fields[1];
/// `BRDUM`, bit 19.
pub const BRDUM: &FieldSpec = &super::REGISTERS[6].fields[2];
/// `BRC`, bits 20..=31.
pub const BRC: &FieldSpec = &super::REGISTERS[6].fields[3];
}
/// The fields of `MDMA_C0SAR`.
pub mod mdma_c0sar {
use super::FieldSpec;
/// `SAR`, bits 0..=31.
pub const SAR: &FieldSpec = &super::REGISTERS[7].fields[0];
}
/// The fields of `MDMA_C0DAR`.
pub mod mdma_c0dar {
use super::FieldSpec;
/// `DAR`, bits 0..=31.
pub const DAR: &FieldSpec = &super::REGISTERS[8].fields[0];
}
/// The fields of `MDMA_C0BRUR`.
pub mod mdma_c0brur {
use super::FieldSpec;
/// `SUV`, bits 0..=15.
pub const SUV: &FieldSpec = &super::REGISTERS[9].fields[0];
/// `DUV`, bits 16..=31.
pub const DUV: &FieldSpec = &super::REGISTERS[9].fields[1];
}
/// The fields of `MDMA_C0LAR`.
pub mod mdma_c0lar {
use super::FieldSpec;
/// `LAR`, bits 0..=31.
pub const LAR: &FieldSpec = &super::REGISTERS[10].fields[0];
}
/// The fields of `MDMA_C0TBR`.
pub mod mdma_c0tbr {
use super::FieldSpec;
/// `TSEL`, bits 0..=5.
pub const TSEL: &FieldSpec = &super::REGISTERS[11].fields[0];
/// `SBUS`, bit 16.
pub const SBUS: &FieldSpec = &super::REGISTERS[11].fields[1];
/// `DBUS`, bit 17.
pub const DBUS: &FieldSpec = &super::REGISTERS[11].fields[2];
}
/// The fields of `MDMA_C0MAR`.
pub mod mdma_c0mar {
use super::FieldSpec;
/// `MAR`, bits 0..=31.
pub const MAR: &FieldSpec = &super::REGISTERS[12].fields[0];
}
/// The fields of `MDMA_C0MDR`.
pub mod mdma_c0mdr {
use super::FieldSpec;
/// `MDR`, bits 0..=31.
pub const MDR: &FieldSpec = &super::REGISTERS[13].fields[0];
}
/// The fields of `MDMA_C1ISR`.
pub mod mdma_c1isr {
use super::FieldSpec;
/// `TEIF1`, bit 0.
pub const TEIF1: &FieldSpec = &super::REGISTERS[14].fields[0];
/// `CTCIF1`, bit 1.
pub const CTCIF1: &FieldSpec = &super::REGISTERS[14].fields[1];
/// `BRTIF1`, bit 2.
pub const BRTIF1: &FieldSpec = &super::REGISTERS[14].fields[2];
/// `BTIF1`, bit 3.
pub const BTIF1: &FieldSpec = &super::REGISTERS[14].fields[3];
/// `TCIF1`, bit 4.
pub const TCIF1: &FieldSpec = &super::REGISTERS[14].fields[4];
/// `CRQA1`, bit 16.
pub const CRQA1: &FieldSpec = &super::REGISTERS[14].fields[5];
}
/// The fields of `MDMA_C1IFCR`.
pub mod mdma_c1ifcr {
use super::FieldSpec;
/// `CTEIF1`, bit 0.
pub const CTEIF1: &FieldSpec = &super::REGISTERS[15].fields[0];
/// `CCTCIF1`, bit 1.
pub const CCTCIF1: &FieldSpec = &super::REGISTERS[15].fields[1];
/// `CBRTIF1`, bit 2.
pub const CBRTIF1: &FieldSpec = &super::REGISTERS[15].fields[2];
/// `CBTIF1`, bit 3.
pub const CBTIF1: &FieldSpec = &super::REGISTERS[15].fields[3];
/// `CLTCIF1`, bit 4.
pub const CLTCIF1: &FieldSpec = &super::REGISTERS[15].fields[4];
}
/// The fields of `MDMA_C1ESR`.
pub mod mdma_c1esr {
use super::FieldSpec;
/// `TEA`, bits 0..=6.
pub const TEA: &FieldSpec = &super::REGISTERS[16].fields[0];
/// `TED`, bit 7.
pub const TED: &FieldSpec = &super::REGISTERS[16].fields[1];
/// `TELD`, bit 8.
pub const TELD: &FieldSpec = &super::REGISTERS[16].fields[2];
/// `TEMD`, bit 9.
pub const TEMD: &FieldSpec = &super::REGISTERS[16].fields[3];
/// `ASE`, bit 10.
pub const ASE: &FieldSpec = &super::REGISTERS[16].fields[4];
/// `BSE`, bit 11.
pub const BSE: &FieldSpec = &super::REGISTERS[16].fields[5];
}
/// The fields of `MDMA_C1CR`.
pub mod mdma_c1cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[17].fields[0];
/// `TEIE`, bit 1.
pub const TEIE: &FieldSpec = &super::REGISTERS[17].fields[1];
/// `CTCIE`, bit 2.
pub const CTCIE: &FieldSpec = &super::REGISTERS[17].fields[2];
/// `BRTIE`, bit 3.
pub const BRTIE: &FieldSpec = &super::REGISTERS[17].fields[3];
/// `BTIE`, bit 4.
pub const BTIE: &FieldSpec = &super::REGISTERS[17].fields[4];
/// `TCIE`, bit 5.
pub const TCIE: &FieldSpec = &super::REGISTERS[17].fields[5];
/// `PL`, bits 6..=7.
pub const PL: &FieldSpec = &super::REGISTERS[17].fields[6];
/// `BEX`, bit 12.
pub const BEX: &FieldSpec = &super::REGISTERS[17].fields[7];
/// `HEX`, bit 13.
pub const HEX: &FieldSpec = &super::REGISTERS[17].fields[8];
/// `WEX`, bit 14.
pub const WEX: &FieldSpec = &super::REGISTERS[17].fields[9];
/// `SWRQ`, bit 16, write-only.
pub const SWRQ: &FieldSpec = &super::REGISTERS[17].fields[10];
}
/// The fields of `MDMA_C1TCR`.
pub mod mdma_c1tcr {
use super::FieldSpec;
/// `SINC`, bits 0..=1.
pub const SINC: &FieldSpec = &super::REGISTERS[18].fields[0];
/// `DINC`, bits 2..=3.
pub const DINC: &FieldSpec = &super::REGISTERS[18].fields[1];
/// `SSIZE`, bits 4..=5.
pub const SSIZE: &FieldSpec = &super::REGISTERS[18].fields[2];
/// `DSIZE`, bits 6..=7.
pub const DSIZE: &FieldSpec = &super::REGISTERS[18].fields[3];
/// `SINCOS`, bits 8..=9.
pub const SINCOS: &FieldSpec = &super::REGISTERS[18].fields[4];
/// `DINCOS`, bits 10..=11.
pub const DINCOS: &FieldSpec = &super::REGISTERS[18].fields[5];
/// `SBURST`, bits 12..=14.
pub const SBURST: &FieldSpec = &super::REGISTERS[18].fields[6];
/// `DBURST`, bits 15..=17.
pub const DBURST: &FieldSpec = &super::REGISTERS[18].fields[7];
/// `TLEN`, bits 18..=24.
pub const TLEN: &FieldSpec = &super::REGISTERS[18].fields[8];
/// `PKE`, bit 25.
pub const PKE: &FieldSpec = &super::REGISTERS[18].fields[9];
/// `PAM`, bits 26..=27.
pub const PAM: &FieldSpec = &super::REGISTERS[18].fields[10];
/// `TRGM`, bits 28..=29.
pub const TRGM: &FieldSpec = &super::REGISTERS[18].fields[11];
/// `SWRM`, bit 30.
pub const SWRM: &FieldSpec = &super::REGISTERS[18].fields[12];
/// `BWM`, bit 31.
pub const BWM: &FieldSpec = &super::REGISTERS[18].fields[13];
}
/// The fields of `MDMA_C1BNDTR`.
pub mod mdma_c1bndtr {
use super::FieldSpec;
/// `BNDT`, bits 0..=16.
pub const BNDT: &FieldSpec = &super::REGISTERS[19].fields[0];
/// `BRSUM`, bit 18.
pub const BRSUM: &FieldSpec = &super::REGISTERS[19].fields[1];
/// `BRDUM`, bit 19.
pub const BRDUM: &FieldSpec = &super::REGISTERS[19].fields[2];
/// `BRC`, bits 20..=31.
pub const BRC: &FieldSpec = &super::REGISTERS[19].fields[3];
}
/// The fields of `MDMA_C1SAR`.
pub mod mdma_c1sar {
use super::FieldSpec;
/// `SAR`, bits 0..=31.
pub const SAR: &FieldSpec = &super::REGISTERS[20].fields[0];
}
/// The fields of `MDMA_C1DAR`.
pub mod mdma_c1dar {
use super::FieldSpec;
/// `DAR`, bits 0..=31.
pub const DAR: &FieldSpec = &super::REGISTERS[21].fields[0];
}
/// The fields of `MDMA_C1BRUR`.
pub mod mdma_c1brur {
use super::FieldSpec;
/// `SUV`, bits 0..=15.
pub const SUV: &FieldSpec = &super::REGISTERS[22].fields[0];
/// `DUV`, bits 16..=31.
pub const DUV: &FieldSpec = &super::REGISTERS[22].fields[1];
}
/// The fields of `MDMA_C1LAR`.
pub mod mdma_c1lar {
use super::FieldSpec;
/// `LAR`, bits 0..=31.
pub const LAR: &FieldSpec = &super::REGISTERS[23].fields[0];
}
/// The fields of `MDMA_C1TBR`.
pub mod mdma_c1tbr {
use super::FieldSpec;
/// `TSEL`, bits 0..=5.
pub const TSEL: &FieldSpec = &super::REGISTERS[24].fields[0];
/// `SBUS`, bit 16.
pub const SBUS: &FieldSpec = &super::REGISTERS[24].fields[1];
/// `DBUS`, bit 17.
pub const DBUS: &FieldSpec = &super::REGISTERS[24].fields[2];
}
/// The fields of `MDMA_C1MAR`.
pub mod mdma_c1mar {
use super::FieldSpec;
/// `MAR`, bits 0..=31.
pub const MAR: &FieldSpec = &super::REGISTERS[25].fields[0];
}
/// The fields of `MDMA_C1MDR`.
pub mod mdma_c1mdr {
use super::FieldSpec;
/// `MDR`, bits 0..=31.
pub const MDR: &FieldSpec = &super::REGISTERS[26].fields[0];
}
/// The fields of `MDMA_C2ISR`.
pub mod mdma_c2isr {
use super::FieldSpec;
/// `TEIF2`, bit 0.
pub const TEIF2: &FieldSpec = &super::REGISTERS[27].fields[0];
/// `CTCIF2`, bit 1.
pub const CTCIF2: &FieldSpec = &super::REGISTERS[27].fields[1];
/// `BRTIF2`, bit 2.
pub const BRTIF2: &FieldSpec = &super::REGISTERS[27].fields[2];
/// `BTIF2`, bit 3.
pub const BTIF2: &FieldSpec = &super::REGISTERS[27].fields[3];
/// `TCIF2`, bit 4.
pub const TCIF2: &FieldSpec = &super::REGISTERS[27].fields[4];
/// `CRQA2`, bit 16.
pub const CRQA2: &FieldSpec = &super::REGISTERS[27].fields[5];
}
/// The fields of `MDMA_C2IFCR`.
pub mod mdma_c2ifcr {
use super::FieldSpec;
/// `CTEIF2`, bit 0.
pub const CTEIF2: &FieldSpec = &super::REGISTERS[28].fields[0];
/// `CCTCIF2`, bit 1.
pub const CCTCIF2: &FieldSpec = &super::REGISTERS[28].fields[1];
/// `CBRTIF2`, bit 2.
pub const CBRTIF2: &FieldSpec = &super::REGISTERS[28].fields[2];
/// `CBTIF2`, bit 3.
pub const CBTIF2: &FieldSpec = &super::REGISTERS[28].fields[3];
/// `CLTCIF2`, bit 4.
pub const CLTCIF2: &FieldSpec = &super::REGISTERS[28].fields[4];
}
/// The fields of `MDMA_C2ESR`.
pub mod mdma_c2esr {
use super::FieldSpec;
/// `TEA`, bits 0..=6.
pub const TEA: &FieldSpec = &super::REGISTERS[29].fields[0];
/// `TED`, bit 7.
pub const TED: &FieldSpec = &super::REGISTERS[29].fields[1];
/// `TELD`, bit 8.
pub const TELD: &FieldSpec = &super::REGISTERS[29].fields[2];
/// `TEMD`, bit 9.
pub const TEMD: &FieldSpec = &super::REGISTERS[29].fields[3];
/// `ASE`, bit 10.
pub const ASE: &FieldSpec = &super::REGISTERS[29].fields[4];
/// `BSE`, bit 11.
pub const BSE: &FieldSpec = &super::REGISTERS[29].fields[5];
}
/// The fields of `MDMA_C2CR`.
pub mod mdma_c2cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[30].fields[0];
/// `TEIE`, bit 1.
pub const TEIE: &FieldSpec = &super::REGISTERS[30].fields[1];
/// `CTCIE`, bit 2.
pub const CTCIE: &FieldSpec = &super::REGISTERS[30].fields[2];
/// `BRTIE`, bit 3.
pub const BRTIE: &FieldSpec = &super::REGISTERS[30].fields[3];
/// `BTIE`, bit 4.
pub const BTIE: &FieldSpec = &super::REGISTERS[30].fields[4];
/// `TCIE`, bit 5.
pub const TCIE: &FieldSpec = &super::REGISTERS[30].fields[5];
/// `PL`, bits 6..=7.
pub const PL: &FieldSpec = &super::REGISTERS[30].fields[6];
/// `BEX`, bit 12.
pub const BEX: &FieldSpec = &super::REGISTERS[30].fields[7];
/// `HEX`, bit 13.
pub const HEX: &FieldSpec = &super::REGISTERS[30].fields[8];
/// `WEX`, bit 14.
pub const WEX: &FieldSpec = &super::REGISTERS[30].fields[9];
/// `SWRQ`, bit 16, write-only.
pub const SWRQ: &FieldSpec = &super::REGISTERS[30].fields[10];
}
/// The fields of `MDMA_C2TCR`.
pub mod mdma_c2tcr {
use super::FieldSpec;
/// `SINC`, bits 0..=1.
pub const SINC: &FieldSpec = &super::REGISTERS[31].fields[0];
/// `DINC`, bits 2..=3.
pub const DINC: &FieldSpec = &super::REGISTERS[31].fields[1];
/// `SSIZE`, bits 4..=5.
pub const SSIZE: &FieldSpec = &super::REGISTERS[31].fields[2];
/// `DSIZE`, bits 6..=7.
pub const DSIZE: &FieldSpec = &super::REGISTERS[31].fields[3];
/// `SINCOS`, bits 8..=9.
pub const SINCOS: &FieldSpec = &super::REGISTERS[31].fields[4];
/// `DINCOS`, bits 10..=11.
pub const DINCOS: &FieldSpec = &super::REGISTERS[31].fields[5];
/// `SBURST`, bits 12..=14.
pub const SBURST: &FieldSpec = &super::REGISTERS[31].fields[6];
/// `DBURST`, bits 15..=17.
pub const DBURST: &FieldSpec = &super::REGISTERS[31].fields[7];
/// `TLEN`, bits 18..=24.
pub const TLEN: &FieldSpec = &super::REGISTERS[31].fields[8];
/// `PKE`, bit 25.
pub const PKE: &FieldSpec = &super::REGISTERS[31].fields[9];
/// `PAM`, bits 26..=27.
pub const PAM: &FieldSpec = &super::REGISTERS[31].fields[10];
/// `TRGM`, bits 28..=29.
pub const TRGM: &FieldSpec = &super::REGISTERS[31].fields[11];
/// `SWRM`, bit 30.
pub const SWRM: &FieldSpec = &super::REGISTERS[31].fields[12];
/// `BWM`, bit 31.
pub const BWM: &FieldSpec = &super::REGISTERS[31].fields[13];
}
/// The fields of `MDMA_C2BNDTR`.
pub mod mdma_c2bndtr {
use super::FieldSpec;
/// `BNDT`, bits 0..=16.
pub const BNDT: &FieldSpec = &super::REGISTERS[32].fields[0];
/// `BRSUM`, bit 18.
pub const BRSUM: &FieldSpec = &super::REGISTERS[32].fields[1];
/// `BRDUM`, bit 19.
pub const BRDUM: &FieldSpec = &super::REGISTERS[32].fields[2];
/// `BRC`, bits 20..=31.
pub const BRC: &FieldSpec = &super::REGISTERS[32].fields[3];
}
/// The fields of `MDMA_C2SAR`.
pub mod mdma_c2sar {
use super::FieldSpec;
/// `SAR`, bits 0..=31.
pub const SAR: &FieldSpec = &super::REGISTERS[33].fields[0];
}
/// The fields of `MDMA_C2DAR`.
pub mod mdma_c2dar {
use super::FieldSpec;
/// `DAR`, bits 0..=31.
pub const DAR: &FieldSpec = &super::REGISTERS[34].fields[0];
}
/// The fields of `MDMA_C2BRUR`.
pub mod mdma_c2brur {
use super::FieldSpec;
/// `SUV`, bits 0..=15.
pub const SUV: &FieldSpec = &super::REGISTERS[35].fields[0];
/// `DUV`, bits 16..=31.
pub const DUV: &FieldSpec = &super::REGISTERS[35].fields[1];
}
/// The fields of `MDMA_C2LAR`.
pub mod mdma_c2lar {
use super::FieldSpec;
/// `LAR`, bits 0..=31.
pub const LAR: &FieldSpec = &super::REGISTERS[36].fields[0];
}
/// The fields of `MDMA_C2TBR`.
pub mod mdma_c2tbr {
use super::FieldSpec;
/// `TSEL`, bits 0..=5.
pub const TSEL: &FieldSpec = &super::REGISTERS[37].fields[0];
/// `SBUS`, bit 16.
pub const SBUS: &FieldSpec = &super::REGISTERS[37].fields[1];
/// `DBUS`, bit 17.
pub const DBUS: &FieldSpec = &super::REGISTERS[37].fields[2];
}
/// The fields of `MDMA_C2MAR`.
pub mod mdma_c2mar {
use super::FieldSpec;
/// `MAR`, bits 0..=31.
pub const MAR: &FieldSpec = &super::REGISTERS[38].fields[0];
}
/// The fields of `MDMA_C2MDR`.
pub mod mdma_c2mdr {
use super::FieldSpec;
/// `MDR`, bits 0..=31.
pub const MDR: &FieldSpec = &super::REGISTERS[39].fields[0];
}
/// The fields of `MDMA_C3ISR`.
pub mod mdma_c3isr {
use super::FieldSpec;
/// `TEIF3`, bit 0.
pub const TEIF3: &FieldSpec = &super::REGISTERS[40].fields[0];
/// `CTCIF3`, bit 1.
pub const CTCIF3: &FieldSpec = &super::REGISTERS[40].fields[1];
/// `BRTIF3`, bit 2.
pub const BRTIF3: &FieldSpec = &super::REGISTERS[40].fields[2];
/// `BTIF3`, bit 3.
pub const BTIF3: &FieldSpec = &super::REGISTERS[40].fields[3];
/// `TCIF3`, bit 4.
pub const TCIF3: &FieldSpec = &super::REGISTERS[40].fields[4];
/// `CRQA3`, bit 16.
pub const CRQA3: &FieldSpec = &super::REGISTERS[40].fields[5];
}
/// The fields of `MDMA_C3IFCR`.
pub mod mdma_c3ifcr {
use super::FieldSpec;
/// `CTEIF3`, bit 0.
pub const CTEIF3: &FieldSpec = &super::REGISTERS[41].fields[0];
/// `CCTCIF3`, bit 1.
pub const CCTCIF3: &FieldSpec = &super::REGISTERS[41].fields[1];
/// `CBRTIF3`, bit 2.
pub const CBRTIF3: &FieldSpec = &super::REGISTERS[41].fields[2];
/// `CBTIF3`, bit 3.
pub const CBTIF3: &FieldSpec = &super::REGISTERS[41].fields[3];
/// `CLTCIF3`, bit 4.
pub const CLTCIF3: &FieldSpec = &super::REGISTERS[41].fields[4];
}
/// The fields of `MDMA_C3ESR`.
pub mod mdma_c3esr {
use super::FieldSpec;
/// `TEA`, bits 0..=6.
pub const TEA: &FieldSpec = &super::REGISTERS[42].fields[0];
/// `TED`, bit 7.
pub const TED: &FieldSpec = &super::REGISTERS[42].fields[1];
/// `TELD`, bit 8.
pub const TELD: &FieldSpec = &super::REGISTERS[42].fields[2];
/// `TEMD`, bit 9.
pub const TEMD: &FieldSpec = &super::REGISTERS[42].fields[3];
/// `ASE`, bit 10.
pub const ASE: &FieldSpec = &super::REGISTERS[42].fields[4];
/// `BSE`, bit 11.
pub const BSE: &FieldSpec = &super::REGISTERS[42].fields[5];
}
/// The fields of `MDMA_C3CR`.
pub mod mdma_c3cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[43].fields[0];
/// `TEIE`, bit 1.
pub const TEIE: &FieldSpec = &super::REGISTERS[43].fields[1];
/// `CTCIE`, bit 2.
pub const CTCIE: &FieldSpec = &super::REGISTERS[43].fields[2];
/// `BRTIE`, bit 3.
pub const BRTIE: &FieldSpec = &super::REGISTERS[43].fields[3];
/// `BTIE`, bit 4.
pub const BTIE: &FieldSpec = &super::REGISTERS[43].fields[4];
/// `TCIE`, bit 5.
pub const TCIE: &FieldSpec = &super::REGISTERS[43].fields[5];
/// `PL`, bits 6..=7.
pub const PL: &FieldSpec = &super::REGISTERS[43].fields[6];
/// `BEX`, bit 12.
pub const BEX: &FieldSpec = &super::REGISTERS[43].fields[7];
/// `HEX`, bit 13.
pub const HEX: &FieldSpec = &super::REGISTERS[43].fields[8];
/// `WEX`, bit 14.
pub const WEX: &FieldSpec = &super::REGISTERS[43].fields[9];
/// `SWRQ`, bit 16, write-only.
pub const SWRQ: &FieldSpec = &super::REGISTERS[43].fields[10];
}
/// The fields of `MDMA_C3TCR`.
pub mod mdma_c3tcr {
use super::FieldSpec;
/// `SINC`, bits 0..=1.
pub const SINC: &FieldSpec = &super::REGISTERS[44].fields[0];
/// `DINC`, bits 2..=3.
pub const DINC: &FieldSpec = &super::REGISTERS[44].fields[1];
/// `SSIZE`, bits 4..=5.
pub const SSIZE: &FieldSpec = &super::REGISTERS[44].fields[2];
/// `DSIZE`, bits 6..=7.
pub const DSIZE: &FieldSpec = &super::REGISTERS[44].fields[3];
/// `SINCOS`, bits 8..=9.
pub const SINCOS: &FieldSpec = &super::REGISTERS[44].fields[4];
/// `DINCOS`, bits 10..=11.
pub const DINCOS: &FieldSpec = &super::REGISTERS[44].fields[5];
/// `SBURST`, bits 12..=14.
pub const SBURST: &FieldSpec = &super::REGISTERS[44].fields[6];
/// `DBURST`, bits 15..=17.
pub const DBURST: &FieldSpec = &super::REGISTERS[44].fields[7];
/// `TLEN`, bits 18..=24.
pub const TLEN: &FieldSpec = &super::REGISTERS[44].fields[8];
/// `PKE`, bit 25.
pub const PKE: &FieldSpec = &super::REGISTERS[44].fields[9];
/// `PAM`, bits 26..=27.
pub const PAM: &FieldSpec = &super::REGISTERS[44].fields[10];
/// `TRGM`, bits 28..=29.
pub const TRGM: &FieldSpec = &super::REGISTERS[44].fields[11];
/// `SWRM`, bit 30.
pub const SWRM: &FieldSpec = &super::REGISTERS[44].fields[12];
/// `BWM`, bit 31.
pub const BWM: &FieldSpec = &super::REGISTERS[44].fields[13];
}
/// The fields of `MDMA_C3BNDTR`.
pub mod mdma_c3bndtr {
use super::FieldSpec;
/// `BNDT`, bits 0..=16.
pub const BNDT: &FieldSpec = &super::REGISTERS[45].fields[0];
/// `BRSUM`, bit 18.
pub const BRSUM: &FieldSpec = &super::REGISTERS[45].fields[1];
/// `BRDUM`, bit 19.
pub const BRDUM: &FieldSpec = &super::REGISTERS[45].fields[2];
/// `BRC`, bits 20..=31.
pub const BRC: &FieldSpec = &super::REGISTERS[45].fields[3];
}
/// The fields of `MDMA_C3SAR`.
pub mod mdma_c3sar {
use super::FieldSpec;
/// `SAR`, bits 0..=31.
pub const SAR: &FieldSpec = &super::REGISTERS[46].fields[0];
}
/// The fields of `MDMA_C3DAR`.
pub mod mdma_c3dar {
use super::FieldSpec;
/// `DAR`, bits 0..=31.
pub const DAR: &FieldSpec = &super::REGISTERS[47].fields[0];
}
/// The fields of `MDMA_C3BRUR`.
pub mod mdma_c3brur {
use super::FieldSpec;
/// `SUV`, bits 0..=15.
pub const SUV: &FieldSpec = &super::REGISTERS[48].fields[0];
/// `DUV`, bits 16..=31.
pub const DUV: &FieldSpec = &super::REGISTERS[48].fields[1];
}
/// The fields of `MDMA_C3LAR`.
pub mod mdma_c3lar {
use super::FieldSpec;
/// `LAR`, bits 0..=31.
pub const LAR: &FieldSpec = &super::REGISTERS[49].fields[0];
}
/// The fields of `MDMA_C3TBR`.
pub mod mdma_c3tbr {
use super::FieldSpec;
/// `TSEL`, bits 0..=5.
pub const TSEL: &FieldSpec = &super::REGISTERS[50].fields[0];
/// `SBUS`, bit 16.
pub const SBUS: &FieldSpec = &super::REGISTERS[50].fields[1];
/// `DBUS`, bit 17.
pub const DBUS: &FieldSpec = &super::REGISTERS[50].fields[2];
}
/// The fields of `MDMA_C3MAR`.
pub mod mdma_c3mar {
use super::FieldSpec;
/// `MAR`, bits 0..=31.
pub const MAR: &FieldSpec = &super::REGISTERS[51].fields[0];
}
/// The fields of `MDMA_C3MDR`.
pub mod mdma_c3mdr {
use super::FieldSpec;
/// `MDR`, bits 0..=31.
pub const MDR: &FieldSpec = &super::REGISTERS[52].fields[0];
}
/// The fields of `MDMA_C4ISR`.
pub mod mdma_c4isr {
use super::FieldSpec;
/// `TEIF4`, bit 0.
pub const TEIF4: &FieldSpec = &super::REGISTERS[53].fields[0];
/// `CTCIF4`, bit 1.
pub const CTCIF4: &FieldSpec = &super::REGISTERS[53].fields[1];
/// `BRTIF4`, bit 2.
pub const BRTIF4: &FieldSpec = &super::REGISTERS[53].fields[2];
/// `BTIF4`, bit 3.
pub const BTIF4: &FieldSpec = &super::REGISTERS[53].fields[3];
/// `TCIF4`, bit 4.
pub const TCIF4: &FieldSpec = &super::REGISTERS[53].fields[4];
/// `CRQA4`, bit 16.
pub const CRQA4: &FieldSpec = &super::REGISTERS[53].fields[5];
}
/// The fields of `MDMA_C4IFCR`.
pub mod mdma_c4ifcr {
use super::FieldSpec;
/// `CTEIF4`, bit 0.
pub const CTEIF4: &FieldSpec = &super::REGISTERS[54].fields[0];
/// `CCTCIF4`, bit 1.
pub const CCTCIF4: &FieldSpec = &super::REGISTERS[54].fields[1];
/// `CBRTIF4`, bit 2.
pub const CBRTIF4: &FieldSpec = &super::REGISTERS[54].fields[2];
/// `CBTIF4`, bit 3.
pub const CBTIF4: &FieldSpec = &super::REGISTERS[54].fields[3];
/// `CLTCIF4`, bit 4.
pub const CLTCIF4: &FieldSpec = &super::REGISTERS[54].fields[4];
}
/// The fields of `MDMA_C4ESR`.
pub mod mdma_c4esr {
use super::FieldSpec;
/// `TEA`, bits 0..=6.
pub const TEA: &FieldSpec = &super::REGISTERS[55].fields[0];
/// `TED`, bit 7.
pub const TED: &FieldSpec = &super::REGISTERS[55].fields[1];
/// `TELD`, bit 8.
pub const TELD: &FieldSpec = &super::REGISTERS[55].fields[2];
/// `TEMD`, bit 9.
pub const TEMD: &FieldSpec = &super::REGISTERS[55].fields[3];
/// `ASE`, bit 10.
pub const ASE: &FieldSpec = &super::REGISTERS[55].fields[4];
/// `BSE`, bit 11.
pub const BSE: &FieldSpec = &super::REGISTERS[55].fields[5];
}
/// The fields of `MDMA_C4CR`.
pub mod mdma_c4cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[56].fields[0];
/// `TEIE`, bit 1.
pub const TEIE: &FieldSpec = &super::REGISTERS[56].fields[1];
/// `CTCIE`, bit 2.
pub const CTCIE: &FieldSpec = &super::REGISTERS[56].fields[2];
/// `BRTIE`, bit 3.
pub const BRTIE: &FieldSpec = &super::REGISTERS[56].fields[3];
/// `BTIE`, bit 4.
pub const BTIE: &FieldSpec = &super::REGISTERS[56].fields[4];
/// `TCIE`, bit 5.
pub const TCIE: &FieldSpec = &super::REGISTERS[56].fields[5];
/// `PL`, bits 6..=7.
pub const PL: &FieldSpec = &super::REGISTERS[56].fields[6];
/// `BEX`, bit 12.
pub const BEX: &FieldSpec = &super::REGISTERS[56].fields[7];
/// `HEX`, bit 13.
pub const HEX: &FieldSpec = &super::REGISTERS[56].fields[8];
/// `WEX`, bit 14.
pub const WEX: &FieldSpec = &super::REGISTERS[56].fields[9];
/// `SWRQ`, bit 16, write-only.
pub const SWRQ: &FieldSpec = &super::REGISTERS[56].fields[10];
}
/// The fields of `MDMA_C4TCR`.
pub mod mdma_c4tcr {
use super::FieldSpec;
/// `SINC`, bits 0..=1.
pub const SINC: &FieldSpec = &super::REGISTERS[57].fields[0];
/// `DINC`, bits 2..=3.
pub const DINC: &FieldSpec = &super::REGISTERS[57].fields[1];
/// `SSIZE`, bits 4..=5.
pub const SSIZE: &FieldSpec = &super::REGISTERS[57].fields[2];
/// `DSIZE`, bits 6..=7.
pub const DSIZE: &FieldSpec = &super::REGISTERS[57].fields[3];
/// `SINCOS`, bits 8..=9.
pub const SINCOS: &FieldSpec = &super::REGISTERS[57].fields[4];
/// `DINCOS`, bits 10..=11.
pub const DINCOS: &FieldSpec = &super::REGISTERS[57].fields[5];
/// `SBURST`, bits 12..=14.
pub const SBURST: &FieldSpec = &super::REGISTERS[57].fields[6];
/// `DBURST`, bits 15..=17.
pub const DBURST: &FieldSpec = &super::REGISTERS[57].fields[7];
/// `TLEN`, bits 18..=24.
pub const TLEN: &FieldSpec = &super::REGISTERS[57].fields[8];
/// `PKE`, bit 25.
pub const PKE: &FieldSpec = &super::REGISTERS[57].fields[9];
/// `PAM`, bits 26..=27.
pub const PAM: &FieldSpec = &super::REGISTERS[57].fields[10];
/// `TRGM`, bits 28..=29.
pub const TRGM: &FieldSpec = &super::REGISTERS[57].fields[11];
/// `SWRM`, bit 30.
pub const SWRM: &FieldSpec = &super::REGISTERS[57].fields[12];
/// `BWM`, bit 31.
pub const BWM: &FieldSpec = &super::REGISTERS[57].fields[13];
}
/// The fields of `MDMA_C4BNDTR`.
pub mod mdma_c4bndtr {
use super::FieldSpec;
/// `BNDT`, bits 0..=16.
pub const BNDT: &FieldSpec = &super::REGISTERS[58].fields[0];
/// `BRSUM`, bit 18.
pub const BRSUM: &FieldSpec = &super::REGISTERS[58].fields[1];
/// `BRDUM`, bit 19.
pub const BRDUM: &FieldSpec = &super::REGISTERS[58].fields[2];
/// `BRC`, bits 20..=31.
pub const BRC: &FieldSpec = &super::REGISTERS[58].fields[3];
}
/// The fields of `MDMA_C4SAR`.
pub mod mdma_c4sar {
use super::FieldSpec;
/// `SAR`, bits 0..=31.
pub const SAR: &FieldSpec = &super::REGISTERS[59].fields[0];
}
/// The fields of `MDMA_C4DAR`.
pub mod mdma_c4dar {
use super::FieldSpec;
/// `DAR`, bits 0..=31.
pub const DAR: &FieldSpec = &super::REGISTERS[60].fields[0];
}
/// The fields of `MDMA_C4BRUR`.
pub mod mdma_c4brur {
use super::FieldSpec;
/// `SUV`, bits 0..=15.
pub const SUV: &FieldSpec = &super::REGISTERS[61].fields[0];
/// `DUV`, bits 16..=31.
pub const DUV: &FieldSpec = &super::REGISTERS[61].fields[1];
}
/// The fields of `MDMA_C4LAR`.
pub mod mdma_c4lar {
use super::FieldSpec;
/// `LAR`, bits 0..=31.
pub const LAR: &FieldSpec = &super::REGISTERS[62].fields[0];
}
/// The fields of `MDMA_C4TBR`.
pub mod mdma_c4tbr {
use super::FieldSpec;
/// `TSEL`, bits 0..=5.
pub const TSEL: &FieldSpec = &super::REGISTERS[63].fields[0];
/// `SBUS`, bit 16.
pub const SBUS: &FieldSpec = &super::REGISTERS[63].fields[1];
/// `DBUS`, bit 17.
pub const DBUS: &FieldSpec = &super::REGISTERS[63].fields[2];
}
/// The fields of `MDMA_C4MAR`.
pub mod mdma_c4mar {
use super::FieldSpec;
/// `MAR`, bits 0..=31.
pub const MAR: &FieldSpec = &super::REGISTERS[64].fields[0];
}
/// The fields of `MDMA_C4MDR`.
pub mod mdma_c4mdr {
use super::FieldSpec;
/// `MDR`, bits 0..=31.
pub const MDR: &FieldSpec = &super::REGISTERS[65].fields[0];
}
/// The fields of `MDMA_C5ISR`.
pub mod mdma_c5isr {
use super::FieldSpec;
/// `TEIF5`, bit 0.
pub const TEIF5: &FieldSpec = &super::REGISTERS[66].fields[0];
/// `CTCIF5`, bit 1.
pub const CTCIF5: &FieldSpec = &super::REGISTERS[66].fields[1];
/// `BRTIF5`, bit 2.
pub const BRTIF5: &FieldSpec = &super::REGISTERS[66].fields[2];
/// `BTIF5`, bit 3.
pub const BTIF5: &FieldSpec = &super::REGISTERS[66].fields[3];
/// `TCIF5`, bit 4.
pub const TCIF5: &FieldSpec = &super::REGISTERS[66].fields[4];
/// `CRQA5`, bit 16.
pub const CRQA5: &FieldSpec = &super::REGISTERS[66].fields[5];
}
/// The fields of `MDMA_C5IFCR`.
pub mod mdma_c5ifcr {
use super::FieldSpec;
/// `CTEIF5`, bit 0.
pub const CTEIF5: &FieldSpec = &super::REGISTERS[67].fields[0];
/// `CCTCIF5`, bit 1.
pub const CCTCIF5: &FieldSpec = &super::REGISTERS[67].fields[1];
/// `CBRTIF5`, bit 2.
pub const CBRTIF5: &FieldSpec = &super::REGISTERS[67].fields[2];
/// `CBTIF5`, bit 3.
pub const CBTIF5: &FieldSpec = &super::REGISTERS[67].fields[3];
/// `CLTCIF5`, bit 4.
pub const CLTCIF5: &FieldSpec = &super::REGISTERS[67].fields[4];
}
/// The fields of `MDMA_C5ESR`.
pub mod mdma_c5esr {
use super::FieldSpec;
/// `TEA`, bits 0..=6.
pub const TEA: &FieldSpec = &super::REGISTERS[68].fields[0];
/// `TED`, bit 7.
pub const TED: &FieldSpec = &super::REGISTERS[68].fields[1];
/// `TELD`, bit 8.
pub const TELD: &FieldSpec = &super::REGISTERS[68].fields[2];
/// `TEMD`, bit 9.
pub const TEMD: &FieldSpec = &super::REGISTERS[68].fields[3];
/// `ASE`, bit 10.
pub const ASE: &FieldSpec = &super::REGISTERS[68].fields[4];
/// `BSE`, bit 11.
pub const BSE: &FieldSpec = &super::REGISTERS[68].fields[5];
}
/// The fields of `MDMA_C5CR`.
pub mod mdma_c5cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[69].fields[0];
/// `TEIE`, bit 1.
pub const TEIE: &FieldSpec = &super::REGISTERS[69].fields[1];
/// `CTCIE`, bit 2.
pub const CTCIE: &FieldSpec = &super::REGISTERS[69].fields[2];
/// `BRTIE`, bit 3.
pub const BRTIE: &FieldSpec = &super::REGISTERS[69].fields[3];
/// `BTIE`, bit 4.
pub const BTIE: &FieldSpec = &super::REGISTERS[69].fields[4];
/// `TCIE`, bit 5.
pub const TCIE: &FieldSpec = &super::REGISTERS[69].fields[5];
/// `PL`, bits 6..=7.
pub const PL: &FieldSpec = &super::REGISTERS[69].fields[6];
/// `BEX`, bit 12.
pub const BEX: &FieldSpec = &super::REGISTERS[69].fields[7];
/// `HEX`, bit 13.
pub const HEX: &FieldSpec = &super::REGISTERS[69].fields[8];
/// `WEX`, bit 14.
pub const WEX: &FieldSpec = &super::REGISTERS[69].fields[9];
/// `SWRQ`, bit 16, write-only.
pub const SWRQ: &FieldSpec = &super::REGISTERS[69].fields[10];
}
/// The fields of `MDMA_C5TCR`.
pub mod mdma_c5tcr {
use super::FieldSpec;
/// `SINC`, bits 0..=1.
pub const SINC: &FieldSpec = &super::REGISTERS[70].fields[0];
/// `DINC`, bits 2..=3.
pub const DINC: &FieldSpec = &super::REGISTERS[70].fields[1];
/// `SSIZE`, bits 4..=5.
pub const SSIZE: &FieldSpec = &super::REGISTERS[70].fields[2];
/// `DSIZE`, bits 6..=7.
pub const DSIZE: &FieldSpec = &super::REGISTERS[70].fields[3];
/// `SINCOS`, bits 8..=9.
pub const SINCOS: &FieldSpec = &super::REGISTERS[70].fields[4];
/// `DINCOS`, bits 10..=11.
pub const DINCOS: &FieldSpec = &super::REGISTERS[70].fields[5];
/// `SBURST`, bits 12..=14.
pub const SBURST: &FieldSpec = &super::REGISTERS[70].fields[6];
/// `DBURST`, bits 15..=17.
pub const DBURST: &FieldSpec = &super::REGISTERS[70].fields[7];
/// `TLEN`, bits 18..=24.
pub const TLEN: &FieldSpec = &super::REGISTERS[70].fields[8];
/// `PKE`, bit 25.
pub const PKE: &FieldSpec = &super::REGISTERS[70].fields[9];
/// `PAM`, bits 26..=27.
pub const PAM: &FieldSpec = &super::REGISTERS[70].fields[10];
/// `TRGM`, bits 28..=29.
pub const TRGM: &FieldSpec = &super::REGISTERS[70].fields[11];
/// `SWRM`, bit 30.
pub const SWRM: &FieldSpec = &super::REGISTERS[70].fields[12];
/// `BWM`, bit 31.
pub const BWM: &FieldSpec = &super::REGISTERS[70].fields[13];
}
/// The fields of `MDMA_C5BNDTR`.
pub mod mdma_c5bndtr {
use super::FieldSpec;
/// `BNDT`, bits 0..=16.
pub const BNDT: &FieldSpec = &super::REGISTERS[71].fields[0];
/// `BRSUM`, bit 18.
pub const BRSUM: &FieldSpec = &super::REGISTERS[71].fields[1];
/// `BRDUM`, bit 19.
pub const BRDUM: &FieldSpec = &super::REGISTERS[71].fields[2];
/// `BRC`, bits 20..=31.
pub const BRC: &FieldSpec = &super::REGISTERS[71].fields[3];
}
/// The fields of `MDMA_C5SAR`.
pub mod mdma_c5sar {
use super::FieldSpec;
/// `SAR`, bits 0..=31.
pub const SAR: &FieldSpec = &super::REGISTERS[72].fields[0];
}
/// The fields of `MDMA_C5DAR`.
pub mod mdma_c5dar {
use super::FieldSpec;
/// `DAR`, bits 0..=31.
pub const DAR: &FieldSpec = &super::REGISTERS[73].fields[0];
}
/// The fields of `MDMA_C5BRUR`.
pub mod mdma_c5brur {
use super::FieldSpec;
/// `SUV`, bits 0..=15.
pub const SUV: &FieldSpec = &super::REGISTERS[74].fields[0];
/// `DUV`, bits 16..=31.
pub const DUV: &FieldSpec = &super::REGISTERS[74].fields[1];
}
/// The fields of `MDMA_C5LAR`.
pub mod mdma_c5lar {
use super::FieldSpec;
/// `LAR`, bits 0..=31.
pub const LAR: &FieldSpec = &super::REGISTERS[75].fields[0];
}
/// The fields of `MDMA_C5TBR`.
pub mod mdma_c5tbr {
use super::FieldSpec;
/// `TSEL`, bits 0..=5.
pub const TSEL: &FieldSpec = &super::REGISTERS[76].fields[0];
/// `SBUS`, bit 16.
pub const SBUS: &FieldSpec = &super::REGISTERS[76].fields[1];
/// `DBUS`, bit 17.
pub const DBUS: &FieldSpec = &super::REGISTERS[76].fields[2];
}
/// The fields of `MDMA_C5MAR`.
pub mod mdma_c5mar {
use super::FieldSpec;
/// `MAR`, bits 0..=31.
pub const MAR: &FieldSpec = &super::REGISTERS[77].fields[0];
}
/// The fields of `MDMA_C5MDR`.
pub mod mdma_c5mdr {
use super::FieldSpec;
/// `MDR`, bits 0..=31.
pub const MDR: &FieldSpec = &super::REGISTERS[78].fields[0];
}
/// The fields of `MDMA_C6ISR`.
pub mod mdma_c6isr {
use super::FieldSpec;
/// `TEIF6`, bit 0.
pub const TEIF6: &FieldSpec = &super::REGISTERS[79].fields[0];
/// `CTCIF6`, bit 1.
pub const CTCIF6: &FieldSpec = &super::REGISTERS[79].fields[1];
/// `BRTIF6`, bit 2.
pub const BRTIF6: &FieldSpec = &super::REGISTERS[79].fields[2];
/// `BTIF6`, bit 3.
pub const BTIF6: &FieldSpec = &super::REGISTERS[79].fields[3];
/// `TCIF6`, bit 4.
pub const TCIF6: &FieldSpec = &super::REGISTERS[79].fields[4];
/// `CRQA6`, bit 16.
pub const CRQA6: &FieldSpec = &super::REGISTERS[79].fields[5];
}
/// The fields of `MDMA_C6IFCR`.
pub mod mdma_c6ifcr {
use super::FieldSpec;
/// `CTEIF6`, bit 0.
pub const CTEIF6: &FieldSpec = &super::REGISTERS[80].fields[0];
/// `CCTCIF6`, bit 1.
pub const CCTCIF6: &FieldSpec = &super::REGISTERS[80].fields[1];
/// `CBRTIF6`, bit 2.
pub const CBRTIF6: &FieldSpec = &super::REGISTERS[80].fields[2];
/// `CBTIF6`, bit 3.
pub const CBTIF6: &FieldSpec = &super::REGISTERS[80].fields[3];
/// `CLTCIF6`, bit 4.
pub const CLTCIF6: &FieldSpec = &super::REGISTERS[80].fields[4];
}
/// The fields of `MDMA_C6ESR`.
pub mod mdma_c6esr {
use super::FieldSpec;
/// `TEA`, bits 0..=6.
pub const TEA: &FieldSpec = &super::REGISTERS[81].fields[0];
/// `TED`, bit 7.
pub const TED: &FieldSpec = &super::REGISTERS[81].fields[1];
/// `TELD`, bit 8.
pub const TELD: &FieldSpec = &super::REGISTERS[81].fields[2];
/// `TEMD`, bit 9.
pub const TEMD: &FieldSpec = &super::REGISTERS[81].fields[3];
/// `ASE`, bit 10.
pub const ASE: &FieldSpec = &super::REGISTERS[81].fields[4];
/// `BSE`, bit 11.
pub const BSE: &FieldSpec = &super::REGISTERS[81].fields[5];
}
/// The fields of `MDMA_C6CR`.
pub mod mdma_c6cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[82].fields[0];
/// `TEIE`, bit 1.
pub const TEIE: &FieldSpec = &super::REGISTERS[82].fields[1];
/// `CTCIE`, bit 2.
pub const CTCIE: &FieldSpec = &super::REGISTERS[82].fields[2];
/// `BRTIE`, bit 3.
pub const BRTIE: &FieldSpec = &super::REGISTERS[82].fields[3];
/// `BTIE`, bit 4.
pub const BTIE: &FieldSpec = &super::REGISTERS[82].fields[4];
/// `TCIE`, bit 5.
pub const TCIE: &FieldSpec = &super::REGISTERS[82].fields[5];
/// `PL`, bits 6..=7.
pub const PL: &FieldSpec = &super::REGISTERS[82].fields[6];
/// `BEX`, bit 12.
pub const BEX: &FieldSpec = &super::REGISTERS[82].fields[7];
/// `HEX`, bit 13.
pub const HEX: &FieldSpec = &super::REGISTERS[82].fields[8];
/// `WEX`, bit 14.
pub const WEX: &FieldSpec = &super::REGISTERS[82].fields[9];
/// `SWRQ`, bit 16, write-only.
pub const SWRQ: &FieldSpec = &super::REGISTERS[82].fields[10];
}
/// The fields of `MDMA_C6TCR`.
pub mod mdma_c6tcr {
use super::FieldSpec;
/// `SINC`, bits 0..=1.
pub const SINC: &FieldSpec = &super::REGISTERS[83].fields[0];
/// `DINC`, bits 2..=3.
pub const DINC: &FieldSpec = &super::REGISTERS[83].fields[1];
/// `SSIZE`, bits 4..=5.
pub const SSIZE: &FieldSpec = &super::REGISTERS[83].fields[2];
/// `DSIZE`, bits 6..=7.
pub const DSIZE: &FieldSpec = &super::REGISTERS[83].fields[3];
/// `SINCOS`, bits 8..=9.
pub const SINCOS: &FieldSpec = &super::REGISTERS[83].fields[4];
/// `DINCOS`, bits 10..=11.
pub const DINCOS: &FieldSpec = &super::REGISTERS[83].fields[5];
/// `SBURST`, bits 12..=14.
pub const SBURST: &FieldSpec = &super::REGISTERS[83].fields[6];
/// `DBURST`, bits 15..=17.
pub const DBURST: &FieldSpec = &super::REGISTERS[83].fields[7];
/// `TLEN`, bits 18..=24.
pub const TLEN: &FieldSpec = &super::REGISTERS[83].fields[8];
/// `PKE`, bit 25.
pub const PKE: &FieldSpec = &super::REGISTERS[83].fields[9];
/// `PAM`, bits 26..=27.
pub const PAM: &FieldSpec = &super::REGISTERS[83].fields[10];
/// `TRGM`, bits 28..=29.
pub const TRGM: &FieldSpec = &super::REGISTERS[83].fields[11];
/// `SWRM`, bit 30.
pub const SWRM: &FieldSpec = &super::REGISTERS[83].fields[12];
/// `BWM`, bit 31.
pub const BWM: &FieldSpec = &super::REGISTERS[83].fields[13];
}
/// The fields of `MDMA_C6BNDTR`.
pub mod mdma_c6bndtr {
use super::FieldSpec;
/// `BNDT`, bits 0..=16.
pub const BNDT: &FieldSpec = &super::REGISTERS[84].fields[0];
/// `BRSUM`, bit 18.
pub const BRSUM: &FieldSpec = &super::REGISTERS[84].fields[1];
/// `BRDUM`, bit 19.
pub const BRDUM: &FieldSpec = &super::REGISTERS[84].fields[2];
/// `BRC`, bits 20..=31.
pub const BRC: &FieldSpec = &super::REGISTERS[84].fields[3];
}
/// The fields of `MDMA_C6SAR`.
pub mod mdma_c6sar {
use super::FieldSpec;
/// `SAR`, bits 0..=31.
pub const SAR: &FieldSpec = &super::REGISTERS[85].fields[0];
}
/// The fields of `MDMA_C6DAR`.
pub mod mdma_c6dar {
use super::FieldSpec;
/// `DAR`, bits 0..=31.
pub const DAR: &FieldSpec = &super::REGISTERS[86].fields[0];
}
/// The fields of `MDMA_C6BRUR`.
pub mod mdma_c6brur {
use super::FieldSpec;
/// `SUV`, bits 0..=15.
pub const SUV: &FieldSpec = &super::REGISTERS[87].fields[0];
/// `DUV`, bits 16..=31.
pub const DUV: &FieldSpec = &super::REGISTERS[87].fields[1];
}
/// The fields of `MDMA_C6LAR`.
pub mod mdma_c6lar {
use super::FieldSpec;
/// `LAR`, bits 0..=31.
pub const LAR: &FieldSpec = &super::REGISTERS[88].fields[0];
}
/// The fields of `MDMA_C6TBR`.
pub mod mdma_c6tbr {
use super::FieldSpec;
/// `TSEL`, bits 0..=5.
pub const TSEL: &FieldSpec = &super::REGISTERS[89].fields[0];
/// `SBUS`, bit 16.
pub const SBUS: &FieldSpec = &super::REGISTERS[89].fields[1];
/// `DBUS`, bit 17.
pub const DBUS: &FieldSpec = &super::REGISTERS[89].fields[2];
}
/// The fields of `MDMA_C6MAR`.
pub mod mdma_c6mar {
use super::FieldSpec;
/// `MAR`, bits 0..=31.
pub const MAR: &FieldSpec = &super::REGISTERS[90].fields[0];
}
/// The fields of `MDMA_C6MDR`.
pub mod mdma_c6mdr {
use super::FieldSpec;
/// `MDR`, bits 0..=31.
pub const MDR: &FieldSpec = &super::REGISTERS[91].fields[0];
}
/// The fields of `MDMA_C7ISR`.
pub mod mdma_c7isr {
use super::FieldSpec;
/// `TEIF7`, bit 0.
pub const TEIF7: &FieldSpec = &super::REGISTERS[92].fields[0];
/// `CTCIF7`, bit 1.
pub const CTCIF7: &FieldSpec = &super::REGISTERS[92].fields[1];
/// `BRTIF7`, bit 2.
pub const BRTIF7: &FieldSpec = &super::REGISTERS[92].fields[2];
/// `BTIF7`, bit 3.
pub const BTIF7: &FieldSpec = &super::REGISTERS[92].fields[3];
/// `TCIF7`, bit 4.
pub const TCIF7: &FieldSpec = &super::REGISTERS[92].fields[4];
/// `CRQA7`, bit 16.
pub const CRQA7: &FieldSpec = &super::REGISTERS[92].fields[5];
}
/// The fields of `MDMA_C7IFCR`.
pub mod mdma_c7ifcr {
use super::FieldSpec;
/// `CTEIF7`, bit 0.
pub const CTEIF7: &FieldSpec = &super::REGISTERS[93].fields[0];
/// `CCTCIF7`, bit 1.
pub const CCTCIF7: &FieldSpec = &super::REGISTERS[93].fields[1];
/// `CBRTIF7`, bit 2.
pub const CBRTIF7: &FieldSpec = &super::REGISTERS[93].fields[2];
/// `CBTIF7`, bit 3.
pub const CBTIF7: &FieldSpec = &super::REGISTERS[93].fields[3];
/// `CLTCIF7`, bit 4.
pub const CLTCIF7: &FieldSpec = &super::REGISTERS[93].fields[4];
}
/// The fields of `MDMA_C7ESR`.
pub mod mdma_c7esr {
use super::FieldSpec;
/// `TEA`, bits 0..=6.
pub const TEA: &FieldSpec = &super::REGISTERS[94].fields[0];
/// `TED`, bit 7.
pub const TED: &FieldSpec = &super::REGISTERS[94].fields[1];
/// `TELD`, bit 8.
pub const TELD: &FieldSpec = &super::REGISTERS[94].fields[2];
/// `TEMD`, bit 9.
pub const TEMD: &FieldSpec = &super::REGISTERS[94].fields[3];
/// `ASE`, bit 10.
pub const ASE: &FieldSpec = &super::REGISTERS[94].fields[4];
/// `BSE`, bit 11.
pub const BSE: &FieldSpec = &super::REGISTERS[94].fields[5];
}
/// The fields of `MDMA_C7CR`.
pub mod mdma_c7cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[95].fields[0];
/// `TEIE`, bit 1.
pub const TEIE: &FieldSpec = &super::REGISTERS[95].fields[1];
/// `CTCIE`, bit 2.
pub const CTCIE: &FieldSpec = &super::REGISTERS[95].fields[2];
/// `BRTIE`, bit 3.
pub const BRTIE: &FieldSpec = &super::REGISTERS[95].fields[3];
/// `BTIE`, bit 4.
pub const BTIE: &FieldSpec = &super::REGISTERS[95].fields[4];
/// `TCIE`, bit 5.
pub const TCIE: &FieldSpec = &super::REGISTERS[95].fields[5];
/// `PL`, bits 6..=7.
pub const PL: &FieldSpec = &super::REGISTERS[95].fields[6];
/// `BEX`, bit 12.
pub const BEX: &FieldSpec = &super::REGISTERS[95].fields[7];
/// `HEX`, bit 13.
pub const HEX: &FieldSpec = &super::REGISTERS[95].fields[8];
/// `WEX`, bit 14.
pub const WEX: &FieldSpec = &super::REGISTERS[95].fields[9];
/// `SWRQ`, bit 16, write-only.
pub const SWRQ: &FieldSpec = &super::REGISTERS[95].fields[10];
}
/// The fields of `MDMA_C7TCR`.
pub mod mdma_c7tcr {
use super::FieldSpec;
/// `SINC`, bits 0..=1.
pub const SINC: &FieldSpec = &super::REGISTERS[96].fields[0];
/// `DINC`, bits 2..=3.
pub const DINC: &FieldSpec = &super::REGISTERS[96].fields[1];
/// `SSIZE`, bits 4..=5.
pub const SSIZE: &FieldSpec = &super::REGISTERS[96].fields[2];
/// `DSIZE`, bits 6..=7.
pub const DSIZE: &FieldSpec = &super::REGISTERS[96].fields[3];
/// `SINCOS`, bits 8..=9.
pub const SINCOS: &FieldSpec = &super::REGISTERS[96].fields[4];
/// `DINCOS`, bits 10..=11.
pub const DINCOS: &FieldSpec = &super::REGISTERS[96].fields[5];
/// `SBURST`, bits 12..=14.
pub const SBURST: &FieldSpec = &super::REGISTERS[96].fields[6];
/// `DBURST`, bits 15..=17.
pub const DBURST: &FieldSpec = &super::REGISTERS[96].fields[7];
/// `TLEN`, bits 18..=24.
pub const TLEN: &FieldSpec = &super::REGISTERS[96].fields[8];
/// `PKE`, bit 25.
pub const PKE: &FieldSpec = &super::REGISTERS[96].fields[9];
/// `PAM`, bits 26..=27.
pub const PAM: &FieldSpec = &super::REGISTERS[96].fields[10];
/// `TRGM`, bits 28..=29.
pub const TRGM: &FieldSpec = &super::REGISTERS[96].fields[11];
/// `SWRM`, bit 30.
pub const SWRM: &FieldSpec = &super::REGISTERS[96].fields[12];
/// `BWM`, bit 31.
pub const BWM: &FieldSpec = &super::REGISTERS[96].fields[13];
}
/// The fields of `MDMA_C7BNDTR`.
pub mod mdma_c7bndtr {
use super::FieldSpec;
/// `BNDT`, bits 0..=16.
pub const BNDT: &FieldSpec = &super::REGISTERS[97].fields[0];
/// `BRSUM`, bit 18.
pub const BRSUM: &FieldSpec = &super::REGISTERS[97].fields[1];
/// `BRDUM`, bit 19.
pub const BRDUM: &FieldSpec = &super::REGISTERS[97].fields[2];
/// `BRC`, bits 20..=31.
pub const BRC: &FieldSpec = &super::REGISTERS[97].fields[3];
}
/// The fields of `MDMA_C7SAR`.
pub mod mdma_c7sar {
use super::FieldSpec;
/// `SAR`, bits 0..=31.
pub const SAR: &FieldSpec = &super::REGISTERS[98].fields[0];
}
/// The fields of `MDMA_C7DAR`.
pub mod mdma_c7dar {
use super::FieldSpec;
/// `DAR`, bits 0..=31.
pub const DAR: &FieldSpec = &super::REGISTERS[99].fields[0];
}
/// The fields of `MDMA_C7BRUR`.
pub mod mdma_c7brur {
use super::FieldSpec;
/// `SUV`, bits 0..=15.
pub const SUV: &FieldSpec = &super::REGISTERS[100].fields[0];
/// `DUV`, bits 16..=31.
pub const DUV: &FieldSpec = &super::REGISTERS[100].fields[1];
}
/// The fields of `MDMA_C7LAR`.
pub mod mdma_c7lar {
use super::FieldSpec;
/// `LAR`, bits 0..=31.
pub const LAR: &FieldSpec = &super::REGISTERS[101].fields[0];
}
/// The fields of `MDMA_C7TBR`.
pub mod mdma_c7tbr {
use super::FieldSpec;
/// `TSEL`, bits 0..=5.
pub const TSEL: &FieldSpec = &super::REGISTERS[102].fields[0];
/// `SBUS`, bit 16.
pub const SBUS: &FieldSpec = &super::REGISTERS[102].fields[1];
/// `DBUS`, bit 17.
pub const DBUS: &FieldSpec = &super::REGISTERS[102].fields[2];
}
/// The fields of `MDMA_C7MAR`.
pub mod mdma_c7mar {
use super::FieldSpec;
/// `MAR`, bits 0..=31.
pub const MAR: &FieldSpec = &super::REGISTERS[103].fields[0];
}
/// The fields of `MDMA_C7MDR`.
pub mod mdma_c7mdr {
use super::FieldSpec;
/// `MDR`, bits 0..=31.
pub const MDR: &FieldSpec = &super::REGISTERS[104].fields[0];
}
/// The fields of `MDMA_C8ISR`.
pub mod mdma_c8isr {
use super::FieldSpec;
/// `TEIF8`, bit 0.
pub const TEIF8: &FieldSpec = &super::REGISTERS[105].fields[0];
/// `CTCIF8`, bit 1.
pub const CTCIF8: &FieldSpec = &super::REGISTERS[105].fields[1];
/// `BRTIF8`, bit 2.
pub const BRTIF8: &FieldSpec = &super::REGISTERS[105].fields[2];
/// `BTIF8`, bit 3.
pub const BTIF8: &FieldSpec = &super::REGISTERS[105].fields[3];
/// `TCIF8`, bit 4.
pub const TCIF8: &FieldSpec = &super::REGISTERS[105].fields[4];
/// `CRQA8`, bit 16.
pub const CRQA8: &FieldSpec = &super::REGISTERS[105].fields[5];
}
/// The fields of `MDMA_C8IFCR`.
pub mod mdma_c8ifcr {
use super::FieldSpec;
/// `CTEIF8`, bit 0.
pub const CTEIF8: &FieldSpec = &super::REGISTERS[106].fields[0];
/// `CCTCIF8`, bit 1.
pub const CCTCIF8: &FieldSpec = &super::REGISTERS[106].fields[1];
/// `CBRTIF8`, bit 2.
pub const CBRTIF8: &FieldSpec = &super::REGISTERS[106].fields[2];
/// `CBTIF8`, bit 3.
pub const CBTIF8: &FieldSpec = &super::REGISTERS[106].fields[3];
/// `CLTCIF8`, bit 4.
pub const CLTCIF8: &FieldSpec = &super::REGISTERS[106].fields[4];
}
/// The fields of `MDMA_C8ESR`.
pub mod mdma_c8esr {
use super::FieldSpec;
/// `TEA`, bits 0..=6.
pub const TEA: &FieldSpec = &super::REGISTERS[107].fields[0];
/// `TED`, bit 7.
pub const TED: &FieldSpec = &super::REGISTERS[107].fields[1];
/// `TELD`, bit 8.
pub const TELD: &FieldSpec = &super::REGISTERS[107].fields[2];
/// `TEMD`, bit 9.
pub const TEMD: &FieldSpec = &super::REGISTERS[107].fields[3];
/// `ASE`, bit 10.
pub const ASE: &FieldSpec = &super::REGISTERS[107].fields[4];
/// `BSE`, bit 11.
pub const BSE: &FieldSpec = &super::REGISTERS[107].fields[5];
}
/// The fields of `MDMA_C8CR`.
pub mod mdma_c8cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[108].fields[0];
/// `TEIE`, bit 1.
pub const TEIE: &FieldSpec = &super::REGISTERS[108].fields[1];
/// `CTCIE`, bit 2.
pub const CTCIE: &FieldSpec = &super::REGISTERS[108].fields[2];
/// `BRTIE`, bit 3.
pub const BRTIE: &FieldSpec = &super::REGISTERS[108].fields[3];
/// `BTIE`, bit 4.
pub const BTIE: &FieldSpec = &super::REGISTERS[108].fields[4];
/// `TCIE`, bit 5.
pub const TCIE: &FieldSpec = &super::REGISTERS[108].fields[5];
/// `PL`, bits 6..=7.
pub const PL: &FieldSpec = &super::REGISTERS[108].fields[6];
/// `BEX`, bit 12.
pub const BEX: &FieldSpec = &super::REGISTERS[108].fields[7];
/// `HEX`, bit 13.
pub const HEX: &FieldSpec = &super::REGISTERS[108].fields[8];
/// `WEX`, bit 14.
pub const WEX: &FieldSpec = &super::REGISTERS[108].fields[9];
/// `SWRQ`, bit 16, write-only.
pub const SWRQ: &FieldSpec = &super::REGISTERS[108].fields[10];
}
/// The fields of `MDMA_C8TCR`.
pub mod mdma_c8tcr {
use super::FieldSpec;
/// `SINC`, bits 0..=1.
pub const SINC: &FieldSpec = &super::REGISTERS[109].fields[0];
/// `DINC`, bits 2..=3.
pub const DINC: &FieldSpec = &super::REGISTERS[109].fields[1];
/// `SSIZE`, bits 4..=5.
pub const SSIZE: &FieldSpec = &super::REGISTERS[109].fields[2];
/// `DSIZE`, bits 6..=7.
pub const DSIZE: &FieldSpec = &super::REGISTERS[109].fields[3];
/// `SINCOS`, bits 8..=9.
pub const SINCOS: &FieldSpec = &super::REGISTERS[109].fields[4];
/// `DINCOS`, bits 10..=11.
pub const DINCOS: &FieldSpec = &super::REGISTERS[109].fields[5];
/// `SBURST`, bits 12..=14.
pub const SBURST: &FieldSpec = &super::REGISTERS[109].fields[6];
/// `DBURST`, bits 15..=17.
pub const DBURST: &FieldSpec = &super::REGISTERS[109].fields[7];
/// `TLEN`, bits 18..=24.
pub const TLEN: &FieldSpec = &super::REGISTERS[109].fields[8];
/// `PKE`, bit 25.
pub const PKE: &FieldSpec = &super::REGISTERS[109].fields[9];
/// `PAM`, bits 26..=27.
pub const PAM: &FieldSpec = &super::REGISTERS[109].fields[10];
/// `TRGM`, bits 28..=29.
pub const TRGM: &FieldSpec = &super::REGISTERS[109].fields[11];
/// `SWRM`, bit 30.
pub const SWRM: &FieldSpec = &super::REGISTERS[109].fields[12];
/// `BWM`, bit 31.
pub const BWM: &FieldSpec = &super::REGISTERS[109].fields[13];
}
/// The fields of `MDMA_C8BNDTR`.
pub mod mdma_c8bndtr {
use super::FieldSpec;
/// `BNDT`, bits 0..=16.
pub const BNDT: &FieldSpec = &super::REGISTERS[110].fields[0];
/// `BRSUM`, bit 18.
pub const BRSUM: &FieldSpec = &super::REGISTERS[110].fields[1];
/// `BRDUM`, bit 19.
pub const BRDUM: &FieldSpec = &super::REGISTERS[110].fields[2];
/// `BRC`, bits 20..=31.
pub const BRC: &FieldSpec = &super::REGISTERS[110].fields[3];
}
/// The fields of `MDMA_C8SAR`.
pub mod mdma_c8sar {
use super::FieldSpec;
/// `SAR`, bits 0..=31.
pub const SAR: &FieldSpec = &super::REGISTERS[111].fields[0];
}
/// The fields of `MDMA_C8DAR`.
pub mod mdma_c8dar {
use super::FieldSpec;
/// `DAR`, bits 0..=31.
pub const DAR: &FieldSpec = &super::REGISTERS[112].fields[0];
}
/// The fields of `MDMA_C8BRUR`.
pub mod mdma_c8brur {
use super::FieldSpec;
/// `SUV`, bits 0..=15.
pub const SUV: &FieldSpec = &super::REGISTERS[113].fields[0];
/// `DUV`, bits 16..=31.
pub const DUV: &FieldSpec = &super::REGISTERS[113].fields[1];
}
/// The fields of `MDMA_C8LAR`.
pub mod mdma_c8lar {
use super::FieldSpec;
/// `LAR`, bits 0..=31.
pub const LAR: &FieldSpec = &super::REGISTERS[114].fields[0];
}
/// The fields of `MDMA_C8TBR`.
pub mod mdma_c8tbr {
use super::FieldSpec;
/// `TSEL`, bits 0..=5.
pub const TSEL: &FieldSpec = &super::REGISTERS[115].fields[0];
/// `SBUS`, bit 16.
pub const SBUS: &FieldSpec = &super::REGISTERS[115].fields[1];
/// `DBUS`, bit 17.
pub const DBUS: &FieldSpec = &super::REGISTERS[115].fields[2];
}
/// The fields of `MDMA_C8MAR`.
pub mod mdma_c8mar {
use super::FieldSpec;
/// `MAR`, bits 0..=31.
pub const MAR: &FieldSpec = &super::REGISTERS[116].fields[0];
}
/// The fields of `MDMA_C8MDR`.
pub mod mdma_c8mdr {
use super::FieldSpec;
/// `MDR`, bits 0..=31.
pub const MDR: &FieldSpec = &super::REGISTERS[117].fields[0];
}
/// The fields of `MDMA_C9ISR`.
pub mod mdma_c9isr {
use super::FieldSpec;
/// `TEIF9`, bit 0.
pub const TEIF9: &FieldSpec = &super::REGISTERS[118].fields[0];
/// `CTCIF9`, bit 1.
pub const CTCIF9: &FieldSpec = &super::REGISTERS[118].fields[1];
/// `BRTIF9`, bit 2.
pub const BRTIF9: &FieldSpec = &super::REGISTERS[118].fields[2];
/// `BTIF9`, bit 3.
pub const BTIF9: &FieldSpec = &super::REGISTERS[118].fields[3];
/// `TCIF9`, bit 4.
pub const TCIF9: &FieldSpec = &super::REGISTERS[118].fields[4];
/// `CRQA9`, bit 16.
pub const CRQA9: &FieldSpec = &super::REGISTERS[118].fields[5];
}
/// The fields of `MDMA_C9IFCR`.
pub mod mdma_c9ifcr {
use super::FieldSpec;
/// `CTEIF9`, bit 0.
pub const CTEIF9: &FieldSpec = &super::REGISTERS[119].fields[0];
/// `CCTCIF9`, bit 1.
pub const CCTCIF9: &FieldSpec = &super::REGISTERS[119].fields[1];
/// `CBRTIF9`, bit 2.
pub const CBRTIF9: &FieldSpec = &super::REGISTERS[119].fields[2];
/// `CBTIF9`, bit 3.
pub const CBTIF9: &FieldSpec = &super::REGISTERS[119].fields[3];
/// `CLTCIF9`, bit 4.
pub const CLTCIF9: &FieldSpec = &super::REGISTERS[119].fields[4];
}
/// The fields of `MDMA_C9ESR`.
pub mod mdma_c9esr {
use super::FieldSpec;
/// `TEA`, bits 0..=6.
pub const TEA: &FieldSpec = &super::REGISTERS[120].fields[0];
/// `TED`, bit 7.
pub const TED: &FieldSpec = &super::REGISTERS[120].fields[1];
/// `TELD`, bit 8.
pub const TELD: &FieldSpec = &super::REGISTERS[120].fields[2];
/// `TEMD`, bit 9.
pub const TEMD: &FieldSpec = &super::REGISTERS[120].fields[3];
/// `ASE`, bit 10.
pub const ASE: &FieldSpec = &super::REGISTERS[120].fields[4];
/// `BSE`, bit 11.
pub const BSE: &FieldSpec = &super::REGISTERS[120].fields[5];
}
/// The fields of `MDMA_C9CR`.
pub mod mdma_c9cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[121].fields[0];
/// `TEIE`, bit 1.
pub const TEIE: &FieldSpec = &super::REGISTERS[121].fields[1];
/// `CTCIE`, bit 2.
pub const CTCIE: &FieldSpec = &super::REGISTERS[121].fields[2];
/// `BRTIE`, bit 3.
pub const BRTIE: &FieldSpec = &super::REGISTERS[121].fields[3];
/// `BTIE`, bit 4.
pub const BTIE: &FieldSpec = &super::REGISTERS[121].fields[4];
/// `TCIE`, bit 5.
pub const TCIE: &FieldSpec = &super::REGISTERS[121].fields[5];
/// `PL`, bits 6..=7.
pub const PL: &FieldSpec = &super::REGISTERS[121].fields[6];
/// `BEX`, bit 12.
pub const BEX: &FieldSpec = &super::REGISTERS[121].fields[7];
/// `HEX`, bit 13.
pub const HEX: &FieldSpec = &super::REGISTERS[121].fields[8];
/// `WEX`, bit 14.
pub const WEX: &FieldSpec = &super::REGISTERS[121].fields[9];
/// `SWRQ`, bit 16, write-only.
pub const SWRQ: &FieldSpec = &super::REGISTERS[121].fields[10];
}
/// The fields of `MDMA_C9TCR`.
pub mod mdma_c9tcr {
use super::FieldSpec;
/// `SINC`, bits 0..=1.
pub const SINC: &FieldSpec = &super::REGISTERS[122].fields[0];
/// `DINC`, bits 2..=3.
pub const DINC: &FieldSpec = &super::REGISTERS[122].fields[1];
/// `SSIZE`, bits 4..=5.
pub const SSIZE: &FieldSpec = &super::REGISTERS[122].fields[2];
/// `DSIZE`, bits 6..=7.
pub const DSIZE: &FieldSpec = &super::REGISTERS[122].fields[3];
/// `SINCOS`, bits 8..=9.
pub const SINCOS: &FieldSpec = &super::REGISTERS[122].fields[4];
/// `DINCOS`, bits 10..=11.
pub const DINCOS: &FieldSpec = &super::REGISTERS[122].fields[5];
/// `SBURST`, bits 12..=14.
pub const SBURST: &FieldSpec = &super::REGISTERS[122].fields[6];
/// `DBURST`, bits 15..=17.
pub const DBURST: &FieldSpec = &super::REGISTERS[122].fields[7];
/// `TLEN`, bits 18..=24.
pub const TLEN: &FieldSpec = &super::REGISTERS[122].fields[8];
/// `PKE`, bit 25.
pub const PKE: &FieldSpec = &super::REGISTERS[122].fields[9];
/// `PAM`, bits 26..=27.
pub const PAM: &FieldSpec = &super::REGISTERS[122].fields[10];
/// `TRGM`, bits 28..=29.
pub const TRGM: &FieldSpec = &super::REGISTERS[122].fields[11];
/// `SWRM`, bit 30.
pub const SWRM: &FieldSpec = &super::REGISTERS[122].fields[12];
/// `BWM`, bit 31.
pub const BWM: &FieldSpec = &super::REGISTERS[122].fields[13];
}
/// The fields of `MDMA_C9BNDTR`.
pub mod mdma_c9bndtr {
use super::FieldSpec;
/// `BNDT`, bits 0..=16.
pub const BNDT: &FieldSpec = &super::REGISTERS[123].fields[0];
/// `BRSUM`, bit 18.
pub const BRSUM: &FieldSpec = &super::REGISTERS[123].fields[1];
/// `BRDUM`, bit 19.
pub const BRDUM: &FieldSpec = &super::REGISTERS[123].fields[2];
/// `BRC`, bits 20..=31.
pub const BRC: &FieldSpec = &super::REGISTERS[123].fields[3];
}
/// The fields of `MDMA_C9SAR`.
pub mod mdma_c9sar {
use super::FieldSpec;
/// `SAR`, bits 0..=31.
pub const SAR: &FieldSpec = &super::REGISTERS[124].fields[0];
}
/// The fields of `MDMA_C9DAR`.
pub mod mdma_c9dar {
use super::FieldSpec;
/// `DAR`, bits 0..=31.
pub const DAR: &FieldSpec = &super::REGISTERS[125].fields[0];
}
/// The fields of `MDMA_C9BRUR`.
pub mod mdma_c9brur {
use super::FieldSpec;
/// `SUV`, bits 0..=15.
pub const SUV: &FieldSpec = &super::REGISTERS[126].fields[0];
/// `DUV`, bits 16..=31.
pub const DUV: &FieldSpec = &super::REGISTERS[126].fields[1];
}
/// The fields of `MDMA_C9LAR`.
pub mod mdma_c9lar {
use super::FieldSpec;
/// `LAR`, bits 0..=31.
pub const LAR: &FieldSpec = &super::REGISTERS[127].fields[0];
}
/// The fields of `MDMA_C9TBR`.
pub mod mdma_c9tbr {
use super::FieldSpec;
/// `TSEL`, bits 0..=5.
pub const TSEL: &FieldSpec = &super::REGISTERS[128].fields[0];
/// `SBUS`, bit 16.
pub const SBUS: &FieldSpec = &super::REGISTERS[128].fields[1];
/// `DBUS`, bit 17.
pub const DBUS: &FieldSpec = &super::REGISTERS[128].fields[2];
}
/// The fields of `MDMA_C9MAR`.
pub mod mdma_c9mar {
use super::FieldSpec;
/// `MAR`, bits 0..=31.
pub const MAR: &FieldSpec = &super::REGISTERS[129].fields[0];
}
/// The fields of `MDMA_C9MDR`.
pub mod mdma_c9mdr {
use super::FieldSpec;
/// `MDR`, bits 0..=31.
pub const MDR: &FieldSpec = &super::REGISTERS[130].fields[0];
}
/// The fields of `MDMA_C10ISR`.
pub mod mdma_c10isr {
use super::FieldSpec;
/// `TEIF10`, bit 0.
pub const TEIF10: &FieldSpec = &super::REGISTERS[131].fields[0];
/// `CTCIF10`, bit 1.
pub const CTCIF10: &FieldSpec = &super::REGISTERS[131].fields[1];
/// `BRTIF10`, bit 2.
pub const BRTIF10: &FieldSpec = &super::REGISTERS[131].fields[2];
/// `BTIF10`, bit 3.
pub const BTIF10: &FieldSpec = &super::REGISTERS[131].fields[3];
/// `TCIF10`, bit 4.
pub const TCIF10: &FieldSpec = &super::REGISTERS[131].fields[4];
/// `CRQA10`, bit 16.
pub const CRQA10: &FieldSpec = &super::REGISTERS[131].fields[5];
}
/// The fields of `MDMA_C10IFCR`.
pub mod mdma_c10ifcr {
use super::FieldSpec;
/// `CTEIF10`, bit 0.
pub const CTEIF10: &FieldSpec = &super::REGISTERS[132].fields[0];
/// `CCTCIF10`, bit 1.
pub const CCTCIF10: &FieldSpec = &super::REGISTERS[132].fields[1];
/// `CBRTIF10`, bit 2.
pub const CBRTIF10: &FieldSpec = &super::REGISTERS[132].fields[2];
/// `CBTIF10`, bit 3.
pub const CBTIF10: &FieldSpec = &super::REGISTERS[132].fields[3];
/// `CLTCIF10`, bit 4.
pub const CLTCIF10: &FieldSpec = &super::REGISTERS[132].fields[4];
}
/// The fields of `MDMA_C10ESR`.
pub mod mdma_c10esr {
use super::FieldSpec;
/// `TEA`, bits 0..=6.
pub const TEA: &FieldSpec = &super::REGISTERS[133].fields[0];
/// `TED`, bit 7.
pub const TED: &FieldSpec = &super::REGISTERS[133].fields[1];
/// `TELD`, bit 8.
pub const TELD: &FieldSpec = &super::REGISTERS[133].fields[2];
/// `TEMD`, bit 9.
pub const TEMD: &FieldSpec = &super::REGISTERS[133].fields[3];
/// `ASE`, bit 10.
pub const ASE: &FieldSpec = &super::REGISTERS[133].fields[4];
/// `BSE`, bit 11.
pub const BSE: &FieldSpec = &super::REGISTERS[133].fields[5];
}
/// The fields of `MDMA_C10CR`.
pub mod mdma_c10cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[134].fields[0];
/// `TEIE`, bit 1.
pub const TEIE: &FieldSpec = &super::REGISTERS[134].fields[1];
/// `CTCIE`, bit 2.
pub const CTCIE: &FieldSpec = &super::REGISTERS[134].fields[2];
/// `BRTIE`, bit 3.
pub const BRTIE: &FieldSpec = &super::REGISTERS[134].fields[3];
/// `BTIE`, bit 4.
pub const BTIE: &FieldSpec = &super::REGISTERS[134].fields[4];
/// `TCIE`, bit 5.
pub const TCIE: &FieldSpec = &super::REGISTERS[134].fields[5];
/// `PL`, bits 6..=7.
pub const PL: &FieldSpec = &super::REGISTERS[134].fields[6];
/// `BEX`, bit 12.
pub const BEX: &FieldSpec = &super::REGISTERS[134].fields[7];
/// `HEX`, bit 13.
pub const HEX: &FieldSpec = &super::REGISTERS[134].fields[8];
/// `WEX`, bit 14.
pub const WEX: &FieldSpec = &super::REGISTERS[134].fields[9];
/// `SWRQ`, bit 16, write-only.
pub const SWRQ: &FieldSpec = &super::REGISTERS[134].fields[10];
}
/// The fields of `MDMA_C10TCR`.
pub mod mdma_c10tcr {
use super::FieldSpec;
/// `SINC`, bits 0..=1.
pub const SINC: &FieldSpec = &super::REGISTERS[135].fields[0];
/// `DINC`, bits 2..=3.
pub const DINC: &FieldSpec = &super::REGISTERS[135].fields[1];
/// `SSIZE`, bits 4..=5.
pub const SSIZE: &FieldSpec = &super::REGISTERS[135].fields[2];
/// `DSIZE`, bits 6..=7.
pub const DSIZE: &FieldSpec = &super::REGISTERS[135].fields[3];
/// `SINCOS`, bits 8..=9.
pub const SINCOS: &FieldSpec = &super::REGISTERS[135].fields[4];
/// `DINCOS`, bits 10..=11.
pub const DINCOS: &FieldSpec = &super::REGISTERS[135].fields[5];
/// `SBURST`, bits 12..=14.
pub const SBURST: &FieldSpec = &super::REGISTERS[135].fields[6];
/// `DBURST`, bits 15..=17.
pub const DBURST: &FieldSpec = &super::REGISTERS[135].fields[7];
/// `TLEN`, bits 18..=24.
pub const TLEN: &FieldSpec = &super::REGISTERS[135].fields[8];
/// `PKE`, bit 25.
pub const PKE: &FieldSpec = &super::REGISTERS[135].fields[9];
/// `PAM`, bits 26..=27.
pub const PAM: &FieldSpec = &super::REGISTERS[135].fields[10];
/// `TRGM`, bits 28..=29.
pub const TRGM: &FieldSpec = &super::REGISTERS[135].fields[11];
/// `SWRM`, bit 30.
pub const SWRM: &FieldSpec = &super::REGISTERS[135].fields[12];
/// `BWM`, bit 31.
pub const BWM: &FieldSpec = &super::REGISTERS[135].fields[13];
}
/// The fields of `MDMA_C10BNDTR`.
pub mod mdma_c10bndtr {
use super::FieldSpec;
/// `BNDT`, bits 0..=16.
pub const BNDT: &FieldSpec = &super::REGISTERS[136].fields[0];
/// `BRSUM`, bit 18.
pub const BRSUM: &FieldSpec = &super::REGISTERS[136].fields[1];
/// `BRDUM`, bit 19.
pub const BRDUM: &FieldSpec = &super::REGISTERS[136].fields[2];
/// `BRC`, bits 20..=31.
pub const BRC: &FieldSpec = &super::REGISTERS[136].fields[3];
}
/// The fields of `MDMA_C10SAR`.
pub mod mdma_c10sar {
use super::FieldSpec;
/// `SAR`, bits 0..=31.
pub const SAR: &FieldSpec = &super::REGISTERS[137].fields[0];
}
/// The fields of `MDMA_C10DAR`.
pub mod mdma_c10dar {
use super::FieldSpec;
/// `DAR`, bits 0..=31.
pub const DAR: &FieldSpec = &super::REGISTERS[138].fields[0];
}
/// The fields of `MDMA_C10BRUR`.
pub mod mdma_c10brur {
use super::FieldSpec;
/// `SUV`, bits 0..=15.
pub const SUV: &FieldSpec = &super::REGISTERS[139].fields[0];
/// `DUV`, bits 16..=31.
pub const DUV: &FieldSpec = &super::REGISTERS[139].fields[1];
}
/// The fields of `MDMA_C10LAR`.
pub mod mdma_c10lar {
use super::FieldSpec;
/// `LAR`, bits 0..=31.
pub const LAR: &FieldSpec = &super::REGISTERS[140].fields[0];
}
/// The fields of `MDMA_C10TBR`.
pub mod mdma_c10tbr {
use super::FieldSpec;
/// `TSEL`, bits 0..=5.
pub const TSEL: &FieldSpec = &super::REGISTERS[141].fields[0];
/// `SBUS`, bit 16.
pub const SBUS: &FieldSpec = &super::REGISTERS[141].fields[1];
/// `DBUS`, bit 17.
pub const DBUS: &FieldSpec = &super::REGISTERS[141].fields[2];
}
/// The fields of `MDMA_C10MAR`.
pub mod mdma_c10mar {
use super::FieldSpec;
/// `MAR`, bits 0..=31.
pub const MAR: &FieldSpec = &super::REGISTERS[142].fields[0];
}
/// The fields of `MDMA_C10MDR`.
pub mod mdma_c10mdr {
use super::FieldSpec;
/// `MDR`, bits 0..=31.
pub const MDR: &FieldSpec = &super::REGISTERS[143].fields[0];
}
/// The fields of `MDMA_C11ISR`.
pub mod mdma_c11isr {
use super::FieldSpec;
/// `TEIF11`, bit 0.
pub const TEIF11: &FieldSpec = &super::REGISTERS[144].fields[0];
/// `CTCIF11`, bit 1.
pub const CTCIF11: &FieldSpec = &super::REGISTERS[144].fields[1];
/// `BRTIF11`, bit 2.
pub const BRTIF11: &FieldSpec = &super::REGISTERS[144].fields[2];
/// `BTIF11`, bit 3.
pub const BTIF11: &FieldSpec = &super::REGISTERS[144].fields[3];
/// `TCIF11`, bit 4.
pub const TCIF11: &FieldSpec = &super::REGISTERS[144].fields[4];
/// `CRQA11`, bit 16.
pub const CRQA11: &FieldSpec = &super::REGISTERS[144].fields[5];
}
/// The fields of `MDMA_C11IFCR`.
pub mod mdma_c11ifcr {
use super::FieldSpec;
/// `CTEIF11`, bit 0.
pub const CTEIF11: &FieldSpec = &super::REGISTERS[145].fields[0];
/// `CCTCIF11`, bit 1.
pub const CCTCIF11: &FieldSpec = &super::REGISTERS[145].fields[1];
/// `CBRTIF11`, bit 2.
pub const CBRTIF11: &FieldSpec = &super::REGISTERS[145].fields[2];
/// `CBTIF11`, bit 3.
pub const CBTIF11: &FieldSpec = &super::REGISTERS[145].fields[3];
/// `CLTCIF11`, bit 4.
pub const CLTCIF11: &FieldSpec = &super::REGISTERS[145].fields[4];
}
/// The fields of `MDMA_C11ESR`.
pub mod mdma_c11esr {
use super::FieldSpec;
/// `TEA`, bits 0..=6.
pub const TEA: &FieldSpec = &super::REGISTERS[146].fields[0];
/// `TED`, bit 7.
pub const TED: &FieldSpec = &super::REGISTERS[146].fields[1];
/// `TELD`, bit 8.
pub const TELD: &FieldSpec = &super::REGISTERS[146].fields[2];
/// `TEMD`, bit 9.
pub const TEMD: &FieldSpec = &super::REGISTERS[146].fields[3];
/// `ASE`, bit 10.
pub const ASE: &FieldSpec = &super::REGISTERS[146].fields[4];
/// `BSE`, bit 11.
pub const BSE: &FieldSpec = &super::REGISTERS[146].fields[5];
}
/// The fields of `MDMA_C11CR`.
pub mod mdma_c11cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[147].fields[0];
/// `TEIE`, bit 1.
pub const TEIE: &FieldSpec = &super::REGISTERS[147].fields[1];
/// `CTCIE`, bit 2.
pub const CTCIE: &FieldSpec = &super::REGISTERS[147].fields[2];
/// `BRTIE`, bit 3.
pub const BRTIE: &FieldSpec = &super::REGISTERS[147].fields[3];
/// `BTIE`, bit 4.
pub const BTIE: &FieldSpec = &super::REGISTERS[147].fields[4];
/// `TCIE`, bit 5.
pub const TCIE: &FieldSpec = &super::REGISTERS[147].fields[5];
/// `PL`, bits 6..=7.
pub const PL: &FieldSpec = &super::REGISTERS[147].fields[6];
/// `BEX`, bit 12.
pub const BEX: &FieldSpec = &super::REGISTERS[147].fields[7];
/// `HEX`, bit 13.
pub const HEX: &FieldSpec = &super::REGISTERS[147].fields[8];
/// `WEX`, bit 14.
pub const WEX: &FieldSpec = &super::REGISTERS[147].fields[9];
/// `SWRQ`, bit 16, write-only.
pub const SWRQ: &FieldSpec = &super::REGISTERS[147].fields[10];
}
/// The fields of `MDMA_C11TCR`.
pub mod mdma_c11tcr {
use super::FieldSpec;
/// `SINC`, bits 0..=1.
pub const SINC: &FieldSpec = &super::REGISTERS[148].fields[0];
/// `DINC`, bits 2..=3.
pub const DINC: &FieldSpec = &super::REGISTERS[148].fields[1];
/// `SSIZE`, bits 4..=5.
pub const SSIZE: &FieldSpec = &super::REGISTERS[148].fields[2];
/// `DSIZE`, bits 6..=7.
pub const DSIZE: &FieldSpec = &super::REGISTERS[148].fields[3];
/// `SINCOS`, bits 8..=9.
pub const SINCOS: &FieldSpec = &super::REGISTERS[148].fields[4];
/// `DINCOS`, bits 10..=11.
pub const DINCOS: &FieldSpec = &super::REGISTERS[148].fields[5];
/// `SBURST`, bits 12..=14.
pub const SBURST: &FieldSpec = &super::REGISTERS[148].fields[6];
/// `DBURST`, bits 15..=17.
pub const DBURST: &FieldSpec = &super::REGISTERS[148].fields[7];
/// `TLEN`, bits 18..=24.
pub const TLEN: &FieldSpec = &super::REGISTERS[148].fields[8];
/// `PKE`, bit 25.
pub const PKE: &FieldSpec = &super::REGISTERS[148].fields[9];
/// `PAM`, bits 26..=27.
pub const PAM: &FieldSpec = &super::REGISTERS[148].fields[10];
/// `TRGM`, bits 28..=29.
pub const TRGM: &FieldSpec = &super::REGISTERS[148].fields[11];
/// `SWRM`, bit 30.
pub const SWRM: &FieldSpec = &super::REGISTERS[148].fields[12];
/// `BWM`, bit 31.
pub const BWM: &FieldSpec = &super::REGISTERS[148].fields[13];
}
/// The fields of `MDMA_C11BNDTR`.
pub mod mdma_c11bndtr {
use super::FieldSpec;
/// `BNDT`, bits 0..=16.
pub const BNDT: &FieldSpec = &super::REGISTERS[149].fields[0];
/// `BRSUM`, bit 18.
pub const BRSUM: &FieldSpec = &super::REGISTERS[149].fields[1];
/// `BRDUM`, bit 19.
pub const BRDUM: &FieldSpec = &super::REGISTERS[149].fields[2];
/// `BRC`, bits 20..=31.
pub const BRC: &FieldSpec = &super::REGISTERS[149].fields[3];
}
/// The fields of `MDMA_C11SAR`.
pub mod mdma_c11sar {
use super::FieldSpec;
/// `SAR`, bits 0..=31.
pub const SAR: &FieldSpec = &super::REGISTERS[150].fields[0];
}
/// The fields of `MDMA_C11DAR`.
pub mod mdma_c11dar {
use super::FieldSpec;
/// `DAR`, bits 0..=31.
pub const DAR: &FieldSpec = &super::REGISTERS[151].fields[0];
}
/// The fields of `MDMA_C11BRUR`.
pub mod mdma_c11brur {
use super::FieldSpec;
/// `SUV`, bits 0..=15.
pub const SUV: &FieldSpec = &super::REGISTERS[152].fields[0];
/// `DUV`, bits 16..=31.
pub const DUV: &FieldSpec = &super::REGISTERS[152].fields[1];
}
/// The fields of `MDMA_C11LAR`.
pub mod mdma_c11lar {
use super::FieldSpec;
/// `LAR`, bits 0..=31.
pub const LAR: &FieldSpec = &super::REGISTERS[153].fields[0];
}
/// The fields of `MDMA_C11TBR`.
pub mod mdma_c11tbr {
use super::FieldSpec;
/// `TSEL`, bits 0..=5.
pub const TSEL: &FieldSpec = &super::REGISTERS[154].fields[0];
/// `SBUS`, bit 16.
pub const SBUS: &FieldSpec = &super::REGISTERS[154].fields[1];
/// `DBUS`, bit 17.
pub const DBUS: &FieldSpec = &super::REGISTERS[154].fields[2];
}
/// The fields of `MDMA_C11MAR`.
pub mod mdma_c11mar {
use super::FieldSpec;
/// `MAR`, bits 0..=31.
pub const MAR: &FieldSpec = &super::REGISTERS[155].fields[0];
}
/// The fields of `MDMA_C11MDR`.
pub mod mdma_c11mdr {
use super::FieldSpec;
/// `MDR`, bits 0..=31.
pub const MDR: &FieldSpec = &super::REGISTERS[156].fields[0];
}
/// The fields of `MDMA_C12ISR`.
pub mod mdma_c12isr {
use super::FieldSpec;
/// `TEIF12`, bit 0.
pub const TEIF12: &FieldSpec = &super::REGISTERS[157].fields[0];
/// `CTCIF12`, bit 1.
pub const CTCIF12: &FieldSpec = &super::REGISTERS[157].fields[1];
/// `BRTIF12`, bit 2.
pub const BRTIF12: &FieldSpec = &super::REGISTERS[157].fields[2];
/// `BTIF12`, bit 3.
pub const BTIF12: &FieldSpec = &super::REGISTERS[157].fields[3];
/// `TCIF12`, bit 4.
pub const TCIF12: &FieldSpec = &super::REGISTERS[157].fields[4];
/// `CRQA12`, bit 16.
pub const CRQA12: &FieldSpec = &super::REGISTERS[157].fields[5];
}
/// The fields of `MDMA_C12IFCR`.
pub mod mdma_c12ifcr {
use super::FieldSpec;
/// `CTEIF12`, bit 0.
pub const CTEIF12: &FieldSpec = &super::REGISTERS[158].fields[0];
/// `CCTCIF12`, bit 1.
pub const CCTCIF12: &FieldSpec = &super::REGISTERS[158].fields[1];
/// `CBRTIF12`, bit 2.
pub const CBRTIF12: &FieldSpec = &super::REGISTERS[158].fields[2];
/// `CBTIF12`, bit 3.
pub const CBTIF12: &FieldSpec = &super::REGISTERS[158].fields[3];
/// `CLTCIF12`, bit 4.
pub const CLTCIF12: &FieldSpec = &super::REGISTERS[158].fields[4];
}
/// The fields of `MDMA_C12ESR`.
pub mod mdma_c12esr {
use super::FieldSpec;
/// `TEA`, bits 0..=6.
pub const TEA: &FieldSpec = &super::REGISTERS[159].fields[0];
/// `TED`, bit 7.
pub const TED: &FieldSpec = &super::REGISTERS[159].fields[1];
/// `TELD`, bit 8.
pub const TELD: &FieldSpec = &super::REGISTERS[159].fields[2];
/// `TEMD`, bit 9.
pub const TEMD: &FieldSpec = &super::REGISTERS[159].fields[3];
/// `ASE`, bit 10.
pub const ASE: &FieldSpec = &super::REGISTERS[159].fields[4];
/// `BSE`, bit 11.
pub const BSE: &FieldSpec = &super::REGISTERS[159].fields[5];
}
/// The fields of `MDMA_C12CR`.
pub mod mdma_c12cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[160].fields[0];
/// `TEIE`, bit 1.
pub const TEIE: &FieldSpec = &super::REGISTERS[160].fields[1];
/// `CTCIE`, bit 2.
pub const CTCIE: &FieldSpec = &super::REGISTERS[160].fields[2];
/// `BRTIE`, bit 3.
pub const BRTIE: &FieldSpec = &super::REGISTERS[160].fields[3];
/// `BTIE`, bit 4.
pub const BTIE: &FieldSpec = &super::REGISTERS[160].fields[4];
/// `TCIE`, bit 5.
pub const TCIE: &FieldSpec = &super::REGISTERS[160].fields[5];
/// `PL`, bits 6..=7.
pub const PL: &FieldSpec = &super::REGISTERS[160].fields[6];
/// `BEX`, bit 12.
pub const BEX: &FieldSpec = &super::REGISTERS[160].fields[7];
/// `HEX`, bit 13.
pub const HEX: &FieldSpec = &super::REGISTERS[160].fields[8];
/// `WEX`, bit 14.
pub const WEX: &FieldSpec = &super::REGISTERS[160].fields[9];
/// `SWRQ`, bit 16, write-only.
pub const SWRQ: &FieldSpec = &super::REGISTERS[160].fields[10];
}
/// The fields of `MDMA_C12TCR`.
pub mod mdma_c12tcr {
use super::FieldSpec;
/// `SINC`, bits 0..=1.
pub const SINC: &FieldSpec = &super::REGISTERS[161].fields[0];
/// `DINC`, bits 2..=3.
pub const DINC: &FieldSpec = &super::REGISTERS[161].fields[1];
/// `SSIZE`, bits 4..=5.
pub const SSIZE: &FieldSpec = &super::REGISTERS[161].fields[2];
/// `DSIZE`, bits 6..=7.
pub const DSIZE: &FieldSpec = &super::REGISTERS[161].fields[3];
/// `SINCOS`, bits 8..=9.
pub const SINCOS: &FieldSpec = &super::REGISTERS[161].fields[4];
/// `DINCOS`, bits 10..=11.
pub const DINCOS: &FieldSpec = &super::REGISTERS[161].fields[5];
/// `SBURST`, bits 12..=14.
pub const SBURST: &FieldSpec = &super::REGISTERS[161].fields[6];
/// `DBURST`, bits 15..=17.
pub const DBURST: &FieldSpec = &super::REGISTERS[161].fields[7];
/// `TLEN`, bits 18..=24.
pub const TLEN: &FieldSpec = &super::REGISTERS[161].fields[8];
/// `PKE`, bit 25.
pub const PKE: &FieldSpec = &super::REGISTERS[161].fields[9];
/// `PAM`, bits 26..=27.
pub const PAM: &FieldSpec = &super::REGISTERS[161].fields[10];
/// `TRGM`, bits 28..=29.
pub const TRGM: &FieldSpec = &super::REGISTERS[161].fields[11];
/// `SWRM`, bit 30.
pub const SWRM: &FieldSpec = &super::REGISTERS[161].fields[12];
/// `BWM`, bit 31.
pub const BWM: &FieldSpec = &super::REGISTERS[161].fields[13];
}
/// The fields of `MDMA_C12BNDTR`.
pub mod mdma_c12bndtr {
use super::FieldSpec;
/// `BNDT`, bits 0..=16.
pub const BNDT: &FieldSpec = &super::REGISTERS[162].fields[0];
/// `BRSUM`, bit 18.
pub const BRSUM: &FieldSpec = &super::REGISTERS[162].fields[1];
/// `BRDUM`, bit 19.
pub const BRDUM: &FieldSpec = &super::REGISTERS[162].fields[2];
/// `BRC`, bits 20..=31.
pub const BRC: &FieldSpec = &super::REGISTERS[162].fields[3];
}
/// The fields of `MDMA_C12SAR`.
pub mod mdma_c12sar {
use super::FieldSpec;
/// `SAR`, bits 0..=31.
pub const SAR: &FieldSpec = &super::REGISTERS[163].fields[0];
}
/// The fields of `MDMA_C12DAR`.
pub mod mdma_c12dar {
use super::FieldSpec;
/// `DAR`, bits 0..=31.
pub const DAR: &FieldSpec = &super::REGISTERS[164].fields[0];
}
/// The fields of `MDMA_C12BRUR`.
pub mod mdma_c12brur {
use super::FieldSpec;
/// `SUV`, bits 0..=15.
pub const SUV: &FieldSpec = &super::REGISTERS[165].fields[0];
/// `DUV`, bits 16..=31.
pub const DUV: &FieldSpec = &super::REGISTERS[165].fields[1];
}
/// The fields of `MDMA_C12LAR`.
pub mod mdma_c12lar {
use super::FieldSpec;
/// `LAR`, bits 0..=31.
pub const LAR: &FieldSpec = &super::REGISTERS[166].fields[0];
}
/// The fields of `MDMA_C12TBR`.
pub mod mdma_c12tbr {
use super::FieldSpec;
/// `TSEL`, bits 0..=5.
pub const TSEL: &FieldSpec = &super::REGISTERS[167].fields[0];
/// `SBUS`, bit 16.
pub const SBUS: &FieldSpec = &super::REGISTERS[167].fields[1];
/// `DBUS`, bit 17.
pub const DBUS: &FieldSpec = &super::REGISTERS[167].fields[2];
}
/// The fields of `MDMA_C12MAR`.
pub mod mdma_c12mar {
use super::FieldSpec;
/// `MAR`, bits 0..=31.
pub const MAR: &FieldSpec = &super::REGISTERS[168].fields[0];
}
/// The fields of `MDMA_C12MDR`.
pub mod mdma_c12mdr {
use super::FieldSpec;
/// `MDR`, bits 0..=31.
pub const MDR: &FieldSpec = &super::REGISTERS[169].fields[0];
}
/// The fields of `MDMA_C13ISR`.
pub mod mdma_c13isr {
use super::FieldSpec;
/// `TEIF13`, bit 0.
pub const TEIF13: &FieldSpec = &super::REGISTERS[170].fields[0];
/// `CTCIF13`, bit 1.
pub const CTCIF13: &FieldSpec = &super::REGISTERS[170].fields[1];
/// `BRTIF13`, bit 2.
pub const BRTIF13: &FieldSpec = &super::REGISTERS[170].fields[2];
/// `BTIF13`, bit 3.
pub const BTIF13: &FieldSpec = &super::REGISTERS[170].fields[3];
/// `TCIF13`, bit 4.
pub const TCIF13: &FieldSpec = &super::REGISTERS[170].fields[4];
/// `CRQA13`, bit 16.
pub const CRQA13: &FieldSpec = &super::REGISTERS[170].fields[5];
}
/// The fields of `MDMA_C13IFCR`.
pub mod mdma_c13ifcr {
use super::FieldSpec;
/// `CTEIF13`, bit 0.
pub const CTEIF13: &FieldSpec = &super::REGISTERS[171].fields[0];
/// `CCTCIF13`, bit 1.
pub const CCTCIF13: &FieldSpec = &super::REGISTERS[171].fields[1];
/// `CBRTIF13`, bit 2.
pub const CBRTIF13: &FieldSpec = &super::REGISTERS[171].fields[2];
/// `CBTIF13`, bit 3.
pub const CBTIF13: &FieldSpec = &super::REGISTERS[171].fields[3];
/// `CLTCIF13`, bit 4.
pub const CLTCIF13: &FieldSpec = &super::REGISTERS[171].fields[4];
}
/// The fields of `MDMA_C13ESR`.
pub mod mdma_c13esr {
use super::FieldSpec;
/// `TEA`, bits 0..=6.
pub const TEA: &FieldSpec = &super::REGISTERS[172].fields[0];
/// `TED`, bit 7.
pub const TED: &FieldSpec = &super::REGISTERS[172].fields[1];
/// `TELD`, bit 8.
pub const TELD: &FieldSpec = &super::REGISTERS[172].fields[2];
/// `TEMD`, bit 9.
pub const TEMD: &FieldSpec = &super::REGISTERS[172].fields[3];
/// `ASE`, bit 10.
pub const ASE: &FieldSpec = &super::REGISTERS[172].fields[4];
/// `BSE`, bit 11.
pub const BSE: &FieldSpec = &super::REGISTERS[172].fields[5];
}
/// The fields of `MDMA_C13CR`.
pub mod mdma_c13cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[173].fields[0];
/// `TEIE`, bit 1.
pub const TEIE: &FieldSpec = &super::REGISTERS[173].fields[1];
/// `CTCIE`, bit 2.
pub const CTCIE: &FieldSpec = &super::REGISTERS[173].fields[2];
/// `BRTIE`, bit 3.
pub const BRTIE: &FieldSpec = &super::REGISTERS[173].fields[3];
/// `BTIE`, bit 4.
pub const BTIE: &FieldSpec = &super::REGISTERS[173].fields[4];
/// `TCIE`, bit 5.
pub const TCIE: &FieldSpec = &super::REGISTERS[173].fields[5];
/// `PL`, bits 6..=7.
pub const PL: &FieldSpec = &super::REGISTERS[173].fields[6];
/// `BEX`, bit 12.
pub const BEX: &FieldSpec = &super::REGISTERS[173].fields[7];
/// `HEX`, bit 13.
pub const HEX: &FieldSpec = &super::REGISTERS[173].fields[8];
/// `WEX`, bit 14.
pub const WEX: &FieldSpec = &super::REGISTERS[173].fields[9];
/// `SWRQ`, bit 16, write-only.
pub const SWRQ: &FieldSpec = &super::REGISTERS[173].fields[10];
}
/// The fields of `MDMA_C13TCR`.
pub mod mdma_c13tcr {
use super::FieldSpec;
/// `SINC`, bits 0..=1.
pub const SINC: &FieldSpec = &super::REGISTERS[174].fields[0];
/// `DINC`, bits 2..=3.
pub const DINC: &FieldSpec = &super::REGISTERS[174].fields[1];
/// `SSIZE`, bits 4..=5.
pub const SSIZE: &FieldSpec = &super::REGISTERS[174].fields[2];
/// `DSIZE`, bits 6..=7.
pub const DSIZE: &FieldSpec = &super::REGISTERS[174].fields[3];
/// `SINCOS`, bits 8..=9.
pub const SINCOS: &FieldSpec = &super::REGISTERS[174].fields[4];
/// `DINCOS`, bits 10..=11.
pub const DINCOS: &FieldSpec = &super::REGISTERS[174].fields[5];
/// `SBURST`, bits 12..=14.
pub const SBURST: &FieldSpec = &super::REGISTERS[174].fields[6];
/// `DBURST`, bits 15..=17.
pub const DBURST: &FieldSpec = &super::REGISTERS[174].fields[7];
/// `TLEN`, bits 18..=24.
pub const TLEN: &FieldSpec = &super::REGISTERS[174].fields[8];
/// `PKE`, bit 25.
pub const PKE: &FieldSpec = &super::REGISTERS[174].fields[9];
/// `PAM`, bits 26..=27.
pub const PAM: &FieldSpec = &super::REGISTERS[174].fields[10];
/// `TRGM`, bits 28..=29.
pub const TRGM: &FieldSpec = &super::REGISTERS[174].fields[11];
/// `SWRM`, bit 30.
pub const SWRM: &FieldSpec = &super::REGISTERS[174].fields[12];
/// `BWM`, bit 31.
pub const BWM: &FieldSpec = &super::REGISTERS[174].fields[13];
}
/// The fields of `MDMA_C13BNDTR`.
pub mod mdma_c13bndtr {
use super::FieldSpec;
/// `BNDT`, bits 0..=16.
pub const BNDT: &FieldSpec = &super::REGISTERS[175].fields[0];
/// `BRSUM`, bit 18.
pub const BRSUM: &FieldSpec = &super::REGISTERS[175].fields[1];
/// `BRDUM`, bit 19.
pub const BRDUM: &FieldSpec = &super::REGISTERS[175].fields[2];
/// `BRC`, bits 20..=31.
pub const BRC: &FieldSpec = &super::REGISTERS[175].fields[3];
}
/// The fields of `MDMA_C13SAR`.
pub mod mdma_c13sar {
use super::FieldSpec;
/// `SAR`, bits 0..=31.
pub const SAR: &FieldSpec = &super::REGISTERS[176].fields[0];
}
/// The fields of `MDMA_C13DAR`.
pub mod mdma_c13dar {
use super::FieldSpec;
/// `DAR`, bits 0..=31.
pub const DAR: &FieldSpec = &super::REGISTERS[177].fields[0];
}
/// The fields of `MDMA_C13BRUR`.
pub mod mdma_c13brur {
use super::FieldSpec;
/// `SUV`, bits 0..=15.
pub const SUV: &FieldSpec = &super::REGISTERS[178].fields[0];
/// `DUV`, bits 16..=31.
pub const DUV: &FieldSpec = &super::REGISTERS[178].fields[1];
}
/// The fields of `MDMA_C13LAR`.
pub mod mdma_c13lar {
use super::FieldSpec;
/// `LAR`, bits 0..=31.
pub const LAR: &FieldSpec = &super::REGISTERS[179].fields[0];
}
/// The fields of `MDMA_C13TBR`.
pub mod mdma_c13tbr {
use super::FieldSpec;
/// `TSEL`, bits 0..=5.
pub const TSEL: &FieldSpec = &super::REGISTERS[180].fields[0];
/// `SBUS`, bit 16.
pub const SBUS: &FieldSpec = &super::REGISTERS[180].fields[1];
/// `DBUS`, bit 17.
pub const DBUS: &FieldSpec = &super::REGISTERS[180].fields[2];
}
/// The fields of `MDMA_C13MAR`.
pub mod mdma_c13mar {
use super::FieldSpec;
/// `MAR`, bits 0..=31.
pub const MAR: &FieldSpec = &super::REGISTERS[181].fields[0];
}
/// The fields of `MDMA_C13MDR`.
pub mod mdma_c13mdr {
use super::FieldSpec;
/// `MDR`, bits 0..=31.
pub const MDR: &FieldSpec = &super::REGISTERS[182].fields[0];
}
/// The fields of `MDMA_C14ISR`.
pub mod mdma_c14isr {
use super::FieldSpec;
/// `TEIF14`, bit 0.
pub const TEIF14: &FieldSpec = &super::REGISTERS[183].fields[0];
/// `CTCIF14`, bit 1.
pub const CTCIF14: &FieldSpec = &super::REGISTERS[183].fields[1];
/// `BRTIF14`, bit 2.
pub const BRTIF14: &FieldSpec = &super::REGISTERS[183].fields[2];
/// `BTIF14`, bit 3.
pub const BTIF14: &FieldSpec = &super::REGISTERS[183].fields[3];
/// `TCIF14`, bit 4.
pub const TCIF14: &FieldSpec = &super::REGISTERS[183].fields[4];
/// `CRQA14`, bit 16.
pub const CRQA14: &FieldSpec = &super::REGISTERS[183].fields[5];
}
/// The fields of `MDMA_C14IFCR`.
pub mod mdma_c14ifcr {
use super::FieldSpec;
/// `CTEIF14`, bit 0.
pub const CTEIF14: &FieldSpec = &super::REGISTERS[184].fields[0];
/// `CCTCIF14`, bit 1.
pub const CCTCIF14: &FieldSpec = &super::REGISTERS[184].fields[1];
/// `CBRTIF14`, bit 2.
pub const CBRTIF14: &FieldSpec = &super::REGISTERS[184].fields[2];
/// `CBTIF14`, bit 3.
pub const CBTIF14: &FieldSpec = &super::REGISTERS[184].fields[3];
/// `CLTCIF14`, bit 4.
pub const CLTCIF14: &FieldSpec = &super::REGISTERS[184].fields[4];
}
/// The fields of `MDMA_C14ESR`.
pub mod mdma_c14esr {
use super::FieldSpec;
/// `TEA`, bits 0..=6.
pub const TEA: &FieldSpec = &super::REGISTERS[185].fields[0];
/// `TED`, bit 7.
pub const TED: &FieldSpec = &super::REGISTERS[185].fields[1];
/// `TELD`, bit 8.
pub const TELD: &FieldSpec = &super::REGISTERS[185].fields[2];
/// `TEMD`, bit 9.
pub const TEMD: &FieldSpec = &super::REGISTERS[185].fields[3];
/// `ASE`, bit 10.
pub const ASE: &FieldSpec = &super::REGISTERS[185].fields[4];
/// `BSE`, bit 11.
pub const BSE: &FieldSpec = &super::REGISTERS[185].fields[5];
}
/// The fields of `MDMA_C14CR`.
pub mod mdma_c14cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[186].fields[0];
/// `TEIE`, bit 1.
pub const TEIE: &FieldSpec = &super::REGISTERS[186].fields[1];
/// `CTCIE`, bit 2.
pub const CTCIE: &FieldSpec = &super::REGISTERS[186].fields[2];
/// `BRTIE`, bit 3.
pub const BRTIE: &FieldSpec = &super::REGISTERS[186].fields[3];
/// `BTIE`, bit 4.
pub const BTIE: &FieldSpec = &super::REGISTERS[186].fields[4];
/// `TCIE`, bit 5.
pub const TCIE: &FieldSpec = &super::REGISTERS[186].fields[5];
/// `PL`, bits 6..=7.
pub const PL: &FieldSpec = &super::REGISTERS[186].fields[6];
/// `BEX`, bit 12.
pub const BEX: &FieldSpec = &super::REGISTERS[186].fields[7];
/// `HEX`, bit 13.
pub const HEX: &FieldSpec = &super::REGISTERS[186].fields[8];
/// `WEX`, bit 14.
pub const WEX: &FieldSpec = &super::REGISTERS[186].fields[9];
/// `SWRQ`, bit 16, write-only.
pub const SWRQ: &FieldSpec = &super::REGISTERS[186].fields[10];
}
/// The fields of `MDMA_C14TCR`.
pub mod mdma_c14tcr {
use super::FieldSpec;
/// `SINC`, bits 0..=1.
pub const SINC: &FieldSpec = &super::REGISTERS[187].fields[0];
/// `DINC`, bits 2..=3.
pub const DINC: &FieldSpec = &super::REGISTERS[187].fields[1];
/// `SSIZE`, bits 4..=5.
pub const SSIZE: &FieldSpec = &super::REGISTERS[187].fields[2];
/// `DSIZE`, bits 6..=7.
pub const DSIZE: &FieldSpec = &super::REGISTERS[187].fields[3];
/// `SINCOS`, bits 8..=9.
pub const SINCOS: &FieldSpec = &super::REGISTERS[187].fields[4];
/// `DINCOS`, bits 10..=11.
pub const DINCOS: &FieldSpec = &super::REGISTERS[187].fields[5];
/// `SBURST`, bits 12..=14.
pub const SBURST: &FieldSpec = &super::REGISTERS[187].fields[6];
/// `DBURST`, bits 15..=17.
pub const DBURST: &FieldSpec = &super::REGISTERS[187].fields[7];
/// `TLEN`, bits 18..=24.
pub const TLEN: &FieldSpec = &super::REGISTERS[187].fields[8];
/// `PKE`, bit 25.
pub const PKE: &FieldSpec = &super::REGISTERS[187].fields[9];
/// `PAM`, bits 26..=27.
pub const PAM: &FieldSpec = &super::REGISTERS[187].fields[10];
/// `TRGM`, bits 28..=29.
pub const TRGM: &FieldSpec = &super::REGISTERS[187].fields[11];
/// `SWRM`, bit 30.
pub const SWRM: &FieldSpec = &super::REGISTERS[187].fields[12];
/// `BWM`, bit 31.
pub const BWM: &FieldSpec = &super::REGISTERS[187].fields[13];
}
/// The fields of `MDMA_C14BNDTR`.
pub mod mdma_c14bndtr {
use super::FieldSpec;
/// `BNDT`, bits 0..=16.
pub const BNDT: &FieldSpec = &super::REGISTERS[188].fields[0];
/// `BRSUM`, bit 18.
pub const BRSUM: &FieldSpec = &super::REGISTERS[188].fields[1];
/// `BRDUM`, bit 19.
pub const BRDUM: &FieldSpec = &super::REGISTERS[188].fields[2];
/// `BRC`, bits 20..=31.
pub const BRC: &FieldSpec = &super::REGISTERS[188].fields[3];
}
/// The fields of `MDMA_C14SAR`.
pub mod mdma_c14sar {
use super::FieldSpec;
/// `SAR`, bits 0..=31.
pub const SAR: &FieldSpec = &super::REGISTERS[189].fields[0];
}
/// The fields of `MDMA_C14DAR`.
pub mod mdma_c14dar {
use super::FieldSpec;
/// `DAR`, bits 0..=31.
pub const DAR: &FieldSpec = &super::REGISTERS[190].fields[0];
}
/// The fields of `MDMA_C14BRUR`.
pub mod mdma_c14brur {
use super::FieldSpec;
/// `SUV`, bits 0..=15.
pub const SUV: &FieldSpec = &super::REGISTERS[191].fields[0];
/// `DUV`, bits 16..=31.
pub const DUV: &FieldSpec = &super::REGISTERS[191].fields[1];
}
/// The fields of `MDMA_C14LAR`.
pub mod mdma_c14lar {
use super::FieldSpec;
/// `LAR`, bits 0..=31.
pub const LAR: &FieldSpec = &super::REGISTERS[192].fields[0];
}
/// The fields of `MDMA_C14TBR`.
pub mod mdma_c14tbr {
use super::FieldSpec;
/// `TSEL`, bits 0..=5.
pub const TSEL: &FieldSpec = &super::REGISTERS[193].fields[0];
/// `SBUS`, bit 16.
pub const SBUS: &FieldSpec = &super::REGISTERS[193].fields[1];
/// `DBUS`, bit 17.
pub const DBUS: &FieldSpec = &super::REGISTERS[193].fields[2];
}
/// The fields of `MDMA_C14MAR`.
pub mod mdma_c14mar {
use super::FieldSpec;
/// `MAR`, bits 0..=31.
pub const MAR: &FieldSpec = &super::REGISTERS[194].fields[0];
}
/// The fields of `MDMA_C14MDR`.
pub mod mdma_c14mdr {
use super::FieldSpec;
/// `MDR`, bits 0..=31.
pub const MDR: &FieldSpec = &super::REGISTERS[195].fields[0];
}
/// The fields of `MDMA_C15ISR`.
pub mod mdma_c15isr {
use super::FieldSpec;
/// `TEIF15`, bit 0.
pub const TEIF15: &FieldSpec = &super::REGISTERS[196].fields[0];
/// `CTCIF15`, bit 1.
pub const CTCIF15: &FieldSpec = &super::REGISTERS[196].fields[1];
/// `BRTIF15`, bit 2.
pub const BRTIF15: &FieldSpec = &super::REGISTERS[196].fields[2];
/// `BTIF15`, bit 3.
pub const BTIF15: &FieldSpec = &super::REGISTERS[196].fields[3];
/// `TCIF15`, bit 4.
pub const TCIF15: &FieldSpec = &super::REGISTERS[196].fields[4];
/// `CRQA15`, bit 16.
pub const CRQA15: &FieldSpec = &super::REGISTERS[196].fields[5];
}
/// The fields of `MDMA_C15IFCR`.
pub mod mdma_c15ifcr {
use super::FieldSpec;
/// `CTEIF15`, bit 0.
pub const CTEIF15: &FieldSpec = &super::REGISTERS[197].fields[0];
/// `CCTCIF15`, bit 1.
pub const CCTCIF15: &FieldSpec = &super::REGISTERS[197].fields[1];
/// `CBRTIF15`, bit 2.
pub const CBRTIF15: &FieldSpec = &super::REGISTERS[197].fields[2];
/// `CBTIF15`, bit 3.
pub const CBTIF15: &FieldSpec = &super::REGISTERS[197].fields[3];
/// `CLTCIF15`, bit 4.
pub const CLTCIF15: &FieldSpec = &super::REGISTERS[197].fields[4];
}
/// The fields of `MDMA_C15ESR`.
pub mod mdma_c15esr {
use super::FieldSpec;
/// `TEA`, bits 0..=6.
pub const TEA: &FieldSpec = &super::REGISTERS[198].fields[0];
/// `TED`, bit 7.
pub const TED: &FieldSpec = &super::REGISTERS[198].fields[1];
/// `TELD`, bit 8.
pub const TELD: &FieldSpec = &super::REGISTERS[198].fields[2];
/// `TEMD`, bit 9.
pub const TEMD: &FieldSpec = &super::REGISTERS[198].fields[3];
/// `ASE`, bit 10.
pub const ASE: &FieldSpec = &super::REGISTERS[198].fields[4];
/// `BSE`, bit 11.
pub const BSE: &FieldSpec = &super::REGISTERS[198].fields[5];
}
/// The fields of `MDMA_C15CR`.
pub mod mdma_c15cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[199].fields[0];
/// `TEIE`, bit 1.
pub const TEIE: &FieldSpec = &super::REGISTERS[199].fields[1];
/// `CTCIE`, bit 2.
pub const CTCIE: &FieldSpec = &super::REGISTERS[199].fields[2];
/// `BRTIE`, bit 3.
pub const BRTIE: &FieldSpec = &super::REGISTERS[199].fields[3];
/// `BTIE`, bit 4.
pub const BTIE: &FieldSpec = &super::REGISTERS[199].fields[4];
/// `TCIE`, bit 5.
pub const TCIE: &FieldSpec = &super::REGISTERS[199].fields[5];
/// `PL`, bits 6..=7.
pub const PL: &FieldSpec = &super::REGISTERS[199].fields[6];
/// `BEX`, bit 12.
pub const BEX: &FieldSpec = &super::REGISTERS[199].fields[7];
/// `HEX`, bit 13.
pub const HEX: &FieldSpec = &super::REGISTERS[199].fields[8];
/// `WEX`, bit 14.
pub const WEX: &FieldSpec = &super::REGISTERS[199].fields[9];
/// `SWRQ`, bit 16, write-only.
pub const SWRQ: &FieldSpec = &super::REGISTERS[199].fields[10];
}
/// The fields of `MDMA_C15TCR`.
pub mod mdma_c15tcr {
use super::FieldSpec;
/// `SINC`, bits 0..=1.
pub const SINC: &FieldSpec = &super::REGISTERS[200].fields[0];
/// `DINC`, bits 2..=3.
pub const DINC: &FieldSpec = &super::REGISTERS[200].fields[1];
/// `SSIZE`, bits 4..=5.
pub const SSIZE: &FieldSpec = &super::REGISTERS[200].fields[2];
/// `DSIZE`, bits 6..=7.
pub const DSIZE: &FieldSpec = &super::REGISTERS[200].fields[3];
/// `SINCOS`, bits 8..=9.
pub const SINCOS: &FieldSpec = &super::REGISTERS[200].fields[4];
/// `DINCOS`, bits 10..=11.
pub const DINCOS: &FieldSpec = &super::REGISTERS[200].fields[5];
/// `SBURST`, bits 12..=14.
pub const SBURST: &FieldSpec = &super::REGISTERS[200].fields[6];
/// `DBURST`, bits 15..=17.
pub const DBURST: &FieldSpec = &super::REGISTERS[200].fields[7];
/// `TLEN`, bits 18..=24.
pub const TLEN: &FieldSpec = &super::REGISTERS[200].fields[8];
/// `PKE`, bit 25.
pub const PKE: &FieldSpec = &super::REGISTERS[200].fields[9];
/// `PAM`, bits 26..=27.
pub const PAM: &FieldSpec = &super::REGISTERS[200].fields[10];
/// `TRGM`, bits 28..=29.
pub const TRGM: &FieldSpec = &super::REGISTERS[200].fields[11];
/// `SWRM`, bit 30.
pub const SWRM: &FieldSpec = &super::REGISTERS[200].fields[12];
/// `BWM`, bit 31.
pub const BWM: &FieldSpec = &super::REGISTERS[200].fields[13];
}
/// The fields of `MDMA_C15BNDTR`.
pub mod mdma_c15bndtr {
use super::FieldSpec;
/// `BNDT`, bits 0..=16.
pub const BNDT: &FieldSpec = &super::REGISTERS[201].fields[0];
/// `BRSUM`, bit 18.
pub const BRSUM: &FieldSpec = &super::REGISTERS[201].fields[1];
/// `BRDUM`, bit 19.
pub const BRDUM: &FieldSpec = &super::REGISTERS[201].fields[2];
/// `BRC`, bits 20..=31.
pub const BRC: &FieldSpec = &super::REGISTERS[201].fields[3];
}
/// The fields of `MDMA_C15SAR`.
pub mod mdma_c15sar {
use super::FieldSpec;
/// `SAR`, bits 0..=31.
pub const SAR: &FieldSpec = &super::REGISTERS[202].fields[0];
}
/// The fields of `MDMA_C15DAR`.
pub mod mdma_c15dar {
use super::FieldSpec;
/// `DAR`, bits 0..=31.
pub const DAR: &FieldSpec = &super::REGISTERS[203].fields[0];
}
/// The fields of `MDMA_C15BRUR`.
pub mod mdma_c15brur {
use super::FieldSpec;
/// `SUV`, bits 0..=15.
pub const SUV: &FieldSpec = &super::REGISTERS[204].fields[0];
/// `DUV`, bits 16..=31.
pub const DUV: &FieldSpec = &super::REGISTERS[204].fields[1];
}
/// The fields of `MDMA_C15LAR`.
pub mod mdma_c15lar {
use super::FieldSpec;
/// `LAR`, bits 0..=31.
pub const LAR: &FieldSpec = &super::REGISTERS[205].fields[0];
}
/// The fields of `MDMA_C15TBR`.
pub mod mdma_c15tbr {
use super::FieldSpec;
/// `TSEL`, bits 0..=5.
pub const TSEL: &FieldSpec = &super::REGISTERS[206].fields[0];
/// `SBUS`, bit 16.
pub const SBUS: &FieldSpec = &super::REGISTERS[206].fields[1];
/// `DBUS`, bit 17.
pub const DBUS: &FieldSpec = &super::REGISTERS[206].fields[2];
}
/// The fields of `MDMA_C15MAR`.
pub mod mdma_c15mar {
use super::FieldSpec;
/// `MAR`, bits 0..=31.
pub const MAR: &FieldSpec = &super::REGISTERS[207].fields[0];
}
/// The fields of `MDMA_C15MDR`.
pub mod mdma_c15mdr {
use super::FieldSpec;
/// `MDR`, bits 0..=31.
pub const MDR: &FieldSpec = &super::REGISTERS[208].fields[0];
}
/// The register table.
pub static REGISTERS: [RegisterSpec; 209] = [
RegisterSpec { name: "MDMA_GISR0", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "GIF0", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GIF1", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GIF2", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GIF3", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GIF4", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GIF5", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GIF6", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GIF7", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GIF8", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GIF9", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GIF10", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GIF11", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GIF12", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GIF13", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GIF14", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GIF15", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C0ISR", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEIF0", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIF0", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIF0", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIF0", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIF0", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRQA0", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C0IFCR", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CTEIF0", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CCTCIF0", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBRTIF0", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBTIF0", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLTCIF0", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C0ESR", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEA", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TED", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TELD", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEMD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ASE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BSE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C0CR", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PL", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BEX", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HEX", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WEX", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRQ", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C0TCR", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SINC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SSIZE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DSIZE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SINCOS", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINCOS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBURST", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBURST", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TLEN", bit: 18, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PKE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PAM", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TRGM", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BWM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C0BNDTR", offset: 0x54, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BNDT", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRSUM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRDUM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRC", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C0SAR", offset: 0x58, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C0DAR", offset: 0x5C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C0BRUR", offset: 0x60, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUV", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DUV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C0LAR", offset: 0x64, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C0TBR", offset: 0x68, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TSEL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBUS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBUS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C0MAR", offset: 0x70, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C0MDR", offset: 0x74, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C1ISR", offset: 0x80, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEIF1", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIF1", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIF1", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIF1", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIF1", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRQA1", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C1IFCR", offset: 0x84, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CTEIF1", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CCTCIF1", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBRTIF1", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBTIF1", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLTCIF1", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C1ESR", offset: 0x88, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEA", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TED", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TELD", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEMD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ASE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BSE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C1CR", offset: 0x8C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PL", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BEX", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HEX", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WEX", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRQ", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C1TCR", offset: 0x90, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SINC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SSIZE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DSIZE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SINCOS", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINCOS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBURST", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBURST", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TLEN", bit: 18, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PKE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PAM", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TRGM", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BWM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C1BNDTR", offset: 0x94, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BNDT", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRSUM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRDUM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRC", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C1SAR", offset: 0x98, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C1DAR", offset: 0x9C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C1BRUR", offset: 0xA0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUV", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DUV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C1LAR", offset: 0xA4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C1TBR", offset: 0xA8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TSEL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBUS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBUS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C1MAR", offset: 0xB0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C1MDR", offset: 0xB4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C2ISR", offset: 0xC0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEIF2", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIF2", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIF2", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIF2", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIF2", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRQA2", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C2IFCR", offset: 0xC4, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CTEIF2", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CCTCIF2", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBRTIF2", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBTIF2", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLTCIF2", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C2ESR", offset: 0xC8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEA", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TED", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TELD", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEMD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ASE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BSE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C2CR", offset: 0xCC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PL", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BEX", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HEX", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WEX", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRQ", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C2TCR", offset: 0xD0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SINC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SSIZE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DSIZE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SINCOS", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINCOS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBURST", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBURST", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TLEN", bit: 18, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PKE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PAM", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TRGM", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BWM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C2BNDTR", offset: 0xD4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BNDT", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRSUM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRDUM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRC", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C2SAR", offset: 0xD8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C2DAR", offset: 0xDC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C2BRUR", offset: 0xE0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUV", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DUV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C2LAR", offset: 0xE4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C2TBR", offset: 0xE8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TSEL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBUS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBUS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C2MAR", offset: 0xF0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C2MDR", offset: 0xF4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C3ISR", offset: 0x100, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEIF3", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIF3", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIF3", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIF3", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIF3", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRQA3", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C3IFCR", offset: 0x104, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CTEIF3", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CCTCIF3", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBRTIF3", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBTIF3", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLTCIF3", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C3ESR", offset: 0x108, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEA", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TED", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TELD", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEMD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ASE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BSE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C3CR", offset: 0x10C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PL", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BEX", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HEX", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WEX", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRQ", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C3TCR", offset: 0x110, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SINC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SSIZE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DSIZE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SINCOS", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINCOS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBURST", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBURST", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TLEN", bit: 18, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PKE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PAM", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TRGM", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BWM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C3BNDTR", offset: 0x114, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BNDT", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRSUM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRDUM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRC", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C3SAR", offset: 0x118, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C3DAR", offset: 0x11C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C3BRUR", offset: 0x120, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUV", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DUV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C3LAR", offset: 0x124, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C3TBR", offset: 0x128, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TSEL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBUS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBUS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C3MAR", offset: 0x130, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C3MDR", offset: 0x134, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C4ISR", offset: 0x140, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEIF4", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIF4", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIF4", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIF4", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIF4", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRQA4", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C4IFCR", offset: 0x144, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CTEIF4", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CCTCIF4", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBRTIF4", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBTIF4", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLTCIF4", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C4ESR", offset: 0x148, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEA", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TED", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TELD", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEMD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ASE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BSE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C4CR", offset: 0x14C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PL", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BEX", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HEX", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WEX", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRQ", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C4TCR", offset: 0x150, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SINC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SSIZE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DSIZE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SINCOS", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINCOS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBURST", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBURST", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TLEN", bit: 18, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PKE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PAM", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TRGM", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BWM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C4BNDTR", offset: 0x154, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BNDT", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRSUM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRDUM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRC", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C4SAR", offset: 0x158, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C4DAR", offset: 0x15C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C4BRUR", offset: 0x160, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUV", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DUV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C4LAR", offset: 0x164, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C4TBR", offset: 0x168, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TSEL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBUS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBUS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C4MAR", offset: 0x170, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C4MDR", offset: 0x174, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C5ISR", offset: 0x180, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEIF5", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIF5", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIF5", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIF5", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIF5", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRQA5", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C5IFCR", offset: 0x184, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CTEIF5", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CCTCIF5", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBRTIF5", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBTIF5", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLTCIF5", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C5ESR", offset: 0x188, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEA", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TED", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TELD", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEMD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ASE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BSE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C5CR", offset: 0x18C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PL", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BEX", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HEX", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WEX", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRQ", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C5TCR", offset: 0x190, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SINC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SSIZE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DSIZE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SINCOS", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINCOS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBURST", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBURST", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TLEN", bit: 18, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PKE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PAM", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TRGM", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BWM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C5BNDTR", offset: 0x194, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BNDT", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRSUM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRDUM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRC", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C5SAR", offset: 0x198, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C5DAR", offset: 0x19C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C5BRUR", offset: 0x1A0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUV", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DUV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C5LAR", offset: 0x1A4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C5TBR", offset: 0x1A8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TSEL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBUS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBUS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C5MAR", offset: 0x1B0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C5MDR", offset: 0x1B4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C6ISR", offset: 0x1C0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEIF6", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIF6", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIF6", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIF6", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIF6", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRQA6", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C6IFCR", offset: 0x1C4, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CTEIF6", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CCTCIF6", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBRTIF6", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBTIF6", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLTCIF6", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C6ESR", offset: 0x1C8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEA", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TED", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TELD", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEMD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ASE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BSE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C6CR", offset: 0x1CC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PL", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BEX", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HEX", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WEX", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRQ", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C6TCR", offset: 0x1D0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SINC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SSIZE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DSIZE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SINCOS", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINCOS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBURST", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBURST", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TLEN", bit: 18, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PKE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PAM", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TRGM", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BWM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C6BNDTR", offset: 0x1D4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BNDT", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRSUM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRDUM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRC", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C6SAR", offset: 0x1D8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C6DAR", offset: 0x1DC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C6BRUR", offset: 0x1E0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUV", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DUV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C6LAR", offset: 0x1E4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C6TBR", offset: 0x1E8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TSEL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBUS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBUS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C6MAR", offset: 0x1F0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C6MDR", offset: 0x1F4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C7ISR", offset: 0x200, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEIF7", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIF7", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIF7", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIF7", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIF7", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRQA7", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C7IFCR", offset: 0x204, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CTEIF7", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CCTCIF7", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBRTIF7", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBTIF7", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLTCIF7", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C7ESR", offset: 0x208, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEA", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TED", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TELD", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEMD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ASE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BSE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C7CR", offset: 0x20C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PL", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BEX", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HEX", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WEX", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRQ", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C7TCR", offset: 0x210, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SINC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SSIZE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DSIZE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SINCOS", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINCOS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBURST", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBURST", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TLEN", bit: 18, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PKE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PAM", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TRGM", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BWM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C7BNDTR", offset: 0x214, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BNDT", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRSUM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRDUM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRC", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C7SAR", offset: 0x218, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C7DAR", offset: 0x21C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C7BRUR", offset: 0x220, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUV", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DUV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C7LAR", offset: 0x224, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C7TBR", offset: 0x228, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TSEL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBUS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBUS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C7MAR", offset: 0x230, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C7MDR", offset: 0x234, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C8ISR", offset: 0x240, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEIF8", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIF8", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIF8", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIF8", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIF8", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRQA8", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C8IFCR", offset: 0x244, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CTEIF8", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CCTCIF8", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBRTIF8", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBTIF8", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLTCIF8", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C8ESR", offset: 0x248, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEA", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TED", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TELD", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEMD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ASE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BSE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C8CR", offset: 0x24C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PL", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BEX", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HEX", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WEX", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRQ", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C8TCR", offset: 0x250, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SINC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SSIZE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DSIZE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SINCOS", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINCOS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBURST", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBURST", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TLEN", bit: 18, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PKE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PAM", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TRGM", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BWM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C8BNDTR", offset: 0x254, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BNDT", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRSUM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRDUM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRC", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C8SAR", offset: 0x258, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C8DAR", offset: 0x25C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C8BRUR", offset: 0x260, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUV", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DUV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C8LAR", offset: 0x264, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C8TBR", offset: 0x268, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TSEL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBUS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBUS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C8MAR", offset: 0x270, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C8MDR", offset: 0x274, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C9ISR", offset: 0x280, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEIF9", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIF9", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIF9", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIF9", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIF9", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRQA9", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C9IFCR", offset: 0x284, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CTEIF9", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CCTCIF9", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBRTIF9", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBTIF9", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLTCIF9", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C9ESR", offset: 0x288, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEA", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TED", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TELD", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEMD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ASE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BSE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C9CR", offset: 0x28C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PL", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BEX", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HEX", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WEX", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRQ", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C9TCR", offset: 0x290, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SINC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SSIZE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DSIZE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SINCOS", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINCOS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBURST", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBURST", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TLEN", bit: 18, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PKE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PAM", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TRGM", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BWM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C9BNDTR", offset: 0x294, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BNDT", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRSUM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRDUM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRC", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C9SAR", offset: 0x298, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C9DAR", offset: 0x29C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C9BRUR", offset: 0x2A0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUV", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DUV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C9LAR", offset: 0x2A4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C9TBR", offset: 0x2A8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TSEL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBUS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBUS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C9MAR", offset: 0x2B0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C9MDR", offset: 0x2B4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C10ISR", offset: 0x2C0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEIF10", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIF10", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIF10", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIF10", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIF10", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRQA10", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C10IFCR", offset: 0x2C4, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CTEIF10", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CCTCIF10", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBRTIF10", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBTIF10", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLTCIF10", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C10ESR", offset: 0x2C8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEA", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TED", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TELD", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEMD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ASE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BSE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C10CR", offset: 0x2CC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PL", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BEX", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HEX", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WEX", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRQ", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C10TCR", offset: 0x2D0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SINC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SSIZE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DSIZE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SINCOS", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINCOS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBURST", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBURST", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TLEN", bit: 18, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PKE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PAM", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TRGM", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BWM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C10BNDTR", offset: 0x2D4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BNDT", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRSUM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRDUM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRC", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C10SAR", offset: 0x2D8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C10DAR", offset: 0x2DC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C10BRUR", offset: 0x2E0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUV", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DUV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C10LAR", offset: 0x2E4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C10TBR", offset: 0x2E8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TSEL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBUS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBUS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C10MAR", offset: 0x2F0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C10MDR", offset: 0x2F4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C11ISR", offset: 0x300, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEIF11", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIF11", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIF11", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIF11", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIF11", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRQA11", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C11IFCR", offset: 0x304, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CTEIF11", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CCTCIF11", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBRTIF11", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBTIF11", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLTCIF11", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C11ESR", offset: 0x308, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEA", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TED", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TELD", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEMD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ASE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BSE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C11CR", offset: 0x30C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PL", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BEX", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HEX", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WEX", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRQ", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C11TCR", offset: 0x310, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SINC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SSIZE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DSIZE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SINCOS", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINCOS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBURST", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBURST", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TLEN", bit: 18, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PKE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PAM", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TRGM", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BWM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C11BNDTR", offset: 0x314, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BNDT", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRSUM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRDUM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRC", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C11SAR", offset: 0x318, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C11DAR", offset: 0x31C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C11BRUR", offset: 0x320, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUV", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DUV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C11LAR", offset: 0x324, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C11TBR", offset: 0x328, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TSEL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBUS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBUS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C11MAR", offset: 0x330, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C11MDR", offset: 0x334, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C12ISR", offset: 0x340, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEIF12", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIF12", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIF12", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIF12", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIF12", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRQA12", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C12IFCR", offset: 0x344, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CTEIF12", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CCTCIF12", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBRTIF12", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBTIF12", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLTCIF12", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C12ESR", offset: 0x348, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEA", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TED", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TELD", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEMD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ASE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BSE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C12CR", offset: 0x34C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PL", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BEX", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HEX", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WEX", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRQ", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C12TCR", offset: 0x350, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SINC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SSIZE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DSIZE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SINCOS", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINCOS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBURST", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBURST", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TLEN", bit: 18, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PKE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PAM", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TRGM", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BWM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C12BNDTR", offset: 0x354, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BNDT", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRSUM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRDUM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRC", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C12SAR", offset: 0x358, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C12DAR", offset: 0x35C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C12BRUR", offset: 0x360, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUV", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DUV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C12LAR", offset: 0x364, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C12TBR", offset: 0x368, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TSEL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBUS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBUS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C12MAR", offset: 0x370, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C12MDR", offset: 0x374, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C13ISR", offset: 0x380, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEIF13", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIF13", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIF13", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIF13", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIF13", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRQA13", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C13IFCR", offset: 0x384, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CTEIF13", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CCTCIF13", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBRTIF13", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBTIF13", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLTCIF13", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C13ESR", offset: 0x388, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEA", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TED", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TELD", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEMD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ASE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BSE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C13CR", offset: 0x38C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PL", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BEX", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HEX", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WEX", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRQ", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C13TCR", offset: 0x390, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SINC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SSIZE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DSIZE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SINCOS", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINCOS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBURST", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBURST", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TLEN", bit: 18, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PKE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PAM", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TRGM", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BWM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C13BNDTR", offset: 0x394, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BNDT", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRSUM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRDUM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRC", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C13SAR", offset: 0x398, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C13DAR", offset: 0x39C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C13BRUR", offset: 0x3A0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUV", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DUV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C13LAR", offset: 0x3A4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C13TBR", offset: 0x3A8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TSEL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBUS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBUS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C13MAR", offset: 0x3B0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C13MDR", offset: 0x3B4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C14ISR", offset: 0x3C0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEIF14", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIF14", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIF14", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIF14", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIF14", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRQA14", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C14IFCR", offset: 0x3C4, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CTEIF14", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CCTCIF14", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBRTIF14", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBTIF14", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLTCIF14", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C14ESR", offset: 0x3C8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEA", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TED", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TELD", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEMD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ASE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BSE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C14CR", offset: 0x3CC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PL", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BEX", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HEX", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WEX", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRQ", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C14TCR", offset: 0x3D0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SINC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SSIZE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DSIZE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SINCOS", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINCOS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBURST", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBURST", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TLEN", bit: 18, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PKE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PAM", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TRGM", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BWM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C14BNDTR", offset: 0x3D4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BNDT", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRSUM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRDUM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRC", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C14SAR", offset: 0x3D8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C14DAR", offset: 0x3DC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C14BRUR", offset: 0x3E0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUV", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DUV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C14LAR", offset: 0x3E4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C14TBR", offset: 0x3E8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TSEL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBUS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBUS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C14MAR", offset: 0x3F0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C14MDR", offset: 0x3F4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C15ISR", offset: 0x400, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEIF15", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIF15", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIF15", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIF15", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIF15", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRQA15", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C15IFCR", offset: 0x404, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CTEIF15", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CCTCIF15", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBRTIF15", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CBTIF15", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLTCIF15", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C15ESR", offset: 0x408, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TEA", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TED", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TELD", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEMD", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ASE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BSE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C15CR", offset: 0x40C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BTIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PL", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BEX", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HEX", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WEX", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRQ", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C15TCR", offset: 0x410, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SINC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SSIZE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DSIZE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SINCOS", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DINCOS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBURST", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBURST", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TLEN", bit: 18, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PKE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PAM", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TRGM", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWRM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BWM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C15BNDTR", offset: 0x414, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BNDT", bit: 0, width: 17, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRSUM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRDUM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BRC", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C15SAR", offset: 0x418, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C15DAR", offset: 0x41C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C15BRUR", offset: 0x420, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUV", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DUV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C15LAR", offset: 0x424, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C15TBR", offset: 0x428, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TSEL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SBUS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBUS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C15MAR", offset: 0x430, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MAR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "MDMA_C15MDR", offset: 0x434, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
];