rigless 0.3.0

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `HSEM` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `HSEM_R0` at offset `0x0`, resets to `0x0000_0000`, read-write.
    HsemR0 = 0,
    /// `HSEM_R1` at offset `0x4`, resets to `0x0000_0000`, read-write.
    HsemR1 = 1,
    /// `HSEM_R2` at offset `0x8`, resets to `0x0000_0000`, read-write.
    HsemR2 = 2,
    /// `HSEM_R3` at offset `0xC`, resets to `0x0000_0000`, read-write.
    HsemR3 = 3,
    /// `HSEM_R4` at offset `0x10`, resets to `0x0000_0000`, read-write.
    HsemR4 = 4,
    /// `HSEM_R5` at offset `0x14`, resets to `0x0000_0000`, read-write.
    HsemR5 = 5,
    /// `HSEM_R6` at offset `0x18`, resets to `0x0000_0000`, read-write.
    HsemR6 = 6,
    /// `HSEM_R7` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    HsemR7 = 7,
    /// `HSEM_R8` at offset `0x20`, resets to `0x0000_0000`, read-write.
    HsemR8 = 8,
    /// `HSEM_R9` at offset `0x24`, resets to `0x0000_0000`, read-write.
    HsemR9 = 9,
    /// `HSEM_R10` at offset `0x28`, resets to `0x0000_0000`, read-write.
    HsemR10 = 10,
    /// `HSEM_R11` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    HsemR11 = 11,
    /// `HSEM_R12` at offset `0x30`, resets to `0x0000_0000`, read-write.
    HsemR12 = 12,
    /// `HSEM_R13` at offset `0x34`, resets to `0x0000_0000`, read-write.
    HsemR13 = 13,
    /// `HSEM_R14` at offset `0x38`, resets to `0x0000_0000`, read-write.
    HsemR14 = 14,
    /// `HSEM_R15` at offset `0x3C`, resets to `0x0000_0000`, read-write.
    HsemR15 = 15,
    /// `HSEM_R16` at offset `0x40`, resets to `0x0000_0000`, read-write.
    HsemR16 = 16,
    /// `HSEM_R17` at offset `0x44`, resets to `0x0000_0000`, read-write.
    HsemR17 = 17,
    /// `HSEM_R18` at offset `0x48`, resets to `0x0000_0000`, read-write.
    HsemR18 = 18,
    /// `HSEM_R19` at offset `0x4C`, resets to `0x0000_0000`, read-write.
    HsemR19 = 19,
    /// `HSEM_R20` at offset `0x50`, resets to `0x0000_0000`, read-write.
    HsemR20 = 20,
    /// `HSEM_R21` at offset `0x54`, resets to `0x0000_0000`, read-write.
    HsemR21 = 21,
    /// `HSEM_R22` at offset `0x58`, resets to `0x0000_0000`, read-write.
    HsemR22 = 22,
    /// `HSEM_R23` at offset `0x5C`, resets to `0x0000_0000`, read-write.
    HsemR23 = 23,
    /// `HSEM_R24` at offset `0x60`, resets to `0x0000_0000`, read-write.
    HsemR24 = 24,
    /// `HSEM_R25` at offset `0x64`, resets to `0x0000_0000`, read-write.
    HsemR25 = 25,
    /// `HSEM_R26` at offset `0x68`, resets to `0x0000_0000`, read-write.
    HsemR26 = 26,
    /// `HSEM_R27` at offset `0x6C`, resets to `0x0000_0000`, read-write.
    HsemR27 = 27,
    /// `HSEM_R28` at offset `0x70`, resets to `0x0000_0000`, read-write.
    HsemR28 = 28,
    /// `HSEM_R29` at offset `0x74`, resets to `0x0000_0000`, read-write.
    HsemR29 = 29,
    /// `HSEM_R30` at offset `0x78`, resets to `0x0000_0000`, read-write.
    HsemR30 = 30,
    /// `HSEM_R31` at offset `0x7C`, resets to `0x0000_0000`, read-write.
    HsemR31 = 31,
    /// `HSEM_RLR0` at offset `0x80`, resets to `0x0000_0000`, read-only.
    HsemRlr0 = 32,
    /// `HSEM_RLR1` at offset `0x84`, resets to `0x0000_0000`, read-only.
    HsemRlr1 = 33,
    /// `HSEM_RLR2` at offset `0x88`, resets to `0x0000_0000`, read-only.
    HsemRlr2 = 34,
    /// `HSEM_RLR3` at offset `0x8C`, resets to `0x0000_0000`, read-only.
    HsemRlr3 = 35,
    /// `HSEM_RLR4` at offset `0x90`, resets to `0x0000_0000`, read-only.
    HsemRlr4 = 36,
    /// `HSEM_RLR5` at offset `0x94`, resets to `0x0000_0000`, read-only.
    HsemRlr5 = 37,
    /// `HSEM_RLR6` at offset `0x98`, resets to `0x0000_0000`, read-only.
    HsemRlr6 = 38,
    /// `HSEM_RLR7` at offset `0x9C`, resets to `0x0000_0000`, read-only.
    HsemRlr7 = 39,
    /// `HSEM_RLR8` at offset `0xA0`, resets to `0x0000_0000`, read-only.
    HsemRlr8 = 40,
    /// `HSEM_RLR9` at offset `0xA4`, resets to `0x0000_0000`, read-only.
    HsemRlr9 = 41,
    /// `HSEM_RLR10` at offset `0xA8`, resets to `0x0000_0000`, read-only.
    HsemRlr10 = 42,
    /// `HSEM_RLR11` at offset `0xAC`, resets to `0x0000_0000`, read-only.
    HsemRlr11 = 43,
    /// `HSEM_RLR12` at offset `0xB0`, resets to `0x0000_0000`, read-only.
    HsemRlr12 = 44,
    /// `HSEM_RLR13` at offset `0xB4`, resets to `0x0000_0000`, read-only.
    HsemRlr13 = 45,
    /// `HSEM_RLR14` at offset `0xB8`, resets to `0x0000_0000`, read-only.
    HsemRlr14 = 46,
    /// `HSEM_RLR15` at offset `0xBC`, resets to `0x0000_0000`, read-only.
    HsemRlr15 = 47,
    /// `HSEM_RLR16` at offset `0xC0`, resets to `0x0000_0000`, read-only.
    HsemRlr16 = 48,
    /// `HSEM_RLR17` at offset `0xC4`, resets to `0x0000_0000`, read-only.
    HsemRlr17 = 49,
    /// `HSEM_RLR18` at offset `0xC8`, resets to `0x0000_0000`, read-only.
    HsemRlr18 = 50,
    /// `HSEM_RLR19` at offset `0xCC`, resets to `0x0000_0000`, read-only.
    HsemRlr19 = 51,
    /// `HSEM_RLR20` at offset `0xD0`, resets to `0x0000_0000`, read-only.
    HsemRlr20 = 52,
    /// `HSEM_RLR21` at offset `0xD4`, resets to `0x0000_0000`, read-only.
    HsemRlr21 = 53,
    /// `HSEM_RLR22` at offset `0xD8`, resets to `0x0000_0000`, read-only.
    HsemRlr22 = 54,
    /// `HSEM_RLR23` at offset `0xDC`, resets to `0x0000_0000`, read-only.
    HsemRlr23 = 55,
    /// `HSEM_RLR24` at offset `0xE0`, resets to `0x0000_0000`, read-only.
    HsemRlr24 = 56,
    /// `HSEM_RLR25` at offset `0xE4`, resets to `0x0000_0000`, read-only.
    HsemRlr25 = 57,
    /// `HSEM_RLR26` at offset `0xE8`, resets to `0x0000_0000`, read-only.
    HsemRlr26 = 58,
    /// `HSEM_RLR27` at offset `0xEC`, resets to `0x0000_0000`, read-only.
    HsemRlr27 = 59,
    /// `HSEM_RLR28` at offset `0xF0`, resets to `0x0000_0000`, read-only.
    HsemRlr28 = 60,
    /// `HSEM_RLR29` at offset `0xF4`, resets to `0x0000_0000`, read-only.
    HsemRlr29 = 61,
    /// `HSEM_RLR30` at offset `0xF8`, resets to `0x0000_0000`, read-only.
    HsemRlr30 = 62,
    /// `HSEM_RLR31` at offset `0xFC`, resets to `0x0000_0000`, read-only.
    HsemRlr31 = 63,
    /// `HSEM_IER` at offset `0x100`, resets to `0x0000_0000`, read-write.
    HsemIer = 64,
    /// `HSEM_ICR` at offset `0x104`, resets to `0x0000_0000`, read-only.
    HsemIcr = 65,
    /// `HSEM_ISR` at offset `0x108`, resets to `0x0000_0000`, read-only.
    HsemIsr = 66,
    /// `HSEM_MISR` at offset `0x10C`, resets to `0x0000_0000`, read-only.
    HsemMisr = 67,
    /// `HSEM_CR` at offset `0x140`, resets to `0x0000_0000`, read-write.
    HsemCr = 68,
    /// `HSEM_KEYR` at offset `0x144`, resets to `0x0000_0000`, read-write.
    HsemKeyr = 69,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 70] = [Self::HsemR0, Self::HsemR1, Self::HsemR2, Self::HsemR3, Self::HsemR4, Self::HsemR5, Self::HsemR6, Self::HsemR7, Self::HsemR8, Self::HsemR9, Self::HsemR10, Self::HsemR11, Self::HsemR12, Self::HsemR13, Self::HsemR14, Self::HsemR15, Self::HsemR16, Self::HsemR17, Self::HsemR18, Self::HsemR19, Self::HsemR20, Self::HsemR21, Self::HsemR22, Self::HsemR23, Self::HsemR24, Self::HsemR25, Self::HsemR26, Self::HsemR27, Self::HsemR28, Self::HsemR29, Self::HsemR30, Self::HsemR31, Self::HsemRlr0, Self::HsemRlr1, Self::HsemRlr2, Self::HsemRlr3, Self::HsemRlr4, Self::HsemRlr5, Self::HsemRlr6, Self::HsemRlr7, Self::HsemRlr8, Self::HsemRlr9, Self::HsemRlr10, Self::HsemRlr11, Self::HsemRlr12, Self::HsemRlr13, Self::HsemRlr14, Self::HsemRlr15, Self::HsemRlr16, Self::HsemRlr17, Self::HsemRlr18, Self::HsemRlr19, Self::HsemRlr20, Self::HsemRlr21, Self::HsemRlr22, Self::HsemRlr23, Self::HsemRlr24, Self::HsemRlr25, Self::HsemRlr26, Self::HsemRlr27, Self::HsemRlr28, Self::HsemRlr29, Self::HsemRlr30, Self::HsemRlr31, Self::HsemIer, Self::HsemIcr, Self::HsemIsr, Self::HsemMisr, Self::HsemCr, Self::HsemKeyr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `HSEM_R0`.
pub mod hsem_r0 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[0].fields[2];
}

/// The fields of `HSEM_R1`.
pub mod hsem_r1 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[1].fields[2];
}

/// The fields of `HSEM_R2`.
pub mod hsem_r2 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[2].fields[2];
}

/// The fields of `HSEM_R3`.
pub mod hsem_r3 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[3].fields[2];
}

/// The fields of `HSEM_R4`.
pub mod hsem_r4 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[4].fields[2];
}

/// The fields of `HSEM_R5`.
pub mod hsem_r5 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[5].fields[2];
}

/// The fields of `HSEM_R6`.
pub mod hsem_r6 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[6].fields[2];
}

/// The fields of `HSEM_R7`.
pub mod hsem_r7 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[7].fields[2];
}

/// The fields of `HSEM_R8`.
pub mod hsem_r8 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[8].fields[2];
}

/// The fields of `HSEM_R9`.
pub mod hsem_r9 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[9].fields[2];
}

/// The fields of `HSEM_R10`.
pub mod hsem_r10 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[10].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[10].fields[2];
}

/// The fields of `HSEM_R11`.
pub mod hsem_r11 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[11].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[11].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[11].fields[2];
}

/// The fields of `HSEM_R12`.
pub mod hsem_r12 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[12].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[12].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[12].fields[2];
}

/// The fields of `HSEM_R13`.
pub mod hsem_r13 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[13].fields[2];
}

/// The fields of `HSEM_R14`.
pub mod hsem_r14 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[14].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[14].fields[2];
}

/// The fields of `HSEM_R15`.
pub mod hsem_r15 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[15].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[15].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[15].fields[2];
}

/// The fields of `HSEM_R16`.
pub mod hsem_r16 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[16].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[16].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[16].fields[2];
}

/// The fields of `HSEM_R17`.
pub mod hsem_r17 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[17].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[17].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[17].fields[2];
}

/// The fields of `HSEM_R18`.
pub mod hsem_r18 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[18].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[18].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[18].fields[2];
}

/// The fields of `HSEM_R19`.
pub mod hsem_r19 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[19].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[19].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[19].fields[2];
}

/// The fields of `HSEM_R20`.
pub mod hsem_r20 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[20].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[20].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[20].fields[2];
}

/// The fields of `HSEM_R21`.
pub mod hsem_r21 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[21].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[21].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[21].fields[2];
}

/// The fields of `HSEM_R22`.
pub mod hsem_r22 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[22].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[22].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[22].fields[2];
}

/// The fields of `HSEM_R23`.
pub mod hsem_r23 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[23].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[23].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[23].fields[2];
}

/// The fields of `HSEM_R24`.
pub mod hsem_r24 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[24].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[24].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[24].fields[2];
}

/// The fields of `HSEM_R25`.
pub mod hsem_r25 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[25].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[25].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[25].fields[2];
}

/// The fields of `HSEM_R26`.
pub mod hsem_r26 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[26].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[26].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[26].fields[2];
}

/// The fields of `HSEM_R27`.
pub mod hsem_r27 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[27].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[27].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[27].fields[2];
}

/// The fields of `HSEM_R28`.
pub mod hsem_r28 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[28].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[28].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[28].fields[2];
}

/// The fields of `HSEM_R29`.
pub mod hsem_r29 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[29].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[29].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[29].fields[2];
}

/// The fields of `HSEM_R30`.
pub mod hsem_r30 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[30].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[30].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[30].fields[2];
}

/// The fields of `HSEM_R31`.
pub mod hsem_r31 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[31].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[31].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[31].fields[2];
}

/// The fields of `HSEM_RLR0`.
pub mod hsem_rlr0 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[32].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[32].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[32].fields[2];
}

/// The fields of `HSEM_RLR1`.
pub mod hsem_rlr1 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[33].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[33].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[33].fields[2];
}

/// The fields of `HSEM_RLR2`.
pub mod hsem_rlr2 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[34].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[34].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[34].fields[2];
}

/// The fields of `HSEM_RLR3`.
pub mod hsem_rlr3 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[35].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[35].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[35].fields[2];
}

/// The fields of `HSEM_RLR4`.
pub mod hsem_rlr4 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[36].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[36].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[36].fields[2];
}

/// The fields of `HSEM_RLR5`.
pub mod hsem_rlr5 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[37].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[37].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[37].fields[2];
}

/// The fields of `HSEM_RLR6`.
pub mod hsem_rlr6 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[38].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[38].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[38].fields[2];
}

/// The fields of `HSEM_RLR7`.
pub mod hsem_rlr7 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[39].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[39].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[39].fields[2];
}

/// The fields of `HSEM_RLR8`.
pub mod hsem_rlr8 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[40].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[40].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[40].fields[2];
}

/// The fields of `HSEM_RLR9`.
pub mod hsem_rlr9 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[41].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[41].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[41].fields[2];
}

/// The fields of `HSEM_RLR10`.
pub mod hsem_rlr10 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[42].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[42].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[42].fields[2];
}

/// The fields of `HSEM_RLR11`.
pub mod hsem_rlr11 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[43].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[43].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[43].fields[2];
}

/// The fields of `HSEM_RLR12`.
pub mod hsem_rlr12 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[44].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[44].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[44].fields[2];
}

/// The fields of `HSEM_RLR13`.
pub mod hsem_rlr13 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[45].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[45].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[45].fields[2];
}

/// The fields of `HSEM_RLR14`.
pub mod hsem_rlr14 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[46].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[46].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[46].fields[2];
}

/// The fields of `HSEM_RLR15`.
pub mod hsem_rlr15 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[47].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[47].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[47].fields[2];
}

/// The fields of `HSEM_RLR16`.
pub mod hsem_rlr16 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[48].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[48].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[48].fields[2];
}

/// The fields of `HSEM_RLR17`.
pub mod hsem_rlr17 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[49].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[49].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[49].fields[2];
}

/// The fields of `HSEM_RLR18`.
pub mod hsem_rlr18 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[50].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[50].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[50].fields[2];
}

/// The fields of `HSEM_RLR19`.
pub mod hsem_rlr19 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[51].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[51].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[51].fields[2];
}

/// The fields of `HSEM_RLR20`.
pub mod hsem_rlr20 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[52].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[52].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[52].fields[2];
}

/// The fields of `HSEM_RLR21`.
pub mod hsem_rlr21 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[53].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[53].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[53].fields[2];
}

/// The fields of `HSEM_RLR22`.
pub mod hsem_rlr22 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[54].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[54].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[54].fields[2];
}

/// The fields of `HSEM_RLR23`.
pub mod hsem_rlr23 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[55].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[55].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[55].fields[2];
}

/// The fields of `HSEM_RLR24`.
pub mod hsem_rlr24 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[56].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[56].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[56].fields[2];
}

/// The fields of `HSEM_RLR25`.
pub mod hsem_rlr25 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[57].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[57].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[57].fields[2];
}

/// The fields of `HSEM_RLR26`.
pub mod hsem_rlr26 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[58].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[58].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[58].fields[2];
}

/// The fields of `HSEM_RLR27`.
pub mod hsem_rlr27 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[59].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[59].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[59].fields[2];
}

/// The fields of `HSEM_RLR28`.
pub mod hsem_rlr28 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[60].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[60].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[60].fields[2];
}

/// The fields of `HSEM_RLR29`.
pub mod hsem_rlr29 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[61].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[61].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[61].fields[2];
}

/// The fields of `HSEM_RLR30`.
pub mod hsem_rlr30 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[62].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[62].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[62].fields[2];
}

/// The fields of `HSEM_RLR31`.
pub mod hsem_rlr31 {
    use super::FieldSpec;
    /// `PROCID`, bits 0..=7.
    pub const PROCID: &FieldSpec = &super::REGISTERS[63].fields[0];
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[63].fields[1];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[63].fields[2];
}

/// The fields of `HSEM_IER`.
pub mod hsem_ier {
    use super::FieldSpec;
    /// `ISEM0`, bit 0.
    pub const ISEM0: &FieldSpec = &super::REGISTERS[64].fields[0];
    /// `ISEM1`, bit 1.
    pub const ISEM1: &FieldSpec = &super::REGISTERS[64].fields[1];
    /// `ISEM2`, bit 2.
    pub const ISEM2: &FieldSpec = &super::REGISTERS[64].fields[2];
    /// `ISEM3`, bit 3.
    pub const ISEM3: &FieldSpec = &super::REGISTERS[64].fields[3];
    /// `ISEM4`, bit 4.
    pub const ISEM4: &FieldSpec = &super::REGISTERS[64].fields[4];
    /// `ISEM5`, bit 5.
    pub const ISEM5: &FieldSpec = &super::REGISTERS[64].fields[5];
    /// `ISEM6`, bit 6.
    pub const ISEM6: &FieldSpec = &super::REGISTERS[64].fields[6];
    /// `ISEM7`, bit 7.
    pub const ISEM7: &FieldSpec = &super::REGISTERS[64].fields[7];
    /// `ISEM8`, bit 8.
    pub const ISEM8: &FieldSpec = &super::REGISTERS[64].fields[8];
    /// `ISEM9`, bit 9.
    pub const ISEM9: &FieldSpec = &super::REGISTERS[64].fields[9];
    /// `ISEM10`, bit 10.
    pub const ISEM10: &FieldSpec = &super::REGISTERS[64].fields[10];
    /// `ISEM11`, bit 11.
    pub const ISEM11: &FieldSpec = &super::REGISTERS[64].fields[11];
    /// `ISEM12`, bit 12.
    pub const ISEM12: &FieldSpec = &super::REGISTERS[64].fields[12];
    /// `ISEM13`, bit 13.
    pub const ISEM13: &FieldSpec = &super::REGISTERS[64].fields[13];
    /// `ISEM14`, bit 14.
    pub const ISEM14: &FieldSpec = &super::REGISTERS[64].fields[14];
    /// `ISEM15`, bit 15.
    pub const ISEM15: &FieldSpec = &super::REGISTERS[64].fields[15];
    /// `ISEM16`, bit 16.
    pub const ISEM16: &FieldSpec = &super::REGISTERS[64].fields[16];
    /// `ISEM17`, bit 17.
    pub const ISEM17: &FieldSpec = &super::REGISTERS[64].fields[17];
    /// `ISEM18`, bit 18.
    pub const ISEM18: &FieldSpec = &super::REGISTERS[64].fields[18];
    /// `ISEM19`, bit 19.
    pub const ISEM19: &FieldSpec = &super::REGISTERS[64].fields[19];
    /// `ISEM20`, bit 20.
    pub const ISEM20: &FieldSpec = &super::REGISTERS[64].fields[20];
    /// `ISEM21`, bit 21.
    pub const ISEM21: &FieldSpec = &super::REGISTERS[64].fields[21];
    /// `ISEM22`, bit 22.
    pub const ISEM22: &FieldSpec = &super::REGISTERS[64].fields[22];
    /// `ISEM23`, bit 23.
    pub const ISEM23: &FieldSpec = &super::REGISTERS[64].fields[23];
    /// `ISEM24`, bit 24.
    pub const ISEM24: &FieldSpec = &super::REGISTERS[64].fields[24];
    /// `ISEM25`, bit 25.
    pub const ISEM25: &FieldSpec = &super::REGISTERS[64].fields[25];
    /// `ISEM26`, bit 26.
    pub const ISEM26: &FieldSpec = &super::REGISTERS[64].fields[26];
    /// `ISEM27`, bit 27.
    pub const ISEM27: &FieldSpec = &super::REGISTERS[64].fields[27];
    /// `ISEM28`, bit 28.
    pub const ISEM28: &FieldSpec = &super::REGISTERS[64].fields[28];
    /// `ISEM29`, bit 29.
    pub const ISEM29: &FieldSpec = &super::REGISTERS[64].fields[29];
    /// `ISEM30`, bit 30.
    pub const ISEM30: &FieldSpec = &super::REGISTERS[64].fields[30];
    /// `ISEM31`, bit 31.
    pub const ISEM31: &FieldSpec = &super::REGISTERS[64].fields[31];
}

/// The fields of `HSEM_ICR`.
pub mod hsem_icr {
    use super::FieldSpec;
    /// `ISEM0`, bit 0.
    pub const ISEM0: &FieldSpec = &super::REGISTERS[65].fields[0];
    /// `ISEM1`, bit 1.
    pub const ISEM1: &FieldSpec = &super::REGISTERS[65].fields[1];
    /// `ISEM2`, bit 2.
    pub const ISEM2: &FieldSpec = &super::REGISTERS[65].fields[2];
    /// `ISEM3`, bit 3.
    pub const ISEM3: &FieldSpec = &super::REGISTERS[65].fields[3];
    /// `ISEM4`, bit 4.
    pub const ISEM4: &FieldSpec = &super::REGISTERS[65].fields[4];
    /// `ISEM5`, bit 5.
    pub const ISEM5: &FieldSpec = &super::REGISTERS[65].fields[5];
    /// `ISEM6`, bit 6.
    pub const ISEM6: &FieldSpec = &super::REGISTERS[65].fields[6];
    /// `ISEM7`, bit 7.
    pub const ISEM7: &FieldSpec = &super::REGISTERS[65].fields[7];
    /// `ISEM8`, bit 8.
    pub const ISEM8: &FieldSpec = &super::REGISTERS[65].fields[8];
    /// `ISEM9`, bit 9.
    pub const ISEM9: &FieldSpec = &super::REGISTERS[65].fields[9];
    /// `ISEM10`, bit 10.
    pub const ISEM10: &FieldSpec = &super::REGISTERS[65].fields[10];
    /// `ISEM11`, bit 11.
    pub const ISEM11: &FieldSpec = &super::REGISTERS[65].fields[11];
    /// `ISEM12`, bit 12.
    pub const ISEM12: &FieldSpec = &super::REGISTERS[65].fields[12];
    /// `ISEM13`, bit 13.
    pub const ISEM13: &FieldSpec = &super::REGISTERS[65].fields[13];
    /// `ISEM14`, bit 14.
    pub const ISEM14: &FieldSpec = &super::REGISTERS[65].fields[14];
    /// `ISEM15`, bit 15.
    pub const ISEM15: &FieldSpec = &super::REGISTERS[65].fields[15];
    /// `ISEM16`, bit 16.
    pub const ISEM16: &FieldSpec = &super::REGISTERS[65].fields[16];
    /// `ISEM17`, bit 17.
    pub const ISEM17: &FieldSpec = &super::REGISTERS[65].fields[17];
    /// `ISEM18`, bit 18.
    pub const ISEM18: &FieldSpec = &super::REGISTERS[65].fields[18];
    /// `ISEM19`, bit 19.
    pub const ISEM19: &FieldSpec = &super::REGISTERS[65].fields[19];
    /// `ISEM20`, bit 20.
    pub const ISEM20: &FieldSpec = &super::REGISTERS[65].fields[20];
    /// `ISEM21`, bit 21.
    pub const ISEM21: &FieldSpec = &super::REGISTERS[65].fields[21];
    /// `ISEM22`, bit 22.
    pub const ISEM22: &FieldSpec = &super::REGISTERS[65].fields[22];
    /// `ISEM23`, bit 23.
    pub const ISEM23: &FieldSpec = &super::REGISTERS[65].fields[23];
    /// `ISEM24`, bit 24.
    pub const ISEM24: &FieldSpec = &super::REGISTERS[65].fields[24];
    /// `ISEM25`, bit 25.
    pub const ISEM25: &FieldSpec = &super::REGISTERS[65].fields[25];
    /// `ISEM26`, bit 26.
    pub const ISEM26: &FieldSpec = &super::REGISTERS[65].fields[26];
    /// `ISEM27`, bit 27.
    pub const ISEM27: &FieldSpec = &super::REGISTERS[65].fields[27];
    /// `ISEM28`, bit 28.
    pub const ISEM28: &FieldSpec = &super::REGISTERS[65].fields[28];
    /// `ISEM29`, bit 29.
    pub const ISEM29: &FieldSpec = &super::REGISTERS[65].fields[29];
    /// `ISEM30`, bit 30.
    pub const ISEM30: &FieldSpec = &super::REGISTERS[65].fields[30];
    /// `ISEM31`, bit 31.
    pub const ISEM31: &FieldSpec = &super::REGISTERS[65].fields[31];
}

/// The fields of `HSEM_ISR`.
pub mod hsem_isr {
    use super::FieldSpec;
    /// `ISEM0`, bit 0.
    pub const ISEM0: &FieldSpec = &super::REGISTERS[66].fields[0];
    /// `ISEM1`, bit 1.
    pub const ISEM1: &FieldSpec = &super::REGISTERS[66].fields[1];
    /// `ISEM2`, bit 2.
    pub const ISEM2: &FieldSpec = &super::REGISTERS[66].fields[2];
    /// `ISEM3`, bit 3.
    pub const ISEM3: &FieldSpec = &super::REGISTERS[66].fields[3];
    /// `ISEM4`, bit 4.
    pub const ISEM4: &FieldSpec = &super::REGISTERS[66].fields[4];
    /// `ISEM5`, bit 5.
    pub const ISEM5: &FieldSpec = &super::REGISTERS[66].fields[5];
    /// `ISEM6`, bit 6.
    pub const ISEM6: &FieldSpec = &super::REGISTERS[66].fields[6];
    /// `ISEM7`, bit 7.
    pub const ISEM7: &FieldSpec = &super::REGISTERS[66].fields[7];
    /// `ISEM8`, bit 8.
    pub const ISEM8: &FieldSpec = &super::REGISTERS[66].fields[8];
    /// `ISEM9`, bit 9.
    pub const ISEM9: &FieldSpec = &super::REGISTERS[66].fields[9];
    /// `ISEM10`, bit 10.
    pub const ISEM10: &FieldSpec = &super::REGISTERS[66].fields[10];
    /// `ISEM11`, bit 11.
    pub const ISEM11: &FieldSpec = &super::REGISTERS[66].fields[11];
    /// `ISEM12`, bit 12.
    pub const ISEM12: &FieldSpec = &super::REGISTERS[66].fields[12];
    /// `ISEM13`, bit 13.
    pub const ISEM13: &FieldSpec = &super::REGISTERS[66].fields[13];
    /// `ISEM14`, bit 14.
    pub const ISEM14: &FieldSpec = &super::REGISTERS[66].fields[14];
    /// `ISEM15`, bit 15.
    pub const ISEM15: &FieldSpec = &super::REGISTERS[66].fields[15];
    /// `ISEM16`, bit 16.
    pub const ISEM16: &FieldSpec = &super::REGISTERS[66].fields[16];
    /// `ISEM17`, bit 17.
    pub const ISEM17: &FieldSpec = &super::REGISTERS[66].fields[17];
    /// `ISEM18`, bit 18.
    pub const ISEM18: &FieldSpec = &super::REGISTERS[66].fields[18];
    /// `ISEM19`, bit 19.
    pub const ISEM19: &FieldSpec = &super::REGISTERS[66].fields[19];
    /// `ISEM20`, bit 20.
    pub const ISEM20: &FieldSpec = &super::REGISTERS[66].fields[20];
    /// `ISEM21`, bit 21.
    pub const ISEM21: &FieldSpec = &super::REGISTERS[66].fields[21];
    /// `ISEM22`, bit 22.
    pub const ISEM22: &FieldSpec = &super::REGISTERS[66].fields[22];
    /// `ISEM23`, bit 23.
    pub const ISEM23: &FieldSpec = &super::REGISTERS[66].fields[23];
    /// `ISEM24`, bit 24.
    pub const ISEM24: &FieldSpec = &super::REGISTERS[66].fields[24];
    /// `ISEM25`, bit 25.
    pub const ISEM25: &FieldSpec = &super::REGISTERS[66].fields[25];
    /// `ISEM26`, bit 26.
    pub const ISEM26: &FieldSpec = &super::REGISTERS[66].fields[26];
    /// `ISEM27`, bit 27.
    pub const ISEM27: &FieldSpec = &super::REGISTERS[66].fields[27];
    /// `ISEM28`, bit 28.
    pub const ISEM28: &FieldSpec = &super::REGISTERS[66].fields[28];
    /// `ISEM29`, bit 29.
    pub const ISEM29: &FieldSpec = &super::REGISTERS[66].fields[29];
    /// `ISEM30`, bit 30.
    pub const ISEM30: &FieldSpec = &super::REGISTERS[66].fields[30];
    /// `ISEM31`, bit 31.
    pub const ISEM31: &FieldSpec = &super::REGISTERS[66].fields[31];
}

/// The fields of `HSEM_MISR`.
pub mod hsem_misr {
    use super::FieldSpec;
    /// `ISEM0`, bit 0.
    pub const ISEM0: &FieldSpec = &super::REGISTERS[67].fields[0];
    /// `ISEM1`, bit 1.
    pub const ISEM1: &FieldSpec = &super::REGISTERS[67].fields[1];
    /// `ISEM2`, bit 2.
    pub const ISEM2: &FieldSpec = &super::REGISTERS[67].fields[2];
    /// `ISEM3`, bit 3.
    pub const ISEM3: &FieldSpec = &super::REGISTERS[67].fields[3];
    /// `ISEM4`, bit 4.
    pub const ISEM4: &FieldSpec = &super::REGISTERS[67].fields[4];
    /// `ISEM5`, bit 5.
    pub const ISEM5: &FieldSpec = &super::REGISTERS[67].fields[5];
    /// `ISEM6`, bit 6.
    pub const ISEM6: &FieldSpec = &super::REGISTERS[67].fields[6];
    /// `ISEM7`, bit 7.
    pub const ISEM7: &FieldSpec = &super::REGISTERS[67].fields[7];
    /// `ISEM8`, bit 8.
    pub const ISEM8: &FieldSpec = &super::REGISTERS[67].fields[8];
    /// `ISEM9`, bit 9.
    pub const ISEM9: &FieldSpec = &super::REGISTERS[67].fields[9];
    /// `ISEM10`, bit 10.
    pub const ISEM10: &FieldSpec = &super::REGISTERS[67].fields[10];
    /// `ISEM11`, bit 11.
    pub const ISEM11: &FieldSpec = &super::REGISTERS[67].fields[11];
    /// `ISEM12`, bit 12.
    pub const ISEM12: &FieldSpec = &super::REGISTERS[67].fields[12];
    /// `ISEM13`, bit 13.
    pub const ISEM13: &FieldSpec = &super::REGISTERS[67].fields[13];
    /// `ISEM14`, bit 14.
    pub const ISEM14: &FieldSpec = &super::REGISTERS[67].fields[14];
    /// `ISEM15`, bit 15.
    pub const ISEM15: &FieldSpec = &super::REGISTERS[67].fields[15];
    /// `ISEM16`, bit 16.
    pub const ISEM16: &FieldSpec = &super::REGISTERS[67].fields[16];
    /// `ISEM17`, bit 17.
    pub const ISEM17: &FieldSpec = &super::REGISTERS[67].fields[17];
    /// `ISEM18`, bit 18.
    pub const ISEM18: &FieldSpec = &super::REGISTERS[67].fields[18];
    /// `ISEM19`, bit 19.
    pub const ISEM19: &FieldSpec = &super::REGISTERS[67].fields[19];
    /// `ISEM20`, bit 20.
    pub const ISEM20: &FieldSpec = &super::REGISTERS[67].fields[20];
    /// `ISEM21`, bit 21.
    pub const ISEM21: &FieldSpec = &super::REGISTERS[67].fields[21];
    /// `ISEM22`, bit 22.
    pub const ISEM22: &FieldSpec = &super::REGISTERS[67].fields[22];
    /// `ISEM23`, bit 23.
    pub const ISEM23: &FieldSpec = &super::REGISTERS[67].fields[23];
    /// `ISEM24`, bit 24.
    pub const ISEM24: &FieldSpec = &super::REGISTERS[67].fields[24];
    /// `ISEM25`, bit 25.
    pub const ISEM25: &FieldSpec = &super::REGISTERS[67].fields[25];
    /// `ISEM26`, bit 26.
    pub const ISEM26: &FieldSpec = &super::REGISTERS[67].fields[26];
    /// `ISEM27`, bit 27.
    pub const ISEM27: &FieldSpec = &super::REGISTERS[67].fields[27];
    /// `ISEM28`, bit 28.
    pub const ISEM28: &FieldSpec = &super::REGISTERS[67].fields[28];
    /// `ISEM29`, bit 29.
    pub const ISEM29: &FieldSpec = &super::REGISTERS[67].fields[29];
    /// `ISEM30`, bit 30.
    pub const ISEM30: &FieldSpec = &super::REGISTERS[67].fields[30];
    /// `ISEM31`, bit 31.
    pub const ISEM31: &FieldSpec = &super::REGISTERS[67].fields[31];
}

/// The fields of `HSEM_CR`.
pub mod hsem_cr {
    use super::FieldSpec;
    /// `MASTERID`, bits 8..=15.
    pub const MASTERID: &FieldSpec = &super::REGISTERS[68].fields[0];
    /// `KEY`, bits 16..=31.
    pub const KEY: &FieldSpec = &super::REGISTERS[68].fields[1];
}

/// The fields of `HSEM_KEYR`.
pub mod hsem_keyr {
    use super::FieldSpec;
    /// `KEY`, bits 16..=31.
    pub const KEY: &FieldSpec = &super::REGISTERS[69].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 70] = [
    RegisterSpec { name: "HSEM_R0", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R1", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R2", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R3", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R4", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R5", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R6", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R7", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R8", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R9", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R10", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R11", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R12", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R13", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R14", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R15", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R16", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R17", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R18", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R19", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R20", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R21", offset: 0x54, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R22", offset: 0x58, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R23", offset: 0x5C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R24", offset: 0x60, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R25", offset: 0x64, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R26", offset: 0x68, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R27", offset: 0x6C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R28", offset: 0x70, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R29", offset: 0x74, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R30", offset: 0x78, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_R31", offset: 0x7C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR0", offset: 0x80, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR1", offset: 0x84, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR2", offset: 0x88, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR3", offset: 0x8C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR4", offset: 0x90, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR5", offset: 0x94, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR6", offset: 0x98, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR7", offset: 0x9C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR8", offset: 0xA0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR9", offset: 0xA4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR10", offset: 0xA8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR11", offset: 0xAC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR12", offset: 0xB0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR13", offset: 0xB4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR14", offset: 0xB8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR15", offset: 0xBC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR16", offset: 0xC0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR17", offset: 0xC4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR18", offset: 0xC8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR19", offset: 0xCC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR20", offset: 0xD0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR21", offset: 0xD4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR22", offset: 0xD8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR23", offset: 0xDC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR24", offset: 0xE0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR25", offset: 0xE4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR26", offset: 0xE8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR27", offset: 0xEC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR28", offset: 0xF0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR29", offset: 0xF4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR30", offset: 0xF8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_RLR31", offset: 0xFC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PROCID", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_IER", offset: 0x100, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ISEM0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM16", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM17", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM18", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM19", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM20", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM21", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM22", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM23", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM24", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM25", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM26", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM27", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM28", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM29", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM30", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM31", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_ICR", offset: 0x104, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ISEM0", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM1", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM2", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM3", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM4", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM5", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM6", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM7", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM8", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM9", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM10", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM11", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM12", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM13", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM14", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM15", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM16", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM17", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM18", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM19", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM20", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM21", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM22", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM23", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM24", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM25", bit: 25, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM26", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM27", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM28", bit: 28, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM29", bit: 29, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM30", bit: 30, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM31", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_ISR", offset: 0x108, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ISEM0", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM1", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM2", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM3", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM4", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM5", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM6", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM7", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM8", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM9", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM10", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM11", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM12", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM13", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM14", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM15", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM16", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM17", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM18", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM19", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM20", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM21", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM22", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM23", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM24", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM25", bit: 25, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM26", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM27", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM28", bit: 28, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM29", bit: 29, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM30", bit: 30, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM31", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_MISR", offset: 0x10C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ISEM0", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM1", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM2", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM3", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM4", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM5", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM6", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM7", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM8", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM9", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM10", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM11", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM12", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM13", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM14", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM15", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM16", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM17", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM18", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM19", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM20", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM21", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM22", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM23", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM24", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM25", bit: 25, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM26", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM27", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM28", bit: 28, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM29", bit: 29, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM30", bit: 30, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ISEM31", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_CR", offset: 0x140, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MASTERID", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "KEY", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HSEM_KEYR", offset: 0x144, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "KEY", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];