rigless 0.3.0

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `DMA1` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `LISR` at offset `0x0`, resets to `0x0000_0000`, read-only.
    Lisr = 0,
    /// `HISR` at offset `0x4`, resets to `0x0000_0000`, read-only.
    Hisr = 1,
    /// `LIFCR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Lifcr = 2,
    /// `HIFCR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Hifcr = 3,
    /// `S0CR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    S0cr = 4,
    /// `S0NDTR` at offset `0x14`, resets to `0x0000_0000`, read-write.
    S0ndtr = 5,
    /// `S0PAR` at offset `0x18`, resets to `0x0000_0000`, read-write.
    S0par = 6,
    /// `S0M0AR` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    S0m0ar = 7,
    /// `S0M1AR` at offset `0x20`, resets to `0x0000_0000`, read-write.
    S0m1ar = 8,
    /// `S0FCR` at offset `0x24`, resets to `0x0000_0021`, read-write.
    S0fcr = 9,
    /// `S1CR` at offset `0x28`, resets to `0x0000_0000`, read-write.
    S1cr = 10,
    /// `S1NDTR` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    S1ndtr = 11,
    /// `S1PAR` at offset `0x30`, resets to `0x0000_0000`, read-write.
    S1par = 12,
    /// `S1M0AR` at offset `0x34`, resets to `0x0000_0000`, read-write.
    S1m0ar = 13,
    /// `S1M1AR` at offset `0x38`, resets to `0x0000_0000`, read-write.
    S1m1ar = 14,
    /// `S1FCR` at offset `0x3C`, resets to `0x0000_0021`, read-write.
    S1fcr = 15,
    /// `S2CR` at offset `0x40`, resets to `0x0000_0000`, read-write.
    S2cr = 16,
    /// `S2NDTR` at offset `0x44`, resets to `0x0000_0000`, read-write.
    S2ndtr = 17,
    /// `S2PAR` at offset `0x48`, resets to `0x0000_0000`, read-write.
    S2par = 18,
    /// `S2M0AR` at offset `0x4C`, resets to `0x0000_0000`, read-write.
    S2m0ar = 19,
    /// `S2M1AR` at offset `0x50`, resets to `0x0000_0000`, read-write.
    S2m1ar = 20,
    /// `S2FCR` at offset `0x54`, resets to `0x0000_0021`, read-write.
    S2fcr = 21,
    /// `S3CR` at offset `0x58`, resets to `0x0000_0000`, read-write.
    S3cr = 22,
    /// `S3NDTR` at offset `0x5C`, resets to `0x0000_0000`, read-write.
    S3ndtr = 23,
    /// `S3PAR` at offset `0x60`, resets to `0x0000_0000`, read-write.
    S3par = 24,
    /// `S3M0AR` at offset `0x64`, resets to `0x0000_0000`, read-write.
    S3m0ar = 25,
    /// `S3M1AR` at offset `0x68`, resets to `0x0000_0000`, read-write.
    S3m1ar = 26,
    /// `S3FCR` at offset `0x6C`, resets to `0x0000_0021`, read-write.
    S3fcr = 27,
    /// `S4CR` at offset `0x70`, resets to `0x0000_0000`, read-write.
    S4cr = 28,
    /// `S4NDTR` at offset `0x74`, resets to `0x0000_0000`, read-write.
    S4ndtr = 29,
    /// `S4PAR` at offset `0x78`, resets to `0x0000_0000`, read-write.
    S4par = 30,
    /// `S4M0AR` at offset `0x7C`, resets to `0x0000_0000`, read-write.
    S4m0ar = 31,
    /// `S4M1AR` at offset `0x80`, resets to `0x0000_0000`, read-write.
    S4m1ar = 32,
    /// `S4FCR` at offset `0x84`, resets to `0x0000_0021`, read-write.
    S4fcr = 33,
    /// `S5CR` at offset `0x88`, resets to `0x0000_0000`, read-write.
    S5cr = 34,
    /// `S5NDTR` at offset `0x8C`, resets to `0x0000_0000`, read-write.
    S5ndtr = 35,
    /// `S5PAR` at offset `0x90`, resets to `0x0000_0000`, read-write.
    S5par = 36,
    /// `S5M0AR` at offset `0x94`, resets to `0x0000_0000`, read-write.
    S5m0ar = 37,
    /// `S5M1AR` at offset `0x98`, resets to `0x0000_0000`, read-write.
    S5m1ar = 38,
    /// `S5FCR` at offset `0x9C`, resets to `0x0000_0021`, read-write.
    S5fcr = 39,
    /// `S6CR` at offset `0xA0`, resets to `0x0000_0000`, read-write.
    S6cr = 40,
    /// `S6NDTR` at offset `0xA4`, resets to `0x0000_0000`, read-write.
    S6ndtr = 41,
    /// `S6PAR` at offset `0xA8`, resets to `0x0000_0000`, read-write.
    S6par = 42,
    /// `S6M0AR` at offset `0xAC`, resets to `0x0000_0000`, read-write.
    S6m0ar = 43,
    /// `S6M1AR` at offset `0xB0`, resets to `0x0000_0000`, read-write.
    S6m1ar = 44,
    /// `S6FCR` at offset `0xB4`, resets to `0x0000_0021`, read-write.
    S6fcr = 45,
    /// `S7CR` at offset `0xB8`, resets to `0x0000_0000`, read-write.
    S7cr = 46,
    /// `S7NDTR` at offset `0xBC`, resets to `0x0000_0000`, read-write.
    S7ndtr = 47,
    /// `S7PAR` at offset `0xC0`, resets to `0x0000_0000`, read-write.
    S7par = 48,
    /// `S7M0AR` at offset `0xC4`, resets to `0x0000_0000`, read-write.
    S7m0ar = 49,
    /// `S7M1AR` at offset `0xC8`, resets to `0x0000_0000`, read-write.
    S7m1ar = 50,
    /// `S7FCR` at offset `0xCC`, resets to `0x0000_0021`, read-write.
    S7fcr = 51,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 52] = [Self::Lisr, Self::Hisr, Self::Lifcr, Self::Hifcr, Self::S0cr, Self::S0ndtr, Self::S0par, Self::S0m0ar, Self::S0m1ar, Self::S0fcr, Self::S1cr, Self::S1ndtr, Self::S1par, Self::S1m0ar, Self::S1m1ar, Self::S1fcr, Self::S2cr, Self::S2ndtr, Self::S2par, Self::S2m0ar, Self::S2m1ar, Self::S2fcr, Self::S3cr, Self::S3ndtr, Self::S3par, Self::S3m0ar, Self::S3m1ar, Self::S3fcr, Self::S4cr, Self::S4ndtr, Self::S4par, Self::S4m0ar, Self::S4m1ar, Self::S4fcr, Self::S5cr, Self::S5ndtr, Self::S5par, Self::S5m0ar, Self::S5m1ar, Self::S5fcr, Self::S6cr, Self::S6ndtr, Self::S6par, Self::S6m0ar, Self::S6m1ar, Self::S6fcr, Self::S7cr, Self::S7ndtr, Self::S7par, Self::S7m0ar, Self::S7m1ar, Self::S7fcr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `LISR`.
pub mod lisr {
    use super::FieldSpec;
    /// `FEIF0`, bit 0.
    pub const FEIF0: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `DMEIF0`, bit 2.
    pub const DMEIF0: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `TEIF0`, bit 3.
    pub const TEIF0: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `HTIF0`, bit 4.
    pub const HTIF0: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `TCIF0`, bit 5.
    pub const TCIF0: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `FEIF1`, bit 6.
    pub const FEIF1: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `DMEIF1`, bit 8.
    pub const DMEIF1: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `TEIF1`, bit 9.
    pub const TEIF1: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `HTIF1`, bit 10.
    pub const HTIF1: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `TCIF1`, bit 11.
    pub const TCIF1: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `FEIF2`, bit 16.
    pub const FEIF2: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `DMEIF2`, bit 18.
    pub const DMEIF2: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `TEIF2`, bit 19.
    pub const TEIF2: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `HTIF2`, bit 20.
    pub const HTIF2: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `TCIF2`, bit 21.
    pub const TCIF2: &FieldSpec = &super::REGISTERS[0].fields[14];
    /// `FEIF3`, bit 22.
    pub const FEIF3: &FieldSpec = &super::REGISTERS[0].fields[15];
    /// `DMEIF3`, bit 24.
    pub const DMEIF3: &FieldSpec = &super::REGISTERS[0].fields[16];
    /// `TEIF3`, bit 25.
    pub const TEIF3: &FieldSpec = &super::REGISTERS[0].fields[17];
    /// `HTIF3`, bit 26.
    pub const HTIF3: &FieldSpec = &super::REGISTERS[0].fields[18];
    /// `TCIF3`, bit 27.
    pub const TCIF3: &FieldSpec = &super::REGISTERS[0].fields[19];
}

/// The fields of `HISR`.
pub mod hisr {
    use super::FieldSpec;
    /// `FEIF4`, bit 0.
    pub const FEIF4: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `DMEIF4`, bit 2.
    pub const DMEIF4: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `TEIF4`, bit 3.
    pub const TEIF4: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `HTIF4`, bit 4.
    pub const HTIF4: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `TCIF4`, bit 5.
    pub const TCIF4: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `FEIF5`, bit 6.
    pub const FEIF5: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `DMEIF5`, bit 8.
    pub const DMEIF5: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `TEIF5`, bit 9.
    pub const TEIF5: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `HTIF5`, bit 10.
    pub const HTIF5: &FieldSpec = &super::REGISTERS[1].fields[8];
    /// `TCIF5`, bit 11.
    pub const TCIF5: &FieldSpec = &super::REGISTERS[1].fields[9];
    /// `FEIF6`, bit 16.
    pub const FEIF6: &FieldSpec = &super::REGISTERS[1].fields[10];
    /// `DMEIF6`, bit 18.
    pub const DMEIF6: &FieldSpec = &super::REGISTERS[1].fields[11];
    /// `TEIF6`, bit 19.
    pub const TEIF6: &FieldSpec = &super::REGISTERS[1].fields[12];
    /// `HTIF6`, bit 20.
    pub const HTIF6: &FieldSpec = &super::REGISTERS[1].fields[13];
    /// `TCIF6`, bit 21.
    pub const TCIF6: &FieldSpec = &super::REGISTERS[1].fields[14];
    /// `FEIF7`, bit 22.
    pub const FEIF7: &FieldSpec = &super::REGISTERS[1].fields[15];
    /// `DMEIF7`, bit 24.
    pub const DMEIF7: &FieldSpec = &super::REGISTERS[1].fields[16];
    /// `TEIF7`, bit 25.
    pub const TEIF7: &FieldSpec = &super::REGISTERS[1].fields[17];
    /// `HTIF7`, bit 26.
    pub const HTIF7: &FieldSpec = &super::REGISTERS[1].fields[18];
    /// `TCIF7`, bit 27.
    pub const TCIF7: &FieldSpec = &super::REGISTERS[1].fields[19];
}

/// The fields of `LIFCR`.
pub mod lifcr {
    use super::FieldSpec;
    /// `CFEIF0`, bit 0.
    pub const CFEIF0: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `CDMEIF0`, bit 2.
    pub const CDMEIF0: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `CTEIF0`, bit 3.
    pub const CTEIF0: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `CHTIF0`, bit 4.
    pub const CHTIF0: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `CTCIF0`, bit 5.
    pub const CTCIF0: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `CFEIF1`, bit 6.
    pub const CFEIF1: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `CDMEIF1`, bit 8.
    pub const CDMEIF1: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `CTEIF1`, bit 9.
    pub const CTEIF1: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `CHTIF1`, bit 10.
    pub const CHTIF1: &FieldSpec = &super::REGISTERS[2].fields[8];
    /// `CTCIF1`, bit 11.
    pub const CTCIF1: &FieldSpec = &super::REGISTERS[2].fields[9];
    /// `CFEIF2`, bit 16.
    pub const CFEIF2: &FieldSpec = &super::REGISTERS[2].fields[10];
    /// `CDMEIF2`, bit 18.
    pub const CDMEIF2: &FieldSpec = &super::REGISTERS[2].fields[11];
    /// `CTEIF2`, bit 19.
    pub const CTEIF2: &FieldSpec = &super::REGISTERS[2].fields[12];
    /// `CHTIF2`, bit 20.
    pub const CHTIF2: &FieldSpec = &super::REGISTERS[2].fields[13];
    /// `CTCIF2`, bit 21.
    pub const CTCIF2: &FieldSpec = &super::REGISTERS[2].fields[14];
    /// `CFEIF3`, bit 22.
    pub const CFEIF3: &FieldSpec = &super::REGISTERS[2].fields[15];
    /// `CDMEIF3`, bit 24.
    pub const CDMEIF3: &FieldSpec = &super::REGISTERS[2].fields[16];
    /// `CTEIF3`, bit 25.
    pub const CTEIF3: &FieldSpec = &super::REGISTERS[2].fields[17];
    /// `CHTIF3`, bit 26.
    pub const CHTIF3: &FieldSpec = &super::REGISTERS[2].fields[18];
    /// `CTCIF3`, bit 27.
    pub const CTCIF3: &FieldSpec = &super::REGISTERS[2].fields[19];
}

/// The fields of `HIFCR`.
pub mod hifcr {
    use super::FieldSpec;
    /// `CFEIF4`, bit 0.
    pub const CFEIF4: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `CDMEIF4`, bit 2.
    pub const CDMEIF4: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `CTEIF4`, bit 3.
    pub const CTEIF4: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `CHTIF4`, bit 4.
    pub const CHTIF4: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `CTCIF4`, bit 5.
    pub const CTCIF4: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `CFEIF5`, bit 6.
    pub const CFEIF5: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `CDMEIF5`, bit 8.
    pub const CDMEIF5: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `CTEIF5`, bit 9.
    pub const CTEIF5: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `CHTIF5`, bit 10.
    pub const CHTIF5: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `CTCIF5`, bit 11.
    pub const CTCIF5: &FieldSpec = &super::REGISTERS[3].fields[9];
    /// `CFEIF6`, bit 16.
    pub const CFEIF6: &FieldSpec = &super::REGISTERS[3].fields[10];
    /// `CDMEIF6`, bit 18.
    pub const CDMEIF6: &FieldSpec = &super::REGISTERS[3].fields[11];
    /// `CTEIF6`, bit 19.
    pub const CTEIF6: &FieldSpec = &super::REGISTERS[3].fields[12];
    /// `CHTIF6`, bit 20.
    pub const CHTIF6: &FieldSpec = &super::REGISTERS[3].fields[13];
    /// `CTCIF6`, bit 21.
    pub const CTCIF6: &FieldSpec = &super::REGISTERS[3].fields[14];
    /// `CFEIF7`, bit 22.
    pub const CFEIF7: &FieldSpec = &super::REGISTERS[3].fields[15];
    /// `CDMEIF7`, bit 24.
    pub const CDMEIF7: &FieldSpec = &super::REGISTERS[3].fields[16];
    /// `CTEIF7`, bit 25.
    pub const CTEIF7: &FieldSpec = &super::REGISTERS[3].fields[17];
    /// `CHTIF7`, bit 26.
    pub const CHTIF7: &FieldSpec = &super::REGISTERS[3].fields[18];
    /// `CTCIF7`, bit 27.
    pub const CTCIF7: &FieldSpec = &super::REGISTERS[3].fields[19];
}

/// The fields of `S0CR`.
pub mod s0cr {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `DMEIE`, bit 1.
    pub const DMEIE: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `TEIE`, bit 2.
    pub const TEIE: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `HTIE`, bit 3.
    pub const HTIE: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `TCIE`, bit 4.
    pub const TCIE: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `PFCTRL`, bit 5.
    pub const PFCTRL: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `DIR`, bits 6..=7.
    pub const DIR: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `CIRC`, bit 8.
    pub const CIRC: &FieldSpec = &super::REGISTERS[4].fields[7];
    /// `PINC`, bit 9.
    pub const PINC: &FieldSpec = &super::REGISTERS[4].fields[8];
    /// `MINC`, bit 10.
    pub const MINC: &FieldSpec = &super::REGISTERS[4].fields[9];
    /// `PSIZE`, bits 11..=12.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[4].fields[10];
    /// `MSIZE`, bits 13..=14.
    pub const MSIZE: &FieldSpec = &super::REGISTERS[4].fields[11];
    /// `PINCOS`, bit 15.
    pub const PINCOS: &FieldSpec = &super::REGISTERS[4].fields[12];
    /// `PL`, bits 16..=17.
    pub const PL: &FieldSpec = &super::REGISTERS[4].fields[13];
    /// `DBM`, bit 18.
    pub const DBM: &FieldSpec = &super::REGISTERS[4].fields[14];
    /// `CT`, bit 19.
    pub const CT: &FieldSpec = &super::REGISTERS[4].fields[15];
    /// `PBURST`, bits 21..=22.
    pub const PBURST: &FieldSpec = &super::REGISTERS[4].fields[16];
    /// `MBURST`, bits 23..=24.
    pub const MBURST: &FieldSpec = &super::REGISTERS[4].fields[17];
}

/// The fields of `S0NDTR`.
pub mod s0ndtr {
    use super::FieldSpec;
    /// `NDT`, bits 0..=15.
    pub const NDT: &FieldSpec = &super::REGISTERS[5].fields[0];
}

/// The fields of `S0PAR`.
pub mod s0par {
    use super::FieldSpec;
    /// `PA`, bits 0..=31.
    pub const PA: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `S0M0AR`.
pub mod s0m0ar {
    use super::FieldSpec;
    /// `M0A`, bits 0..=31.
    pub const M0A: &FieldSpec = &super::REGISTERS[7].fields[0];
}

/// The fields of `S0M1AR`.
pub mod s0m1ar {
    use super::FieldSpec;
    /// `M1A`, bits 0..=31.
    pub const M1A: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The fields of `S0FCR`.
pub mod s0fcr {
    use super::FieldSpec;
    /// `FTH`, bits 0..=1.
    pub const FTH: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `DMDIS`, bit 2.
    pub const DMDIS: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `FS`, bits 3..=5, read-only.
    pub const FS: &FieldSpec = &super::REGISTERS[9].fields[2];
    /// `FEIE`, bit 7.
    pub const FEIE: &FieldSpec = &super::REGISTERS[9].fields[3];
}

/// The fields of `S1CR`.
pub mod s1cr {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `DMEIE`, bit 1.
    pub const DMEIE: &FieldSpec = &super::REGISTERS[10].fields[1];
    /// `TEIE`, bit 2.
    pub const TEIE: &FieldSpec = &super::REGISTERS[10].fields[2];
    /// `HTIE`, bit 3.
    pub const HTIE: &FieldSpec = &super::REGISTERS[10].fields[3];
    /// `TCIE`, bit 4.
    pub const TCIE: &FieldSpec = &super::REGISTERS[10].fields[4];
    /// `PFCTRL`, bit 5.
    pub const PFCTRL: &FieldSpec = &super::REGISTERS[10].fields[5];
    /// `DIR`, bits 6..=7.
    pub const DIR: &FieldSpec = &super::REGISTERS[10].fields[6];
    /// `CIRC`, bit 8.
    pub const CIRC: &FieldSpec = &super::REGISTERS[10].fields[7];
    /// `PINC`, bit 9.
    pub const PINC: &FieldSpec = &super::REGISTERS[10].fields[8];
    /// `MINC`, bit 10.
    pub const MINC: &FieldSpec = &super::REGISTERS[10].fields[9];
    /// `PSIZE`, bits 11..=12.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[10].fields[10];
    /// `MSIZE`, bits 13..=14.
    pub const MSIZE: &FieldSpec = &super::REGISTERS[10].fields[11];
    /// `PINCOS`, bit 15.
    pub const PINCOS: &FieldSpec = &super::REGISTERS[10].fields[12];
    /// `PL`, bits 16..=17.
    pub const PL: &FieldSpec = &super::REGISTERS[10].fields[13];
    /// `DBM`, bit 18.
    pub const DBM: &FieldSpec = &super::REGISTERS[10].fields[14];
    /// `CT`, bit 19.
    pub const CT: &FieldSpec = &super::REGISTERS[10].fields[15];
    /// `ACK`, bit 20.
    pub const ACK: &FieldSpec = &super::REGISTERS[10].fields[16];
    /// `PBURST`, bits 21..=22.
    pub const PBURST: &FieldSpec = &super::REGISTERS[10].fields[17];
    /// `MBURST`, bits 23..=24.
    pub const MBURST: &FieldSpec = &super::REGISTERS[10].fields[18];
}

/// The fields of `S1NDTR`.
pub mod s1ndtr {
    use super::FieldSpec;
    /// `NDT`, bits 0..=15.
    pub const NDT: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The fields of `S1PAR`.
pub mod s1par {
    use super::FieldSpec;
    /// `PA`, bits 0..=31.
    pub const PA: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The fields of `S1M0AR`.
pub mod s1m0ar {
    use super::FieldSpec;
    /// `M0A`, bits 0..=31.
    pub const M0A: &FieldSpec = &super::REGISTERS[13].fields[0];
}

/// The fields of `S1M1AR`.
pub mod s1m1ar {
    use super::FieldSpec;
    /// `M1A`, bits 0..=31.
    pub const M1A: &FieldSpec = &super::REGISTERS[14].fields[0];
}

/// The fields of `S1FCR`.
pub mod s1fcr {
    use super::FieldSpec;
    /// `FTH`, bits 0..=1.
    pub const FTH: &FieldSpec = &super::REGISTERS[15].fields[0];
    /// `DMDIS`, bit 2.
    pub const DMDIS: &FieldSpec = &super::REGISTERS[15].fields[1];
    /// `FS`, bits 3..=5, read-only.
    pub const FS: &FieldSpec = &super::REGISTERS[15].fields[2];
    /// `FEIE`, bit 7.
    pub const FEIE: &FieldSpec = &super::REGISTERS[15].fields[3];
}

/// The fields of `S2CR`.
pub mod s2cr {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[16].fields[0];
    /// `DMEIE`, bit 1.
    pub const DMEIE: &FieldSpec = &super::REGISTERS[16].fields[1];
    /// `TEIE`, bit 2.
    pub const TEIE: &FieldSpec = &super::REGISTERS[16].fields[2];
    /// `HTIE`, bit 3.
    pub const HTIE: &FieldSpec = &super::REGISTERS[16].fields[3];
    /// `TCIE`, bit 4.
    pub const TCIE: &FieldSpec = &super::REGISTERS[16].fields[4];
    /// `PFCTRL`, bit 5.
    pub const PFCTRL: &FieldSpec = &super::REGISTERS[16].fields[5];
    /// `DIR`, bits 6..=7.
    pub const DIR: &FieldSpec = &super::REGISTERS[16].fields[6];
    /// `CIRC`, bit 8.
    pub const CIRC: &FieldSpec = &super::REGISTERS[16].fields[7];
    /// `PINC`, bit 9.
    pub const PINC: &FieldSpec = &super::REGISTERS[16].fields[8];
    /// `MINC`, bit 10.
    pub const MINC: &FieldSpec = &super::REGISTERS[16].fields[9];
    /// `PSIZE`, bits 11..=12.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[16].fields[10];
    /// `MSIZE`, bits 13..=14.
    pub const MSIZE: &FieldSpec = &super::REGISTERS[16].fields[11];
    /// `PINCOS`, bit 15.
    pub const PINCOS: &FieldSpec = &super::REGISTERS[16].fields[12];
    /// `PL`, bits 16..=17.
    pub const PL: &FieldSpec = &super::REGISTERS[16].fields[13];
    /// `DBM`, bit 18.
    pub const DBM: &FieldSpec = &super::REGISTERS[16].fields[14];
    /// `CT`, bit 19.
    pub const CT: &FieldSpec = &super::REGISTERS[16].fields[15];
    /// `ACK`, bit 20.
    pub const ACK: &FieldSpec = &super::REGISTERS[16].fields[16];
    /// `PBURST`, bits 21..=22.
    pub const PBURST: &FieldSpec = &super::REGISTERS[16].fields[17];
    /// `MBURST`, bits 23..=24.
    pub const MBURST: &FieldSpec = &super::REGISTERS[16].fields[18];
}

/// The fields of `S2NDTR`.
pub mod s2ndtr {
    use super::FieldSpec;
    /// `NDT`, bits 0..=15.
    pub const NDT: &FieldSpec = &super::REGISTERS[17].fields[0];
}

/// The fields of `S2PAR`.
pub mod s2par {
    use super::FieldSpec;
    /// `PA`, bits 0..=31.
    pub const PA: &FieldSpec = &super::REGISTERS[18].fields[0];
}

/// The fields of `S2M0AR`.
pub mod s2m0ar {
    use super::FieldSpec;
    /// `M0A`, bits 0..=31.
    pub const M0A: &FieldSpec = &super::REGISTERS[19].fields[0];
}

/// The fields of `S2M1AR`.
pub mod s2m1ar {
    use super::FieldSpec;
    /// `M1A`, bits 0..=31.
    pub const M1A: &FieldSpec = &super::REGISTERS[20].fields[0];
}

/// The fields of `S2FCR`.
pub mod s2fcr {
    use super::FieldSpec;
    /// `FTH`, bits 0..=1.
    pub const FTH: &FieldSpec = &super::REGISTERS[21].fields[0];
    /// `DMDIS`, bit 2.
    pub const DMDIS: &FieldSpec = &super::REGISTERS[21].fields[1];
    /// `FS`, bits 3..=5, read-only.
    pub const FS: &FieldSpec = &super::REGISTERS[21].fields[2];
    /// `FEIE`, bit 7.
    pub const FEIE: &FieldSpec = &super::REGISTERS[21].fields[3];
}

/// The fields of `S3CR`.
pub mod s3cr {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[22].fields[0];
    /// `DMEIE`, bit 1.
    pub const DMEIE: &FieldSpec = &super::REGISTERS[22].fields[1];
    /// `TEIE`, bit 2.
    pub const TEIE: &FieldSpec = &super::REGISTERS[22].fields[2];
    /// `HTIE`, bit 3.
    pub const HTIE: &FieldSpec = &super::REGISTERS[22].fields[3];
    /// `TCIE`, bit 4.
    pub const TCIE: &FieldSpec = &super::REGISTERS[22].fields[4];
    /// `PFCTRL`, bit 5.
    pub const PFCTRL: &FieldSpec = &super::REGISTERS[22].fields[5];
    /// `DIR`, bits 6..=7.
    pub const DIR: &FieldSpec = &super::REGISTERS[22].fields[6];
    /// `CIRC`, bit 8.
    pub const CIRC: &FieldSpec = &super::REGISTERS[22].fields[7];
    /// `PINC`, bit 9.
    pub const PINC: &FieldSpec = &super::REGISTERS[22].fields[8];
    /// `MINC`, bit 10.
    pub const MINC: &FieldSpec = &super::REGISTERS[22].fields[9];
    /// `PSIZE`, bits 11..=12.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[22].fields[10];
    /// `MSIZE`, bits 13..=14.
    pub const MSIZE: &FieldSpec = &super::REGISTERS[22].fields[11];
    /// `PINCOS`, bit 15.
    pub const PINCOS: &FieldSpec = &super::REGISTERS[22].fields[12];
    /// `PL`, bits 16..=17.
    pub const PL: &FieldSpec = &super::REGISTERS[22].fields[13];
    /// `DBM`, bit 18.
    pub const DBM: &FieldSpec = &super::REGISTERS[22].fields[14];
    /// `CT`, bit 19.
    pub const CT: &FieldSpec = &super::REGISTERS[22].fields[15];
    /// `ACK`, bit 20.
    pub const ACK: &FieldSpec = &super::REGISTERS[22].fields[16];
    /// `PBURST`, bits 21..=22.
    pub const PBURST: &FieldSpec = &super::REGISTERS[22].fields[17];
    /// `MBURST`, bits 23..=24.
    pub const MBURST: &FieldSpec = &super::REGISTERS[22].fields[18];
}

/// The fields of `S3NDTR`.
pub mod s3ndtr {
    use super::FieldSpec;
    /// `NDT`, bits 0..=15.
    pub const NDT: &FieldSpec = &super::REGISTERS[23].fields[0];
}

/// The fields of `S3PAR`.
pub mod s3par {
    use super::FieldSpec;
    /// `PA`, bits 0..=31.
    pub const PA: &FieldSpec = &super::REGISTERS[24].fields[0];
}

/// The fields of `S3M0AR`.
pub mod s3m0ar {
    use super::FieldSpec;
    /// `M0A`, bits 0..=31.
    pub const M0A: &FieldSpec = &super::REGISTERS[25].fields[0];
}

/// The fields of `S3M1AR`.
pub mod s3m1ar {
    use super::FieldSpec;
    /// `M1A`, bits 0..=31.
    pub const M1A: &FieldSpec = &super::REGISTERS[26].fields[0];
}

/// The fields of `S3FCR`.
pub mod s3fcr {
    use super::FieldSpec;
    /// `FTH`, bits 0..=1.
    pub const FTH: &FieldSpec = &super::REGISTERS[27].fields[0];
    /// `DMDIS`, bit 2.
    pub const DMDIS: &FieldSpec = &super::REGISTERS[27].fields[1];
    /// `FS`, bits 3..=5, read-only.
    pub const FS: &FieldSpec = &super::REGISTERS[27].fields[2];
    /// `FEIE`, bit 7.
    pub const FEIE: &FieldSpec = &super::REGISTERS[27].fields[3];
}

/// The fields of `S4CR`.
pub mod s4cr {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[28].fields[0];
    /// `DMEIE`, bit 1.
    pub const DMEIE: &FieldSpec = &super::REGISTERS[28].fields[1];
    /// `TEIE`, bit 2.
    pub const TEIE: &FieldSpec = &super::REGISTERS[28].fields[2];
    /// `HTIE`, bit 3.
    pub const HTIE: &FieldSpec = &super::REGISTERS[28].fields[3];
    /// `TCIE`, bit 4.
    pub const TCIE: &FieldSpec = &super::REGISTERS[28].fields[4];
    /// `PFCTRL`, bit 5.
    pub const PFCTRL: &FieldSpec = &super::REGISTERS[28].fields[5];
    /// `DIR`, bits 6..=7.
    pub const DIR: &FieldSpec = &super::REGISTERS[28].fields[6];
    /// `CIRC`, bit 8.
    pub const CIRC: &FieldSpec = &super::REGISTERS[28].fields[7];
    /// `PINC`, bit 9.
    pub const PINC: &FieldSpec = &super::REGISTERS[28].fields[8];
    /// `MINC`, bit 10.
    pub const MINC: &FieldSpec = &super::REGISTERS[28].fields[9];
    /// `PSIZE`, bits 11..=12.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[28].fields[10];
    /// `MSIZE`, bits 13..=14.
    pub const MSIZE: &FieldSpec = &super::REGISTERS[28].fields[11];
    /// `PINCOS`, bit 15.
    pub const PINCOS: &FieldSpec = &super::REGISTERS[28].fields[12];
    /// `PL`, bits 16..=17.
    pub const PL: &FieldSpec = &super::REGISTERS[28].fields[13];
    /// `DBM`, bit 18.
    pub const DBM: &FieldSpec = &super::REGISTERS[28].fields[14];
    /// `CT`, bit 19.
    pub const CT: &FieldSpec = &super::REGISTERS[28].fields[15];
    /// `ACK`, bit 20.
    pub const ACK: &FieldSpec = &super::REGISTERS[28].fields[16];
    /// `PBURST`, bits 21..=22.
    pub const PBURST: &FieldSpec = &super::REGISTERS[28].fields[17];
    /// `MBURST`, bits 23..=24.
    pub const MBURST: &FieldSpec = &super::REGISTERS[28].fields[18];
}

/// The fields of `S4NDTR`.
pub mod s4ndtr {
    use super::FieldSpec;
    /// `NDT`, bits 0..=15.
    pub const NDT: &FieldSpec = &super::REGISTERS[29].fields[0];
}

/// The fields of `S4PAR`.
pub mod s4par {
    use super::FieldSpec;
    /// `PA`, bits 0..=31.
    pub const PA: &FieldSpec = &super::REGISTERS[30].fields[0];
}

/// The fields of `S4M0AR`.
pub mod s4m0ar {
    use super::FieldSpec;
    /// `M0A`, bits 0..=31.
    pub const M0A: &FieldSpec = &super::REGISTERS[31].fields[0];
}

/// The fields of `S4M1AR`.
pub mod s4m1ar {
    use super::FieldSpec;
    /// `M1A`, bits 0..=31.
    pub const M1A: &FieldSpec = &super::REGISTERS[32].fields[0];
}

/// The fields of `S4FCR`.
pub mod s4fcr {
    use super::FieldSpec;
    /// `FTH`, bits 0..=1.
    pub const FTH: &FieldSpec = &super::REGISTERS[33].fields[0];
    /// `DMDIS`, bit 2.
    pub const DMDIS: &FieldSpec = &super::REGISTERS[33].fields[1];
    /// `FS`, bits 3..=5, read-only.
    pub const FS: &FieldSpec = &super::REGISTERS[33].fields[2];
    /// `FEIE`, bit 7.
    pub const FEIE: &FieldSpec = &super::REGISTERS[33].fields[3];
}

/// The fields of `S5CR`.
pub mod s5cr {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[34].fields[0];
    /// `DMEIE`, bit 1.
    pub const DMEIE: &FieldSpec = &super::REGISTERS[34].fields[1];
    /// `TEIE`, bit 2.
    pub const TEIE: &FieldSpec = &super::REGISTERS[34].fields[2];
    /// `HTIE`, bit 3.
    pub const HTIE: &FieldSpec = &super::REGISTERS[34].fields[3];
    /// `TCIE`, bit 4.
    pub const TCIE: &FieldSpec = &super::REGISTERS[34].fields[4];
    /// `PFCTRL`, bit 5.
    pub const PFCTRL: &FieldSpec = &super::REGISTERS[34].fields[5];
    /// `DIR`, bits 6..=7.
    pub const DIR: &FieldSpec = &super::REGISTERS[34].fields[6];
    /// `CIRC`, bit 8.
    pub const CIRC: &FieldSpec = &super::REGISTERS[34].fields[7];
    /// `PINC`, bit 9.
    pub const PINC: &FieldSpec = &super::REGISTERS[34].fields[8];
    /// `MINC`, bit 10.
    pub const MINC: &FieldSpec = &super::REGISTERS[34].fields[9];
    /// `PSIZE`, bits 11..=12.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[34].fields[10];
    /// `MSIZE`, bits 13..=14.
    pub const MSIZE: &FieldSpec = &super::REGISTERS[34].fields[11];
    /// `PINCOS`, bit 15.
    pub const PINCOS: &FieldSpec = &super::REGISTERS[34].fields[12];
    /// `PL`, bits 16..=17.
    pub const PL: &FieldSpec = &super::REGISTERS[34].fields[13];
    /// `DBM`, bit 18.
    pub const DBM: &FieldSpec = &super::REGISTERS[34].fields[14];
    /// `CT`, bit 19.
    pub const CT: &FieldSpec = &super::REGISTERS[34].fields[15];
    /// `ACK`, bit 20.
    pub const ACK: &FieldSpec = &super::REGISTERS[34].fields[16];
    /// `PBURST`, bits 21..=22.
    pub const PBURST: &FieldSpec = &super::REGISTERS[34].fields[17];
    /// `MBURST`, bits 23..=24.
    pub const MBURST: &FieldSpec = &super::REGISTERS[34].fields[18];
}

/// The fields of `S5NDTR`.
pub mod s5ndtr {
    use super::FieldSpec;
    /// `NDT`, bits 0..=15.
    pub const NDT: &FieldSpec = &super::REGISTERS[35].fields[0];
}

/// The fields of `S5PAR`.
pub mod s5par {
    use super::FieldSpec;
    /// `PA`, bits 0..=31.
    pub const PA: &FieldSpec = &super::REGISTERS[36].fields[0];
}

/// The fields of `S5M0AR`.
pub mod s5m0ar {
    use super::FieldSpec;
    /// `M0A`, bits 0..=31.
    pub const M0A: &FieldSpec = &super::REGISTERS[37].fields[0];
}

/// The fields of `S5M1AR`.
pub mod s5m1ar {
    use super::FieldSpec;
    /// `M1A`, bits 0..=31.
    pub const M1A: &FieldSpec = &super::REGISTERS[38].fields[0];
}

/// The fields of `S5FCR`.
pub mod s5fcr {
    use super::FieldSpec;
    /// `FTH`, bits 0..=1.
    pub const FTH: &FieldSpec = &super::REGISTERS[39].fields[0];
    /// `DMDIS`, bit 2.
    pub const DMDIS: &FieldSpec = &super::REGISTERS[39].fields[1];
    /// `FS`, bits 3..=5, read-only.
    pub const FS: &FieldSpec = &super::REGISTERS[39].fields[2];
    /// `FEIE`, bit 7.
    pub const FEIE: &FieldSpec = &super::REGISTERS[39].fields[3];
}

/// The fields of `S6CR`.
pub mod s6cr {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[40].fields[0];
    /// `DMEIE`, bit 1.
    pub const DMEIE: &FieldSpec = &super::REGISTERS[40].fields[1];
    /// `TEIE`, bit 2.
    pub const TEIE: &FieldSpec = &super::REGISTERS[40].fields[2];
    /// `HTIE`, bit 3.
    pub const HTIE: &FieldSpec = &super::REGISTERS[40].fields[3];
    /// `TCIE`, bit 4.
    pub const TCIE: &FieldSpec = &super::REGISTERS[40].fields[4];
    /// `PFCTRL`, bit 5.
    pub const PFCTRL: &FieldSpec = &super::REGISTERS[40].fields[5];
    /// `DIR`, bits 6..=7.
    pub const DIR: &FieldSpec = &super::REGISTERS[40].fields[6];
    /// `CIRC`, bit 8.
    pub const CIRC: &FieldSpec = &super::REGISTERS[40].fields[7];
    /// `PINC`, bit 9.
    pub const PINC: &FieldSpec = &super::REGISTERS[40].fields[8];
    /// `MINC`, bit 10.
    pub const MINC: &FieldSpec = &super::REGISTERS[40].fields[9];
    /// `PSIZE`, bits 11..=12.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[40].fields[10];
    /// `MSIZE`, bits 13..=14.
    pub const MSIZE: &FieldSpec = &super::REGISTERS[40].fields[11];
    /// `PINCOS`, bit 15.
    pub const PINCOS: &FieldSpec = &super::REGISTERS[40].fields[12];
    /// `PL`, bits 16..=17.
    pub const PL: &FieldSpec = &super::REGISTERS[40].fields[13];
    /// `DBM`, bit 18.
    pub const DBM: &FieldSpec = &super::REGISTERS[40].fields[14];
    /// `CT`, bit 19.
    pub const CT: &FieldSpec = &super::REGISTERS[40].fields[15];
    /// `ACK`, bit 20.
    pub const ACK: &FieldSpec = &super::REGISTERS[40].fields[16];
    /// `PBURST`, bits 21..=22.
    pub const PBURST: &FieldSpec = &super::REGISTERS[40].fields[17];
    /// `MBURST`, bits 23..=24.
    pub const MBURST: &FieldSpec = &super::REGISTERS[40].fields[18];
}

/// The fields of `S6NDTR`.
pub mod s6ndtr {
    use super::FieldSpec;
    /// `NDT`, bits 0..=15.
    pub const NDT: &FieldSpec = &super::REGISTERS[41].fields[0];
}

/// The fields of `S6PAR`.
pub mod s6par {
    use super::FieldSpec;
    /// `PA`, bits 0..=31.
    pub const PA: &FieldSpec = &super::REGISTERS[42].fields[0];
}

/// The fields of `S6M0AR`.
pub mod s6m0ar {
    use super::FieldSpec;
    /// `M0A`, bits 0..=31.
    pub const M0A: &FieldSpec = &super::REGISTERS[43].fields[0];
}

/// The fields of `S6M1AR`.
pub mod s6m1ar {
    use super::FieldSpec;
    /// `M1A`, bits 0..=31.
    pub const M1A: &FieldSpec = &super::REGISTERS[44].fields[0];
}

/// The fields of `S6FCR`.
pub mod s6fcr {
    use super::FieldSpec;
    /// `FTH`, bits 0..=1.
    pub const FTH: &FieldSpec = &super::REGISTERS[45].fields[0];
    /// `DMDIS`, bit 2.
    pub const DMDIS: &FieldSpec = &super::REGISTERS[45].fields[1];
    /// `FS`, bits 3..=5, read-only.
    pub const FS: &FieldSpec = &super::REGISTERS[45].fields[2];
    /// `FEIE`, bit 7.
    pub const FEIE: &FieldSpec = &super::REGISTERS[45].fields[3];
}

/// The fields of `S7CR`.
pub mod s7cr {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[46].fields[0];
    /// `DMEIE`, bit 1.
    pub const DMEIE: &FieldSpec = &super::REGISTERS[46].fields[1];
    /// `TEIE`, bit 2.
    pub const TEIE: &FieldSpec = &super::REGISTERS[46].fields[2];
    /// `HTIE`, bit 3.
    pub const HTIE: &FieldSpec = &super::REGISTERS[46].fields[3];
    /// `TCIE`, bit 4.
    pub const TCIE: &FieldSpec = &super::REGISTERS[46].fields[4];
    /// `PFCTRL`, bit 5.
    pub const PFCTRL: &FieldSpec = &super::REGISTERS[46].fields[5];
    /// `DIR`, bits 6..=7.
    pub const DIR: &FieldSpec = &super::REGISTERS[46].fields[6];
    /// `CIRC`, bit 8.
    pub const CIRC: &FieldSpec = &super::REGISTERS[46].fields[7];
    /// `PINC`, bit 9.
    pub const PINC: &FieldSpec = &super::REGISTERS[46].fields[8];
    /// `MINC`, bit 10.
    pub const MINC: &FieldSpec = &super::REGISTERS[46].fields[9];
    /// `PSIZE`, bits 11..=12.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[46].fields[10];
    /// `MSIZE`, bits 13..=14.
    pub const MSIZE: &FieldSpec = &super::REGISTERS[46].fields[11];
    /// `PINCOS`, bit 15.
    pub const PINCOS: &FieldSpec = &super::REGISTERS[46].fields[12];
    /// `PL`, bits 16..=17.
    pub const PL: &FieldSpec = &super::REGISTERS[46].fields[13];
    /// `DBM`, bit 18.
    pub const DBM: &FieldSpec = &super::REGISTERS[46].fields[14];
    /// `CT`, bit 19.
    pub const CT: &FieldSpec = &super::REGISTERS[46].fields[15];
    /// `ACK`, bit 20.
    pub const ACK: &FieldSpec = &super::REGISTERS[46].fields[16];
    /// `PBURST`, bits 21..=22.
    pub const PBURST: &FieldSpec = &super::REGISTERS[46].fields[17];
    /// `MBURST`, bits 23..=24.
    pub const MBURST: &FieldSpec = &super::REGISTERS[46].fields[18];
}

/// The fields of `S7NDTR`.
pub mod s7ndtr {
    use super::FieldSpec;
    /// `NDT`, bits 0..=15.
    pub const NDT: &FieldSpec = &super::REGISTERS[47].fields[0];
}

/// The fields of `S7PAR`.
pub mod s7par {
    use super::FieldSpec;
    /// `PA`, bits 0..=31.
    pub const PA: &FieldSpec = &super::REGISTERS[48].fields[0];
}

/// The fields of `S7M0AR`.
pub mod s7m0ar {
    use super::FieldSpec;
    /// `M0A`, bits 0..=31.
    pub const M0A: &FieldSpec = &super::REGISTERS[49].fields[0];
}

/// The fields of `S7M1AR`.
pub mod s7m1ar {
    use super::FieldSpec;
    /// `M1A`, bits 0..=31.
    pub const M1A: &FieldSpec = &super::REGISTERS[50].fields[0];
}

/// The fields of `S7FCR`.
pub mod s7fcr {
    use super::FieldSpec;
    /// `FTH`, bits 0..=1.
    pub const FTH: &FieldSpec = &super::REGISTERS[51].fields[0];
    /// `DMDIS`, bit 2.
    pub const DMDIS: &FieldSpec = &super::REGISTERS[51].fields[1];
    /// `FS`, bits 3..=5, read-only.
    pub const FS: &FieldSpec = &super::REGISTERS[51].fields[2];
    /// `FEIE`, bit 7.
    pub const FEIE: &FieldSpec = &super::REGISTERS[51].fields[3];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 52] = [
    RegisterSpec { name: "LISR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FEIF0", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMEIF0", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIF0", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIF0", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF0", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEIF1", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMEIF1", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIF1", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIF1", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF1", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEIF2", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMEIF2", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIF2", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIF2", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF2", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEIF3", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMEIF3", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIF3", bit: 25, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIF3", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF3", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HISR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FEIF4", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMEIF4", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIF4", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIF4", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF4", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEIF5", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMEIF5", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIF5", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIF5", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF5", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEIF6", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMEIF6", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIF6", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIF6", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF6", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEIF7", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMEIF7", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIF7", bit: 25, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIF7", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF7", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "LIFCR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CFEIF0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CDMEIF0", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTEIF0", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHTIF0", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF0", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CFEIF1", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CDMEIF1", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTEIF1", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHTIF1", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF1", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CFEIF2", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CDMEIF2", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTEIF2", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHTIF2", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF2", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CFEIF3", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CDMEIF3", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTEIF3", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHTIF3", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF3", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HIFCR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CFEIF4", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CDMEIF4", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTEIF4", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHTIF4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF4", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CFEIF5", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CDMEIF5", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTEIF5", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHTIF5", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF5", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CFEIF6", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CDMEIF6", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTEIF6", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHTIF6", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF6", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CFEIF7", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CDMEIF7", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTEIF7", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHTIF7", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF7", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S0CR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PFCTRL", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CIRC", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINC", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MINC", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 11, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSIZE", bit: 13, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINCOS", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CT", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PBURST", bit: 21, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MBURST", bit: 23, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S0NDTR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NDT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S0PAR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S0M0AR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "M0A", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S0M1AR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "M1A", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S0FCR", offset: 0x24, width: Width::W32, reset: 0x0000_0021, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FTH", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMDIS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FS", bit: 3, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S1CR", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PFCTRL", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CIRC", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINC", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MINC", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 11, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSIZE", bit: 13, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINCOS", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CT", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACK", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PBURST", bit: 21, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MBURST", bit: 23, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S1NDTR", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NDT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S1PAR", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S1M0AR", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "M0A", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S1M1AR", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "M1A", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S1FCR", offset: 0x3C, width: Width::W32, reset: 0x0000_0021, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FTH", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMDIS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FS", bit: 3, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S2CR", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PFCTRL", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CIRC", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINC", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MINC", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 11, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSIZE", bit: 13, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINCOS", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CT", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACK", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PBURST", bit: 21, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MBURST", bit: 23, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S2NDTR", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NDT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S2PAR", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S2M0AR", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "M0A", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S2M1AR", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "M1A", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S2FCR", offset: 0x54, width: Width::W32, reset: 0x0000_0021, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FTH", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMDIS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FS", bit: 3, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S3CR", offset: 0x58, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PFCTRL", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CIRC", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINC", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MINC", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 11, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSIZE", bit: 13, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINCOS", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CT", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACK", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PBURST", bit: 21, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MBURST", bit: 23, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S3NDTR", offset: 0x5C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NDT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S3PAR", offset: 0x60, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S3M0AR", offset: 0x64, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "M0A", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S3M1AR", offset: 0x68, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "M1A", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S3FCR", offset: 0x6C, width: Width::W32, reset: 0x0000_0021, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FTH", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMDIS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FS", bit: 3, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S4CR", offset: 0x70, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PFCTRL", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CIRC", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINC", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MINC", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 11, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSIZE", bit: 13, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINCOS", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CT", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACK", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PBURST", bit: 21, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MBURST", bit: 23, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S4NDTR", offset: 0x74, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NDT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S4PAR", offset: 0x78, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S4M0AR", offset: 0x7C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "M0A", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S4M1AR", offset: 0x80, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "M1A", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S4FCR", offset: 0x84, width: Width::W32, reset: 0x0000_0021, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FTH", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMDIS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FS", bit: 3, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S5CR", offset: 0x88, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PFCTRL", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CIRC", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINC", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MINC", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 11, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSIZE", bit: 13, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINCOS", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CT", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACK", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PBURST", bit: 21, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MBURST", bit: 23, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S5NDTR", offset: 0x8C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NDT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S5PAR", offset: 0x90, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S5M0AR", offset: 0x94, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "M0A", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S5M1AR", offset: 0x98, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "M1A", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S5FCR", offset: 0x9C, width: Width::W32, reset: 0x0000_0021, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FTH", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMDIS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FS", bit: 3, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S6CR", offset: 0xA0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PFCTRL", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CIRC", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINC", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MINC", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 11, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSIZE", bit: 13, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINCOS", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CT", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACK", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PBURST", bit: 21, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MBURST", bit: 23, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S6NDTR", offset: 0xA4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NDT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S6PAR", offset: 0xA8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S6M0AR", offset: 0xAC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "M0A", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S6M1AR", offset: 0xB0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "M1A", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S6FCR", offset: 0xB4, width: Width::W32, reset: 0x0000_0021, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FTH", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMDIS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FS", bit: 3, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S7CR", offset: 0xB8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PFCTRL", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CIRC", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINC", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MINC", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 11, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSIZE", bit: 13, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PINCOS", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CT", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACK", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PBURST", bit: 21, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MBURST", bit: 23, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S7NDTR", offset: 0xBC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NDT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S7PAR", offset: 0xC0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S7M0AR", offset: 0xC4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "M0A", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S7M1AR", offset: 0xC8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "M1A", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "S7FCR", offset: 0xCC, width: Width::W32, reset: 0x0000_0021, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FTH", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMDIS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FS", bit: 3, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];