rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `CRC` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `DR` at offset `0x0`, resets to `0xFFFF_FFFF`, read-write.
    Dr = 0,
    /// `IDR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Idr = 1,
    /// `CR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Cr = 2,
    /// `INIT` at offset `0x10`, resets to `0xFFFF_FFFF`, read-write.
    Init = 3,
    /// `POL` at offset `0x14`, resets to `0x04C1_1DB7`, read-write.
    Pol = 4,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 5] = [Self::Dr, Self::Idr, Self::Cr, Self::Init, Self::Pol];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `DR`.
pub mod dr {
    use super::FieldSpec;
    /// `DR`, bits 0..=31.
    pub const DR: &FieldSpec = &super::REGISTERS[0].fields[0];
}

/// The fields of `IDR`.
pub mod idr {
    use super::FieldSpec;
    /// `IDR`, bits 0..=31.
    pub const IDR: &FieldSpec = &super::REGISTERS[1].fields[0];
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `RESET`, bit 0, write-only.
    pub const RESET: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `POLYSIZE`, bits 3..=4.
    pub const POLYSIZE: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `REV_IN`, bits 5..=6.
    pub const REV_IN: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `REV_OUT`, bit 7.
    pub const REV_OUT: &FieldSpec = &super::REGISTERS[2].fields[3];
}

/// The fields of `INIT`.
pub mod init {
    use super::FieldSpec;
    /// `CRC_INIT`, bits 0..=31.
    pub const CRC_INIT: &FieldSpec = &super::REGISTERS[3].fields[0];
}

/// The fields of `POL`.
pub mod pol {
    use super::FieldSpec;
    /// `POL`, bits 0..=31.
    pub const POL: &FieldSpec = &super::REGISTERS[4].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 5] = [
    RegisterSpec { name: "DR", offset: 0x0, width: Width::W32, reset: 0xFFFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IDR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RESET", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "POLYSIZE", bit: 3, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REV_IN", bit: 5, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REV_OUT", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "INIT", offset: 0x10, width: Width::W32, reset: 0xFFFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CRC_INIT", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "POL", offset: 0x14, width: Width::W32, reset: 0x04C1_1DB7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "POL", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];