rigless 0.3.0

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `SPI1` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR1` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr1 = 0,
    /// `CR2` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Cr2 = 1,
    /// `CFG1` at offset `0x8`, resets to `0x0007_0007`, read-write.
    Cfg1 = 2,
    /// `CFG2` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Cfg2 = 3,
    /// `IER` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Ier = 4,
    /// `SR` at offset `0x14`, resets to `0x0000_1002`, read-only.
    Sr = 5,
    /// `IFCR` at offset `0x18`, resets to `0x0000_0000`, write-only.
    Ifcr = 6,
    /// `TXDR` at offset `0x20`, resets to `0x0000_0000`, write-only.
    Txdr = 7,
    /// `RXDR` at offset `0x30`, resets to `0x0000_0000`, read-only.
    Rxdr = 8,
    /// `CRCPOLY` at offset `0x40`, resets to `0x0000_0107`, read-write.
    Crcpoly = 9,
    /// `TXCRC` at offset `0x44`, resets to `0x0000_0000`, read-write.
    Txcrc = 10,
    /// `RXCRC` at offset `0x48`, resets to `0x0000_0000`, read-write.
    Rxcrc = 11,
    /// `UDRDR` at offset `0x4C`, resets to `0x0000_0000`, read-write.
    Udrdr = 12,
    /// `CGFR` at offset `0x50`, resets to `0x0000_0000`, read-write.
    Cgfr = 13,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 14] = [Self::Cr1, Self::Cr2, Self::Cfg1, Self::Cfg2, Self::Ier, Self::Sr, Self::Ifcr, Self::Txdr, Self::Rxdr, Self::Crcpoly, Self::Txcrc, Self::Rxcrc, Self::Udrdr, Self::Cgfr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR1`.
pub mod cr1 {
    use super::FieldSpec;
    /// `SPE`, bit 0.
    pub const SPE: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `MASRX`, bit 8.
    pub const MASRX: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `CSTART`, bit 9, read-only.
    pub const CSTART: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `CSUSP`, bit 10, write-only.
    pub const CSUSP: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `HDDIR`, bit 11.
    pub const HDDIR: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `SSI`, bit 12.
    pub const SSI: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `CRC33_17`, bit 13.
    pub const CRC33_17: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `RCRCI`, bit 14.
    pub const RCRCI: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `TCRCI`, bit 15.
    pub const TCRCI: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `IOLOCK`, bit 16, read-only.
    pub const IOLOCK: &FieldSpec = &super::REGISTERS[0].fields[9];
}

/// The fields of `CR2`.
pub mod cr2 {
    use super::FieldSpec;
    /// `TSIZE`, bits 0..=15.
    pub const TSIZE: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `TSER`, bits 16..=31, read-only.
    pub const TSER: &FieldSpec = &super::REGISTERS[1].fields[1];
}

/// The fields of `CFG1`.
pub mod cfg1 {
    use super::FieldSpec;
    /// `DSIZE`, bits 0..=4.
    pub const DSIZE: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `FTHVL`, bits 5..=8.
    pub const FTHVL: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `UDRCFG`, bits 9..=10.
    pub const UDRCFG: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `UDRDET`, bits 11..=12.
    pub const UDRDET: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `RXDMAEN`, bit 14.
    pub const RXDMAEN: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `TXDMAEN`, bit 15.
    pub const TXDMAEN: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `CRCSIZE`, bits 16..=20.
    pub const CRCSIZE: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `CRCEN`, bit 22.
    pub const CRCEN: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `MBR`, bits 28..=30.
    pub const MBR: &FieldSpec = &super::REGISTERS[2].fields[8];
}

/// The fields of `CFG2`.
pub mod cfg2 {
    use super::FieldSpec;
    /// `MSSI`, bits 0..=3.
    pub const MSSI: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `MIDI`, bits 4..=7.
    pub const MIDI: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `IOSWP`, bit 15.
    pub const IOSWP: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `COMM`, bits 17..=18.
    pub const COMM: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `SP`, bits 19..=21.
    pub const SP: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `MASTER`, bit 22.
    pub const MASTER: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `LSBFRST`, bit 23.
    pub const LSBFRST: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `CPHA`, bit 24.
    pub const CPHA: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `CPOL`, bit 25.
    pub const CPOL: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `SSM`, bit 26.
    pub const SSM: &FieldSpec = &super::REGISTERS[3].fields[9];
    /// `SSIOP`, bit 28.
    pub const SSIOP: &FieldSpec = &super::REGISTERS[3].fields[10];
    /// `SSOE`, bit 29.
    pub const SSOE: &FieldSpec = &super::REGISTERS[3].fields[11];
    /// `SSOM`, bit 30.
    pub const SSOM: &FieldSpec = &super::REGISTERS[3].fields[12];
    /// `AFCNTR`, bit 31.
    pub const AFCNTR: &FieldSpec = &super::REGISTERS[3].fields[13];
}

/// The fields of `IER`.
pub mod ier {
    use super::FieldSpec;
    /// `RXPIE`, bit 0.
    pub const RXPIE: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `TXPIE`, bit 1, read-only.
    pub const TXPIE: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `DPXPIE`, bit 2, read-only.
    pub const DPXPIE: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `EOTIE`, bit 3.
    pub const EOTIE: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `TXTFIE`, bit 4.
    pub const TXTFIE: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `UDRIE`, bit 5.
    pub const UDRIE: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `OVRIE`, bit 6.
    pub const OVRIE: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `CRCEIE`, bit 7.
    pub const CRCEIE: &FieldSpec = &super::REGISTERS[4].fields[7];
    /// `TIFREIE`, bit 8.
    pub const TIFREIE: &FieldSpec = &super::REGISTERS[4].fields[8];
    /// `MODFIE`, bit 9.
    pub const MODFIE: &FieldSpec = &super::REGISTERS[4].fields[9];
    /// `TSERFIE`, bit 10.
    pub const TSERFIE: &FieldSpec = &super::REGISTERS[4].fields[10];
}

/// The fields of `SR`.
pub mod sr {
    use super::FieldSpec;
    /// `RXP`, bit 0.
    pub const RXP: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `TXP`, bit 1.
    pub const TXP: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `DXP`, bit 2.
    pub const DXP: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `EOT`, bit 3.
    pub const EOT: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `TXTF`, bit 4.
    pub const TXTF: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `UDR`, bit 5.
    pub const UDR: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `OVR`, bit 6.
    pub const OVR: &FieldSpec = &super::REGISTERS[5].fields[6];
    /// `CRCE`, bit 7.
    pub const CRCE: &FieldSpec = &super::REGISTERS[5].fields[7];
    /// `TIFRE`, bit 8.
    pub const TIFRE: &FieldSpec = &super::REGISTERS[5].fields[8];
    /// `MODF`, bit 9.
    pub const MODF: &FieldSpec = &super::REGISTERS[5].fields[9];
    /// `TSERF`, bit 10.
    pub const TSERF: &FieldSpec = &super::REGISTERS[5].fields[10];
    /// `SUSP`, bit 11.
    pub const SUSP: &FieldSpec = &super::REGISTERS[5].fields[11];
    /// `TXC`, bit 12.
    pub const TXC: &FieldSpec = &super::REGISTERS[5].fields[12];
    /// `RXPLVL`, bits 13..=14.
    pub const RXPLVL: &FieldSpec = &super::REGISTERS[5].fields[13];
    /// `RXWNE`, bit 15.
    pub const RXWNE: &FieldSpec = &super::REGISTERS[5].fields[14];
    /// `CTSIZE`, bits 16..=31.
    pub const CTSIZE: &FieldSpec = &super::REGISTERS[5].fields[15];
}

/// The fields of `IFCR`.
pub mod ifcr {
    use super::FieldSpec;
    /// `EOTC`, bit 3.
    pub const EOTC: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `TXTFC`, bit 4.
    pub const TXTFC: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `UDRC`, bit 5.
    pub const UDRC: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `OVRC`, bit 6.
    pub const OVRC: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `CRCEC`, bit 7.
    pub const CRCEC: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `TIFREC`, bit 8.
    pub const TIFREC: &FieldSpec = &super::REGISTERS[6].fields[5];
    /// `MODFC`, bit 9.
    pub const MODFC: &FieldSpec = &super::REGISTERS[6].fields[6];
    /// `TSERFC`, bit 10.
    pub const TSERFC: &FieldSpec = &super::REGISTERS[6].fields[7];
    /// `SUSPC`, bit 11.
    pub const SUSPC: &FieldSpec = &super::REGISTERS[6].fields[8];
}

/// The fields of `TXDR`.
pub mod txdr {
    use super::FieldSpec;
    /// `TXDR`, bits 0..=31.
    pub const TXDR: &FieldSpec = &super::REGISTERS[7].fields[0];
}

/// The fields of `RXDR`.
pub mod rxdr {
    use super::FieldSpec;
    /// `RXDR`, bits 0..=31.
    pub const RXDR: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The fields of `CRCPOLY`.
pub mod crcpoly {
    use super::FieldSpec;
    /// `CRCPOLY`, bits 0..=31.
    pub const CRCPOLY: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `TXCRC`.
pub mod txcrc {
    use super::FieldSpec;
    /// `TXCRC`, bits 0..=31.
    pub const TXCRC: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The fields of `RXCRC`.
pub mod rxcrc {
    use super::FieldSpec;
    /// `RXCRC`, bits 0..=31.
    pub const RXCRC: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The fields of `UDRDR`.
pub mod udrdr {
    use super::FieldSpec;
    /// `UDRDR`, bits 0..=31.
    pub const UDRDR: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The fields of `CGFR`.
pub mod cgfr {
    use super::FieldSpec;
    /// `I2SMOD`, bit 0.
    pub const I2SMOD: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `I2SCFG`, bits 1..=3.
    pub const I2SCFG: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `I2SSTD`, bits 4..=5.
    pub const I2SSTD: &FieldSpec = &super::REGISTERS[13].fields[2];
    /// `PCMSYNC`, bit 7.
    pub const PCMSYNC: &FieldSpec = &super::REGISTERS[13].fields[3];
    /// `DATLEN`, bits 8..=9.
    pub const DATLEN: &FieldSpec = &super::REGISTERS[13].fields[4];
    /// `CHLEN`, bit 10.
    pub const CHLEN: &FieldSpec = &super::REGISTERS[13].fields[5];
    /// `CKPOL`, bit 11.
    pub const CKPOL: &FieldSpec = &super::REGISTERS[13].fields[6];
    /// `FIXCH`, bit 12.
    pub const FIXCH: &FieldSpec = &super::REGISTERS[13].fields[7];
    /// `WSINV`, bit 13.
    pub const WSINV: &FieldSpec = &super::REGISTERS[13].fields[8];
    /// `DATFMT`, bit 14.
    pub const DATFMT: &FieldSpec = &super::REGISTERS[13].fields[9];
    /// `I2SDIV`, bits 16..=23.
    pub const I2SDIV: &FieldSpec = &super::REGISTERS[13].fields[10];
    /// `ODD`, bit 24.
    pub const ODD: &FieldSpec = &super::REGISTERS[13].fields[11];
    /// `MCKOE`, bit 25.
    pub const MCKOE: &FieldSpec = &super::REGISTERS[13].fields[12];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 14] = [
    RegisterSpec { name: "CR1", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SPE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASRX", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSTART", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSUSP", bit: 10, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HDDIR", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SSI", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRC33_17", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RCRCI", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCRCI", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IOLOCK", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR2", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TSIZE", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSER", bit: 16, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CFG1", offset: 0x8, width: Width::W32, reset: 0x0007_0007, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DSIZE", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FTHVL", bit: 5, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UDRCFG", bit: 9, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UDRDET", bit: 11, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXDMAEN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXDMAEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRCSIZE", bit: 16, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRCEN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MBR", bit: 28, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CFG2", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MSSI", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MIDI", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IOSWP", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COMM", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SP", bit: 19, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MASTER", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSBFRST", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CPHA", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CPOL", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SSM", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SSIOP", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SSOE", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SSOM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFCNTR", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IER", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXPIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXPIE", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DPXPIE", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXTFIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UDRIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVRIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRCEIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIFREIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODFIE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSERFIE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR", offset: 0x14, width: Width::W32, reset: 0x0000_1002, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXP", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXP", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DXP", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOT", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXTF", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UDR", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVR", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRCE", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIFRE", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODF", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSERF", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SUSP", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXC", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXPLVL", bit: 13, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXWNE", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTSIZE", bit: 16, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IFCR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EOTC", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXTFC", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UDRC", bit: 5, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVRC", bit: 6, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRCEC", bit: 7, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIFREC", bit: 8, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODFC", bit: 9, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSERFC", bit: 10, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SUSPC", bit: 11, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TXDR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TXDR", bit: 0, width: 32, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RXDR", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXDR", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CRCPOLY", offset: 0x40, width: Width::W32, reset: 0x0000_0107, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CRCPOLY", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TXCRC", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TXCRC", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RXCRC", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXCRC", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UDRDR", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "UDRDR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CGFR", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "I2SMOD", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2SCFG", bit: 1, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2SSTD", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCMSYNC", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATLEN", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHLEN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKPOL", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FIXCH", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WSINV", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATFMT", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2SDIV", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODD", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCKOE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];