// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `Flash` and the instances derived from it.
use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};
/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
/// `ACR` at offset `0x0`, resets to `0x0000_0037`, read-write.
Acr = 0,
/// `KEYR1` at offset `0x4`, resets to `0x0000_0000`, read-write.
Keyr1 = 1,
/// `OPTKEYR` at offset `0x8`, resets to `0x0000_0000`, read-write.
Optkeyr = 2,
/// `CR1` at offset `0xC`, resets to `0x0000_0000`, read-write.
Cr1 = 3,
/// `SR1` at offset `0x10`, resets to `0x0000_0000`, read-write.
Sr1 = 4,
/// `CCR1` at offset `0x14`, resets to `0x0000_0000`, read-write.
Ccr1 = 5,
/// `OPTCR` at offset `0x18`, resets to `0x0000_0000`, read-write.
Optcr = 6,
/// `OPTSR_CUR` at offset `0x1C`, resets to `0x0000_0000`, read-write.
OptsrCur = 7,
/// `OPTSR_PRG` at offset `0x20`, resets to `0x0000_0000`, read-write.
OptsrPrg = 8,
/// `OPTCCR` at offset `0x24`, resets to `0x0000_0000`, write-only.
Optccr = 9,
/// `PRAR_CUR1` at offset `0x28`, resets to `0x0000_0000`, read-only.
PrarCur1 = 10,
/// `PRAR_PRG1` at offset `0x2C`, resets to `0x0000_0000`, read-write.
PrarPrg1 = 11,
/// `SCAR_CUR1` at offset `0x30`, resets to `0x0000_0000`, read-write.
ScarCur1 = 12,
/// `SCAR_PRG1` at offset `0x34`, resets to `0x0000_0000`, read-write.
ScarPrg1 = 13,
/// `WPSN_CUR1R` at offset `0x38`, resets to `0x0000_0000`, read-only.
WpsnCur1r = 14,
/// `WPSN_PRG1R` at offset `0x3C`, resets to `0x0000_0000`, read-write.
WpsnPrg1r = 15,
/// `BOOT_CURR` at offset `0x40`, resets to `0x0000_0000`, read-only.
BootCurr = 16,
/// `BOOT_PRGR` at offset `0x44`, resets to `0x0000_0000`, read-only.
BootPrgr = 17,
/// `CRCCR1` at offset `0x50`, resets to `0x0000_0000`, read-write.
Crccr1 = 18,
/// `CRCSADD1R` at offset `0x54`, resets to `0x0000_0000`, read-write.
Crcsadd1r = 19,
/// `CRCEADD1R` at offset `0x58`, resets to `0x0000_0000`, read-write.
Crceadd1r = 20,
/// `CRCDATAR` at offset `0x5C`, resets to `0x0000_0000`, read-write.
Crcdatar = 21,
/// `ECC_FA1R` at offset `0x60`, resets to `0x0000_0000`, read-only.
EccFa1r = 22,
/// `ACR_` at offset `0x100`, resets to `0x0000_0037`, read-write.
Acr_ = 23,
/// `KEYR2` at offset `0x104`, resets to `0x0000_0000`, read-only.
Keyr2 = 24,
/// `OPTKEYR_` at offset `0x108`, resets to `0x0000_0000`, read-write.
Optkeyr_ = 25,
/// `CR2` at offset `0x10C`, resets to `0x0000_0031`, read-write.
Cr2 = 26,
/// `SR2` at offset `0x110`, resets to `0x0000_0000`, read-write.
Sr2 = 27,
/// `CCR2` at offset `0x114`, resets to `0x0000_0000`, read-write.
Ccr2 = 28,
/// `OPTCR_` at offset `0x118`, resets to `0x0000_0000`, read-write.
Optcr_ = 29,
/// `OPTSR_CUR_` at offset `0x11C`, resets to `0x0000_0000`, read-write.
OptsrCur_ = 30,
/// `OPTSR_PRG_` at offset `0x120`, resets to `0x0000_0000`, read-write.
OptsrPrg_ = 31,
/// `OPTCCR_` at offset `0x124`, resets to `0x0000_0000`, write-only.
Optccr_ = 32,
/// `PRAR_CUR2` at offset `0x128`, resets to `0x0000_0000`, read-only.
PrarCur2 = 33,
/// `PRAR_PRG2` at offset `0x12C`, resets to `0x0000_0000`, read-write.
PrarPrg2 = 34,
/// `SCAR_CUR2` at offset `0x130`, resets to `0x0000_0000`, read-write.
ScarCur2 = 35,
/// `SCAR_PRG2` at offset `0x134`, resets to `0x0000_0000`, read-write.
ScarPrg2 = 36,
/// `WPSN_CUR2R` at offset `0x138`, resets to `0x0000_0000`, read-only.
WpsnCur2r = 37,
/// `WPSN_PRG2R` at offset `0x13C`, resets to `0x0000_0000`, read-write.
WpsnPrg2r = 38,
/// `BOOT_CURR_` at offset `0x140`, resets to `0x0000_0000`, read-only.
BootCurr_ = 39,
/// `BOOT_PRGR_` at offset `0x144`, resets to `0x0000_0000`, read-only.
BootPrgr_ = 40,
/// `CRCCR2` at offset `0x150`, resets to `0x0000_0000`, read-write.
Crccr2 = 41,
/// `CRCSADD2R` at offset `0x154`, resets to `0x0000_0000`, read-write.
Crcsadd2r = 42,
/// `CRCEADD2R` at offset `0x158`, resets to `0x0000_0000`, read-write.
Crceadd2r = 43,
/// `CRCDATAR_` at offset `0x15C`, resets to `0x0000_0000`, read-write.
Crcdatar_ = 44,
/// `ECC_FA2R` at offset `0x160`, resets to `0x0000_0000`, read-only.
EccFa2r = 45,
}
impl Register {
/// Every register, in table order.
pub const ALL: [Self; 46] = [Self::Acr, Self::Keyr1, Self::Optkeyr, Self::Cr1, Self::Sr1, Self::Ccr1, Self::Optcr, Self::OptsrCur, Self::OptsrPrg, Self::Optccr, Self::PrarCur1, Self::PrarPrg1, Self::ScarCur1, Self::ScarPrg1, Self::WpsnCur1r, Self::WpsnPrg1r, Self::BootCurr, Self::BootPrgr, Self::Crccr1, Self::Crcsadd1r, Self::Crceadd1r, Self::Crcdatar, Self::EccFa1r, Self::Acr_, Self::Keyr2, Self::Optkeyr_, Self::Cr2, Self::Sr2, Self::Ccr2, Self::Optcr_, Self::OptsrCur_, Self::OptsrPrg_, Self::Optccr_, Self::PrarCur2, Self::PrarPrg2, Self::ScarCur2, Self::ScarPrg2, Self::WpsnCur2r, Self::WpsnPrg2r, Self::BootCurr_, Self::BootPrgr_, Self::Crccr2, Self::Crcsadd2r, Self::Crceadd2r, Self::Crcdatar_, Self::EccFa2r];
}
impl Layout for Register {
const REGISTERS: &'static [RegisterSpec] = ®ISTERS;
fn from_index(index: usize) -> Option<Self> {
Self::ALL.get(index).copied()
}
fn index(self) -> usize {
self as usize
}
}
/// The fields of `ACR`.
pub mod acr {
use super::FieldSpec;
/// `LATENCY`, bits 0..=3.
pub const LATENCY: &FieldSpec = &super::REGISTERS[0].fields[0];
/// `WRHIGHFREQ`, bits 4..=5.
pub const WRHIGHFREQ: &FieldSpec = &super::REGISTERS[0].fields[1];
}
/// The fields of `KEYR1`.
pub mod keyr1 {
use super::FieldSpec;
/// `KEY1R`, bits 0..=31.
pub const KEY1R: &FieldSpec = &super::REGISTERS[1].fields[0];
}
/// The fields of `OPTKEYR`.
pub mod optkeyr {
use super::FieldSpec;
/// `OPTKEYR`, bits 0..=31.
pub const OPTKEYR: &FieldSpec = &super::REGISTERS[2].fields[0];
}
/// The fields of `CR1`.
pub mod cr1 {
use super::FieldSpec;
/// `LOCK1`, bit 0.
pub const LOCK1: &FieldSpec = &super::REGISTERS[3].fields[0];
/// `PG1`, bit 1.
pub const PG1: &FieldSpec = &super::REGISTERS[3].fields[1];
/// `SER1`, bit 2.
pub const SER1: &FieldSpec = &super::REGISTERS[3].fields[2];
/// `BER1`, bit 3.
pub const BER1: &FieldSpec = &super::REGISTERS[3].fields[3];
/// `PSIZE1`, bits 4..=5.
pub const PSIZE1: &FieldSpec = &super::REGISTERS[3].fields[4];
/// `FW1`, bit 6.
pub const FW1: &FieldSpec = &super::REGISTERS[3].fields[5];
/// `START1`, bit 7.
pub const START1: &FieldSpec = &super::REGISTERS[3].fields[6];
/// `SNB1`, bits 8..=10.
pub const SNB1: &FieldSpec = &super::REGISTERS[3].fields[7];
/// `CRC_EN`, bit 15.
pub const CRC_EN: &FieldSpec = &super::REGISTERS[3].fields[8];
/// `EOPIE1`, bit 16.
pub const EOPIE1: &FieldSpec = &super::REGISTERS[3].fields[9];
/// `WRPERRIE1`, bit 17.
pub const WRPERRIE1: &FieldSpec = &super::REGISTERS[3].fields[10];
/// `PGSERRIE1`, bit 18.
pub const PGSERRIE1: &FieldSpec = &super::REGISTERS[3].fields[11];
/// `STRBERRIE1`, bit 19.
pub const STRBERRIE1: &FieldSpec = &super::REGISTERS[3].fields[12];
/// `INCERRIE1`, bit 21.
pub const INCERRIE1: &FieldSpec = &super::REGISTERS[3].fields[13];
/// `OPERRIE1`, bit 22.
pub const OPERRIE1: &FieldSpec = &super::REGISTERS[3].fields[14];
/// `RDPERRIE1`, bit 23.
pub const RDPERRIE1: &FieldSpec = &super::REGISTERS[3].fields[15];
/// `RDSERRIE1`, bit 24.
pub const RDSERRIE1: &FieldSpec = &super::REGISTERS[3].fields[16];
/// `SNECCERR1`, bit 25.
pub const SNECCERR1: &FieldSpec = &super::REGISTERS[3].fields[17];
/// `DBECCERRIE1`, bit 26.
pub const DBECCERRIE1: &FieldSpec = &super::REGISTERS[3].fields[18];
/// `CRCENDIE1`, bit 27.
pub const CRCENDIE1: &FieldSpec = &super::REGISTERS[3].fields[19];
/// `CRCRDERRIE1`, bit 28.
pub const CRCRDERRIE1: &FieldSpec = &super::REGISTERS[3].fields[20];
}
/// The fields of `SR1`.
pub mod sr1 {
use super::FieldSpec;
/// `BSY1`, bit 0.
pub const BSY1: &FieldSpec = &super::REGISTERS[4].fields[0];
/// `WBNE1`, bit 1.
pub const WBNE1: &FieldSpec = &super::REGISTERS[4].fields[1];
/// `QW1`, bit 2.
pub const QW1: &FieldSpec = &super::REGISTERS[4].fields[2];
/// `CRC_BUSY1`, bit 3.
pub const CRC_BUSY1: &FieldSpec = &super::REGISTERS[4].fields[3];
/// `EOP1`, bit 16.
pub const EOP1: &FieldSpec = &super::REGISTERS[4].fields[4];
/// `WRPERR1`, bit 17.
pub const WRPERR1: &FieldSpec = &super::REGISTERS[4].fields[5];
/// `PGSERR1`, bit 18.
pub const PGSERR1: &FieldSpec = &super::REGISTERS[4].fields[6];
/// `STRBERR1`, bit 19.
pub const STRBERR1: &FieldSpec = &super::REGISTERS[4].fields[7];
/// `INCERR1`, bit 21.
pub const INCERR1: &FieldSpec = &super::REGISTERS[4].fields[8];
/// `OPERR1`, bit 22.
pub const OPERR1: &FieldSpec = &super::REGISTERS[4].fields[9];
/// `RDPERR1`, bit 23.
pub const RDPERR1: &FieldSpec = &super::REGISTERS[4].fields[10];
/// `RDSERR1`, bit 24.
pub const RDSERR1: &FieldSpec = &super::REGISTERS[4].fields[11];
/// `SNECCERR`, bit 25.
pub const SNECCERR: &FieldSpec = &super::REGISTERS[4].fields[12];
/// `DBECCERR1`, bit 26.
pub const DBECCERR1: &FieldSpec = &super::REGISTERS[4].fields[13];
/// `CRCEND1`, bit 27.
pub const CRCEND1: &FieldSpec = &super::REGISTERS[4].fields[14];
/// `CRCRDERR1`, bit 28, read-only.
pub const CRCRDERR1: &FieldSpec = &super::REGISTERS[4].fields[15];
}
/// The fields of `CCR1`.
pub mod ccr1 {
use super::FieldSpec;
/// `CLR_EOP1`, bit 16.
pub const CLR_EOP1: &FieldSpec = &super::REGISTERS[5].fields[0];
/// `CLR_WRPERR1`, bit 17.
pub const CLR_WRPERR1: &FieldSpec = &super::REGISTERS[5].fields[1];
/// `CLR_PGSERR1`, bit 18.
pub const CLR_PGSERR1: &FieldSpec = &super::REGISTERS[5].fields[2];
/// `CLR_STRBERR1`, bit 19.
pub const CLR_STRBERR1: &FieldSpec = &super::REGISTERS[5].fields[3];
/// `CLR_INCERR1`, bit 21.
pub const CLR_INCERR1: &FieldSpec = &super::REGISTERS[5].fields[4];
/// `CLR_OPERR1`, bit 22.
pub const CLR_OPERR1: &FieldSpec = &super::REGISTERS[5].fields[5];
/// `CLR_RDPERR1`, bit 23.
pub const CLR_RDPERR1: &FieldSpec = &super::REGISTERS[5].fields[6];
/// `CLR_RDSERR1`, bit 24.
pub const CLR_RDSERR1: &FieldSpec = &super::REGISTERS[5].fields[7];
/// `CLR_SNECCERR1`, bit 25.
pub const CLR_SNECCERR1: &FieldSpec = &super::REGISTERS[5].fields[8];
/// `CLR_DBECCERR1`, bit 26.
pub const CLR_DBECCERR1: &FieldSpec = &super::REGISTERS[5].fields[9];
/// `CLR_CRCEND1`, bit 27.
pub const CLR_CRCEND1: &FieldSpec = &super::REGISTERS[5].fields[10];
/// `CLR_CRCRDERR1`, bit 28, write-only.
pub const CLR_CRCRDERR1: &FieldSpec = &super::REGISTERS[5].fields[11];
}
/// The fields of `OPTCR`.
pub mod optcr {
use super::FieldSpec;
/// `OPTLOCK`, bit 0.
pub const OPTLOCK: &FieldSpec = &super::REGISTERS[6].fields[0];
/// `OPTSTART`, bit 1.
pub const OPTSTART: &FieldSpec = &super::REGISTERS[6].fields[1];
/// `MER`, bit 4.
pub const MER: &FieldSpec = &super::REGISTERS[6].fields[2];
/// `OPTCHANGEERRIE`, bit 30.
pub const OPTCHANGEERRIE: &FieldSpec = &super::REGISTERS[6].fields[3];
/// `SWAP_BANK`, bit 31.
pub const SWAP_BANK: &FieldSpec = &super::REGISTERS[6].fields[4];
}
/// The fields of `OPTSR_CUR`.
pub mod optsr_cur {
use super::FieldSpec;
/// `OPT_BUSY`, bit 0.
pub const OPT_BUSY: &FieldSpec = &super::REGISTERS[7].fields[0];
/// `BOR_LEV`, bits 2..=3.
pub const BOR_LEV: &FieldSpec = &super::REGISTERS[7].fields[1];
/// `IWDG1_SW`, bit 4.
pub const IWDG1_SW: &FieldSpec = &super::REGISTERS[7].fields[2];
/// `NRST_STOP_D1`, bit 6.
pub const NRST_STOP_D1: &FieldSpec = &super::REGISTERS[7].fields[3];
/// `NRST_STBY_D1`, bit 7.
pub const NRST_STBY_D1: &FieldSpec = &super::REGISTERS[7].fields[4];
/// `RDP`, bits 8..=15.
pub const RDP: &FieldSpec = &super::REGISTERS[7].fields[5];
/// `IWDG_FZ_STOP`, bit 17.
pub const IWDG_FZ_STOP: &FieldSpec = &super::REGISTERS[7].fields[6];
/// `IWDG_FZ_SDBY`, bit 18.
pub const IWDG_FZ_SDBY: &FieldSpec = &super::REGISTERS[7].fields[7];
/// `ST_RAM_SIZE`, bits 19..=20.
pub const ST_RAM_SIZE: &FieldSpec = &super::REGISTERS[7].fields[8];
/// `SECURITY`, bit 21.
pub const SECURITY: &FieldSpec = &super::REGISTERS[7].fields[9];
/// `IO_HSLV`, bit 29.
pub const IO_HSLV: &FieldSpec = &super::REGISTERS[7].fields[10];
/// `OPTCHANGEERR`, bit 30.
pub const OPTCHANGEERR: &FieldSpec = &super::REGISTERS[7].fields[11];
/// `SWAP_BANK_OPT`, bit 31.
pub const SWAP_BANK_OPT: &FieldSpec = &super::REGISTERS[7].fields[12];
}
/// The fields of `OPTSR_PRG`.
pub mod optsr_prg {
use super::FieldSpec;
/// `BOR_LEV`, bits 2..=3.
pub const BOR_LEV: &FieldSpec = &super::REGISTERS[8].fields[0];
/// `IWDG1_SW`, bit 4.
pub const IWDG1_SW: &FieldSpec = &super::REGISTERS[8].fields[1];
/// `NRST_STOP_D1`, bit 6.
pub const NRST_STOP_D1: &FieldSpec = &super::REGISTERS[8].fields[2];
/// `NRST_STBY_D1`, bit 7.
pub const NRST_STBY_D1: &FieldSpec = &super::REGISTERS[8].fields[3];
/// `RDP`, bits 8..=15.
pub const RDP: &FieldSpec = &super::REGISTERS[8].fields[4];
/// `IWDG_FZ_STOP`, bit 17.
pub const IWDG_FZ_STOP: &FieldSpec = &super::REGISTERS[8].fields[5];
/// `IWDG_FZ_SDBY`, bit 18.
pub const IWDG_FZ_SDBY: &FieldSpec = &super::REGISTERS[8].fields[6];
/// `ST_RAM_SIZE`, bits 19..=20.
pub const ST_RAM_SIZE: &FieldSpec = &super::REGISTERS[8].fields[7];
/// `SECURITY`, bit 21.
pub const SECURITY: &FieldSpec = &super::REGISTERS[8].fields[8];
/// `IO_HSLV`, bit 29.
pub const IO_HSLV: &FieldSpec = &super::REGISTERS[8].fields[9];
/// `SWAP_BANK_OPT`, bit 31.
pub const SWAP_BANK_OPT: &FieldSpec = &super::REGISTERS[8].fields[10];
}
/// The fields of `OPTCCR`.
pub mod optccr {
use super::FieldSpec;
/// `CLR_OPTCHANGEERR`, bit 30.
pub const CLR_OPTCHANGEERR: &FieldSpec = &super::REGISTERS[9].fields[0];
}
/// The fields of `PRAR_CUR1`.
pub mod prar_cur1 {
use super::FieldSpec;
/// `PROT_AREA_START1`, bits 0..=11.
pub const PROT_AREA_START1: &FieldSpec = &super::REGISTERS[10].fields[0];
/// `PROT_AREA_END1`, bits 16..=27.
pub const PROT_AREA_END1: &FieldSpec = &super::REGISTERS[10].fields[1];
/// `DMEP1`, bit 31.
pub const DMEP1: &FieldSpec = &super::REGISTERS[10].fields[2];
}
/// The fields of `PRAR_PRG1`.
pub mod prar_prg1 {
use super::FieldSpec;
/// `PROT_AREA_START1`, bits 0..=11.
pub const PROT_AREA_START1: &FieldSpec = &super::REGISTERS[11].fields[0];
/// `PROT_AREA_END1`, bits 16..=27.
pub const PROT_AREA_END1: &FieldSpec = &super::REGISTERS[11].fields[1];
/// `DMEP1`, bit 31.
pub const DMEP1: &FieldSpec = &super::REGISTERS[11].fields[2];
}
/// The fields of `SCAR_CUR1`.
pub mod scar_cur1 {
use super::FieldSpec;
/// `SEC_AREA_START1`, bits 0..=11.
pub const SEC_AREA_START1: &FieldSpec = &super::REGISTERS[12].fields[0];
/// `SEC_AREA_END1`, bits 16..=27.
pub const SEC_AREA_END1: &FieldSpec = &super::REGISTERS[12].fields[1];
/// `DMES1`, bit 31.
pub const DMES1: &FieldSpec = &super::REGISTERS[12].fields[2];
}
/// The fields of `SCAR_PRG1`.
pub mod scar_prg1 {
use super::FieldSpec;
/// `SEC_AREA_START1`, bits 0..=11.
pub const SEC_AREA_START1: &FieldSpec = &super::REGISTERS[13].fields[0];
/// `SEC_AREA_END1`, bits 16..=27.
pub const SEC_AREA_END1: &FieldSpec = &super::REGISTERS[13].fields[1];
/// `DMES1`, bit 31.
pub const DMES1: &FieldSpec = &super::REGISTERS[13].fields[2];
}
/// The fields of `WPSN_CUR1R`.
pub mod wpsn_cur1r {
use super::FieldSpec;
/// `WRPSn1`, bits 0..=7.
pub const WRPSN1: &FieldSpec = &super::REGISTERS[14].fields[0];
}
/// The fields of `WPSN_PRG1R`.
pub mod wpsn_prg1r {
use super::FieldSpec;
/// `WRPSn1`, bits 0..=7.
pub const WRPSN1: &FieldSpec = &super::REGISTERS[15].fields[0];
}
/// The fields of `BOOT_CURR`.
pub mod boot_curr {
use super::FieldSpec;
/// `BOOT_ADD0`, bits 0..=15.
pub const BOOT_ADD0: &FieldSpec = &super::REGISTERS[16].fields[0];
/// `BOOT_ADD1`, bits 16..=31.
pub const BOOT_ADD1: &FieldSpec = &super::REGISTERS[16].fields[1];
}
/// The fields of `BOOT_PRGR`.
pub mod boot_prgr {
use super::FieldSpec;
/// `BOOT_ADD0`, bits 0..=15.
pub const BOOT_ADD0: &FieldSpec = &super::REGISTERS[17].fields[0];
/// `BOOT_ADD1`, bits 16..=31.
pub const BOOT_ADD1: &FieldSpec = &super::REGISTERS[17].fields[1];
}
/// The fields of `CRCCR1`.
pub mod crccr1 {
use super::FieldSpec;
/// `CRC_SECT`, bits 0..=2.
pub const CRC_SECT: &FieldSpec = &super::REGISTERS[18].fields[0];
/// `ALL_BANK`, bit 7.
pub const ALL_BANK: &FieldSpec = &super::REGISTERS[18].fields[1];
/// `CRC_BY_SECT`, bit 8.
pub const CRC_BY_SECT: &FieldSpec = &super::REGISTERS[18].fields[2];
/// `ADD_SECT`, bit 9.
pub const ADD_SECT: &FieldSpec = &super::REGISTERS[18].fields[3];
/// `CLEAN_SECT`, bit 10.
pub const CLEAN_SECT: &FieldSpec = &super::REGISTERS[18].fields[4];
/// `START_CRC`, bit 16.
pub const START_CRC: &FieldSpec = &super::REGISTERS[18].fields[5];
/// `CLEAN_CRC`, bit 17.
pub const CLEAN_CRC: &FieldSpec = &super::REGISTERS[18].fields[6];
/// `CRC_BURST`, bits 20..=21.
pub const CRC_BURST: &FieldSpec = &super::REGISTERS[18].fields[7];
}
/// The fields of `CRCSADD1R`.
pub mod crcsadd1r {
use super::FieldSpec;
/// `CRC_START_ADDR`, bits 2..=19.
pub const CRC_START_ADDR: &FieldSpec = &super::REGISTERS[19].fields[0];
}
/// The fields of `CRCEADD1R`.
pub mod crceadd1r {
use super::FieldSpec;
/// `CRC_END_ADDR`, bits 2..=19.
pub const CRC_END_ADDR: &FieldSpec = &super::REGISTERS[20].fields[0];
}
/// The fields of `CRCDATAR`.
pub mod crcdatar {
use super::FieldSpec;
/// `CRC_DATA`, bits 0..=31.
pub const CRC_DATA: &FieldSpec = &super::REGISTERS[21].fields[0];
}
/// The fields of `ECC_FA1R`.
pub mod ecc_fa1r {
use super::FieldSpec;
/// `FAIL_ECC_ADDR1`, bits 0..=14.
pub const FAIL_ECC_ADDR1: &FieldSpec = &super::REGISTERS[22].fields[0];
}
/// The fields of `ACR_`.
pub mod acr_ {
use super::FieldSpec;
/// `LATENCY`, bits 0..=3.
pub const LATENCY: &FieldSpec = &super::REGISTERS[23].fields[0];
/// `WRHIGHFREQ`, bits 4..=5.
pub const WRHIGHFREQ: &FieldSpec = &super::REGISTERS[23].fields[1];
}
/// The fields of `KEYR2`.
pub mod keyr2 {
use super::FieldSpec;
/// `KEYR2`, bits 0..=31.
pub const KEYR2: &FieldSpec = &super::REGISTERS[24].fields[0];
}
/// The fields of `OPTKEYR_`.
pub mod optkeyr_ {
use super::FieldSpec;
/// `OPTKEYR`, bits 0..=31.
pub const OPTKEYR: &FieldSpec = &super::REGISTERS[25].fields[0];
}
/// The fields of `CR2`.
pub mod cr2 {
use super::FieldSpec;
/// `LOCK2`, bit 0.
pub const LOCK2: &FieldSpec = &super::REGISTERS[26].fields[0];
/// `PG2`, bit 1.
pub const PG2: &FieldSpec = &super::REGISTERS[26].fields[1];
/// `SER2`, bit 2.
pub const SER2: &FieldSpec = &super::REGISTERS[26].fields[2];
/// `BER2`, bit 3.
pub const BER2: &FieldSpec = &super::REGISTERS[26].fields[3];
/// `PSIZE2`, bits 4..=5.
pub const PSIZE2: &FieldSpec = &super::REGISTERS[26].fields[4];
/// `FW2`, bit 6.
pub const FW2: &FieldSpec = &super::REGISTERS[26].fields[5];
/// `START2`, bit 7.
pub const START2: &FieldSpec = &super::REGISTERS[26].fields[6];
/// `SNB2`, bits 8..=10.
pub const SNB2: &FieldSpec = &super::REGISTERS[26].fields[7];
/// `SPSS2`, bit 14.
pub const SPSS2: &FieldSpec = &super::REGISTERS[26].fields[8];
/// `CRC_EN`, bit 15.
pub const CRC_EN: &FieldSpec = &super::REGISTERS[26].fields[9];
/// `EOPIE2`, bit 16.
pub const EOPIE2: &FieldSpec = &super::REGISTERS[26].fields[10];
/// `WRPERRIE2`, bit 17.
pub const WRPERRIE2: &FieldSpec = &super::REGISTERS[26].fields[11];
/// `PGSERRIE2`, bit 18.
pub const PGSERRIE2: &FieldSpec = &super::REGISTERS[26].fields[12];
/// `STRBERRIE2`, bit 19.
pub const STRBERRIE2: &FieldSpec = &super::REGISTERS[26].fields[13];
/// `INCERRIE2`, bit 21.
pub const INCERRIE2: &FieldSpec = &super::REGISTERS[26].fields[14];
/// `OPERRIE2`, bit 22.
pub const OPERRIE2: &FieldSpec = &super::REGISTERS[26].fields[15];
/// `RDPERRIE2`, bit 23.
pub const RDPERRIE2: &FieldSpec = &super::REGISTERS[26].fields[16];
/// `RDSERRIE2`, bit 24.
pub const RDSERRIE2: &FieldSpec = &super::REGISTERS[26].fields[17];
/// `SNECCERRIE2`, bit 25.
pub const SNECCERRIE2: &FieldSpec = &super::REGISTERS[26].fields[18];
/// `DBECCERRIE2`, bit 26.
pub const DBECCERRIE2: &FieldSpec = &super::REGISTERS[26].fields[19];
/// `CRCENDIE2`, bit 27.
pub const CRCENDIE2: &FieldSpec = &super::REGISTERS[26].fields[20];
/// `CRCRDERRIE2`, bit 28.
pub const CRCRDERRIE2: &FieldSpec = &super::REGISTERS[26].fields[21];
}
/// The fields of `SR2`.
pub mod sr2 {
use super::FieldSpec;
/// `BSY2`, bit 0.
pub const BSY2: &FieldSpec = &super::REGISTERS[27].fields[0];
/// `WBNE2`, bit 1.
pub const WBNE2: &FieldSpec = &super::REGISTERS[27].fields[1];
/// `QW2`, bit 2.
pub const QW2: &FieldSpec = &super::REGISTERS[27].fields[2];
/// `CRC_BUSY2`, bit 3.
pub const CRC_BUSY2: &FieldSpec = &super::REGISTERS[27].fields[3];
/// `EOP2`, bit 16.
pub const EOP2: &FieldSpec = &super::REGISTERS[27].fields[4];
/// `WRPERR2`, bit 17.
pub const WRPERR2: &FieldSpec = &super::REGISTERS[27].fields[5];
/// `PGSERR2`, bit 18.
pub const PGSERR2: &FieldSpec = &super::REGISTERS[27].fields[6];
/// `STRBERR2`, bit 19.
pub const STRBERR2: &FieldSpec = &super::REGISTERS[27].fields[7];
/// `INCERR2`, bit 21.
pub const INCERR2: &FieldSpec = &super::REGISTERS[27].fields[8];
/// `OPERR2`, bit 22.
pub const OPERR2: &FieldSpec = &super::REGISTERS[27].fields[9];
/// `RDPERR2`, bit 23.
pub const RDPERR2: &FieldSpec = &super::REGISTERS[27].fields[10];
/// `RDSERR2`, bit 24.
pub const RDSERR2: &FieldSpec = &super::REGISTERS[27].fields[11];
/// `SNECCERR2`, bit 25.
pub const SNECCERR2: &FieldSpec = &super::REGISTERS[27].fields[12];
/// `DBECCERR2`, bit 26.
pub const DBECCERR2: &FieldSpec = &super::REGISTERS[27].fields[13];
/// `CRCEND2`, bit 27.
pub const CRCEND2: &FieldSpec = &super::REGISTERS[27].fields[14];
}
/// The fields of `CCR2`.
pub mod ccr2 {
use super::FieldSpec;
/// `CLR_EOP2`, bit 16.
pub const CLR_EOP2: &FieldSpec = &super::REGISTERS[28].fields[0];
/// `CLR_WRPERR2`, bit 17.
pub const CLR_WRPERR2: &FieldSpec = &super::REGISTERS[28].fields[1];
/// `CLR_PGSERR2`, bit 18.
pub const CLR_PGSERR2: &FieldSpec = &super::REGISTERS[28].fields[2];
/// `CLR_STRBERR2`, bit 19.
pub const CLR_STRBERR2: &FieldSpec = &super::REGISTERS[28].fields[3];
/// `CLR_INCERR2`, bit 21.
pub const CLR_INCERR2: &FieldSpec = &super::REGISTERS[28].fields[4];
/// `CLR_OPERR2`, bit 22.
pub const CLR_OPERR2: &FieldSpec = &super::REGISTERS[28].fields[5];
/// `CLR_RDPERR2`, bit 23.
pub const CLR_RDPERR2: &FieldSpec = &super::REGISTERS[28].fields[6];
/// `CLR_RDSERR1`, bit 24.
pub const CLR_RDSERR1: &FieldSpec = &super::REGISTERS[28].fields[7];
/// `CLR_SNECCERR2`, bit 25.
pub const CLR_SNECCERR2: &FieldSpec = &super::REGISTERS[28].fields[8];
/// `CLR_DBECCERR1`, bit 26.
pub const CLR_DBECCERR1: &FieldSpec = &super::REGISTERS[28].fields[9];
/// `CLR_CRCEND2`, bit 27.
pub const CLR_CRCEND2: &FieldSpec = &super::REGISTERS[28].fields[10];
}
/// The fields of `OPTCR_`.
pub mod optcr_ {
use super::FieldSpec;
/// `OPTLOCK`, bit 0.
pub const OPTLOCK: &FieldSpec = &super::REGISTERS[29].fields[0];
/// `OPTSTART`, bit 1.
pub const OPTSTART: &FieldSpec = &super::REGISTERS[29].fields[1];
/// `MER`, bit 4.
pub const MER: &FieldSpec = &super::REGISTERS[29].fields[2];
/// `OPTCHANGEERRIE`, bit 30.
pub const OPTCHANGEERRIE: &FieldSpec = &super::REGISTERS[29].fields[3];
/// `SWAP_BANK`, bit 31.
pub const SWAP_BANK: &FieldSpec = &super::REGISTERS[29].fields[4];
}
/// The fields of `OPTSR_CUR_`.
pub mod optsr_cur_ {
use super::FieldSpec;
/// `OPT_BUSY`, bit 0.
pub const OPT_BUSY: &FieldSpec = &super::REGISTERS[30].fields[0];
/// `BOR_LEV`, bits 2..=3.
pub const BOR_LEV: &FieldSpec = &super::REGISTERS[30].fields[1];
/// `IWDG1_SW`, bit 4.
pub const IWDG1_SW: &FieldSpec = &super::REGISTERS[30].fields[2];
/// `NRST_STOP_D1`, bit 6.
pub const NRST_STOP_D1: &FieldSpec = &super::REGISTERS[30].fields[3];
/// `NRST_STBY_D1`, bit 7.
pub const NRST_STBY_D1: &FieldSpec = &super::REGISTERS[30].fields[4];
/// `RDP`, bits 8..=15.
pub const RDP: &FieldSpec = &super::REGISTERS[30].fields[5];
/// `IWDG_FZ_STOP`, bit 17.
pub const IWDG_FZ_STOP: &FieldSpec = &super::REGISTERS[30].fields[6];
/// `IWDG_FZ_SDBY`, bit 18.
pub const IWDG_FZ_SDBY: &FieldSpec = &super::REGISTERS[30].fields[7];
/// `ST_RAM_SIZE`, bits 19..=20.
pub const ST_RAM_SIZE: &FieldSpec = &super::REGISTERS[30].fields[8];
/// `SECURITY`, bit 21.
pub const SECURITY: &FieldSpec = &super::REGISTERS[30].fields[9];
/// `IO_HSLV`, bit 29.
pub const IO_HSLV: &FieldSpec = &super::REGISTERS[30].fields[10];
/// `OPTCHANGEERR`, bit 30.
pub const OPTCHANGEERR: &FieldSpec = &super::REGISTERS[30].fields[11];
/// `SWAP_BANK_OPT`, bit 31.
pub const SWAP_BANK_OPT: &FieldSpec = &super::REGISTERS[30].fields[12];
}
/// The fields of `OPTSR_PRG_`.
pub mod optsr_prg_ {
use super::FieldSpec;
/// `BOR_LEV`, bits 2..=3.
pub const BOR_LEV: &FieldSpec = &super::REGISTERS[31].fields[0];
/// `IWDG1_SW`, bit 4.
pub const IWDG1_SW: &FieldSpec = &super::REGISTERS[31].fields[1];
/// `nRST_STOP`, bit 6.
pub const NRST_STOP: &FieldSpec = &super::REGISTERS[31].fields[2];
/// `nRST_STDY`, bit 7.
pub const NRST_STDY: &FieldSpec = &super::REGISTERS[31].fields[3];
/// `RDP`, bits 8..=15.
pub const RDP: &FieldSpec = &super::REGISTERS[31].fields[4];
/// `FZ_IWDG_STOP`, bit 17.
pub const FZ_IWDG_STOP: &FieldSpec = &super::REGISTERS[31].fields[5];
/// `FZ_IWDG_SDBY`, bit 18.
pub const FZ_IWDG_SDBY: &FieldSpec = &super::REGISTERS[31].fields[6];
/// `ST_RAM_SIZE`, bits 19..=20.
pub const ST_RAM_SIZE: &FieldSpec = &super::REGISTERS[31].fields[7];
/// `SECURITY`, bit 21.
pub const SECURITY: &FieldSpec = &super::REGISTERS[31].fields[8];
/// `IO_HSLV`, bit 29.
pub const IO_HSLV: &FieldSpec = &super::REGISTERS[31].fields[9];
/// `SWAP_BANK_OPT`, bit 31.
pub const SWAP_BANK_OPT: &FieldSpec = &super::REGISTERS[31].fields[10];
}
/// The fields of `OPTCCR_`.
pub mod optccr_ {
use super::FieldSpec;
/// `CLR_OPTCHANGEERR`, bit 30.
pub const CLR_OPTCHANGEERR: &FieldSpec = &super::REGISTERS[32].fields[0];
}
/// The fields of `PRAR_CUR2`.
pub mod prar_cur2 {
use super::FieldSpec;
/// `PROT_AREA_START2`, bits 0..=11.
pub const PROT_AREA_START2: &FieldSpec = &super::REGISTERS[33].fields[0];
/// `PROT_AREA_END2`, bits 16..=27.
pub const PROT_AREA_END2: &FieldSpec = &super::REGISTERS[33].fields[1];
/// `DMEP2`, bit 31.
pub const DMEP2: &FieldSpec = &super::REGISTERS[33].fields[2];
}
/// The fields of `PRAR_PRG2`.
pub mod prar_prg2 {
use super::FieldSpec;
/// `PROT_AREA_START2`, bits 0..=11.
pub const PROT_AREA_START2: &FieldSpec = &super::REGISTERS[34].fields[0];
/// `PROT_AREA_END2`, bits 16..=27.
pub const PROT_AREA_END2: &FieldSpec = &super::REGISTERS[34].fields[1];
/// `DMEP2`, bit 31.
pub const DMEP2: &FieldSpec = &super::REGISTERS[34].fields[2];
}
/// The fields of `SCAR_CUR2`.
pub mod scar_cur2 {
use super::FieldSpec;
/// `SEC_AREA_START2`, bits 0..=11.
pub const SEC_AREA_START2: &FieldSpec = &super::REGISTERS[35].fields[0];
/// `SEC_AREA_END2`, bits 16..=27.
pub const SEC_AREA_END2: &FieldSpec = &super::REGISTERS[35].fields[1];
/// `DMES2`, bit 31.
pub const DMES2: &FieldSpec = &super::REGISTERS[35].fields[2];
}
/// The fields of `SCAR_PRG2`.
pub mod scar_prg2 {
use super::FieldSpec;
/// `SEC_AREA_START2`, bits 0..=11.
pub const SEC_AREA_START2: &FieldSpec = &super::REGISTERS[36].fields[0];
/// `SEC_AREA_END2`, bits 16..=27.
pub const SEC_AREA_END2: &FieldSpec = &super::REGISTERS[36].fields[1];
/// `DMES2`, bit 31.
pub const DMES2: &FieldSpec = &super::REGISTERS[36].fields[2];
}
/// The fields of `WPSN_CUR2R`.
pub mod wpsn_cur2r {
use super::FieldSpec;
/// `WRPSn2`, bits 0..=7.
pub const WRPSN2: &FieldSpec = &super::REGISTERS[37].fields[0];
}
/// The fields of `WPSN_PRG2R`.
pub mod wpsn_prg2r {
use super::FieldSpec;
/// `WRPSn2`, bits 0..=7.
pub const WRPSN2: &FieldSpec = &super::REGISTERS[38].fields[0];
}
/// The fields of `BOOT_CURR_`.
pub mod boot_curr_ {
use super::FieldSpec;
/// `BOOT_ADD0`, bits 0..=15.
pub const BOOT_ADD0: &FieldSpec = &super::REGISTERS[39].fields[0];
/// `BOOT_ADD1`, bits 16..=31.
pub const BOOT_ADD1: &FieldSpec = &super::REGISTERS[39].fields[1];
}
/// The fields of `BOOT_PRGR_`.
pub mod boot_prgr_ {
use super::FieldSpec;
/// `BOOT_ADD0`, bits 0..=15.
pub const BOOT_ADD0: &FieldSpec = &super::REGISTERS[40].fields[0];
/// `BOOT_ADD1`, bits 16..=31.
pub const BOOT_ADD1: &FieldSpec = &super::REGISTERS[40].fields[1];
}
/// The fields of `CRCCR2`.
pub mod crccr2 {
use super::FieldSpec;
/// `CRC_SECT`, bits 0..=2.
pub const CRC_SECT: &FieldSpec = &super::REGISTERS[41].fields[0];
/// `ALL_BANK`, bit 7.
pub const ALL_BANK: &FieldSpec = &super::REGISTERS[41].fields[1];
/// `CRC_BY_SECT`, bit 8.
pub const CRC_BY_SECT: &FieldSpec = &super::REGISTERS[41].fields[2];
/// `ADD_SECT`, bit 9.
pub const ADD_SECT: &FieldSpec = &super::REGISTERS[41].fields[3];
/// `CLEAN_SECT`, bit 10.
pub const CLEAN_SECT: &FieldSpec = &super::REGISTERS[41].fields[4];
/// `START_CRC`, bit 16.
pub const START_CRC: &FieldSpec = &super::REGISTERS[41].fields[5];
/// `CLEAN_CRC`, bit 17.
pub const CLEAN_CRC: &FieldSpec = &super::REGISTERS[41].fields[6];
/// `CRC_BURST`, bits 20..=21.
pub const CRC_BURST: &FieldSpec = &super::REGISTERS[41].fields[7];
}
/// The fields of `CRCSADD2R`.
pub mod crcsadd2r {
use super::FieldSpec;
/// `CRC_START_ADDR`, bits 2..=19.
pub const CRC_START_ADDR: &FieldSpec = &super::REGISTERS[42].fields[0];
}
/// The fields of `CRCEADD2R`.
pub mod crceadd2r {
use super::FieldSpec;
/// `CRC_END_ADDR`, bits 2..=19.
pub const CRC_END_ADDR: &FieldSpec = &super::REGISTERS[43].fields[0];
}
/// The fields of `CRCDATAR_`.
pub mod crcdatar_ {
use super::FieldSpec;
/// `CRC_DATA`, bits 0..=31.
pub const CRC_DATA: &FieldSpec = &super::REGISTERS[44].fields[0];
}
/// The fields of `ECC_FA2R`.
pub mod ecc_fa2r {
use super::FieldSpec;
/// `FAIL_ECC_ADDR2`, bits 0..=14.
pub const FAIL_ECC_ADDR2: &FieldSpec = &super::REGISTERS[45].fields[0];
}
/// The register table.
pub static REGISTERS: [RegisterSpec; 46] = [
RegisterSpec { name: "ACR", offset: 0x0, width: Width::W32, reset: 0x0000_0037, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LATENCY", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRHIGHFREQ", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "KEYR1", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "KEY1R", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "OPTKEYR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "OPTKEYR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CR1", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LOCK1", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PG1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SER1", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BER1", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PSIZE1", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FW1", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "START1", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SNB1", bit: 8, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRC_EN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "EOPIE1", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRPERRIE1", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PGSERRIE1", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "STRBERRIE1", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "INCERRIE1", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "OPERRIE1", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RDPERRIE1", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RDSERRIE1", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SNECCERR1", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBECCERRIE1", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRCENDIE1", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRCRDERRIE1", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "SR1", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BSY1", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WBNE1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "QW1", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRC_BUSY1", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "EOP1", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRPERR1", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PGSERR1", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "STRBERR1", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "INCERR1", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "OPERR1", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RDPERR1", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RDSERR1", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SNECCERR", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBECCERR1", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRCEND1", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRCRDERR1", bit: 28, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CCR1", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CLR_EOP1", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_WRPERR1", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_PGSERR1", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_STRBERR1", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_INCERR1", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_OPERR1", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_RDPERR1", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_RDSERR1", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_SNECCERR1", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_DBECCERR1", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_CRCEND1", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_CRCRDERR1", bit: 28, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "OPTCR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "OPTLOCK", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "OPTSTART", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MER", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "OPTCHANGEERRIE", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWAP_BANK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "OPTSR_CUR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "OPT_BUSY", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BOR_LEV", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "IWDG1_SW", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "NRST_STOP_D1", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "NRST_STBY_D1", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RDP", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "IWDG_FZ_STOP", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "IWDG_FZ_SDBY", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ST_RAM_SIZE", bit: 19, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SECURITY", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "IO_HSLV", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "OPTCHANGEERR", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWAP_BANK_OPT", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "OPTSR_PRG", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BOR_LEV", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "IWDG1_SW", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "NRST_STOP_D1", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "NRST_STBY_D1", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RDP", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "IWDG_FZ_STOP", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "IWDG_FZ_SDBY", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ST_RAM_SIZE", bit: 19, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SECURITY", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "IO_HSLV", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWAP_BANK_OPT", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "OPTCCR", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CLR_OPTCHANGEERR", bit: 30, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "PRAR_CUR1", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "PROT_AREA_START1", bit: 0, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PROT_AREA_END1", bit: 16, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMEP1", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "PRAR_PRG1", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "PROT_AREA_START1", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PROT_AREA_END1", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMEP1", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "SCAR_CUR1", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SEC_AREA_START1", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SEC_AREA_END1", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMES1", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "SCAR_PRG1", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SEC_AREA_START1", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SEC_AREA_END1", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMES1", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "WPSN_CUR1R", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "WRPSn1", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "WPSN_PRG1R", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "WRPSn1", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BOOT_CURR", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BOOT_ADD0", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BOOT_ADD1", bit: 16, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BOOT_PRGR", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BOOT_ADD0", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BOOT_ADD1", bit: 16, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CRCCR1", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CRC_SECT", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ALL_BANK", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRC_BY_SECT", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ADD_SECT", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLEAN_SECT", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "START_CRC", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLEAN_CRC", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRC_BURST", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CRCSADD1R", offset: 0x54, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CRC_START_ADDR", bit: 2, width: 18, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CRCEADD1R", offset: 0x58, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CRC_END_ADDR", bit: 2, width: 18, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CRCDATAR", offset: 0x5C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CRC_DATA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "ECC_FA1R", offset: 0x60, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "FAIL_ECC_ADDR1", bit: 0, width: 15, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "ACR_", offset: 0x100, width: Width::W32, reset: 0x0000_0037, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LATENCY", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRHIGHFREQ", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "KEYR2", offset: 0x104, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "KEYR2", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "OPTKEYR_", offset: 0x108, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "OPTKEYR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CR2", offset: 0x10C, width: Width::W32, reset: 0x0000_0031, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LOCK2", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PG2", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SER2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BER2", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PSIZE2", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FW2", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "START2", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SNB2", bit: 8, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPSS2", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRC_EN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "EOPIE2", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRPERRIE2", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PGSERRIE2", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "STRBERRIE2", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "INCERRIE2", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "OPERRIE2", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RDPERRIE2", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RDSERRIE2", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SNECCERRIE2", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBECCERRIE2", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRCENDIE2", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRCRDERRIE2", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "SR2", offset: 0x110, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BSY2", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WBNE2", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "QW2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRC_BUSY2", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "EOP2", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRPERR2", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PGSERR2", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "STRBERR2", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "INCERR2", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "OPERR2", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RDPERR2", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RDSERR2", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SNECCERR2", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DBECCERR2", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRCEND2", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CCR2", offset: 0x114, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CLR_EOP2", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_WRPERR2", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_PGSERR2", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_STRBERR2", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_INCERR2", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_OPERR2", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_RDPERR2", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_RDSERR1", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_SNECCERR2", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_DBECCERR1", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLR_CRCEND2", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "OPTCR_", offset: 0x118, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "OPTLOCK", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "OPTSTART", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MER", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "OPTCHANGEERRIE", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWAP_BANK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "OPTSR_CUR_", offset: 0x11C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "OPT_BUSY", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BOR_LEV", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "IWDG1_SW", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "NRST_STOP_D1", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "NRST_STBY_D1", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RDP", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "IWDG_FZ_STOP", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "IWDG_FZ_SDBY", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ST_RAM_SIZE", bit: 19, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SECURITY", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "IO_HSLV", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "OPTCHANGEERR", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWAP_BANK_OPT", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "OPTSR_PRG_", offset: 0x120, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BOR_LEV", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "IWDG1_SW", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "nRST_STOP", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "nRST_STDY", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RDP", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FZ_IWDG_STOP", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FZ_IWDG_SDBY", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ST_RAM_SIZE", bit: 19, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SECURITY", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "IO_HSLV", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWAP_BANK_OPT", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "OPTCCR_", offset: 0x124, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CLR_OPTCHANGEERR", bit: 30, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "PRAR_CUR2", offset: 0x128, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "PROT_AREA_START2", bit: 0, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PROT_AREA_END2", bit: 16, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMEP2", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "PRAR_PRG2", offset: 0x12C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "PROT_AREA_START2", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PROT_AREA_END2", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMEP2", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "SCAR_CUR2", offset: 0x130, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SEC_AREA_START2", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SEC_AREA_END2", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMES2", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "SCAR_PRG2", offset: 0x134, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SEC_AREA_START2", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SEC_AREA_END2", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMES2", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "WPSN_CUR2R", offset: 0x138, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "WRPSn2", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "WPSN_PRG2R", offset: 0x13C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "WRPSn2", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BOOT_CURR_", offset: 0x140, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BOOT_ADD0", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BOOT_ADD1", bit: 16, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BOOT_PRGR_", offset: 0x144, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BOOT_ADD0", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BOOT_ADD1", bit: 16, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CRCCR2", offset: 0x150, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CRC_SECT", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ALL_BANK", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRC_BY_SECT", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ADD_SECT", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLEAN_SECT", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "START_CRC", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLEAN_CRC", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRC_BURST", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CRCSADD2R", offset: 0x154, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CRC_START_ADDR", bit: 2, width: 18, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CRCEADD2R", offset: 0x158, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CRC_END_ADDR", bit: 2, width: 18, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CRCDATAR_", offset: 0x15C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CRC_DATA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "ECC_FA2R", offset: 0x160, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "FAIL_ECC_ADDR2", bit: 0, width: 15, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
];