rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `CAN_CCU` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CREL` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Crel = 0,
    /// `CCFG` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Ccfg = 1,
    /// `CSTAT` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Cstat = 2,
    /// `CWD` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Cwd = 3,
    /// `IR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Ir = 4,
    /// `IE` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Ie = 5,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 6] = [Self::Crel, Self::Ccfg, Self::Cstat, Self::Cwd, Self::Ir, Self::Ie];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CREL`.
pub mod crel {
    use super::FieldSpec;
    /// `DAY`, bits 0..=7.
    pub const DAY: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `MON`, bits 8..=15.
    pub const MON: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `YEAR`, bits 16..=19.
    pub const YEAR: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `SUBSTEP`, bits 20..=23.
    pub const SUBSTEP: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `STEP`, bits 24..=27.
    pub const STEP: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `REL`, bits 28..=31.
    pub const REL: &FieldSpec = &super::REGISTERS[0].fields[5];
}

/// The fields of `CCFG`.
pub mod ccfg {
    use super::FieldSpec;
    /// `TQBT`, bits 0..=4.
    pub const TQBT: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `BCC`, bit 6.
    pub const BCC: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `CFL`, bit 7.
    pub const CFL: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `OCPM`, bits 8..=15.
    pub const OCPM: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `CDIV`, bits 16..=19.
    pub const CDIV: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `SWR`, bit 31.
    pub const SWR: &FieldSpec = &super::REGISTERS[1].fields[5];
}

/// The fields of `CSTAT`.
pub mod cstat {
    use super::FieldSpec;
    /// `OCPC`, bits 0..=17.
    pub const OCPC: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `TQC`, bits 18..=28.
    pub const TQC: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `CALS`, bits 30..=31.
    pub const CALS: &FieldSpec = &super::REGISTERS[2].fields[2];
}

/// The fields of `CWD`.
pub mod cwd {
    use super::FieldSpec;
    /// `WDC`, bits 0..=15.
    pub const WDC: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `WDV`, bits 16..=31.
    pub const WDV: &FieldSpec = &super::REGISTERS[3].fields[1];
}

/// The fields of `IR`.
pub mod ir {
    use super::FieldSpec;
    /// `CWE`, bit 0.
    pub const CWE: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `CSC`, bit 1.
    pub const CSC: &FieldSpec = &super::REGISTERS[4].fields[1];
}

/// The fields of `IE`.
pub mod ie {
    use super::FieldSpec;
    /// `CWEE`, bit 0.
    pub const CWEE: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `CSCE`, bit 1.
    pub const CSCE: &FieldSpec = &super::REGISTERS[5].fields[1];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 6] = [
    RegisterSpec { name: "CREL", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DAY", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MON", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "YEAR", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SUBSTEP", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STEP", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REL", bit: 28, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCFG", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TQBT", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BCC", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CFL", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OCPM", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CDIV", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWR", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CSTAT", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OCPC", bit: 0, width: 18, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TQC", bit: 18, width: 11, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CALS", bit: 30, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CWD", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WDC", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WDV", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CWE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSC", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IE", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CWEE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSCE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];