rigless 0.3.0

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `EXTI` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `RTSR1` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Rtsr1 = 0,
    /// `FTSR1` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Ftsr1 = 1,
    /// `SWIER1` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Swier1 = 2,
    /// `D3PMR1` at offset `0xC`, resets to `0x0000_0000`, read-write.
    D3pmr1 = 3,
    /// `D3PCR1L` at offset `0x10`, resets to `0x0000_0000`, read-write.
    D3pcr1l = 4,
    /// `D3PCR1H` at offset `0x14`, resets to `0x0000_0000`, read-write.
    D3pcr1h = 5,
    /// `RTSR2` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Rtsr2 = 6,
    /// `FTSR2` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Ftsr2 = 7,
    /// `SWIER2` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Swier2 = 8,
    /// `D3PMR2` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    D3pmr2 = 9,
    /// `D3PCR2L` at offset `0x30`, resets to `0x0000_0000`, read-write.
    D3pcr2l = 10,
    /// `D3PCR2H` at offset `0x34`, resets to `0x0000_0000`, read-write.
    D3pcr2h = 11,
    /// `RTSR3` at offset `0x40`, resets to `0x0000_0000`, read-write.
    Rtsr3 = 12,
    /// `FTSR3` at offset `0x44`, resets to `0x0000_0000`, read-write.
    Ftsr3 = 13,
    /// `SWIER3` at offset `0x48`, resets to `0x0000_0000`, read-write.
    Swier3 = 14,
    /// `D3PMR3` at offset `0x4C`, resets to `0x0000_0000`, read-write.
    D3pmr3 = 15,
    /// `D3PCR3H` at offset `0x54`, resets to `0x0000_0000`, read-write.
    D3pcr3h = 16,
    /// `CPUIMR1` at offset `0x80`, resets to `0xFFC0_0000`, read-write.
    Cpuimr1 = 17,
    /// `CPUEMR1` at offset `0x84`, resets to `0x0000_0000`, read-write.
    Cpuemr1 = 18,
    /// `CPUPR1` at offset `0x88`, resets to `0x0000_0000`, read-write.
    Cpupr1 = 19,
    /// `CPUIMR2` at offset `0x90`, resets to `0x0000_0000`, read-write.
    Cpuimr2 = 20,
    /// `CPUEMR2` at offset `0x94`, resets to `0x0000_0000`, read-write.
    Cpuemr2 = 21,
    /// `CPUPR2` at offset `0x98`, resets to `0x0000_0000`, read-only.
    Cpupr2 = 22,
    /// `CPUIMR3` at offset `0xA0`, resets to `0x0000_0000`, read-only.
    Cpuimr3 = 23,
    /// `CPUEMR3` at offset `0xA4`, resets to `0x0000_0000`, read-only.
    Cpuemr3 = 24,
    /// `CPUPR3` at offset `0xA8`, resets to `0x0000_0000`, read-only.
    Cpupr3 = 25,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 26] = [Self::Rtsr1, Self::Ftsr1, Self::Swier1, Self::D3pmr1, Self::D3pcr1l, Self::D3pcr1h, Self::Rtsr2, Self::Ftsr2, Self::Swier2, Self::D3pmr2, Self::D3pcr2l, Self::D3pcr2h, Self::Rtsr3, Self::Ftsr3, Self::Swier3, Self::D3pmr3, Self::D3pcr3h, Self::Cpuimr1, Self::Cpuemr1, Self::Cpupr1, Self::Cpuimr2, Self::Cpuemr2, Self::Cpupr2, Self::Cpuimr3, Self::Cpuemr3, Self::Cpupr3];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `RTSR1`.
pub mod rtsr1 {
    use super::FieldSpec;
    /// `TR0`, bit 0.
    pub const TR0: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `TR1`, bit 1.
    pub const TR1: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `TR2`, bit 2.
    pub const TR2: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `TR3`, bit 3.
    pub const TR3: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `TR4`, bit 4.
    pub const TR4: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `TR5`, bit 5.
    pub const TR5: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `TR6`, bit 6.
    pub const TR6: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `TR7`, bit 7.
    pub const TR7: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `TR8`, bit 8.
    pub const TR8: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `TR9`, bit 9.
    pub const TR9: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `TR10`, bit 10.
    pub const TR10: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `TR11`, bit 11.
    pub const TR11: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `TR12`, bit 12.
    pub const TR12: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `TR13`, bit 13.
    pub const TR13: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `TR14`, bit 14.
    pub const TR14: &FieldSpec = &super::REGISTERS[0].fields[14];
    /// `TR15`, bit 15.
    pub const TR15: &FieldSpec = &super::REGISTERS[0].fields[15];
    /// `TR16`, bit 16.
    pub const TR16: &FieldSpec = &super::REGISTERS[0].fields[16];
    /// `TR17`, bit 17.
    pub const TR17: &FieldSpec = &super::REGISTERS[0].fields[17];
    /// `TR18`, bit 18.
    pub const TR18: &FieldSpec = &super::REGISTERS[0].fields[18];
    /// `TR19`, bit 19.
    pub const TR19: &FieldSpec = &super::REGISTERS[0].fields[19];
    /// `TR20`, bit 20.
    pub const TR20: &FieldSpec = &super::REGISTERS[0].fields[20];
    /// `TR21`, bit 21.
    pub const TR21: &FieldSpec = &super::REGISTERS[0].fields[21];
}

/// The fields of `FTSR1`.
pub mod ftsr1 {
    use super::FieldSpec;
    /// `TR0`, bit 0.
    pub const TR0: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `TR1`, bit 1.
    pub const TR1: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `TR2`, bit 2.
    pub const TR2: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `TR3`, bit 3.
    pub const TR3: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `TR4`, bit 4.
    pub const TR4: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `TR5`, bit 5.
    pub const TR5: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `TR6`, bit 6.
    pub const TR6: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `TR7`, bit 7.
    pub const TR7: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `TR8`, bit 8.
    pub const TR8: &FieldSpec = &super::REGISTERS[1].fields[8];
    /// `TR9`, bit 9.
    pub const TR9: &FieldSpec = &super::REGISTERS[1].fields[9];
    /// `TR10`, bit 10.
    pub const TR10: &FieldSpec = &super::REGISTERS[1].fields[10];
    /// `TR11`, bit 11.
    pub const TR11: &FieldSpec = &super::REGISTERS[1].fields[11];
    /// `TR12`, bit 12.
    pub const TR12: &FieldSpec = &super::REGISTERS[1].fields[12];
    /// `TR13`, bit 13.
    pub const TR13: &FieldSpec = &super::REGISTERS[1].fields[13];
    /// `TR14`, bit 14.
    pub const TR14: &FieldSpec = &super::REGISTERS[1].fields[14];
    /// `TR15`, bit 15.
    pub const TR15: &FieldSpec = &super::REGISTERS[1].fields[15];
    /// `TR16`, bit 16.
    pub const TR16: &FieldSpec = &super::REGISTERS[1].fields[16];
    /// `TR17`, bit 17.
    pub const TR17: &FieldSpec = &super::REGISTERS[1].fields[17];
    /// `TR18`, bit 18.
    pub const TR18: &FieldSpec = &super::REGISTERS[1].fields[18];
    /// `TR19`, bit 19.
    pub const TR19: &FieldSpec = &super::REGISTERS[1].fields[19];
    /// `TR20`, bit 20.
    pub const TR20: &FieldSpec = &super::REGISTERS[1].fields[20];
    /// `TR21`, bit 21.
    pub const TR21: &FieldSpec = &super::REGISTERS[1].fields[21];
}

/// The fields of `SWIER1`.
pub mod swier1 {
    use super::FieldSpec;
    /// `SWIER0`, bit 0.
    pub const SWIER0: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `SWIER1`, bit 1.
    pub const SWIER1: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `SWIER2`, bit 2.
    pub const SWIER2: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `SWIER3`, bit 3.
    pub const SWIER3: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `SWIER4`, bit 4.
    pub const SWIER4: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `SWIER5`, bit 5.
    pub const SWIER5: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `SWIER6`, bit 6.
    pub const SWIER6: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `SWIER7`, bit 7.
    pub const SWIER7: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `SWIER8`, bit 8.
    pub const SWIER8: &FieldSpec = &super::REGISTERS[2].fields[8];
    /// `SWIER9`, bit 9.
    pub const SWIER9: &FieldSpec = &super::REGISTERS[2].fields[9];
    /// `SWIER10`, bit 10.
    pub const SWIER10: &FieldSpec = &super::REGISTERS[2].fields[10];
    /// `SWIER11`, bit 11.
    pub const SWIER11: &FieldSpec = &super::REGISTERS[2].fields[11];
    /// `SWIER12`, bit 12.
    pub const SWIER12: &FieldSpec = &super::REGISTERS[2].fields[12];
    /// `SWIER13`, bit 13.
    pub const SWIER13: &FieldSpec = &super::REGISTERS[2].fields[13];
    /// `SWIER14`, bit 14.
    pub const SWIER14: &FieldSpec = &super::REGISTERS[2].fields[14];
    /// `SWIER15`, bit 15.
    pub const SWIER15: &FieldSpec = &super::REGISTERS[2].fields[15];
    /// `SWIER16`, bit 16.
    pub const SWIER16: &FieldSpec = &super::REGISTERS[2].fields[16];
    /// `SWIER17`, bit 17.
    pub const SWIER17: &FieldSpec = &super::REGISTERS[2].fields[17];
    /// `SWIER18`, bit 18.
    pub const SWIER18: &FieldSpec = &super::REGISTERS[2].fields[18];
    /// `SWIER19`, bit 19.
    pub const SWIER19: &FieldSpec = &super::REGISTERS[2].fields[19];
    /// `SWIER20`, bit 20.
    pub const SWIER20: &FieldSpec = &super::REGISTERS[2].fields[20];
    /// `SWIER21`, bit 21.
    pub const SWIER21: &FieldSpec = &super::REGISTERS[2].fields[21];
}

/// The fields of `D3PMR1`.
pub mod d3pmr1 {
    use super::FieldSpec;
    /// `MR0`, bit 0.
    pub const MR0: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `MR1`, bit 1.
    pub const MR1: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `MR2`, bit 2.
    pub const MR2: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `MR3`, bit 3.
    pub const MR3: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `MR4`, bit 4.
    pub const MR4: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `MR5`, bit 5.
    pub const MR5: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `MR6`, bit 6.
    pub const MR6: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `MR7`, bit 7.
    pub const MR7: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `MR8`, bit 8.
    pub const MR8: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `MR9`, bit 9.
    pub const MR9: &FieldSpec = &super::REGISTERS[3].fields[9];
    /// `MR10`, bit 10.
    pub const MR10: &FieldSpec = &super::REGISTERS[3].fields[10];
    /// `MR11`, bit 11.
    pub const MR11: &FieldSpec = &super::REGISTERS[3].fields[11];
    /// `MR12`, bit 12.
    pub const MR12: &FieldSpec = &super::REGISTERS[3].fields[12];
    /// `MR13`, bit 13.
    pub const MR13: &FieldSpec = &super::REGISTERS[3].fields[13];
    /// `MR14`, bit 14.
    pub const MR14: &FieldSpec = &super::REGISTERS[3].fields[14];
    /// `MR15`, bit 15.
    pub const MR15: &FieldSpec = &super::REGISTERS[3].fields[15];
    /// `MR19`, bit 19.
    pub const MR19: &FieldSpec = &super::REGISTERS[3].fields[16];
    /// `MR20`, bit 20.
    pub const MR20: &FieldSpec = &super::REGISTERS[3].fields[17];
    /// `MR21`, bit 21.
    pub const MR21: &FieldSpec = &super::REGISTERS[3].fields[18];
    /// `MR25`, bit 25.
    pub const MR25: &FieldSpec = &super::REGISTERS[3].fields[19];
}

/// The fields of `D3PCR1L`.
pub mod d3pcr1l {
    use super::FieldSpec;
    /// `PCS0`, bits 0..=1.
    pub const PCS0: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `PCS1`, bits 2..=3.
    pub const PCS1: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `PCS2`, bits 4..=5.
    pub const PCS2: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `PCS3`, bits 6..=7.
    pub const PCS3: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `PCS4`, bits 8..=9.
    pub const PCS4: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `PCS5`, bits 10..=11.
    pub const PCS5: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `PCS6`, bits 12..=13.
    pub const PCS6: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `PCS7`, bits 14..=15.
    pub const PCS7: &FieldSpec = &super::REGISTERS[4].fields[7];
    /// `PCS8`, bits 16..=17.
    pub const PCS8: &FieldSpec = &super::REGISTERS[4].fields[8];
    /// `PCS9`, bits 18..=19.
    pub const PCS9: &FieldSpec = &super::REGISTERS[4].fields[9];
    /// `PCS10`, bits 20..=21.
    pub const PCS10: &FieldSpec = &super::REGISTERS[4].fields[10];
    /// `PCS11`, bits 22..=23.
    pub const PCS11: &FieldSpec = &super::REGISTERS[4].fields[11];
    /// `PCS12`, bits 24..=25.
    pub const PCS12: &FieldSpec = &super::REGISTERS[4].fields[12];
    /// `PCS13`, bits 26..=27.
    pub const PCS13: &FieldSpec = &super::REGISTERS[4].fields[13];
    /// `PCS14`, bits 28..=29.
    pub const PCS14: &FieldSpec = &super::REGISTERS[4].fields[14];
    /// `PCS15`, bits 30..=31.
    pub const PCS15: &FieldSpec = &super::REGISTERS[4].fields[15];
}

/// The fields of `D3PCR1H`.
pub mod d3pcr1h {
    use super::FieldSpec;
    /// `PCS19`, bits 6..=7.
    pub const PCS19: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `PCS20`, bits 8..=9.
    pub const PCS20: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `PCS21`, bits 10..=11.
    pub const PCS21: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `PCS25`, bits 18..=19.
    pub const PCS25: &FieldSpec = &super::REGISTERS[5].fields[3];
}

/// The fields of `RTSR2`.
pub mod rtsr2 {
    use super::FieldSpec;
    /// `TR49`, bit 17.
    pub const TR49: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `TR51`, bit 19.
    pub const TR51: &FieldSpec = &super::REGISTERS[6].fields[1];
}

/// The fields of `FTSR2`.
pub mod ftsr2 {
    use super::FieldSpec;
    /// `TR49`, bit 17.
    pub const TR49: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `TR51`, bit 19.
    pub const TR51: &FieldSpec = &super::REGISTERS[7].fields[1];
}

/// The fields of `SWIER2`.
pub mod swier2 {
    use super::FieldSpec;
    /// `SWIER49`, bit 17.
    pub const SWIER49: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `SWIER51`, bit 19.
    pub const SWIER51: &FieldSpec = &super::REGISTERS[8].fields[1];
}

/// The fields of `D3PMR2`.
pub mod d3pmr2 {
    use super::FieldSpec;
    /// `MR34`, bit 2.
    pub const MR34: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `MR35`, bit 3.
    pub const MR35: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `MR41`, bit 9.
    pub const MR41: &FieldSpec = &super::REGISTERS[9].fields[2];
    /// `MR48`, bit 16.
    pub const MR48: &FieldSpec = &super::REGISTERS[9].fields[3];
    /// `MR49`, bit 17.
    pub const MR49: &FieldSpec = &super::REGISTERS[9].fields[4];
    /// `MR50`, bit 18.
    pub const MR50: &FieldSpec = &super::REGISTERS[9].fields[5];
    /// `MR51`, bit 19.
    pub const MR51: &FieldSpec = &super::REGISTERS[9].fields[6];
    /// `MR52`, bit 20.
    pub const MR52: &FieldSpec = &super::REGISTERS[9].fields[7];
    /// `MR53`, bit 21.
    pub const MR53: &FieldSpec = &super::REGISTERS[9].fields[8];
}

/// The fields of `D3PCR2L`.
pub mod d3pcr2l {
    use super::FieldSpec;
    /// `PCS34`, bits 4..=5.
    pub const PCS34: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `PCS35`, bits 6..=7.
    pub const PCS35: &FieldSpec = &super::REGISTERS[10].fields[1];
    /// `PCS41`, bits 18..=19.
    pub const PCS41: &FieldSpec = &super::REGISTERS[10].fields[2];
}

/// The fields of `D3PCR2H`.
pub mod d3pcr2h {
    use super::FieldSpec;
    /// `PCS48`, bits 0..=1.
    pub const PCS48: &FieldSpec = &super::REGISTERS[11].fields[0];
    /// `PCS49`, bits 2..=3.
    pub const PCS49: &FieldSpec = &super::REGISTERS[11].fields[1];
    /// `PCS50`, bits 4..=5.
    pub const PCS50: &FieldSpec = &super::REGISTERS[11].fields[2];
    /// `PCS51`, bits 6..=7.
    pub const PCS51: &FieldSpec = &super::REGISTERS[11].fields[3];
    /// `PCS52`, bits 8..=9.
    pub const PCS52: &FieldSpec = &super::REGISTERS[11].fields[4];
    /// `PCS53`, bits 10..=11.
    pub const PCS53: &FieldSpec = &super::REGISTERS[11].fields[5];
}

/// The fields of `RTSR3`.
pub mod rtsr3 {
    use super::FieldSpec;
    /// `TR82`, bit 18.
    pub const TR82: &FieldSpec = &super::REGISTERS[12].fields[0];
    /// `TR84`, bit 20.
    pub const TR84: &FieldSpec = &super::REGISTERS[12].fields[1];
    /// `TR85`, bit 21.
    pub const TR85: &FieldSpec = &super::REGISTERS[12].fields[2];
    /// `TR86`, bit 22.
    pub const TR86: &FieldSpec = &super::REGISTERS[12].fields[3];
}

/// The fields of `FTSR3`.
pub mod ftsr3 {
    use super::FieldSpec;
    /// `TR82`, bit 18.
    pub const TR82: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `TR84`, bit 20.
    pub const TR84: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `TR85`, bit 21.
    pub const TR85: &FieldSpec = &super::REGISTERS[13].fields[2];
    /// `TR86`, bit 22.
    pub const TR86: &FieldSpec = &super::REGISTERS[13].fields[3];
}

/// The fields of `SWIER3`.
pub mod swier3 {
    use super::FieldSpec;
    /// `SWIER82`, bit 18.
    pub const SWIER82: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `SWIER84`, bit 20.
    pub const SWIER84: &FieldSpec = &super::REGISTERS[14].fields[1];
    /// `SWIER85`, bit 21.
    pub const SWIER85: &FieldSpec = &super::REGISTERS[14].fields[2];
    /// `SWIER86`, bit 22.
    pub const SWIER86: &FieldSpec = &super::REGISTERS[14].fields[3];
}

/// The fields of `D3PMR3`.
pub mod d3pmr3 {
    use super::FieldSpec;
    /// `MR88`, bit 24.
    pub const MR88: &FieldSpec = &super::REGISTERS[15].fields[0];
}

/// The fields of `D3PCR3H`.
pub mod d3pcr3h {
    use super::FieldSpec;
    /// `PCS88`, bits 18..=19.
    pub const PCS88: &FieldSpec = &super::REGISTERS[16].fields[0];
}

/// The fields of `CPUIMR1`.
pub mod cpuimr1 {
    use super::FieldSpec;
    /// `MR0`, bit 0.
    pub const MR0: &FieldSpec = &super::REGISTERS[17].fields[0];
    /// `MR1`, bit 1.
    pub const MR1: &FieldSpec = &super::REGISTERS[17].fields[1];
    /// `MR2`, bit 2.
    pub const MR2: &FieldSpec = &super::REGISTERS[17].fields[2];
    /// `MR3`, bit 3.
    pub const MR3: &FieldSpec = &super::REGISTERS[17].fields[3];
    /// `MR4`, bit 4.
    pub const MR4: &FieldSpec = &super::REGISTERS[17].fields[4];
    /// `MR5`, bit 5.
    pub const MR5: &FieldSpec = &super::REGISTERS[17].fields[5];
    /// `MR6`, bit 6.
    pub const MR6: &FieldSpec = &super::REGISTERS[17].fields[6];
    /// `MR7`, bit 7.
    pub const MR7: &FieldSpec = &super::REGISTERS[17].fields[7];
    /// `MR8`, bit 8.
    pub const MR8: &FieldSpec = &super::REGISTERS[17].fields[8];
    /// `MR9`, bit 9.
    pub const MR9: &FieldSpec = &super::REGISTERS[17].fields[9];
    /// `MR10`, bit 10.
    pub const MR10: &FieldSpec = &super::REGISTERS[17].fields[10];
    /// `MR11`, bit 11.
    pub const MR11: &FieldSpec = &super::REGISTERS[17].fields[11];
    /// `MR12`, bit 12.
    pub const MR12: &FieldSpec = &super::REGISTERS[17].fields[12];
    /// `MR13`, bit 13.
    pub const MR13: &FieldSpec = &super::REGISTERS[17].fields[13];
    /// `MR14`, bit 14.
    pub const MR14: &FieldSpec = &super::REGISTERS[17].fields[14];
    /// `MR15`, bit 15.
    pub const MR15: &FieldSpec = &super::REGISTERS[17].fields[15];
    /// `MR16`, bit 16.
    pub const MR16: &FieldSpec = &super::REGISTERS[17].fields[16];
    /// `MR17`, bit 17.
    pub const MR17: &FieldSpec = &super::REGISTERS[17].fields[17];
    /// `MR18`, bit 18.
    pub const MR18: &FieldSpec = &super::REGISTERS[17].fields[18];
    /// `MR19`, bit 19.
    pub const MR19: &FieldSpec = &super::REGISTERS[17].fields[19];
    /// `MR20`, bit 20.
    pub const MR20: &FieldSpec = &super::REGISTERS[17].fields[20];
    /// `MR21`, bit 21.
    pub const MR21: &FieldSpec = &super::REGISTERS[17].fields[21];
    /// `MR22`, bit 22.
    pub const MR22: &FieldSpec = &super::REGISTERS[17].fields[22];
    /// `MR23`, bit 23.
    pub const MR23: &FieldSpec = &super::REGISTERS[17].fields[23];
    /// `MR24`, bit 24.
    pub const MR24: &FieldSpec = &super::REGISTERS[17].fields[24];
    /// `MR25`, bit 25.
    pub const MR25: &FieldSpec = &super::REGISTERS[17].fields[25];
    /// `MR26`, bit 26.
    pub const MR26: &FieldSpec = &super::REGISTERS[17].fields[26];
    /// `MR27`, bit 27.
    pub const MR27: &FieldSpec = &super::REGISTERS[17].fields[27];
    /// `MR28`, bit 28.
    pub const MR28: &FieldSpec = &super::REGISTERS[17].fields[28];
    /// `MR29`, bit 29.
    pub const MR29: &FieldSpec = &super::REGISTERS[17].fields[29];
    /// `MR30`, bit 30.
    pub const MR30: &FieldSpec = &super::REGISTERS[17].fields[30];
    /// `MR31`, bit 31.
    pub const MR31: &FieldSpec = &super::REGISTERS[17].fields[31];
}

/// The fields of `CPUEMR1`.
pub mod cpuemr1 {
    use super::FieldSpec;
    /// `MR0`, bit 0.
    pub const MR0: &FieldSpec = &super::REGISTERS[18].fields[0];
    /// `MR1`, bit 1.
    pub const MR1: &FieldSpec = &super::REGISTERS[18].fields[1];
    /// `MR2`, bit 2.
    pub const MR2: &FieldSpec = &super::REGISTERS[18].fields[2];
    /// `MR3`, bit 3.
    pub const MR3: &FieldSpec = &super::REGISTERS[18].fields[3];
    /// `MR4`, bit 4.
    pub const MR4: &FieldSpec = &super::REGISTERS[18].fields[4];
    /// `MR5`, bit 5.
    pub const MR5: &FieldSpec = &super::REGISTERS[18].fields[5];
    /// `MR6`, bit 6.
    pub const MR6: &FieldSpec = &super::REGISTERS[18].fields[6];
    /// `MR7`, bit 7.
    pub const MR7: &FieldSpec = &super::REGISTERS[18].fields[7];
    /// `MR8`, bit 8.
    pub const MR8: &FieldSpec = &super::REGISTERS[18].fields[8];
    /// `MR9`, bit 9.
    pub const MR9: &FieldSpec = &super::REGISTERS[18].fields[9];
    /// `MR10`, bit 10.
    pub const MR10: &FieldSpec = &super::REGISTERS[18].fields[10];
    /// `MR11`, bit 11.
    pub const MR11: &FieldSpec = &super::REGISTERS[18].fields[11];
    /// `MR12`, bit 12.
    pub const MR12: &FieldSpec = &super::REGISTERS[18].fields[12];
    /// `MR13`, bit 13.
    pub const MR13: &FieldSpec = &super::REGISTERS[18].fields[13];
    /// `MR14`, bit 14.
    pub const MR14: &FieldSpec = &super::REGISTERS[18].fields[14];
    /// `MR15`, bit 15.
    pub const MR15: &FieldSpec = &super::REGISTERS[18].fields[15];
    /// `MR16`, bit 16.
    pub const MR16: &FieldSpec = &super::REGISTERS[18].fields[16];
    /// `MR17`, bit 17.
    pub const MR17: &FieldSpec = &super::REGISTERS[18].fields[17];
    /// `MR18`, bit 18.
    pub const MR18: &FieldSpec = &super::REGISTERS[18].fields[18];
    /// `MR19`, bit 19.
    pub const MR19: &FieldSpec = &super::REGISTERS[18].fields[19];
    /// `MR20`, bit 20.
    pub const MR20: &FieldSpec = &super::REGISTERS[18].fields[20];
    /// `MR21`, bit 21.
    pub const MR21: &FieldSpec = &super::REGISTERS[18].fields[21];
    /// `MR22`, bit 22.
    pub const MR22: &FieldSpec = &super::REGISTERS[18].fields[22];
    /// `MR23`, bit 23.
    pub const MR23: &FieldSpec = &super::REGISTERS[18].fields[23];
    /// `MR24`, bit 24.
    pub const MR24: &FieldSpec = &super::REGISTERS[18].fields[24];
    /// `MR25`, bit 25.
    pub const MR25: &FieldSpec = &super::REGISTERS[18].fields[25];
    /// `MR26`, bit 26.
    pub const MR26: &FieldSpec = &super::REGISTERS[18].fields[26];
    /// `MR27`, bit 27.
    pub const MR27: &FieldSpec = &super::REGISTERS[18].fields[27];
    /// `MR28`, bit 28.
    pub const MR28: &FieldSpec = &super::REGISTERS[18].fields[28];
    /// `MR29`, bit 29.
    pub const MR29: &FieldSpec = &super::REGISTERS[18].fields[29];
    /// `MR30`, bit 30.
    pub const MR30: &FieldSpec = &super::REGISTERS[18].fields[30];
    /// `MR31`, bit 31.
    pub const MR31: &FieldSpec = &super::REGISTERS[18].fields[31];
}

/// The fields of `CPUPR1`.
pub mod cpupr1 {
    use super::FieldSpec;
    /// `PR0`, bit 0.
    pub const PR0: &FieldSpec = &super::REGISTERS[19].fields[0];
    /// `PR1`, bit 1.
    pub const PR1: &FieldSpec = &super::REGISTERS[19].fields[1];
    /// `PR2`, bit 2.
    pub const PR2: &FieldSpec = &super::REGISTERS[19].fields[2];
    /// `PR3`, bit 3.
    pub const PR3: &FieldSpec = &super::REGISTERS[19].fields[3];
    /// `PR4`, bit 4.
    pub const PR4: &FieldSpec = &super::REGISTERS[19].fields[4];
    /// `PR5`, bit 5.
    pub const PR5: &FieldSpec = &super::REGISTERS[19].fields[5];
    /// `PR6`, bit 6.
    pub const PR6: &FieldSpec = &super::REGISTERS[19].fields[6];
    /// `PR7`, bit 7.
    pub const PR7: &FieldSpec = &super::REGISTERS[19].fields[7];
    /// `PR8`, bit 8.
    pub const PR8: &FieldSpec = &super::REGISTERS[19].fields[8];
    /// `PR9`, bit 9.
    pub const PR9: &FieldSpec = &super::REGISTERS[19].fields[9];
    /// `PR10`, bit 10.
    pub const PR10: &FieldSpec = &super::REGISTERS[19].fields[10];
    /// `PR11`, bit 11.
    pub const PR11: &FieldSpec = &super::REGISTERS[19].fields[11];
    /// `PR12`, bit 12.
    pub const PR12: &FieldSpec = &super::REGISTERS[19].fields[12];
    /// `PR13`, bit 13.
    pub const PR13: &FieldSpec = &super::REGISTERS[19].fields[13];
    /// `PR14`, bit 14.
    pub const PR14: &FieldSpec = &super::REGISTERS[19].fields[14];
    /// `PR15`, bit 15.
    pub const PR15: &FieldSpec = &super::REGISTERS[19].fields[15];
    /// `PR16`, bit 16.
    pub const PR16: &FieldSpec = &super::REGISTERS[19].fields[16];
    /// `PR17`, bit 17.
    pub const PR17: &FieldSpec = &super::REGISTERS[19].fields[17];
    /// `PR18`, bit 18.
    pub const PR18: &FieldSpec = &super::REGISTERS[19].fields[18];
    /// `PR19`, bit 19.
    pub const PR19: &FieldSpec = &super::REGISTERS[19].fields[19];
    /// `PR20`, bit 20.
    pub const PR20: &FieldSpec = &super::REGISTERS[19].fields[20];
    /// `PR21`, bit 21.
    pub const PR21: &FieldSpec = &super::REGISTERS[19].fields[21];
}

/// The fields of `CPUIMR2`.
pub mod cpuimr2 {
    use super::FieldSpec;
    /// `MR0`, bit 0.
    pub const MR0: &FieldSpec = &super::REGISTERS[20].fields[0];
    /// `MR1`, bit 1.
    pub const MR1: &FieldSpec = &super::REGISTERS[20].fields[1];
    /// `MR2`, bit 2.
    pub const MR2: &FieldSpec = &super::REGISTERS[20].fields[2];
    /// `MR3`, bit 3.
    pub const MR3: &FieldSpec = &super::REGISTERS[20].fields[3];
    /// `MR4`, bit 4.
    pub const MR4: &FieldSpec = &super::REGISTERS[20].fields[4];
    /// `MR5`, bit 5.
    pub const MR5: &FieldSpec = &super::REGISTERS[20].fields[5];
    /// `MR6`, bit 6.
    pub const MR6: &FieldSpec = &super::REGISTERS[20].fields[6];
    /// `MR7`, bit 7.
    pub const MR7: &FieldSpec = &super::REGISTERS[20].fields[7];
    /// `MR8`, bit 8.
    pub const MR8: &FieldSpec = &super::REGISTERS[20].fields[8];
    /// `MR9`, bit 9.
    pub const MR9: &FieldSpec = &super::REGISTERS[20].fields[9];
    /// `MR10`, bit 10.
    pub const MR10: &FieldSpec = &super::REGISTERS[20].fields[10];
    /// `MR11`, bit 11.
    pub const MR11: &FieldSpec = &super::REGISTERS[20].fields[11];
    /// `MR12`, bit 12.
    pub const MR12: &FieldSpec = &super::REGISTERS[20].fields[12];
    /// `MR14`, bit 14.
    pub const MR14: &FieldSpec = &super::REGISTERS[20].fields[13];
    /// `MR15`, bit 15.
    pub const MR15: &FieldSpec = &super::REGISTERS[20].fields[14];
    /// `MR16`, bit 16.
    pub const MR16: &FieldSpec = &super::REGISTERS[20].fields[15];
    /// `MR17`, bit 17.
    pub const MR17: &FieldSpec = &super::REGISTERS[20].fields[16];
    /// `MR18`, bit 18.
    pub const MR18: &FieldSpec = &super::REGISTERS[20].fields[17];
    /// `MR19`, bit 19.
    pub const MR19: &FieldSpec = &super::REGISTERS[20].fields[18];
    /// `MR20`, bit 20.
    pub const MR20: &FieldSpec = &super::REGISTERS[20].fields[19];
    /// `MR21`, bit 21.
    pub const MR21: &FieldSpec = &super::REGISTERS[20].fields[20];
    /// `MR22`, bit 22.
    pub const MR22: &FieldSpec = &super::REGISTERS[20].fields[21];
    /// `MR23`, bit 23.
    pub const MR23: &FieldSpec = &super::REGISTERS[20].fields[22];
    /// `MR24`, bit 24.
    pub const MR24: &FieldSpec = &super::REGISTERS[20].fields[23];
    /// `MR25`, bit 25.
    pub const MR25: &FieldSpec = &super::REGISTERS[20].fields[24];
    /// `MR26`, bit 26.
    pub const MR26: &FieldSpec = &super::REGISTERS[20].fields[25];
    /// `MR27`, bit 27.
    pub const MR27: &FieldSpec = &super::REGISTERS[20].fields[26];
    /// `MR28`, bit 28.
    pub const MR28: &FieldSpec = &super::REGISTERS[20].fields[27];
    /// `MR29`, bit 29.
    pub const MR29: &FieldSpec = &super::REGISTERS[20].fields[28];
    /// `MR30`, bit 30.
    pub const MR30: &FieldSpec = &super::REGISTERS[20].fields[29];
    /// `MR31`, bit 31.
    pub const MR31: &FieldSpec = &super::REGISTERS[20].fields[30];
}

/// The fields of `CPUEMR2`.
pub mod cpuemr2 {
    use super::FieldSpec;
    /// `MR32`, bit 0.
    pub const MR32: &FieldSpec = &super::REGISTERS[21].fields[0];
    /// `MR33`, bit 1.
    pub const MR33: &FieldSpec = &super::REGISTERS[21].fields[1];
    /// `MR34`, bit 2.
    pub const MR34: &FieldSpec = &super::REGISTERS[21].fields[2];
    /// `MR35`, bit 3.
    pub const MR35: &FieldSpec = &super::REGISTERS[21].fields[3];
    /// `MR36`, bit 4.
    pub const MR36: &FieldSpec = &super::REGISTERS[21].fields[4];
    /// `MR37`, bit 5.
    pub const MR37: &FieldSpec = &super::REGISTERS[21].fields[5];
    /// `MR38`, bit 6.
    pub const MR38: &FieldSpec = &super::REGISTERS[21].fields[6];
    /// `MR39`, bit 7.
    pub const MR39: &FieldSpec = &super::REGISTERS[21].fields[7];
    /// `MR40`, bit 8.
    pub const MR40: &FieldSpec = &super::REGISTERS[21].fields[8];
    /// `MR41`, bit 9.
    pub const MR41: &FieldSpec = &super::REGISTERS[21].fields[9];
    /// `MR42`, bit 10.
    pub const MR42: &FieldSpec = &super::REGISTERS[21].fields[10];
    /// `MR43`, bit 11.
    pub const MR43: &FieldSpec = &super::REGISTERS[21].fields[11];
    /// `MR44`, bit 12.
    pub const MR44: &FieldSpec = &super::REGISTERS[21].fields[12];
    /// `MR46`, bit 14.
    pub const MR46: &FieldSpec = &super::REGISTERS[21].fields[13];
    /// `MR47`, bit 15.
    pub const MR47: &FieldSpec = &super::REGISTERS[21].fields[14];
    /// `MR48`, bit 16.
    pub const MR48: &FieldSpec = &super::REGISTERS[21].fields[15];
    /// `MR49`, bit 17.
    pub const MR49: &FieldSpec = &super::REGISTERS[21].fields[16];
    /// `MR50`, bit 18.
    pub const MR50: &FieldSpec = &super::REGISTERS[21].fields[17];
    /// `MR51`, bit 19.
    pub const MR51: &FieldSpec = &super::REGISTERS[21].fields[18];
    /// `MR52`, bit 20.
    pub const MR52: &FieldSpec = &super::REGISTERS[21].fields[19];
    /// `MR53`, bit 21.
    pub const MR53: &FieldSpec = &super::REGISTERS[21].fields[20];
    /// `MR54`, bit 22.
    pub const MR54: &FieldSpec = &super::REGISTERS[21].fields[21];
    /// `MR55`, bit 23.
    pub const MR55: &FieldSpec = &super::REGISTERS[21].fields[22];
    /// `MR56`, bit 24.
    pub const MR56: &FieldSpec = &super::REGISTERS[21].fields[23];
    /// `MR57`, bit 25.
    pub const MR57: &FieldSpec = &super::REGISTERS[21].fields[24];
    /// `MR58`, bit 26.
    pub const MR58: &FieldSpec = &super::REGISTERS[21].fields[25];
    /// `MR59`, bit 27.
    pub const MR59: &FieldSpec = &super::REGISTERS[21].fields[26];
    /// `MR60`, bit 28.
    pub const MR60: &FieldSpec = &super::REGISTERS[21].fields[27];
    /// `MR61`, bit 29.
    pub const MR61: &FieldSpec = &super::REGISTERS[21].fields[28];
    /// `MR62`, bit 30.
    pub const MR62: &FieldSpec = &super::REGISTERS[21].fields[29];
    /// `MR63`, bit 31.
    pub const MR63: &FieldSpec = &super::REGISTERS[21].fields[30];
}

/// The fields of `CPUPR2`.
pub mod cpupr2 {
    use super::FieldSpec;
    /// `PR49`, bit 17.
    pub const PR49: &FieldSpec = &super::REGISTERS[22].fields[0];
    /// `PR51`, bit 19.
    pub const PR51: &FieldSpec = &super::REGISTERS[22].fields[1];
}

/// The fields of `CPUIMR3`.
pub mod cpuimr3 {
    use super::FieldSpec;
    /// `MR64`, bit 0.
    pub const MR64: &FieldSpec = &super::REGISTERS[23].fields[0];
    /// `MR65`, bit 1.
    pub const MR65: &FieldSpec = &super::REGISTERS[23].fields[1];
    /// `MR66`, bit 2.
    pub const MR66: &FieldSpec = &super::REGISTERS[23].fields[2];
    /// `MR67`, bit 3.
    pub const MR67: &FieldSpec = &super::REGISTERS[23].fields[3];
    /// `MR68`, bit 4.
    pub const MR68: &FieldSpec = &super::REGISTERS[23].fields[4];
    /// `MR69`, bit 5.
    pub const MR69: &FieldSpec = &super::REGISTERS[23].fields[5];
    /// `MR70`, bit 6.
    pub const MR70: &FieldSpec = &super::REGISTERS[23].fields[6];
    /// `MR71`, bit 7.
    pub const MR71: &FieldSpec = &super::REGISTERS[23].fields[7];
    /// `MR72`, bit 8.
    pub const MR72: &FieldSpec = &super::REGISTERS[23].fields[8];
    /// `MR73`, bit 9.
    pub const MR73: &FieldSpec = &super::REGISTERS[23].fields[9];
    /// `MR74`, bit 10.
    pub const MR74: &FieldSpec = &super::REGISTERS[23].fields[10];
    /// `MR75`, bit 11.
    pub const MR75: &FieldSpec = &super::REGISTERS[23].fields[11];
    /// `MR76`, bit 12.
    pub const MR76: &FieldSpec = &super::REGISTERS[23].fields[12];
    /// `MR77`, bit 13.
    pub const MR77: &FieldSpec = &super::REGISTERS[23].fields[13];
    /// `MR78`, bit 14.
    pub const MR78: &FieldSpec = &super::REGISTERS[23].fields[14];
    /// `MR79`, bit 15.
    pub const MR79: &FieldSpec = &super::REGISTERS[23].fields[15];
    /// `MR80`, bit 16.
    pub const MR80: &FieldSpec = &super::REGISTERS[23].fields[16];
    /// `MR82`, bit 18.
    pub const MR82: &FieldSpec = &super::REGISTERS[23].fields[17];
    /// `MR84`, bit 20.
    pub const MR84: &FieldSpec = &super::REGISTERS[23].fields[18];
    /// `MR85`, bit 21.
    pub const MR85: &FieldSpec = &super::REGISTERS[23].fields[19];
    /// `MR86`, bit 22.
    pub const MR86: &FieldSpec = &super::REGISTERS[23].fields[20];
    /// `MR87`, bit 23.
    pub const MR87: &FieldSpec = &super::REGISTERS[23].fields[21];
    /// `MR88`, bit 24.
    pub const MR88: &FieldSpec = &super::REGISTERS[23].fields[22];
}

/// The fields of `CPUEMR3`.
pub mod cpuemr3 {
    use super::FieldSpec;
    /// `MR64`, bit 0.
    pub const MR64: &FieldSpec = &super::REGISTERS[24].fields[0];
    /// `MR65`, bit 1.
    pub const MR65: &FieldSpec = &super::REGISTERS[24].fields[1];
    /// `MR66`, bit 2.
    pub const MR66: &FieldSpec = &super::REGISTERS[24].fields[2];
    /// `MR67`, bit 3.
    pub const MR67: &FieldSpec = &super::REGISTERS[24].fields[3];
    /// `MR68`, bit 4.
    pub const MR68: &FieldSpec = &super::REGISTERS[24].fields[4];
    /// `MR69`, bit 5.
    pub const MR69: &FieldSpec = &super::REGISTERS[24].fields[5];
    /// `MR70`, bit 6.
    pub const MR70: &FieldSpec = &super::REGISTERS[24].fields[6];
    /// `MR71`, bit 7.
    pub const MR71: &FieldSpec = &super::REGISTERS[24].fields[7];
    /// `MR72`, bit 8.
    pub const MR72: &FieldSpec = &super::REGISTERS[24].fields[8];
    /// `MR73`, bit 9.
    pub const MR73: &FieldSpec = &super::REGISTERS[24].fields[9];
    /// `MR74`, bit 10.
    pub const MR74: &FieldSpec = &super::REGISTERS[24].fields[10];
    /// `MR75`, bit 11.
    pub const MR75: &FieldSpec = &super::REGISTERS[24].fields[11];
    /// `MR76`, bit 12.
    pub const MR76: &FieldSpec = &super::REGISTERS[24].fields[12];
    /// `MR77`, bit 13.
    pub const MR77: &FieldSpec = &super::REGISTERS[24].fields[13];
    /// `MR78`, bit 14.
    pub const MR78: &FieldSpec = &super::REGISTERS[24].fields[14];
    /// `MR79`, bit 15.
    pub const MR79: &FieldSpec = &super::REGISTERS[24].fields[15];
    /// `MR80`, bit 16.
    pub const MR80: &FieldSpec = &super::REGISTERS[24].fields[16];
    /// `MR82`, bit 18.
    pub const MR82: &FieldSpec = &super::REGISTERS[24].fields[17];
    /// `MR84`, bit 20.
    pub const MR84: &FieldSpec = &super::REGISTERS[24].fields[18];
    /// `MR85`, bit 21.
    pub const MR85: &FieldSpec = &super::REGISTERS[24].fields[19];
    /// `MR86`, bit 22.
    pub const MR86: &FieldSpec = &super::REGISTERS[24].fields[20];
    /// `MR87`, bit 23.
    pub const MR87: &FieldSpec = &super::REGISTERS[24].fields[21];
    /// `MR88`, bit 24.
    pub const MR88: &FieldSpec = &super::REGISTERS[24].fields[22];
}

/// The fields of `CPUPR3`.
pub mod cpupr3 {
    use super::FieldSpec;
    /// `PR82`, bit 18.
    pub const PR82: &FieldSpec = &super::REGISTERS[25].fields[0];
    /// `PR84`, bit 20.
    pub const PR84: &FieldSpec = &super::REGISTERS[25].fields[1];
    /// `PR85`, bit 21.
    pub const PR85: &FieldSpec = &super::REGISTERS[25].fields[2];
    /// `PR86`, bit 22.
    pub const PR86: &FieldSpec = &super::REGISTERS[25].fields[3];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 26] = [
    RegisterSpec { name: "RTSR1", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TR0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR16", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR17", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR18", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR19", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR20", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR21", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FTSR1", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TR0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR16", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR17", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR18", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR19", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR20", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR21", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SWIER1", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SWIER0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER16", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER17", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER18", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER19", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER20", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER21", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "D3PMR1", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MR0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR19", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR20", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR21", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR25", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "D3PCR1L", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PCS0", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS1", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS2", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS3", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS4", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS5", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS6", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS7", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS8", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS9", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS10", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS11", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS12", bit: 24, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS13", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS14", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS15", bit: 30, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "D3PCR1H", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PCS19", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS20", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS21", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS25", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RTSR2", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TR49", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR51", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FTSR2", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TR49", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR51", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SWIER2", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SWIER49", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER51", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "D3PMR2", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MR34", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR35", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR41", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR48", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR49", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR50", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR51", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR52", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR53", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "D3PCR2L", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PCS34", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS35", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS41", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "D3PCR2H", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PCS48", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS49", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS50", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS51", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS52", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCS53", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RTSR3", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TR82", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR84", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR85", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR86", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FTSR3", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TR82", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR84", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR85", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR86", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SWIER3", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SWIER82", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER84", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER85", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER86", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "D3PMR3", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MR88", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "D3PCR3H", offset: 0x54, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PCS88", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CPUIMR1", offset: 0x80, width: Width::W32, reset: 0xFFC0_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MR0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR16", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR17", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR18", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR19", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR20", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR21", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR22", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR23", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR24", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR25", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR26", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR27", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR28", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR29", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR30", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR31", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CPUEMR1", offset: 0x84, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MR0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR16", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR17", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR18", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR19", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR20", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR21", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR22", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR23", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR24", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR25", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR26", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR27", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR28", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR29", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR30", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR31", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CPUPR1", offset: 0x88, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PR0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR16", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR17", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR18", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR19", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR20", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR21", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CPUIMR2", offset: 0x90, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MR0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR16", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR17", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR18", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR19", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR20", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR21", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR22", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR23", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR24", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR25", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR26", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR27", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR28", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR29", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR30", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR31", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CPUEMR2", offset: 0x94, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MR32", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR33", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR34", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR35", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR36", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR37", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR38", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR39", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR40", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR41", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR42", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR43", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR44", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR46", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR47", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR48", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR49", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR50", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR51", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR52", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR53", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR54", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR55", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR56", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR57", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR58", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR59", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR60", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR61", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR62", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR63", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CPUPR2", offset: 0x98, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PR49", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR51", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CPUIMR3", offset: 0xA0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MR64", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR65", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR66", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR67", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR68", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR69", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR70", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR71", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR72", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR73", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR74", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR75", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR76", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR77", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR78", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR79", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR80", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR82", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR84", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR85", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR86", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR87", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR88", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CPUEMR3", offset: 0xA4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MR64", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR65", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR66", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR67", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR68", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR69", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR70", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR71", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR72", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR73", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR74", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR75", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR76", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR77", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR78", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR79", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR80", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR82", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR84", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR85", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR86", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR87", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR88", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CPUPR3", offset: 0xA8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PR82", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR84", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR85", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR86", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];