rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `DBGMCU` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `IDC` at offset `0x0`, resets to `0x1000_6450`, read-only.
    Idc = 0,
    /// `CR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Cr = 1,
    /// `APB3FZ1` at offset `0x34`, resets to `0x0000_0000`, read-write.
    Apb3fz1 = 2,
    /// `APB1LFZ1` at offset `0x3C`, resets to `0x0000_0000`, read-write.
    Apb1lfz1 = 3,
    /// `APB2FZ1` at offset `0x4C`, resets to `0x0000_0000`, read-write.
    Apb2fz1 = 4,
    /// `APB4FZ1` at offset `0x54`, resets to `0x0000_0000`, read-write.
    Apb4fz1 = 5,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 6] = [Self::Idc, Self::Cr, Self::Apb3fz1, Self::Apb1lfz1, Self::Apb2fz1, Self::Apb4fz1];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `IDC`.
pub mod idc {
    use super::FieldSpec;
    /// `DEV_ID`, bits 0..=11.
    pub const DEV_ID: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `REV_ID`, bits 16..=31.
    pub const REV_ID: &FieldSpec = &super::REGISTERS[0].fields[1];
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `DBGSLEEP_D1`, bit 0.
    pub const DBGSLEEP_D1: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `DBGSTOP_D1`, bit 1.
    pub const DBGSTOP_D1: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `DBGSTBY_D1`, bit 2.
    pub const DBGSTBY_D1: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `DBGSLEEP_D2`, bit 3.
    pub const DBGSLEEP_D2: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `DBGSTOP_D2`, bit 4.
    pub const DBGSTOP_D2: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `DBGSTBY_D2`, bit 5.
    pub const DBGSTBY_D2: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `DBGSTOP_D3`, bit 7.
    pub const DBGSTOP_D3: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `DBGSTBY_D3`, bit 8.
    pub const DBGSTBY_D3: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `TRACECLKEN`, bit 20.
    pub const TRACECLKEN: &FieldSpec = &super::REGISTERS[1].fields[8];
    /// `D1DBGCKEN`, bit 21.
    pub const D1DBGCKEN: &FieldSpec = &super::REGISTERS[1].fields[9];
    /// `D3DBGCKEN`, bit 22.
    pub const D3DBGCKEN: &FieldSpec = &super::REGISTERS[1].fields[10];
    /// `TRGOEN`, bit 28.
    pub const TRGOEN: &FieldSpec = &super::REGISTERS[1].fields[11];
}

/// The fields of `APB3FZ1`.
pub mod apb3fz1 {
    use super::FieldSpec;
    /// `WWDG1`, bit 6.
    pub const WWDG1: &FieldSpec = &super::REGISTERS[2].fields[0];
}

/// The fields of `APB1LFZ1`.
pub mod apb1lfz1 {
    use super::FieldSpec;
    /// `DBG_TIM2`, bit 0.
    pub const DBG_TIM2: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `DBG_TIM3`, bit 1.
    pub const DBG_TIM3: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `DBG_TIM4`, bit 2.
    pub const DBG_TIM4: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `DBG_TIM5`, bit 3.
    pub const DBG_TIM5: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `DBG_TIM6`, bit 4.
    pub const DBG_TIM6: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `DBG_TIM7`, bit 5.
    pub const DBG_TIM7: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `DBG_TIM12`, bit 6.
    pub const DBG_TIM12: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `DBG_TIM13`, bit 7.
    pub const DBG_TIM13: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `DBG_TIM14`, bit 8.
    pub const DBG_TIM14: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `DBG_LPTIM1`, bit 9.
    pub const DBG_LPTIM1: &FieldSpec = &super::REGISTERS[3].fields[9];
    /// `DBG_I2C1`, bit 21.
    pub const DBG_I2C1: &FieldSpec = &super::REGISTERS[3].fields[10];
    /// `DBG_I2C2`, bit 22.
    pub const DBG_I2C2: &FieldSpec = &super::REGISTERS[3].fields[11];
    /// `DBG_I2C3`, bit 23.
    pub const DBG_I2C3: &FieldSpec = &super::REGISTERS[3].fields[12];
}

/// The fields of `APB2FZ1`.
pub mod apb2fz1 {
    use super::FieldSpec;
    /// `DBG_TIM1`, bit 0.
    pub const DBG_TIM1: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `DBG_TIM8`, bit 1.
    pub const DBG_TIM8: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `DBG_TIM15`, bit 16.
    pub const DBG_TIM15: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `DBG_TIM16`, bit 17.
    pub const DBG_TIM16: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `DBG_TIM17`, bit 18.
    pub const DBG_TIM17: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `DBG_HRTIM`, bit 29.
    pub const DBG_HRTIM: &FieldSpec = &super::REGISTERS[4].fields[5];
}

/// The fields of `APB4FZ1`.
pub mod apb4fz1 {
    use super::FieldSpec;
    /// `DBG_I2C4`, bit 7.
    pub const DBG_I2C4: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `DBG_LPTIM2`, bit 9.
    pub const DBG_LPTIM2: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `DBG_LPTIM3`, bit 10.
    pub const DBG_LPTIM3: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `DBG_LPTIM4`, bit 11.
    pub const DBG_LPTIM4: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `DBG_LPTIM5`, bit 12.
    pub const DBG_LPTIM5: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `DBG_RTC`, bit 16.
    pub const DBG_RTC: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `DBG_IWDG1`, bit 18.
    pub const DBG_IWDG1: &FieldSpec = &super::REGISTERS[5].fields[6];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 6] = [
    RegisterSpec { name: "IDC", offset: 0x0, width: Width::W32, reset: 0x1000_6450, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DEV_ID", bit: 0, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REV_ID", bit: 16, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DBGSLEEP_D1", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBGSTOP_D1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBGSTBY_D1", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBGSLEEP_D2", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBGSTOP_D2", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBGSTBY_D2", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBGSTOP_D3", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBGSTBY_D3", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRACECLKEN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "D1DBGCKEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "D3DBGCKEN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRGOEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "APB3FZ1", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WWDG1", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "APB1LFZ1", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DBG_TIM2", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM3", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM4", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM5", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM6", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM7", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM12", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM13", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM14", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_LPTIM1", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_I2C1", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_I2C2", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_I2C3", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "APB2FZ1", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DBG_TIM1", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM8", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM15", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM16", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM17", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_HRTIM", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "APB4FZ1", offset: 0x54, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DBG_I2C4", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_LPTIM2", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_LPTIM3", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_LPTIM4", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_LPTIM5", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_RTC", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_IWDG1", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];