/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"USB Host and Device Controller"]
unsafe impl ::core::marker::Send for super::Usbfs {}
unsafe impl ::core::marker::Sync for super::Usbfs {}
impl super::Usbfs {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "USB Device"]
#[inline(always)]
pub const fn usbdev(self) -> crate::usbfs::Usbdev {
unsafe { crate::usbfs::_Usbdev::_svd2pac_from_ptr(self._svd2pac_as_ptr().add(0usize)) }
}
#[doc = "USB Device LPM and PHY Test"]
#[inline(always)]
pub const fn usblpm(self) -> crate::usbfs::Usblpm {
unsafe { crate::usbfs::_Usblpm::_svd2pac_from_ptr(self._svd2pac_as_ptr().add(8192usize)) }
}
#[doc = "USB Host Controller"]
#[inline(always)]
pub const fn usbhost(self) -> crate::usbfs::Usbhost {
unsafe { crate::usbfs::_Usbhost::_svd2pac_from_ptr(self._svd2pac_as_ptr().add(16384usize)) }
}
}
#[doc = "USB Device"]
#[non_exhaustive]
pub struct _Usbdev;
#[doc = "USB Device"]
pub type Usbdev = &'static _Usbdev;
unsafe impl ::core::marker::Sync for _Usbdev {}
impl _Usbdev {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "Control End point EP0 Data Register"]
#[inline(always)]
pub const fn ep0_dr(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<usbdev::Ep0Dr_SPEC, crate::common::RW>,
8,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x0usize))
}
}
#[doc = "USB control 0 Register"]
#[inline(always)]
pub const fn cr0(&self) -> &'static crate::common::Reg<usbdev::Cr0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::Cr0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "USB control 1 Register"]
#[inline(always)]
pub const fn cr1(&self) -> &'static crate::common::Reg<usbdev::Cr1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::Cr1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
#[doc = "USB SIE Data Endpoints Interrupt Enable Register"]
#[inline(always)]
pub const fn sie_ep_int_en(
&self,
) -> &'static crate::common::Reg<usbdev::SieEpIntEn_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEpIntEn_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(40usize),
)
}
}
#[doc = "USB SIE Data Endpoint Interrupt Status"]
#[inline(always)]
pub const fn sie_ep_int_sr(
&self,
) -> &'static crate::common::Reg<usbdev::SieEpIntSr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEpIntSr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(44usize),
)
}
}
#[doc = "Non-control endpoint count register"]
#[inline(always)]
pub const fn sie_ep1_cnt0(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp1Cnt0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp1Cnt0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(48usize),
)
}
}
#[doc = "Non-control endpoint count register"]
#[inline(always)]
pub const fn sie_ep1_cnt1(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp1Cnt1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp1Cnt1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(52usize),
)
}
}
#[doc = "Non-control endpoint\'s control Register"]
#[inline(always)]
pub const fn sie_ep1_cr0(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp1Cr0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp1Cr0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(56usize),
)
}
}
#[doc = "USBIO Control 0 Register"]
#[inline(always)]
pub const fn usbio_cr0(
&self,
) -> &'static crate::common::Reg<usbdev::UsbioCr0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::UsbioCr0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(64usize),
)
}
}
#[doc = "USBIO control 2 Register"]
#[inline(always)]
pub const fn usbio_cr2(
&self,
) -> &'static crate::common::Reg<usbdev::UsbioCr2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::UsbioCr2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(68usize),
)
}
}
#[doc = "USBIO control 1 Register"]
#[inline(always)]
pub const fn usbio_cr1(
&self,
) -> &'static crate::common::Reg<usbdev::UsbioCr1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::UsbioCr1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(72usize),
)
}
}
#[doc = "USB Dynamic reconfiguration register"]
#[inline(always)]
pub const fn dyn_reconfig(
&self,
) -> &'static crate::common::Reg<usbdev::DynReconfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::DynReconfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(80usize),
)
}
}
#[doc = "Start Of Frame Register"]
#[inline(always)]
pub const fn sof0(&self) -> &'static crate::common::Reg<usbdev::Sof0_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbdev::Sof0_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(96usize),
)
}
}
#[doc = "Start Of Frame Register"]
#[inline(always)]
pub const fn sof1(&self) -> &'static crate::common::Reg<usbdev::Sof1_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbdev::Sof1_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(100usize),
)
}
}
#[doc = "Non-control endpoint count register"]
#[inline(always)]
pub const fn sie_ep2_cnt0(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp2Cnt0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp2Cnt0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(112usize),
)
}
}
#[doc = "Non-control endpoint count register"]
#[inline(always)]
pub const fn sie_ep2_cnt1(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp2Cnt1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp2Cnt1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(116usize),
)
}
}
#[doc = "Non-control endpoint\'s control Register"]
#[inline(always)]
pub const fn sie_ep2_cr0(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp2Cr0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp2Cr0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(120usize),
)
}
}
#[doc = "Oscillator lock data register 0"]
#[inline(always)]
pub const fn osclk_dr0(
&self,
) -> &'static crate::common::Reg<usbdev::OsclkDr0_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbdev::OsclkDr0_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(128usize),
)
}
}
#[doc = "Oscillator lock data register 1"]
#[inline(always)]
pub const fn osclk_dr1(
&self,
) -> &'static crate::common::Reg<usbdev::OsclkDr1_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbdev::OsclkDr1_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(132usize),
)
}
}
#[doc = "Endpoint0 control Register"]
#[inline(always)]
pub const fn ep0_cr(
&self,
) -> &'static crate::common::Reg<usbdev::Ep0Cr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::Ep0Cr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(160usize),
)
}
}
#[doc = "Endpoint0 count Register"]
#[inline(always)]
pub const fn ep0_cnt(
&self,
) -> &'static crate::common::Reg<usbdev::Ep0Cnt_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::Ep0Cnt_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(164usize),
)
}
}
#[doc = "Non-control endpoint count register"]
#[inline(always)]
pub const fn sie_ep3_cnt0(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp3Cnt0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp3Cnt0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(176usize),
)
}
}
#[doc = "Non-control endpoint count register"]
#[inline(always)]
pub const fn sie_ep3_cnt1(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp3Cnt1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp3Cnt1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(180usize),
)
}
}
#[doc = "Non-control endpoint\'s control Register"]
#[inline(always)]
pub const fn sie_ep3_cr0(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp3Cr0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp3Cr0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(184usize),
)
}
}
#[doc = "Non-control endpoint count register"]
#[inline(always)]
pub const fn sie_ep4_cnt0(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp4Cnt0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp4Cnt0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(240usize),
)
}
}
#[doc = "Non-control endpoint count register"]
#[inline(always)]
pub const fn sie_ep4_cnt1(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp4Cnt1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp4Cnt1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(244usize),
)
}
}
#[doc = "Non-control endpoint\'s control Register"]
#[inline(always)]
pub const fn sie_ep4_cr0(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp4Cr0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp4Cr0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(248usize),
)
}
}
#[doc = "Non-control endpoint count register"]
#[inline(always)]
pub const fn sie_ep5_cnt0(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp5Cnt0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp5Cnt0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(304usize),
)
}
}
#[doc = "Non-control endpoint count register"]
#[inline(always)]
pub const fn sie_ep5_cnt1(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp5Cnt1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp5Cnt1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(308usize),
)
}
}
#[doc = "Non-control endpoint\'s control Register"]
#[inline(always)]
pub const fn sie_ep5_cr0(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp5Cr0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp5Cr0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(312usize),
)
}
}
#[doc = "Non-control endpoint count register"]
#[inline(always)]
pub const fn sie_ep6_cnt0(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp6Cnt0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp6Cnt0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(368usize),
)
}
}
#[doc = "Non-control endpoint count register"]
#[inline(always)]
pub const fn sie_ep6_cnt1(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp6Cnt1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp6Cnt1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(372usize),
)
}
}
#[doc = "Non-control endpoint\'s control Register"]
#[inline(always)]
pub const fn sie_ep6_cr0(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp6Cr0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp6Cr0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(376usize),
)
}
}
#[doc = "Non-control endpoint count register"]
#[inline(always)]
pub const fn sie_ep7_cnt0(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp7Cnt0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp7Cnt0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(432usize),
)
}
}
#[doc = "Non-control endpoint count register"]
#[inline(always)]
pub const fn sie_ep7_cnt1(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp7Cnt1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp7Cnt1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(436usize),
)
}
}
#[doc = "Non-control endpoint\'s control Register"]
#[inline(always)]
pub const fn sie_ep7_cr0(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp7Cr0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp7Cr0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(440usize),
)
}
}
#[doc = "Non-control endpoint count register"]
#[inline(always)]
pub const fn sie_ep8_cnt0(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp8Cnt0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp8Cnt0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(496usize),
)
}
}
#[doc = "Non-control endpoint count register"]
#[inline(always)]
pub const fn sie_ep8_cnt1(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp8Cnt1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp8Cnt1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(500usize),
)
}
}
#[doc = "Non-control endpoint\'s control Register"]
#[inline(always)]
pub const fn sie_ep8_cr0(
&self,
) -> &'static crate::common::Reg<usbdev::SieEp8Cr0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::SieEp8Cr0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(504usize),
)
}
}
#[doc = "Endpoint Configuration Register *1"]
#[inline(always)]
pub const fn arb_ep1_cfg(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp1Cfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp1Cfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(512usize),
)
}
}
#[doc = "Endpoint Interrupt Enable Register *1"]
#[inline(always)]
pub const fn arb_ep1_int_en(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp1IntEn_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp1IntEn_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(516usize),
)
}
}
#[doc = "Endpoint Interrupt Enable Register *1"]
#[inline(always)]
pub const fn arb_ep1_sr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp1Sr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp1Sr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(520usize),
)
}
}
#[doc = "Endpoint Write Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw1_wa(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw1Wa_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw1Wa_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(528usize),
)
}
}
#[doc = "Endpoint Write Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw1_wa_msb(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw1WaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw1WaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(532usize),
)
}
}
#[doc = "Endpoint Read Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw1_ra(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw1Ra_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw1Ra_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(536usize),
)
}
}
#[doc = "Endpoint Read Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw1_ra_msb(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw1RaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw1RaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(540usize),
)
}
}
#[doc = "Endpoint Data Register"]
#[inline(always)]
pub const fn arb_rw1_dr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw1Dr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw1Dr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(544usize),
)
}
}
#[doc = "Dedicated Endpoint Buffer Size Register *1"]
#[inline(always)]
pub const fn buf_size(
&self,
) -> &'static crate::common::Reg<usbdev::BufSize_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::BufSize_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(560usize),
)
}
}
#[doc = "Endpoint Active Indication Register *1"]
#[inline(always)]
pub const fn ep_active(
&self,
) -> &'static crate::common::Reg<usbdev::EpActive_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::EpActive_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(568usize),
)
}
}
#[doc = "Endpoint Type (IN/OUT) Indication *1"]
#[inline(always)]
pub const fn ep_type(
&self,
) -> &'static crate::common::Reg<usbdev::EpType_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::EpType_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(572usize),
)
}
}
#[doc = "Endpoint Configuration Register *1"]
#[inline(always)]
pub const fn arb_ep2_cfg(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp2Cfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp2Cfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(576usize),
)
}
}
#[doc = "Endpoint Interrupt Enable Register *1"]
#[inline(always)]
pub const fn arb_ep2_int_en(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp2IntEn_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp2IntEn_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(580usize),
)
}
}
#[doc = "Endpoint Interrupt Enable Register *1"]
#[inline(always)]
pub const fn arb_ep2_sr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp2Sr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp2Sr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(584usize),
)
}
}
#[doc = "Endpoint Write Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw2_wa(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw2Wa_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw2Wa_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(592usize),
)
}
}
#[doc = "Endpoint Write Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw2_wa_msb(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw2WaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw2WaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(596usize),
)
}
}
#[doc = "Endpoint Read Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw2_ra(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw2Ra_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw2Ra_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(600usize),
)
}
}
#[doc = "Endpoint Read Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw2_ra_msb(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw2RaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw2RaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(604usize),
)
}
}
#[doc = "Endpoint Data Register"]
#[inline(always)]
pub const fn arb_rw2_dr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw2Dr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw2Dr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(608usize),
)
}
}
#[doc = "Arbiter Configuration Register *1"]
#[inline(always)]
pub const fn arb_cfg(
&self,
) -> &'static crate::common::Reg<usbdev::ArbCfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbCfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(624usize),
)
}
}
#[doc = "USB Block Clock Enable Register"]
#[inline(always)]
pub const fn usb_clk_en(
&self,
) -> &'static crate::common::Reg<usbdev::UsbClkEn_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::UsbClkEn_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(628usize),
)
}
}
#[doc = "Arbiter Interrupt Enable *1"]
#[inline(always)]
pub const fn arb_int_en(
&self,
) -> &'static crate::common::Reg<usbdev::ArbIntEn_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbIntEn_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(632usize),
)
}
}
#[doc = "Arbiter Interrupt Status *1"]
#[inline(always)]
pub const fn arb_int_sr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbIntSr_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbdev::ArbIntSr_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(636usize),
)
}
}
#[doc = "Endpoint Configuration Register *1"]
#[inline(always)]
pub const fn arb_ep3_cfg(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp3Cfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp3Cfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(640usize),
)
}
}
#[doc = "Endpoint Interrupt Enable Register *1"]
#[inline(always)]
pub const fn arb_ep3_int_en(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp3IntEn_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp3IntEn_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(644usize),
)
}
}
#[doc = "Endpoint Interrupt Enable Register *1"]
#[inline(always)]
pub const fn arb_ep3_sr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp3Sr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp3Sr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(648usize),
)
}
}
#[doc = "Endpoint Write Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw3_wa(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw3Wa_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw3Wa_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(656usize),
)
}
}
#[doc = "Endpoint Write Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw3_wa_msb(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw3WaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw3WaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(660usize),
)
}
}
#[doc = "Endpoint Read Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw3_ra(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw3Ra_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw3Ra_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(664usize),
)
}
}
#[doc = "Endpoint Read Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw3_ra_msb(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw3RaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw3RaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(668usize),
)
}
}
#[doc = "Endpoint Data Register"]
#[inline(always)]
pub const fn arb_rw3_dr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw3Dr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw3Dr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(672usize),
)
}
}
#[doc = "Common Area Write Address *1"]
#[inline(always)]
pub const fn cwa(&self) -> &'static crate::common::Reg<usbdev::Cwa_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::Cwa_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(688usize),
)
}
}
#[doc = "Endpoint Read Address value *1"]
#[inline(always)]
pub const fn cwa_msb(
&self,
) -> &'static crate::common::Reg<usbdev::CwaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::CwaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(692usize),
)
}
}
#[doc = "Endpoint Configuration Register *1"]
#[inline(always)]
pub const fn arb_ep4_cfg(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp4Cfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp4Cfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(704usize),
)
}
}
#[doc = "Endpoint Interrupt Enable Register *1"]
#[inline(always)]
pub const fn arb_ep4_int_en(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp4IntEn_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp4IntEn_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(708usize),
)
}
}
#[doc = "Endpoint Interrupt Enable Register *1"]
#[inline(always)]
pub const fn arb_ep4_sr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp4Sr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp4Sr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(712usize),
)
}
}
#[doc = "Endpoint Write Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw4_wa(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw4Wa_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw4Wa_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(720usize),
)
}
}
#[doc = "Endpoint Write Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw4_wa_msb(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw4WaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw4WaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(724usize),
)
}
}
#[doc = "Endpoint Read Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw4_ra(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw4Ra_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw4Ra_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(728usize),
)
}
}
#[doc = "Endpoint Read Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw4_ra_msb(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw4RaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw4RaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(732usize),
)
}
}
#[doc = "Endpoint Data Register"]
#[inline(always)]
pub const fn arb_rw4_dr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw4Dr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw4Dr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(736usize),
)
}
}
#[doc = "DMA Burst / Threshold Configuration"]
#[inline(always)]
pub const fn dma_thres(
&self,
) -> &'static crate::common::Reg<usbdev::DmaThres_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::DmaThres_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(752usize),
)
}
}
#[doc = "DMA Burst / Threshold Configuration"]
#[inline(always)]
pub const fn dma_thres_msb(
&self,
) -> &'static crate::common::Reg<usbdev::DmaThresMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::DmaThresMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(756usize),
)
}
}
#[doc = "Endpoint Configuration Register *1"]
#[inline(always)]
pub const fn arb_ep5_cfg(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp5Cfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp5Cfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(768usize),
)
}
}
#[doc = "Endpoint Interrupt Enable Register *1"]
#[inline(always)]
pub const fn arb_ep5_int_en(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp5IntEn_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp5IntEn_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(772usize),
)
}
}
#[doc = "Endpoint Interrupt Enable Register *1"]
#[inline(always)]
pub const fn arb_ep5_sr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp5Sr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp5Sr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(776usize),
)
}
}
#[doc = "Endpoint Write Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw5_wa(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw5Wa_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw5Wa_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(784usize),
)
}
}
#[doc = "Endpoint Write Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw5_wa_msb(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw5WaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw5WaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(788usize),
)
}
}
#[doc = "Endpoint Read Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw5_ra(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw5Ra_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw5Ra_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(792usize),
)
}
}
#[doc = "Endpoint Read Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw5_ra_msb(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw5RaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw5RaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(796usize),
)
}
}
#[doc = "Endpoint Data Register"]
#[inline(always)]
pub const fn arb_rw5_dr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw5Dr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw5Dr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(800usize),
)
}
}
#[doc = "Bus Reset Count Register"]
#[inline(always)]
pub const fn bus_rst_cnt(
&self,
) -> &'static crate::common::Reg<usbdev::BusRstCnt_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::BusRstCnt_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(816usize),
)
}
}
#[doc = "Endpoint Configuration Register *1"]
#[inline(always)]
pub const fn arb_ep6_cfg(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp6Cfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp6Cfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(832usize),
)
}
}
#[doc = "Endpoint Interrupt Enable Register *1"]
#[inline(always)]
pub const fn arb_ep6_int_en(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp6IntEn_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp6IntEn_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(836usize),
)
}
}
#[doc = "Endpoint Interrupt Enable Register *1"]
#[inline(always)]
pub const fn arb_ep6_sr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp6Sr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp6Sr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(840usize),
)
}
}
#[doc = "Endpoint Write Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw6_wa(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw6Wa_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw6Wa_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(848usize),
)
}
}
#[doc = "Endpoint Write Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw6_wa_msb(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw6WaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw6WaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(852usize),
)
}
}
#[doc = "Endpoint Read Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw6_ra(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw6Ra_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw6Ra_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(856usize),
)
}
}
#[doc = "Endpoint Read Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw6_ra_msb(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw6RaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw6RaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(860usize),
)
}
}
#[doc = "Endpoint Data Register"]
#[inline(always)]
pub const fn arb_rw6_dr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw6Dr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw6Dr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(864usize),
)
}
}
#[doc = "Endpoint Configuration Register *1"]
#[inline(always)]
pub const fn arb_ep7_cfg(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp7Cfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp7Cfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(896usize),
)
}
}
#[doc = "Endpoint Interrupt Enable Register *1"]
#[inline(always)]
pub const fn arb_ep7_int_en(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp7IntEn_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp7IntEn_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(900usize),
)
}
}
#[doc = "Endpoint Interrupt Enable Register *1"]
#[inline(always)]
pub const fn arb_ep7_sr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp7Sr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp7Sr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(904usize),
)
}
}
#[doc = "Endpoint Write Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw7_wa(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw7Wa_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw7Wa_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(912usize),
)
}
}
#[doc = "Endpoint Write Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw7_wa_msb(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw7WaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw7WaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(916usize),
)
}
}
#[doc = "Endpoint Read Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw7_ra(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw7Ra_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw7Ra_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(920usize),
)
}
}
#[doc = "Endpoint Read Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw7_ra_msb(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw7RaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw7RaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(924usize),
)
}
}
#[doc = "Endpoint Data Register"]
#[inline(always)]
pub const fn arb_rw7_dr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw7Dr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw7Dr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(928usize),
)
}
}
#[doc = "Endpoint Configuration Register *1"]
#[inline(always)]
pub const fn arb_ep8_cfg(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp8Cfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp8Cfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(960usize),
)
}
}
#[doc = "Endpoint Interrupt Enable Register *1"]
#[inline(always)]
pub const fn arb_ep8_int_en(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp8IntEn_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp8IntEn_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(964usize),
)
}
}
#[doc = "Endpoint Interrupt Enable Register *1"]
#[inline(always)]
pub const fn arb_ep8_sr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbEp8Sr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbEp8Sr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(968usize),
)
}
}
#[doc = "Endpoint Write Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw8_wa(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw8Wa_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw8Wa_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(976usize),
)
}
}
#[doc = "Endpoint Write Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw8_wa_msb(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw8WaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw8WaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(980usize),
)
}
}
#[doc = "Endpoint Read Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw8_ra(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw8Ra_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw8Ra_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(984usize),
)
}
}
#[doc = "Endpoint Read Address value *1, *2"]
#[inline(always)]
pub const fn arb_rw8_ra_msb(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw8RaMsb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw8RaMsb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(988usize),
)
}
}
#[doc = "Endpoint Data Register"]
#[inline(always)]
pub const fn arb_rw8_dr(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw8Dr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw8Dr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(992usize),
)
}
}
#[doc = "DATA"]
#[inline(always)]
pub const fn mem_data(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<usbdev::MemData_SPEC, crate::common::RW>,
512,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x400usize))
}
}
#[doc = "Start Of Frame Register"]
#[inline(always)]
pub const fn sof16(&self) -> &'static crate::common::Reg<usbdev::Sof16_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbdev::Sof16_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(4192usize),
)
}
}
#[doc = "Oscillator lock data register"]
#[inline(always)]
pub const fn osclk_dr16(
&self,
) -> &'static crate::common::Reg<usbdev::OsclkDr16_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbdev::OsclkDr16_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(4224usize),
)
}
}
#[doc = "Endpoint Write Address value *3"]
#[inline(always)]
pub const fn arb_rw1_wa16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw1Wa16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw1Wa16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4624usize),
)
}
}
#[doc = "Endpoint Read Address value *3"]
#[inline(always)]
pub const fn arb_rw1_ra16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw1Ra16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw1Ra16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4632usize),
)
}
}
#[doc = "Endpoint Data Register"]
#[inline(always)]
pub const fn arb_rw1_dr16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw1Dr16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw1Dr16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4640usize),
)
}
}
#[doc = "Endpoint Write Address value *3"]
#[inline(always)]
pub const fn arb_rw2_wa16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw2Wa16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw2Wa16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4688usize),
)
}
}
#[doc = "Endpoint Read Address value *3"]
#[inline(always)]
pub const fn arb_rw2_ra16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw2Ra16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw2Ra16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4696usize),
)
}
}
#[doc = "Endpoint Data Register"]
#[inline(always)]
pub const fn arb_rw2_dr16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw2Dr16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw2Dr16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4704usize),
)
}
}
#[doc = "Endpoint Write Address value *3"]
#[inline(always)]
pub const fn arb_rw3_wa16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw3Wa16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw3Wa16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4752usize),
)
}
}
#[doc = "Endpoint Read Address value *3"]
#[inline(always)]
pub const fn arb_rw3_ra16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw3Ra16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw3Ra16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4760usize),
)
}
}
#[doc = "Endpoint Data Register"]
#[inline(always)]
pub const fn arb_rw3_dr16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw3Dr16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw3Dr16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4768usize),
)
}
}
#[doc = "Common Area Write Address"]
#[inline(always)]
pub const fn cwa16(
&self,
) -> &'static crate::common::Reg<usbdev::Cwa16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::Cwa16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4784usize),
)
}
}
#[doc = "Endpoint Write Address value *3"]
#[inline(always)]
pub const fn arb_rw4_wa16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw4Wa16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw4Wa16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4816usize),
)
}
}
#[doc = "Endpoint Read Address value *3"]
#[inline(always)]
pub const fn arb_rw4_ra16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw4Ra16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw4Ra16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4824usize),
)
}
}
#[doc = "Endpoint Data Register"]
#[inline(always)]
pub const fn arb_rw4_dr16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw4Dr16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw4Dr16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4832usize),
)
}
}
#[doc = "DMA Burst / Threshold Configuration"]
#[inline(always)]
pub const fn dma_thres16(
&self,
) -> &'static crate::common::Reg<usbdev::DmaThres16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::DmaThres16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4848usize),
)
}
}
#[doc = "Endpoint Write Address value *3"]
#[inline(always)]
pub const fn arb_rw5_wa16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw5Wa16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw5Wa16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4880usize),
)
}
}
#[doc = "Endpoint Read Address value *3"]
#[inline(always)]
pub const fn arb_rw5_ra16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw5Ra16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw5Ra16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4888usize),
)
}
}
#[doc = "Endpoint Data Register"]
#[inline(always)]
pub const fn arb_rw5_dr16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw5Dr16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw5Dr16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4896usize),
)
}
}
#[doc = "Endpoint Write Address value *3"]
#[inline(always)]
pub const fn arb_rw6_wa16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw6Wa16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw6Wa16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4944usize),
)
}
}
#[doc = "Endpoint Read Address value *3"]
#[inline(always)]
pub const fn arb_rw6_ra16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw6Ra16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw6Ra16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4952usize),
)
}
}
#[doc = "Endpoint Data Register"]
#[inline(always)]
pub const fn arb_rw6_dr16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw6Dr16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw6Dr16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4960usize),
)
}
}
#[doc = "Endpoint Write Address value *3"]
#[inline(always)]
pub const fn arb_rw7_wa16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw7Wa16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw7Wa16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(5008usize),
)
}
}
#[doc = "Endpoint Read Address value *3"]
#[inline(always)]
pub const fn arb_rw7_ra16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw7Ra16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw7Ra16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(5016usize),
)
}
}
#[doc = "Endpoint Data Register"]
#[inline(always)]
pub const fn arb_rw7_dr16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw7Dr16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw7Dr16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(5024usize),
)
}
}
#[doc = "Endpoint Write Address value *3"]
#[inline(always)]
pub const fn arb_rw8_wa16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw8Wa16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw8Wa16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(5072usize),
)
}
}
#[doc = "Endpoint Read Address value *3"]
#[inline(always)]
pub const fn arb_rw8_ra16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw8Ra16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw8Ra16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(5080usize),
)
}
}
#[doc = "Endpoint Data Register"]
#[inline(always)]
pub const fn arb_rw8_dr16(
&self,
) -> &'static crate::common::Reg<usbdev::ArbRw8Dr16_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbdev::ArbRw8Dr16_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(5088usize),
)
}
}
}
pub mod usbdev {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ep0Dr_SPEC;
impl crate::sealed::RegSpec for Ep0Dr_SPEC {
type DataType = u32;
}
#[doc = "Control End point EP0 Data Register"]
pub type Ep0Dr = crate::RegValueT<Ep0Dr_SPEC>;
impl Ep0Dr {
#[doc = "This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred."]
#[inline(always)]
pub fn data_byte(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Ep0Dr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Ep0Dr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ep0Dr {
#[inline(always)]
fn default() -> Ep0Dr {
<crate::RegValueT<Ep0Dr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cr0_SPEC;
impl crate::sealed::RegSpec for Cr0_SPEC {
type DataType = u32;
}
#[doc = "USB control 0 Register"]
pub type Cr0 = crate::RegValueT<Cr0_SPEC>;
impl Cr0 {
#[doc = "These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware.\nIf USB bus reset is detected, these bits are initialized."]
#[inline(always)]
pub fn device_address(
self,
) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, Cr0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7f,1,0,u8,u8,Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit enables the device to respond to USB traffic.\nIf USB bus reset is detected, this bit is cleared.\nNote:\nWhen USB PHY is GPIO mode(USBIO_CR1.IOMODE=0), USB bus reset is detected. Therefore, when USB PHY is GPIO mode, this bit is cleared even if this bit is set to 1. If this bit is set to 1, write this bit upon USB bus reset interrupt, and do not write to this bit during initialization steps."]
#[inline(always)]
pub fn usb_enable(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7, 1, 0, Cr0_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Cr0 {
#[inline(always)]
fn default() -> Cr0 {
<crate::RegValueT<Cr0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cr1_SPEC;
impl crate::sealed::RegSpec for Cr1_SPEC {
type DataType = u32;
}
#[doc = "USB control 1 Register"]
pub type Cr1 = crate::RegValueT<Cr1_SPEC>;
impl Cr1 {
#[doc = "This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply."]
#[inline(always)]
pub fn reg_enable(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Cr1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Cr1_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation."]
#[inline(always)]
pub fn enable_lock(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Cr1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Cr1_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High\nvalue until firmware clears it."]
#[inline(always)]
pub fn bus_activity(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, Cr1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, Cr1_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_3(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Cr1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, Cr1_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Cr1 {
#[inline(always)]
fn default() -> Cr1 {
<crate::RegValueT<Cr1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEpIntEn_SPEC;
impl crate::sealed::RegSpec for SieEpIntEn_SPEC {
type DataType = u32;
}
#[doc = "USB SIE Data Endpoints Interrupt Enable Register"]
pub type SieEpIntEn = crate::RegValueT<SieEpIntEn_SPEC>;
impl SieEpIntEn {
#[doc = "Enables interrupt for EP1"]
#[inline(always)]
pub fn ep1_intr_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, SieEpIntEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,SieEpIntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables interrupt for EP2"]
#[inline(always)]
pub fn ep2_intr_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, SieEpIntEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,SieEpIntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables interrupt for EP3"]
#[inline(always)]
pub fn ep3_intr_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, SieEpIntEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,SieEpIntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables interrupt for EP4"]
#[inline(always)]
pub fn ep4_intr_en(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, SieEpIntEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,SieEpIntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables interrupt for EP5"]
#[inline(always)]
pub fn ep5_intr_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, SieEpIntEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,SieEpIntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables interrupt for EP6"]
#[inline(always)]
pub fn ep6_intr_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, SieEpIntEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,SieEpIntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables interrupt for EP7"]
#[inline(always)]
pub fn ep7_intr_en(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, SieEpIntEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,SieEpIntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables interrupt for EP8"]
#[inline(always)]
pub fn ep8_intr_en(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEpIntEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEpIntEn_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEpIntEn {
#[inline(always)]
fn default() -> SieEpIntEn {
<crate::RegValueT<SieEpIntEn_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEpIntSr_SPEC;
impl crate::sealed::RegSpec for SieEpIntSr_SPEC {
type DataType = u32;
}
#[doc = "USB SIE Data Endpoint Interrupt Status"]
pub type SieEpIntSr = crate::RegValueT<SieEpIntSr_SPEC>;
impl SieEpIntSr {
#[doc = "Interrupt status for EP1"]
#[inline(always)]
pub fn ep1_intr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, SieEpIntSr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,SieEpIntSr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Interrupt status for EP2"]
#[inline(always)]
pub fn ep2_intr(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, SieEpIntSr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,SieEpIntSr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Interrupt status for EP3"]
#[inline(always)]
pub fn ep3_intr(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, SieEpIntSr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,SieEpIntSr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Interrupt status for EP4"]
#[inline(always)]
pub fn ep4_intr(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, SieEpIntSr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,SieEpIntSr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Interrupt status for EP5"]
#[inline(always)]
pub fn ep5_intr(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, SieEpIntSr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,SieEpIntSr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Interrupt status for EP6"]
#[inline(always)]
pub fn ep6_intr(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, SieEpIntSr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,SieEpIntSr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Interrupt status for EP7"]
#[inline(always)]
pub fn ep7_intr(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, SieEpIntSr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,SieEpIntSr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Interrupt status for EP8"]
#[inline(always)]
pub fn ep8_intr(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEpIntSr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEpIntSr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEpIntSr {
#[inline(always)]
fn default() -> SieEpIntSr {
<crate::RegValueT<SieEpIntSr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp1Cnt0_SPEC;
impl crate::sealed::RegSpec for SieEp1Cnt0_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint count register"]
pub type SieEp1Cnt0 = crate::RegValueT<SieEp1Cnt0_SPEC>;
impl SieEp1Cnt0 {
#[doc = "These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count\\[7:0\\] bits of the CNT1 register. Refer to the CNT1 register for more information."]
#[inline(always)]
pub fn data_count_msb(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, SieEp1Cnt0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,SieEp1Cnt0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used for OUT transactions only and is read only. It is cleared to \'0\' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings."]
#[inline(always)]
pub fn data_valid(
self,
) -> crate::common::RegisterField<
6,
0x1,
1,
0,
sie_ep1_cnt0::DataValid,
sie_ep1_cnt0::DataValid,
SieEp1Cnt0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
6,
0x1,
1,
0,
sie_ep1_cnt0::DataValid,
sie_ep1_cnt0::DataValid,
SieEp1Cnt0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This bit selects the DATA packet\'s toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit."]
#[inline(always)]
pub fn data_toggle(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEp1Cnt0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEp1Cnt0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp1Cnt0 {
#[inline(always)]
fn default() -> SieEp1Cnt0 {
<crate::RegValueT<SieEp1Cnt0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sie_ep1_cnt0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DataValid_SPEC;
pub type DataValid = crate::EnumBitfieldStruct<u8, DataValid_SPEC>;
impl DataValid {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const DATA_ERROR: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const DATA_VALID: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp1Cnt1_SPEC;
impl crate::sealed::RegSpec for SieEp1Cnt1_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint count register"]
pub type SieEp1Cnt1 = crate::RegValueT<SieEp1Cnt1_SPEC>;
impl SieEp1Cnt1 {
#[doc = "These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."]
#[inline(always)]
pub fn data_count(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, SieEp1Cnt1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,SieEp1Cnt1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp1Cnt1 {
#[inline(always)]
fn default() -> SieEp1Cnt1 {
<crate::RegValueT<SieEp1Cnt1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp1Cr0_SPEC;
impl crate::sealed::RegSpec for SieEp1Cr0_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint\'s control Register"]
pub type SieEp1Cr0 = crate::RegValueT<SieEp1Cr0_SPEC>;
impl SieEp1Cr0 {
#[doc = "The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."]
#[inline(always)]
pub fn mode(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
sie_ep1_cr0::Mode,
sie_ep1_cr0::Mode,
SieEp1Cr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
sie_ep1_cr0::Mode,
sie_ep1_cr0::Mode,
SieEp1Cr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "The ACK\'d transaction bit is set whenever the SIE engages in a transaction to the register\'s endpoint that completes with an ACK packet. This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn acked_txn(
self,
) -> crate::common::RegisterField<
4,
0x1,
1,
0,
sie_ep1_cr0::AckedTxn,
sie_ep1_cr0::AckedTxn,
SieEp1Cr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x1,
1,
0,
sie_ep1_cr0::AckedTxn,
sie_ep1_cr0::AckedTxn,
SieEp1Cr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK."]
#[inline(always)]
pub fn nak_int_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, SieEp1Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,SieEp1Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID\nerror/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn err_in_txn(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, SieEp1Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,SieEp1Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes."]
#[inline(always)]
pub fn stall(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEp1Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEp1Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp1Cr0 {
#[inline(always)]
fn default() -> SieEp1Cr0 {
<crate::RegValueT<SieEp1Cr0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sie_ep1_cr0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Mode_SPEC;
pub type Mode = crate::EnumBitfieldStruct<u8, Mode_SPEC>;
impl Mode {
#[doc = "Ignore all USB traffic to this endpoint"]
pub const DISABLE: Self = Self::new(0);
#[doc = "SETUP: Accept\nIN: NAK\nOUT: NAK"]
pub const NAK_INOUT: Self = Self::new(1);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: ACK 0B tokens, NAK others"]
pub const STATUS_OUT_ONLY: Self = Self::new(2);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: STALL"]
pub const STALL_INOUT: Self = Self::new(3);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept Isochronous OUT token"]
pub const ISO_OUT: Self = Self::new(5);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Stall"]
pub const STATUS_IN_ONLY: Self = Self::new(6);
#[doc = "SETUP: Ignore\nIN: Accept Isochronous IN token\nOUT: Ignore"]
pub const ISO_IN: Self = Self::new(7);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: NAK"]
pub const NAK_OUT: Self = Self::new(8);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept data and ACK if STALL=0, STALL otherwise. ..."]
pub const ACK_OUT: Self = Self::new(9);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Accept data"]
pub const ACK_OUT_STATUS_IN: Self = Self::new(11);
#[doc = "SETUP: Ignore\nIN: NAK\nOUT: Ignore"]
pub const NAK_IN: Self = Self::new(12);
#[doc = "SETUP: Ignore\nIN: Respond to IN with data if STALL=0, STALL otherwise\nOUT: Ignore"]
pub const ACK_IN: Self = Self::new(13);
#[doc = "SETUP: Accept\nIN: Respond to IN with data\nOUT: ACK 0B tokens, NAK others"]
pub const ACK_IN_STATUS_OUT: Self = Self::new(15);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct AckedTxn_SPEC;
pub type AckedTxn = crate::EnumBitfieldStruct<u8, AckedTxn_SPEC>;
impl AckedTxn {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const ACKED_NO: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const ACKED_YES: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UsbioCr0_SPEC;
impl crate::sealed::RegSpec for UsbioCr0_SPEC {
type DataType = u32;
}
#[doc = "USBIO Control 0 Register"]
pub type UsbioCr0 = crate::RegValueT<UsbioCr0_SPEC>;
impl UsbioCr0 {
#[doc = "Received Data. This read only bit gives the state of the USB differential receiver when IOMODE bit is \'0\' and USB doesn\'t transmit. This bit is valid if USB Device.\nIf D+=D- (SE0), this value is undefined."]
#[inline(always)]
pub fn rd(
self,
) -> crate::common::RegisterField<
0,
0x1,
1,
0,
usbio_cr0::Rd,
usbio_cr0::Rd,
UsbioCr0_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0x1,
1,
0,
usbio_cr0::Rd,
usbio_cr0::Rd,
UsbioCr0_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1."]
#[inline(always)]
pub fn td(
self,
) -> crate::common::RegisterField<
5,
0x1,
1,
0,
usbio_cr0::Td,
usbio_cr0::Td,
UsbioCr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
5,
0x1,
1,
0,
usbio_cr0::Td,
usbio_cr0::Td,
UsbioCr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0."]
#[inline(always)]
pub fn tse0(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, UsbioCr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,UsbioCr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually\ntransmitting is to force a resume state on the bus."]
#[inline(always)]
pub fn ten(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, UsbioCr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,UsbioCr0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for UsbioCr0 {
#[inline(always)]
fn default() -> UsbioCr0 {
<crate::RegValueT<UsbioCr0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod usbio_cr0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Rd_SPEC;
pub type Rd = crate::EnumBitfieldStruct<u8, Rd_SPEC>;
impl Rd {
#[doc = "D+ < D- (K state)"]
pub const DIFF_LOW: Self = Self::new(0);
#[doc = "D+ > D- (J state)"]
pub const DIFF_HIGH: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Td_SPEC;
pub type Td = crate::EnumBitfieldStruct<u8, Td_SPEC>;
impl Td {
#[doc = "Force USB K state (D+ is low D- is high)."]
pub const DIFF_K: Self = Self::new(0);
#[doc = "Force USB J state (D+ is high D- is low)."]
pub const DIFF_J: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UsbioCr2_SPEC;
impl crate::sealed::RegSpec for UsbioCr2_SPEC {
type DataType = u32;
}
#[doc = "USBIO control 2 Register"]
pub type UsbioCr2 = crate::RegValueT<UsbioCr2_SPEC>;
impl UsbioCr2 {
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_5_0(
self,
) -> crate::common::RegisterField<0, 0x3f, 1, 0, u8, u8, UsbioCr2_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x3f,1,0,u8,u8,UsbioCr2_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit enables the device to transmit a packet in response to an internally generated IN packet. When set, one packet will be generated."]
#[inline(always)]
pub fn test_pkt(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, UsbioCr2_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,UsbioCr2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_7(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, UsbioCr2_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,UsbioCr2_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for UsbioCr2 {
#[inline(always)]
fn default() -> UsbioCr2 {
<crate::RegValueT<UsbioCr2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UsbioCr1_SPEC;
impl crate::sealed::RegSpec for UsbioCr1_SPEC {
type DataType = u32;
}
#[doc = "USBIO control 1 Register"]
pub type UsbioCr1 = crate::RegValueT<UsbioCr1_SPEC>;
impl UsbioCr1 {
#[doc = "This read only bit gives the state of the D- pin when IOMODE bit is \'0\' and USB doesn\'t transmit.\nThis bit is \'0\' when USB transmits SE0, and this bit is \'1\' when USB transmits other than SE0.\nThis bit is valid if USB Device."]
#[inline(always)]
pub fn dmo(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, UsbioCr1_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,UsbioCr1_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This read only bit gives the state of the D+ pin when IOMODE bit is \'0\' and USB doesn\'t transmit.\nThis bit displays the output value of D+ pin when USB transmits SE0 or data.\nThis bit is valid if USB Device."]
#[inline(always)]
pub fn dpo(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, UsbioCr1_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,UsbioCr1_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, UsbioCr1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,UsbioCr1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins."]
#[inline(always)]
pub fn iomode(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, UsbioCr1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,UsbioCr1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for UsbioCr1 {
#[inline(always)]
fn default() -> UsbioCr1 {
<crate::RegValueT<UsbioCr1_SPEC> as RegisterValue<_>>::new(32)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DynReconfig_SPEC;
impl crate::sealed::RegSpec for DynReconfig_SPEC {
type DataType = u32;
}
#[doc = "USB Dynamic reconfiguration register"]
pub type DynReconfig = crate::RegValueT<DynReconfig_SPEC>;
impl DynReconfig {
#[doc = "This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP.\nUse 0 for EP1, 1 for EP2, etc."]
#[inline(always)]
pub fn dyn_config_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, DynReconfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,DynReconfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1."]
#[inline(always)]
pub fn dyn_reconfig_epno(
self,
) -> crate::common::RegisterField<1, 0x7, 1, 0, u8, u8, DynReconfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<1,0x7,1,0,u8,u8,DynReconfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit indicates the ready status for the dynamic reconfiguration, when set to 1, indicates the block is ready for reconfiguration."]
#[inline(always)]
pub fn dyn_reconfig_rdy_sts(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, DynReconfig_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4,1,0,DynReconfig_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for DynReconfig {
#[inline(always)]
fn default() -> DynReconfig {
<crate::RegValueT<DynReconfig_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Sof0_SPEC;
impl crate::sealed::RegSpec for Sof0_SPEC {
type DataType = u32;
}
#[doc = "Start Of Frame Register"]
pub type Sof0 = crate::RegValueT<Sof0_SPEC>;
impl Sof0 {
#[doc = "It has the lower 8 bits \\[7:0\\] of the SOF frame number."]
#[inline(always)]
pub fn frame_number(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Sof0_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Sof0_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Sof0 {
#[inline(always)]
fn default() -> Sof0 {
<crate::RegValueT<Sof0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Sof1_SPEC;
impl crate::sealed::RegSpec for Sof1_SPEC {
type DataType = u32;
}
#[doc = "Start Of Frame Register"]
pub type Sof1 = crate::RegValueT<Sof1_SPEC>;
impl Sof1 {
#[doc = "It has the upper 3 bits \\[10:8\\] of the SOF frame number."]
#[inline(always)]
pub fn frame_number_msb(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, Sof1_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,Sof1_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Sof1 {
#[inline(always)]
fn default() -> Sof1 {
<crate::RegValueT<Sof1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp2Cnt0_SPEC;
impl crate::sealed::RegSpec for SieEp2Cnt0_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint count register"]
pub type SieEp2Cnt0 = crate::RegValueT<SieEp2Cnt0_SPEC>;
impl SieEp2Cnt0 {
#[doc = "These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count\\[7:0\\] bits of the CNT1 register. Refer to the CNT1 register for more information."]
#[inline(always)]
pub fn data_count_msb(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, SieEp2Cnt0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,SieEp2Cnt0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used for OUT transactions only and is read only. It is cleared to \'0\' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings."]
#[inline(always)]
pub fn data_valid(
self,
) -> crate::common::RegisterField<
6,
0x1,
1,
0,
sie_ep2_cnt0::DataValid,
sie_ep2_cnt0::DataValid,
SieEp2Cnt0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
6,
0x1,
1,
0,
sie_ep2_cnt0::DataValid,
sie_ep2_cnt0::DataValid,
SieEp2Cnt0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This bit selects the DATA packet\'s toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit."]
#[inline(always)]
pub fn data_toggle(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEp2Cnt0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEp2Cnt0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp2Cnt0 {
#[inline(always)]
fn default() -> SieEp2Cnt0 {
<crate::RegValueT<SieEp2Cnt0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sie_ep2_cnt0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DataValid_SPEC;
pub type DataValid = crate::EnumBitfieldStruct<u8, DataValid_SPEC>;
impl DataValid {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const DATA_ERROR: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const DATA_VALID: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp2Cnt1_SPEC;
impl crate::sealed::RegSpec for SieEp2Cnt1_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint count register"]
pub type SieEp2Cnt1 = crate::RegValueT<SieEp2Cnt1_SPEC>;
impl SieEp2Cnt1 {
#[doc = "These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."]
#[inline(always)]
pub fn data_count(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, SieEp2Cnt1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,SieEp2Cnt1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp2Cnt1 {
#[inline(always)]
fn default() -> SieEp2Cnt1 {
<crate::RegValueT<SieEp2Cnt1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp2Cr0_SPEC;
impl crate::sealed::RegSpec for SieEp2Cr0_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint\'s control Register"]
pub type SieEp2Cr0 = crate::RegValueT<SieEp2Cr0_SPEC>;
impl SieEp2Cr0 {
#[doc = "The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."]
#[inline(always)]
pub fn mode(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
sie_ep2_cr0::Mode,
sie_ep2_cr0::Mode,
SieEp2Cr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
sie_ep2_cr0::Mode,
sie_ep2_cr0::Mode,
SieEp2Cr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "The ACK\'d transaction bit is set whenever the SIE engages in a transaction to the register\'s endpoint that completes with an ACK packet. This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn acked_txn(
self,
) -> crate::common::RegisterField<
4,
0x1,
1,
0,
sie_ep2_cr0::AckedTxn,
sie_ep2_cr0::AckedTxn,
SieEp2Cr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x1,
1,
0,
sie_ep2_cr0::AckedTxn,
sie_ep2_cr0::AckedTxn,
SieEp2Cr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK."]
#[inline(always)]
pub fn nak_int_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, SieEp2Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,SieEp2Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID\nerror/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn err_in_txn(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, SieEp2Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,SieEp2Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes."]
#[inline(always)]
pub fn stall(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEp2Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEp2Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp2Cr0 {
#[inline(always)]
fn default() -> SieEp2Cr0 {
<crate::RegValueT<SieEp2Cr0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sie_ep2_cr0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Mode_SPEC;
pub type Mode = crate::EnumBitfieldStruct<u8, Mode_SPEC>;
impl Mode {
#[doc = "Ignore all USB traffic to this endpoint"]
pub const DISABLE: Self = Self::new(0);
#[doc = "SETUP: Accept\nIN: NAK\nOUT: NAK"]
pub const NAK_INOUT: Self = Self::new(1);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: ACK 0B tokens, NAK others"]
pub const STATUS_OUT_ONLY: Self = Self::new(2);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: STALL"]
pub const STALL_INOUT: Self = Self::new(3);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept Isochronous OUT token"]
pub const ISO_OUT: Self = Self::new(5);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Stall"]
pub const STATUS_IN_ONLY: Self = Self::new(6);
#[doc = "SETUP: Ignore\nIN: Accept Isochronous IN token\nOUT: Ignore"]
pub const ISO_IN: Self = Self::new(7);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: NAK"]
pub const NAK_OUT: Self = Self::new(8);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept data and ACK if STALL=0, STALL otherwise. ..."]
pub const ACK_OUT: Self = Self::new(9);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Accept data"]
pub const ACK_OUT_STATUS_IN: Self = Self::new(11);
#[doc = "SETUP: Ignore\nIN: NAK\nOUT: Ignore"]
pub const NAK_IN: Self = Self::new(12);
#[doc = "SETUP: Ignore\nIN: Respond to IN with data if STALL=0, STALL otherwise\nOUT: Ignore"]
pub const ACK_IN: Self = Self::new(13);
#[doc = "SETUP: Accept\nIN: Respond to IN with data\nOUT: ACK 0B tokens, NAK others"]
pub const ACK_IN_STATUS_OUT: Self = Self::new(15);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct AckedTxn_SPEC;
pub type AckedTxn = crate::EnumBitfieldStruct<u8, AckedTxn_SPEC>;
impl AckedTxn {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const ACKED_NO: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const ACKED_YES: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct OsclkDr0_SPEC;
impl crate::sealed::RegSpec for OsclkDr0_SPEC {
type DataType = u32;
}
#[doc = "Oscillator lock data register 0"]
pub type OsclkDr0 = crate::RegValueT<OsclkDr0_SPEC>;
impl OsclkDr0 {
#[doc = "These bits return the lower 8 bits of the oscillator locking circuits adder output."]
#[inline(always)]
pub fn adder(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, OsclkDr0_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,OsclkDr0_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for OsclkDr0 {
#[inline(always)]
fn default() -> OsclkDr0 {
<crate::RegValueT<OsclkDr0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct OsclkDr1_SPEC;
impl crate::sealed::RegSpec for OsclkDr1_SPEC {
type DataType = u32;
}
#[doc = "Oscillator lock data register 1"]
pub type OsclkDr1 = crate::RegValueT<OsclkDr1_SPEC>;
impl OsclkDr1 {
#[doc = "These bits return the upper 7 bits of the oscillator locking circuits adder output."]
#[inline(always)]
pub fn adder_msb(
self,
) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, OsclkDr1_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x7f,1,0,u8,u8,OsclkDr1_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for OsclkDr1 {
#[inline(always)]
fn default() -> OsclkDr1 {
<crate::RegValueT<OsclkDr1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ep0Cr_SPEC;
impl crate::sealed::RegSpec for Ep0Cr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint0 control Register"]
pub type Ep0Cr = crate::RegValueT<Ep0Cr_SPEC>;
impl Ep0Cr {
#[doc = "The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."]
#[inline(always)]
pub fn mode(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
ep0_cr::Mode,
ep0_cr::Mode,
Ep0Cr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
ep0_cr::Mode,
ep0_cr::Mode,
Ep0Cr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "The ACK\'d transaction bit is set whenever the SIE engages in a transaction to the register\'s endpoint that completes with an ACK packet. This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn acked_txn(
self,
) -> crate::common::RegisterField<
4,
0x1,
1,
0,
ep0_cr::AckedTxn,
ep0_cr::AckedTxn,
Ep0Cr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x1,
1,
0,
ep0_cr::AckedTxn,
ep0_cr::AckedTxn,
Ep0Cr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to \'1\' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the register."]
#[inline(always)]
pub fn out_rcvd(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Ep0Cr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,Ep0Cr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When set this bit indicates a valid IN packet has been received. This bit is updated to \'1\' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK handshake. It is cleared by any writes to the register."]
#[inline(always)]
pub fn in_rcvd(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, Ep0Cr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,Ep0Cr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval. After this interval the bit will remain set until cleared by firmware. While this bit is set to \'1\' the CPU cannot write to the EP0_DRx registers. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. This bit is cleared by any non-locked writes to the register."]
#[inline(always)]
pub fn setup_rcvd(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Ep0Cr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,Ep0Cr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ep0Cr {
#[inline(always)]
fn default() -> Ep0Cr {
<crate::RegValueT<Ep0Cr_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod ep0_cr {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Mode_SPEC;
pub type Mode = crate::EnumBitfieldStruct<u8, Mode_SPEC>;
impl Mode {
#[doc = "Ignore all USB traffic to this endpoint"]
pub const DISABLE: Self = Self::new(0);
#[doc = "SETUP: Accept\nIN: NAK\nOUT: NAK"]
pub const NAK_INOUT: Self = Self::new(1);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: ACK 0B tokens, NAK others"]
pub const STATUS_OUT_ONLY: Self = Self::new(2);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: STALL"]
pub const STALL_INOUT: Self = Self::new(3);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept Isochronous OUT token"]
pub const ISO_OUT: Self = Self::new(5);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Stall"]
pub const STATUS_IN_ONLY: Self = Self::new(6);
#[doc = "SETUP: Ignore\nIN: Accept Isochronous IN token\nOUT: Ignore"]
pub const ISO_IN: Self = Self::new(7);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: NAK"]
pub const NAK_OUT: Self = Self::new(8);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept data and ACK if STALL=0, STALL otherwise. ..."]
pub const ACK_OUT: Self = Self::new(9);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Accept data"]
pub const ACK_OUT_STATUS_IN: Self = Self::new(11);
#[doc = "SETUP: Ignore\nIN: NAK\nOUT: Ignore"]
pub const NAK_IN: Self = Self::new(12);
#[doc = "SETUP: Ignore\nIN: Respond to IN with data if STALL=0, STALL otherwise\nOUT: Ignore"]
pub const ACK_IN: Self = Self::new(13);
#[doc = "SETUP: Accept\nIN: Respond to IN with data\nOUT: ACK 0B tokens, NAK others"]
pub const ACK_IN_STATUS_OUT: Self = Self::new(15);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct AckedTxn_SPEC;
pub type AckedTxn = crate::EnumBitfieldStruct<u8, AckedTxn_SPEC>;
impl AckedTxn {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const ACKED_NO: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const ACKED_YES: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ep0Cnt_SPEC;
impl crate::sealed::RegSpec for Ep0Cnt_SPEC {
type DataType = u32;
}
#[doc = "Endpoint0 count Register"]
pub type Ep0Cnt = crate::RegValueT<Ep0Cnt_SPEC>;
impl Ep0Cnt {
#[doc = "These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10."]
#[inline(always)]
pub fn byte_count(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, Ep0Cnt_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,Ep0Cnt_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used for OUT/SETUP transactions only and is read only. It is cleared to \'0\' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings."]
#[inline(always)]
pub fn data_valid(
self,
) -> crate::common::RegisterField<
6,
0x1,
1,
0,
ep0_cnt::DataValid,
ep0_cnt::DataValid,
Ep0Cnt_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
6,
0x1,
1,
0,
ep0_cnt::DataValid,
ep0_cnt::DataValid,
Ep0Cnt_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This bit selects the DATA packet\'s toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit."]
#[inline(always)]
pub fn data_toggle(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Ep0Cnt_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,Ep0Cnt_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ep0Cnt {
#[inline(always)]
fn default() -> Ep0Cnt {
<crate::RegValueT<Ep0Cnt_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod ep0_cnt {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DataValid_SPEC;
pub type DataValid = crate::EnumBitfieldStruct<u8, DataValid_SPEC>;
impl DataValid {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const DATA_ERROR: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const DATA_VALID: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp3Cnt0_SPEC;
impl crate::sealed::RegSpec for SieEp3Cnt0_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint count register"]
pub type SieEp3Cnt0 = crate::RegValueT<SieEp3Cnt0_SPEC>;
impl SieEp3Cnt0 {
#[doc = "These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count\\[7:0\\] bits of the CNT1 register. Refer to the CNT1 register for more information."]
#[inline(always)]
pub fn data_count_msb(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, SieEp3Cnt0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,SieEp3Cnt0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used for OUT transactions only and is read only. It is cleared to \'0\' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings."]
#[inline(always)]
pub fn data_valid(
self,
) -> crate::common::RegisterField<
6,
0x1,
1,
0,
sie_ep3_cnt0::DataValid,
sie_ep3_cnt0::DataValid,
SieEp3Cnt0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
6,
0x1,
1,
0,
sie_ep3_cnt0::DataValid,
sie_ep3_cnt0::DataValid,
SieEp3Cnt0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This bit selects the DATA packet\'s toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit."]
#[inline(always)]
pub fn data_toggle(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEp3Cnt0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEp3Cnt0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp3Cnt0 {
#[inline(always)]
fn default() -> SieEp3Cnt0 {
<crate::RegValueT<SieEp3Cnt0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sie_ep3_cnt0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DataValid_SPEC;
pub type DataValid = crate::EnumBitfieldStruct<u8, DataValid_SPEC>;
impl DataValid {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const DATA_ERROR: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const DATA_VALID: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp3Cnt1_SPEC;
impl crate::sealed::RegSpec for SieEp3Cnt1_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint count register"]
pub type SieEp3Cnt1 = crate::RegValueT<SieEp3Cnt1_SPEC>;
impl SieEp3Cnt1 {
#[doc = "These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."]
#[inline(always)]
pub fn data_count(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, SieEp3Cnt1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,SieEp3Cnt1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp3Cnt1 {
#[inline(always)]
fn default() -> SieEp3Cnt1 {
<crate::RegValueT<SieEp3Cnt1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp3Cr0_SPEC;
impl crate::sealed::RegSpec for SieEp3Cr0_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint\'s control Register"]
pub type SieEp3Cr0 = crate::RegValueT<SieEp3Cr0_SPEC>;
impl SieEp3Cr0 {
#[doc = "The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."]
#[inline(always)]
pub fn mode(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
sie_ep3_cr0::Mode,
sie_ep3_cr0::Mode,
SieEp3Cr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
sie_ep3_cr0::Mode,
sie_ep3_cr0::Mode,
SieEp3Cr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "The ACK\'d transaction bit is set whenever the SIE engages in a transaction to the register\'s endpoint that completes with an ACK packet. This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn acked_txn(
self,
) -> crate::common::RegisterField<
4,
0x1,
1,
0,
sie_ep3_cr0::AckedTxn,
sie_ep3_cr0::AckedTxn,
SieEp3Cr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x1,
1,
0,
sie_ep3_cr0::AckedTxn,
sie_ep3_cr0::AckedTxn,
SieEp3Cr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK."]
#[inline(always)]
pub fn nak_int_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, SieEp3Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,SieEp3Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID\nerror/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn err_in_txn(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, SieEp3Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,SieEp3Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes."]
#[inline(always)]
pub fn stall(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEp3Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEp3Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp3Cr0 {
#[inline(always)]
fn default() -> SieEp3Cr0 {
<crate::RegValueT<SieEp3Cr0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sie_ep3_cr0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Mode_SPEC;
pub type Mode = crate::EnumBitfieldStruct<u8, Mode_SPEC>;
impl Mode {
#[doc = "Ignore all USB traffic to this endpoint"]
pub const DISABLE: Self = Self::new(0);
#[doc = "SETUP: Accept\nIN: NAK\nOUT: NAK"]
pub const NAK_INOUT: Self = Self::new(1);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: ACK 0B tokens, NAK others"]
pub const STATUS_OUT_ONLY: Self = Self::new(2);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: STALL"]
pub const STALL_INOUT: Self = Self::new(3);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept Isochronous OUT token"]
pub const ISO_OUT: Self = Self::new(5);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Stall"]
pub const STATUS_IN_ONLY: Self = Self::new(6);
#[doc = "SETUP: Ignore\nIN: Accept Isochronous IN token\nOUT: Ignore"]
pub const ISO_IN: Self = Self::new(7);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: NAK"]
pub const NAK_OUT: Self = Self::new(8);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept data and ACK if STALL=0, STALL otherwise. ..."]
pub const ACK_OUT: Self = Self::new(9);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Accept data"]
pub const ACK_OUT_STATUS_IN: Self = Self::new(11);
#[doc = "SETUP: Ignore\nIN: NAK\nOUT: Ignore"]
pub const NAK_IN: Self = Self::new(12);
#[doc = "SETUP: Ignore\nIN: Respond to IN with data if STALL=0, STALL otherwise\nOUT: Ignore"]
pub const ACK_IN: Self = Self::new(13);
#[doc = "SETUP: Accept\nIN: Respond to IN with data\nOUT: ACK 0B tokens, NAK others"]
pub const ACK_IN_STATUS_OUT: Self = Self::new(15);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct AckedTxn_SPEC;
pub type AckedTxn = crate::EnumBitfieldStruct<u8, AckedTxn_SPEC>;
impl AckedTxn {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const ACKED_NO: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const ACKED_YES: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp4Cnt0_SPEC;
impl crate::sealed::RegSpec for SieEp4Cnt0_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint count register"]
pub type SieEp4Cnt0 = crate::RegValueT<SieEp4Cnt0_SPEC>;
impl SieEp4Cnt0 {
#[doc = "These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count\\[7:0\\] bits of the CNT1 register. Refer to the CNT1 register for more information."]
#[inline(always)]
pub fn data_count_msb(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, SieEp4Cnt0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,SieEp4Cnt0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used for OUT transactions only and is read only. It is cleared to \'0\' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings."]
#[inline(always)]
pub fn data_valid(
self,
) -> crate::common::RegisterField<
6,
0x1,
1,
0,
sie_ep4_cnt0::DataValid,
sie_ep4_cnt0::DataValid,
SieEp4Cnt0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
6,
0x1,
1,
0,
sie_ep4_cnt0::DataValid,
sie_ep4_cnt0::DataValid,
SieEp4Cnt0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This bit selects the DATA packet\'s toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit."]
#[inline(always)]
pub fn data_toggle(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEp4Cnt0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEp4Cnt0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp4Cnt0 {
#[inline(always)]
fn default() -> SieEp4Cnt0 {
<crate::RegValueT<SieEp4Cnt0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sie_ep4_cnt0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DataValid_SPEC;
pub type DataValid = crate::EnumBitfieldStruct<u8, DataValid_SPEC>;
impl DataValid {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const DATA_ERROR: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const DATA_VALID: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp4Cnt1_SPEC;
impl crate::sealed::RegSpec for SieEp4Cnt1_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint count register"]
pub type SieEp4Cnt1 = crate::RegValueT<SieEp4Cnt1_SPEC>;
impl SieEp4Cnt1 {
#[doc = "These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."]
#[inline(always)]
pub fn data_count(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, SieEp4Cnt1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,SieEp4Cnt1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp4Cnt1 {
#[inline(always)]
fn default() -> SieEp4Cnt1 {
<crate::RegValueT<SieEp4Cnt1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp4Cr0_SPEC;
impl crate::sealed::RegSpec for SieEp4Cr0_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint\'s control Register"]
pub type SieEp4Cr0 = crate::RegValueT<SieEp4Cr0_SPEC>;
impl SieEp4Cr0 {
#[doc = "The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."]
#[inline(always)]
pub fn mode(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
sie_ep4_cr0::Mode,
sie_ep4_cr0::Mode,
SieEp4Cr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
sie_ep4_cr0::Mode,
sie_ep4_cr0::Mode,
SieEp4Cr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "The ACK\'d transaction bit is set whenever the SIE engages in a transaction to the register\'s endpoint that completes with an ACK packet. This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn acked_txn(
self,
) -> crate::common::RegisterField<
4,
0x1,
1,
0,
sie_ep4_cr0::AckedTxn,
sie_ep4_cr0::AckedTxn,
SieEp4Cr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x1,
1,
0,
sie_ep4_cr0::AckedTxn,
sie_ep4_cr0::AckedTxn,
SieEp4Cr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK."]
#[inline(always)]
pub fn nak_int_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, SieEp4Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,SieEp4Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID\nerror/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn err_in_txn(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, SieEp4Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,SieEp4Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes."]
#[inline(always)]
pub fn stall(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEp4Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEp4Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp4Cr0 {
#[inline(always)]
fn default() -> SieEp4Cr0 {
<crate::RegValueT<SieEp4Cr0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sie_ep4_cr0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Mode_SPEC;
pub type Mode = crate::EnumBitfieldStruct<u8, Mode_SPEC>;
impl Mode {
#[doc = "Ignore all USB traffic to this endpoint"]
pub const DISABLE: Self = Self::new(0);
#[doc = "SETUP: Accept\nIN: NAK\nOUT: NAK"]
pub const NAK_INOUT: Self = Self::new(1);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: ACK 0B tokens, NAK others"]
pub const STATUS_OUT_ONLY: Self = Self::new(2);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: STALL"]
pub const STALL_INOUT: Self = Self::new(3);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept Isochronous OUT token"]
pub const ISO_OUT: Self = Self::new(5);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Stall"]
pub const STATUS_IN_ONLY: Self = Self::new(6);
#[doc = "SETUP: Ignore\nIN: Accept Isochronous IN token\nOUT: Ignore"]
pub const ISO_IN: Self = Self::new(7);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: NAK"]
pub const NAK_OUT: Self = Self::new(8);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept data and ACK if STALL=0, STALL otherwise. ..."]
pub const ACK_OUT: Self = Self::new(9);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Accept data"]
pub const ACK_OUT_STATUS_IN: Self = Self::new(11);
#[doc = "SETUP: Ignore\nIN: NAK\nOUT: Ignore"]
pub const NAK_IN: Self = Self::new(12);
#[doc = "SETUP: Ignore\nIN: Respond to IN with data if STALL=0, STALL otherwise\nOUT: Ignore"]
pub const ACK_IN: Self = Self::new(13);
#[doc = "SETUP: Accept\nIN: Respond to IN with data\nOUT: ACK 0B tokens, NAK others"]
pub const ACK_IN_STATUS_OUT: Self = Self::new(15);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct AckedTxn_SPEC;
pub type AckedTxn = crate::EnumBitfieldStruct<u8, AckedTxn_SPEC>;
impl AckedTxn {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const ACKED_NO: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const ACKED_YES: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp5Cnt0_SPEC;
impl crate::sealed::RegSpec for SieEp5Cnt0_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint count register"]
pub type SieEp5Cnt0 = crate::RegValueT<SieEp5Cnt0_SPEC>;
impl SieEp5Cnt0 {
#[doc = "These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count\\[7:0\\] bits of the CNT1 register. Refer to the CNT1 register for more information."]
#[inline(always)]
pub fn data_count_msb(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, SieEp5Cnt0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,SieEp5Cnt0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used for OUT transactions only and is read only. It is cleared to \'0\' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings."]
#[inline(always)]
pub fn data_valid(
self,
) -> crate::common::RegisterField<
6,
0x1,
1,
0,
sie_ep5_cnt0::DataValid,
sie_ep5_cnt0::DataValid,
SieEp5Cnt0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
6,
0x1,
1,
0,
sie_ep5_cnt0::DataValid,
sie_ep5_cnt0::DataValid,
SieEp5Cnt0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This bit selects the DATA packet\'s toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit."]
#[inline(always)]
pub fn data_toggle(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEp5Cnt0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEp5Cnt0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp5Cnt0 {
#[inline(always)]
fn default() -> SieEp5Cnt0 {
<crate::RegValueT<SieEp5Cnt0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sie_ep5_cnt0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DataValid_SPEC;
pub type DataValid = crate::EnumBitfieldStruct<u8, DataValid_SPEC>;
impl DataValid {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const DATA_ERROR: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const DATA_VALID: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp5Cnt1_SPEC;
impl crate::sealed::RegSpec for SieEp5Cnt1_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint count register"]
pub type SieEp5Cnt1 = crate::RegValueT<SieEp5Cnt1_SPEC>;
impl SieEp5Cnt1 {
#[doc = "These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."]
#[inline(always)]
pub fn data_count(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, SieEp5Cnt1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,SieEp5Cnt1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp5Cnt1 {
#[inline(always)]
fn default() -> SieEp5Cnt1 {
<crate::RegValueT<SieEp5Cnt1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp5Cr0_SPEC;
impl crate::sealed::RegSpec for SieEp5Cr0_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint\'s control Register"]
pub type SieEp5Cr0 = crate::RegValueT<SieEp5Cr0_SPEC>;
impl SieEp5Cr0 {
#[doc = "The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."]
#[inline(always)]
pub fn mode(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
sie_ep5_cr0::Mode,
sie_ep5_cr0::Mode,
SieEp5Cr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
sie_ep5_cr0::Mode,
sie_ep5_cr0::Mode,
SieEp5Cr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "The ACK\'d transaction bit is set whenever the SIE engages in a transaction to the register\'s endpoint that completes with an ACK packet. This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn acked_txn(
self,
) -> crate::common::RegisterField<
4,
0x1,
1,
0,
sie_ep5_cr0::AckedTxn,
sie_ep5_cr0::AckedTxn,
SieEp5Cr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x1,
1,
0,
sie_ep5_cr0::AckedTxn,
sie_ep5_cr0::AckedTxn,
SieEp5Cr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK."]
#[inline(always)]
pub fn nak_int_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, SieEp5Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,SieEp5Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID\nerror/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn err_in_txn(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, SieEp5Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,SieEp5Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes."]
#[inline(always)]
pub fn stall(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEp5Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEp5Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp5Cr0 {
#[inline(always)]
fn default() -> SieEp5Cr0 {
<crate::RegValueT<SieEp5Cr0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sie_ep5_cr0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Mode_SPEC;
pub type Mode = crate::EnumBitfieldStruct<u8, Mode_SPEC>;
impl Mode {
#[doc = "Ignore all USB traffic to this endpoint"]
pub const DISABLE: Self = Self::new(0);
#[doc = "SETUP: Accept\nIN: NAK\nOUT: NAK"]
pub const NAK_INOUT: Self = Self::new(1);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: ACK 0B tokens, NAK others"]
pub const STATUS_OUT_ONLY: Self = Self::new(2);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: STALL"]
pub const STALL_INOUT: Self = Self::new(3);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept Isochronous OUT token"]
pub const ISO_OUT: Self = Self::new(5);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Stall"]
pub const STATUS_IN_ONLY: Self = Self::new(6);
#[doc = "SETUP: Ignore\nIN: Accept Isochronous IN token\nOUT: Ignore"]
pub const ISO_IN: Self = Self::new(7);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: NAK"]
pub const NAK_OUT: Self = Self::new(8);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept data and ACK if STALL=0, STALL otherwise. ..."]
pub const ACK_OUT: Self = Self::new(9);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Accept data"]
pub const ACK_OUT_STATUS_IN: Self = Self::new(11);
#[doc = "SETUP: Ignore\nIN: NAK\nOUT: Ignore"]
pub const NAK_IN: Self = Self::new(12);
#[doc = "SETUP: Ignore\nIN: Respond to IN with data if STALL=0, STALL otherwise\nOUT: Ignore"]
pub const ACK_IN: Self = Self::new(13);
#[doc = "SETUP: Accept\nIN: Respond to IN with data\nOUT: ACK 0B tokens, NAK others"]
pub const ACK_IN_STATUS_OUT: Self = Self::new(15);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct AckedTxn_SPEC;
pub type AckedTxn = crate::EnumBitfieldStruct<u8, AckedTxn_SPEC>;
impl AckedTxn {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const ACKED_NO: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const ACKED_YES: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp6Cnt0_SPEC;
impl crate::sealed::RegSpec for SieEp6Cnt0_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint count register"]
pub type SieEp6Cnt0 = crate::RegValueT<SieEp6Cnt0_SPEC>;
impl SieEp6Cnt0 {
#[doc = "These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count\\[7:0\\] bits of the CNT1 register. Refer to the CNT1 register for more information."]
#[inline(always)]
pub fn data_count_msb(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, SieEp6Cnt0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,SieEp6Cnt0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used for OUT transactions only and is read only. It is cleared to \'0\' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings."]
#[inline(always)]
pub fn data_valid(
self,
) -> crate::common::RegisterField<
6,
0x1,
1,
0,
sie_ep6_cnt0::DataValid,
sie_ep6_cnt0::DataValid,
SieEp6Cnt0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
6,
0x1,
1,
0,
sie_ep6_cnt0::DataValid,
sie_ep6_cnt0::DataValid,
SieEp6Cnt0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This bit selects the DATA packet\'s toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit."]
#[inline(always)]
pub fn data_toggle(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEp6Cnt0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEp6Cnt0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp6Cnt0 {
#[inline(always)]
fn default() -> SieEp6Cnt0 {
<crate::RegValueT<SieEp6Cnt0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sie_ep6_cnt0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DataValid_SPEC;
pub type DataValid = crate::EnumBitfieldStruct<u8, DataValid_SPEC>;
impl DataValid {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const DATA_ERROR: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const DATA_VALID: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp6Cnt1_SPEC;
impl crate::sealed::RegSpec for SieEp6Cnt1_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint count register"]
pub type SieEp6Cnt1 = crate::RegValueT<SieEp6Cnt1_SPEC>;
impl SieEp6Cnt1 {
#[doc = "These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."]
#[inline(always)]
pub fn data_count(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, SieEp6Cnt1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,SieEp6Cnt1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp6Cnt1 {
#[inline(always)]
fn default() -> SieEp6Cnt1 {
<crate::RegValueT<SieEp6Cnt1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp6Cr0_SPEC;
impl crate::sealed::RegSpec for SieEp6Cr0_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint\'s control Register"]
pub type SieEp6Cr0 = crate::RegValueT<SieEp6Cr0_SPEC>;
impl SieEp6Cr0 {
#[doc = "The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."]
#[inline(always)]
pub fn mode(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
sie_ep6_cr0::Mode,
sie_ep6_cr0::Mode,
SieEp6Cr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
sie_ep6_cr0::Mode,
sie_ep6_cr0::Mode,
SieEp6Cr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "The ACK\'d transaction bit is set whenever the SIE engages in a transaction to the register\'s endpoint that completes with an ACK packet. This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn acked_txn(
self,
) -> crate::common::RegisterField<
4,
0x1,
1,
0,
sie_ep6_cr0::AckedTxn,
sie_ep6_cr0::AckedTxn,
SieEp6Cr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x1,
1,
0,
sie_ep6_cr0::AckedTxn,
sie_ep6_cr0::AckedTxn,
SieEp6Cr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK."]
#[inline(always)]
pub fn nak_int_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, SieEp6Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,SieEp6Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID\nerror/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn err_in_txn(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, SieEp6Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,SieEp6Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes."]
#[inline(always)]
pub fn stall(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEp6Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEp6Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp6Cr0 {
#[inline(always)]
fn default() -> SieEp6Cr0 {
<crate::RegValueT<SieEp6Cr0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sie_ep6_cr0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Mode_SPEC;
pub type Mode = crate::EnumBitfieldStruct<u8, Mode_SPEC>;
impl Mode {
#[doc = "Ignore all USB traffic to this endpoint"]
pub const DISABLE: Self = Self::new(0);
#[doc = "SETUP: Accept\nIN: NAK\nOUT: NAK"]
pub const NAK_INOUT: Self = Self::new(1);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: ACK 0B tokens, NAK others"]
pub const STATUS_OUT_ONLY: Self = Self::new(2);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: STALL"]
pub const STALL_INOUT: Self = Self::new(3);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept Isochronous OUT token"]
pub const ISO_OUT: Self = Self::new(5);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Stall"]
pub const STATUS_IN_ONLY: Self = Self::new(6);
#[doc = "SETUP: Ignore\nIN: Accept Isochronous IN token\nOUT: Ignore"]
pub const ISO_IN: Self = Self::new(7);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: NAK"]
pub const NAK_OUT: Self = Self::new(8);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept data and ACK if STALL=0, STALL otherwise. ..."]
pub const ACK_OUT: Self = Self::new(9);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Accept data"]
pub const ACK_OUT_STATUS_IN: Self = Self::new(11);
#[doc = "SETUP: Ignore\nIN: NAK\nOUT: Ignore"]
pub const NAK_IN: Self = Self::new(12);
#[doc = "SETUP: Ignore\nIN: Respond to IN with data if STALL=0, STALL otherwise\nOUT: Ignore"]
pub const ACK_IN: Self = Self::new(13);
#[doc = "SETUP: Accept\nIN: Respond to IN with data\nOUT: ACK 0B tokens, NAK others"]
pub const ACK_IN_STATUS_OUT: Self = Self::new(15);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct AckedTxn_SPEC;
pub type AckedTxn = crate::EnumBitfieldStruct<u8, AckedTxn_SPEC>;
impl AckedTxn {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const ACKED_NO: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const ACKED_YES: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp7Cnt0_SPEC;
impl crate::sealed::RegSpec for SieEp7Cnt0_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint count register"]
pub type SieEp7Cnt0 = crate::RegValueT<SieEp7Cnt0_SPEC>;
impl SieEp7Cnt0 {
#[doc = "These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count\\[7:0\\] bits of the CNT1 register. Refer to the CNT1 register for more information."]
#[inline(always)]
pub fn data_count_msb(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, SieEp7Cnt0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,SieEp7Cnt0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used for OUT transactions only and is read only. It is cleared to \'0\' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings."]
#[inline(always)]
pub fn data_valid(
self,
) -> crate::common::RegisterField<
6,
0x1,
1,
0,
sie_ep7_cnt0::DataValid,
sie_ep7_cnt0::DataValid,
SieEp7Cnt0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
6,
0x1,
1,
0,
sie_ep7_cnt0::DataValid,
sie_ep7_cnt0::DataValid,
SieEp7Cnt0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This bit selects the DATA packet\'s toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit."]
#[inline(always)]
pub fn data_toggle(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEp7Cnt0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEp7Cnt0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp7Cnt0 {
#[inline(always)]
fn default() -> SieEp7Cnt0 {
<crate::RegValueT<SieEp7Cnt0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sie_ep7_cnt0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DataValid_SPEC;
pub type DataValid = crate::EnumBitfieldStruct<u8, DataValid_SPEC>;
impl DataValid {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const DATA_ERROR: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const DATA_VALID: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp7Cnt1_SPEC;
impl crate::sealed::RegSpec for SieEp7Cnt1_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint count register"]
pub type SieEp7Cnt1 = crate::RegValueT<SieEp7Cnt1_SPEC>;
impl SieEp7Cnt1 {
#[doc = "These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."]
#[inline(always)]
pub fn data_count(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, SieEp7Cnt1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,SieEp7Cnt1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp7Cnt1 {
#[inline(always)]
fn default() -> SieEp7Cnt1 {
<crate::RegValueT<SieEp7Cnt1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp7Cr0_SPEC;
impl crate::sealed::RegSpec for SieEp7Cr0_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint\'s control Register"]
pub type SieEp7Cr0 = crate::RegValueT<SieEp7Cr0_SPEC>;
impl SieEp7Cr0 {
#[doc = "The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."]
#[inline(always)]
pub fn mode(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
sie_ep7_cr0::Mode,
sie_ep7_cr0::Mode,
SieEp7Cr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
sie_ep7_cr0::Mode,
sie_ep7_cr0::Mode,
SieEp7Cr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "The ACK\'d transaction bit is set whenever the SIE engages in a transaction to the register\'s endpoint that completes with an ACK packet. This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn acked_txn(
self,
) -> crate::common::RegisterField<
4,
0x1,
1,
0,
sie_ep7_cr0::AckedTxn,
sie_ep7_cr0::AckedTxn,
SieEp7Cr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x1,
1,
0,
sie_ep7_cr0::AckedTxn,
sie_ep7_cr0::AckedTxn,
SieEp7Cr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK."]
#[inline(always)]
pub fn nak_int_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, SieEp7Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,SieEp7Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID\nerror/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn err_in_txn(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, SieEp7Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,SieEp7Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes."]
#[inline(always)]
pub fn stall(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEp7Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEp7Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp7Cr0 {
#[inline(always)]
fn default() -> SieEp7Cr0 {
<crate::RegValueT<SieEp7Cr0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sie_ep7_cr0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Mode_SPEC;
pub type Mode = crate::EnumBitfieldStruct<u8, Mode_SPEC>;
impl Mode {
#[doc = "Ignore all USB traffic to this endpoint"]
pub const DISABLE: Self = Self::new(0);
#[doc = "SETUP: Accept\nIN: NAK\nOUT: NAK"]
pub const NAK_INOUT: Self = Self::new(1);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: ACK 0B tokens, NAK others"]
pub const STATUS_OUT_ONLY: Self = Self::new(2);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: STALL"]
pub const STALL_INOUT: Self = Self::new(3);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept Isochronous OUT token"]
pub const ISO_OUT: Self = Self::new(5);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Stall"]
pub const STATUS_IN_ONLY: Self = Self::new(6);
#[doc = "SETUP: Ignore\nIN: Accept Isochronous IN token\nOUT: Ignore"]
pub const ISO_IN: Self = Self::new(7);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: NAK"]
pub const NAK_OUT: Self = Self::new(8);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept data and ACK if STALL=0, STALL otherwise. ..."]
pub const ACK_OUT: Self = Self::new(9);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Accept data"]
pub const ACK_OUT_STATUS_IN: Self = Self::new(11);
#[doc = "SETUP: Ignore\nIN: NAK\nOUT: Ignore"]
pub const NAK_IN: Self = Self::new(12);
#[doc = "SETUP: Ignore\nIN: Respond to IN with data if STALL=0, STALL otherwise\nOUT: Ignore"]
pub const ACK_IN: Self = Self::new(13);
#[doc = "SETUP: Accept\nIN: Respond to IN with data\nOUT: ACK 0B tokens, NAK others"]
pub const ACK_IN_STATUS_OUT: Self = Self::new(15);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct AckedTxn_SPEC;
pub type AckedTxn = crate::EnumBitfieldStruct<u8, AckedTxn_SPEC>;
impl AckedTxn {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const ACKED_NO: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const ACKED_YES: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp8Cnt0_SPEC;
impl crate::sealed::RegSpec for SieEp8Cnt0_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint count register"]
pub type SieEp8Cnt0 = crate::RegValueT<SieEp8Cnt0_SPEC>;
impl SieEp8Cnt0 {
#[doc = "These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count\\[7:0\\] bits of the CNT1 register. Refer to the CNT1 register for more information."]
#[inline(always)]
pub fn data_count_msb(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, SieEp8Cnt0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,SieEp8Cnt0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used for OUT transactions only and is read only. It is cleared to \'0\' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings."]
#[inline(always)]
pub fn data_valid(
self,
) -> crate::common::RegisterField<
6,
0x1,
1,
0,
sie_ep8_cnt0::DataValid,
sie_ep8_cnt0::DataValid,
SieEp8Cnt0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
6,
0x1,
1,
0,
sie_ep8_cnt0::DataValid,
sie_ep8_cnt0::DataValid,
SieEp8Cnt0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This bit selects the DATA packet\'s toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit."]
#[inline(always)]
pub fn data_toggle(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEp8Cnt0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEp8Cnt0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp8Cnt0 {
#[inline(always)]
fn default() -> SieEp8Cnt0 {
<crate::RegValueT<SieEp8Cnt0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sie_ep8_cnt0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DataValid_SPEC;
pub type DataValid = crate::EnumBitfieldStruct<u8, DataValid_SPEC>;
impl DataValid {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const DATA_ERROR: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const DATA_VALID: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp8Cnt1_SPEC;
impl crate::sealed::RegSpec for SieEp8Cnt1_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint count register"]
pub type SieEp8Cnt1 = crate::RegValueT<SieEp8Cnt1_SPEC>;
impl SieEp8Cnt1 {
#[doc = "These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction."]
#[inline(always)]
pub fn data_count(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, SieEp8Cnt1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,SieEp8Cnt1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp8Cnt1 {
#[inline(always)]
fn default() -> SieEp8Cnt1 {
<crate::RegValueT<SieEp8Cnt1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SieEp8Cr0_SPEC;
impl crate::sealed::RegSpec for SieEp8Cr0_SPEC {
type DataType = u32;
}
#[doc = "Non-control endpoint\'s control Register"]
pub type SieEp8Cr0 = crate::RegValueT<SieEp8Cr0_SPEC>;
impl SieEp8Cr0 {
#[doc = "The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint."]
#[inline(always)]
pub fn mode(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
sie_ep8_cr0::Mode,
sie_ep8_cr0::Mode,
SieEp8Cr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
sie_ep8_cr0::Mode,
sie_ep8_cr0::Mode,
SieEp8Cr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "The ACK\'d transaction bit is set whenever the SIE engages in a transaction to the register\'s endpoint that completes with an ACK packet. This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn acked_txn(
self,
) -> crate::common::RegisterField<
4,
0x1,
1,
0,
sie_ep8_cr0::AckedTxn,
sie_ep8_cr0::AckedTxn,
SieEp8Cr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x1,
1,
0,
sie_ep8_cr0::AckedTxn,
sie_ep8_cr0::AckedTxn,
SieEp8Cr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK."]
#[inline(always)]
pub fn nak_int_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, SieEp8Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,SieEp8Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID\nerror/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register."]
#[inline(always)]
pub fn err_in_txn(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, SieEp8Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,SieEp8Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes."]
#[inline(always)]
pub fn stall(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SieEp8Cr0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SieEp8Cr0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SieEp8Cr0 {
#[inline(always)]
fn default() -> SieEp8Cr0 {
<crate::RegValueT<SieEp8Cr0_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sie_ep8_cr0 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Mode_SPEC;
pub type Mode = crate::EnumBitfieldStruct<u8, Mode_SPEC>;
impl Mode {
#[doc = "Ignore all USB traffic to this endpoint"]
pub const DISABLE: Self = Self::new(0);
#[doc = "SETUP: Accept\nIN: NAK\nOUT: NAK"]
pub const NAK_INOUT: Self = Self::new(1);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: ACK 0B tokens, NAK others"]
pub const STATUS_OUT_ONLY: Self = Self::new(2);
#[doc = "SETUP: Accept\nIN: STALL\nOUT: STALL"]
pub const STALL_INOUT: Self = Self::new(3);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept Isochronous OUT token"]
pub const ISO_OUT: Self = Self::new(5);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Stall"]
pub const STATUS_IN_ONLY: Self = Self::new(6);
#[doc = "SETUP: Ignore\nIN: Accept Isochronous IN token\nOUT: Ignore"]
pub const ISO_IN: Self = Self::new(7);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: NAK"]
pub const NAK_OUT: Self = Self::new(8);
#[doc = "SETUP: Ignore\nIN: Ignore\nOUT: Accept data and ACK if STALL=0, STALL otherwise. ..."]
pub const ACK_OUT: Self = Self::new(9);
#[doc = "SETUP: Accept\nIN: Respond with 0B data\nOUT: Accept data"]
pub const ACK_OUT_STATUS_IN: Self = Self::new(11);
#[doc = "SETUP: Ignore\nIN: NAK\nOUT: Ignore"]
pub const NAK_IN: Self = Self::new(12);
#[doc = "SETUP: Ignore\nIN: Respond to IN with data if STALL=0, STALL otherwise\nOUT: Ignore"]
pub const ACK_IN: Self = Self::new(13);
#[doc = "SETUP: Accept\nIN: Respond to IN with data\nOUT: ACK 0B tokens, NAK others"]
pub const ACK_IN_STATUS_OUT: Self = Self::new(15);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct AckedTxn_SPEC;
pub type AckedTxn = crate::EnumBitfieldStruct<u8, AckedTxn_SPEC>;
impl AckedTxn {
#[doc = "No ACK\'d transactions since bit was last cleared."]
pub const ACKED_NO: Self = Self::new(0);
#[doc = "Indicates a transaction ended with an ACK."]
pub const ACKED_YES: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp1Cfg_SPEC;
impl crate::sealed::RegSpec for ArbEp1Cfg_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Configuration Register *1"]
pub type ArbEp1Cfg = crate::RegValueT<ArbEp1Cfg_SPEC>;
impl ArbEp1Cfg {
#[doc = "Indication that Endpoint Packet Data is Ready in Main memory"]
#[inline(always)]
pub fn in_data_rdy(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp1Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbEp1Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated."]
#[inline(always)]
pub fn dma_req(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp1Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbEp1Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware"]
#[inline(always)]
pub fn crc_bypass(
self,
) -> crate::common::RegisterField<
2,
0x1,
1,
0,
arb_ep1_cfg::CrcBypass,
arb_ep1_cfg::CrcBypass,
ArbEp1Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0x1,
1,
0,
arb_ep1_cfg::CrcBypass,
arb_ep1_cfg::CrcBypass,
ArbEp1Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction."]
#[inline(always)]
pub fn reset_ptr(
self,
) -> crate::common::RegisterField<
3,
0x1,
1,
0,
arb_ep1_cfg::ResetPtr,
arb_ep1_cfg::ResetPtr,
ArbEp1Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
3,
0x1,
1,
0,
arb_ep1_cfg::ResetPtr,
arb_ep1_cfg::ResetPtr,
ArbEp1Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbEp1Cfg {
#[inline(always)]
fn default() -> ArbEp1Cfg {
<crate::RegValueT<ArbEp1Cfg_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod arb_ep1_cfg {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CrcBypass_SPEC;
pub type CrcBypass = crate::EnumBitfieldStruct<u8, CrcBypass_SPEC>;
impl CrcBypass {
#[doc = "No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s"]
pub const CRC_NORMAL: Self = Self::new(0);
#[doc = "CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s"]
pub const CRC_BYPASS: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ResetPtr_SPEC;
pub type ResetPtr = crate::EnumBitfieldStruct<u8, ResetPtr_SPEC>;
impl ResetPtr {
#[doc = "Do not Reset Pointer; Krypton Backward compatibility mode"]
pub const RESET_KRYPTON: Self = Self::new(0);
#[doc = "Reset Pointer; recommended value for reduction of CPU Configuration Writes."]
pub const RESET_NORMAL: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp1IntEn_SPEC;
impl crate::sealed::RegSpec for ArbEp1IntEn_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Interrupt Enable Register *1"]
pub type ArbEp1IntEn = crate::RegValueT<ArbEp1IntEn_SPEC>;
impl ArbEp1IntEn {
#[doc = "IN Endpoint Local Buffer Full Enable"]
#[inline(always)]
pub fn in_buf_full_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp1IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbEp1IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Grant Enable"]
#[inline(always)]
pub fn dma_gnt_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp1IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,ArbEp1IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Overflow Enable"]
#[inline(always)]
pub fn buf_over_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbEp1IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,ArbEp1IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Underflow Enable"]
#[inline(always)]
pub fn buf_under_en(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbEp1IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,ArbEp1IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Error in Transaction Interrupt Enable"]
#[inline(always)]
pub fn err_int_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ArbEp1IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,ArbEp1IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Terminated Enable"]
#[inline(always)]
pub fn dma_termin_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbEp1IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,ArbEp1IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbEp1IntEn {
#[inline(always)]
fn default() -> ArbEp1IntEn {
<crate::RegValueT<ArbEp1IntEn_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp1Sr_SPEC;
impl crate::sealed::RegSpec for ArbEp1Sr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Interrupt Enable Register *1"]
pub type ArbEp1Sr = crate::RegValueT<ArbEp1Sr_SPEC>;
impl ArbEp1Sr {
#[doc = "IN Endpoint Local Buffer Full Interrupt"]
#[inline(always)]
pub fn in_buf_full(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp1Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbEp1Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Grant Interrupt"]
#[inline(always)]
pub fn dma_gnt(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp1Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbEp1Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Overflow Interrupt"]
#[inline(always)]
pub fn buf_over(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbEp1Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,ArbEp1Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Underflow Interrupt"]
#[inline(always)]
pub fn buf_under(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbEp1Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,ArbEp1Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Terminated Interrupt"]
#[inline(always)]
pub fn dma_termin(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbEp1Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,ArbEp1Sr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbEp1Sr {
#[inline(always)]
fn default() -> ArbEp1Sr {
<crate::RegValueT<ArbEp1Sr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw1Wa_SPEC;
impl crate::sealed::RegSpec for ArbRw1Wa_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *1, *2"]
pub type ArbRw1Wa = crate::RegValueT<ArbRw1Wa_SPEC>;
impl ArbRw1Wa {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw1Wa_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw1Wa_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw1Wa {
#[inline(always)]
fn default() -> ArbRw1Wa {
<crate::RegValueT<ArbRw1Wa_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw1WaMsb_SPEC;
impl crate::sealed::RegSpec for ArbRw1WaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *1, *2"]
pub type ArbRw1WaMsb = crate::RegValueT<ArbRw1WaMsb_SPEC>;
impl ArbRw1WaMsb {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbRw1WaMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbRw1WaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw1WaMsb {
#[inline(always)]
fn default() -> ArbRw1WaMsb {
<crate::RegValueT<ArbRw1WaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw1Ra_SPEC;
impl crate::sealed::RegSpec for ArbRw1Ra_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1, *2"]
pub type ArbRw1Ra = crate::RegValueT<ArbRw1Ra_SPEC>;
impl ArbRw1Ra {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw1Ra_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw1Ra_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw1Ra {
#[inline(always)]
fn default() -> ArbRw1Ra {
<crate::RegValueT<ArbRw1Ra_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw1RaMsb_SPEC;
impl crate::sealed::RegSpec for ArbRw1RaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1, *2"]
pub type ArbRw1RaMsb = crate::RegValueT<ArbRw1RaMsb_SPEC>;
impl ArbRw1RaMsb {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbRw1RaMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbRw1RaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw1RaMsb {
#[inline(always)]
fn default() -> ArbRw1RaMsb {
<crate::RegValueT<ArbRw1RaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw1Dr_SPEC;
impl crate::sealed::RegSpec for ArbRw1Dr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Data Register"]
pub type ArbRw1Dr = crate::RegValueT<ArbRw1Dr_SPEC>;
impl ArbRw1Dr {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw1Dr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw1Dr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw1Dr {
#[inline(always)]
fn default() -> ArbRw1Dr {
<crate::RegValueT<ArbRw1Dr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct BufSize_SPEC;
impl crate::sealed::RegSpec for BufSize_SPEC {
type DataType = u32;
}
#[doc = "Dedicated Endpoint Buffer Size Register *1"]
pub type BufSize = crate::RegValueT<BufSize_SPEC>;
impl BufSize {
#[doc = "Buffer size for IN Endpoints."]
#[inline(always)]
pub fn in_buf(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, BufSize_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,BufSize_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Buffer size for OUT Endpoints."]
#[inline(always)]
pub fn out_buf(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, BufSize_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0xf,1,0,u8,u8,BufSize_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for BufSize {
#[inline(always)]
fn default() -> BufSize {
<crate::RegValueT<BufSize_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EpActive_SPEC;
impl crate::sealed::RegSpec for EpActive_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Active Indication Register *1"]
pub type EpActive = crate::RegValueT<EpActive_SPEC>;
impl EpActive {
#[doc = "Indicates that Endpoint is currently active."]
#[inline(always)]
pub fn ep1_act(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, EpActive_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,EpActive_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates that Endpoint is currently active."]
#[inline(always)]
pub fn ep2_act(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, EpActive_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,EpActive_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates that Endpoint is currently active."]
#[inline(always)]
pub fn ep3_act(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, EpActive_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,EpActive_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates that Endpoint is currently active."]
#[inline(always)]
pub fn ep4_act(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, EpActive_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,EpActive_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates that Endpoint is currently active."]
#[inline(always)]
pub fn ep5_act(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, EpActive_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,EpActive_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates that Endpoint is currently active."]
#[inline(always)]
pub fn ep6_act(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, EpActive_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,EpActive_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates that Endpoint is currently active."]
#[inline(always)]
pub fn ep7_act(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, EpActive_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,EpActive_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates that Endpoint is currently active."]
#[inline(always)]
pub fn ep8_act(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, EpActive_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,EpActive_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for EpActive {
#[inline(always)]
fn default() -> EpActive {
<crate::RegValueT<EpActive_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EpType_SPEC;
impl crate::sealed::RegSpec for EpType_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Type (IN/OUT) Indication *1"]
pub type EpType = crate::RegValueT<EpType_SPEC>;
impl EpType {
#[doc = "Endpoint Type Indication."]
#[inline(always)]
pub fn ep1_typ(
self,
) -> crate::common::RegisterField<
0,
0x1,
1,
0,
ep_type::Ep1Typ,
ep_type::Ep1Typ,
EpType_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1,
1,
0,
ep_type::Ep1Typ,
ep_type::Ep1Typ,
EpType_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Endpoint Type Indication."]
#[inline(always)]
pub fn ep2_typ(
self,
) -> crate::common::RegisterField<
1,
0x1,
1,
0,
ep_type::Ep2Typ,
ep_type::Ep2Typ,
EpType_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
1,
0x1,
1,
0,
ep_type::Ep2Typ,
ep_type::Ep2Typ,
EpType_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Endpoint Type Indication."]
#[inline(always)]
pub fn ep3_typ(
self,
) -> crate::common::RegisterField<
2,
0x1,
1,
0,
ep_type::Ep3Typ,
ep_type::Ep3Typ,
EpType_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0x1,
1,
0,
ep_type::Ep3Typ,
ep_type::Ep3Typ,
EpType_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Endpoint Type Indication."]
#[inline(always)]
pub fn ep4_typ(
self,
) -> crate::common::RegisterField<
3,
0x1,
1,
0,
ep_type::Ep4Typ,
ep_type::Ep4Typ,
EpType_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
3,
0x1,
1,
0,
ep_type::Ep4Typ,
ep_type::Ep4Typ,
EpType_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Endpoint Type Indication."]
#[inline(always)]
pub fn ep5_typ(
self,
) -> crate::common::RegisterField<
4,
0x1,
1,
0,
ep_type::Ep5Typ,
ep_type::Ep5Typ,
EpType_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x1,
1,
0,
ep_type::Ep5Typ,
ep_type::Ep5Typ,
EpType_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Endpoint Type Indication."]
#[inline(always)]
pub fn ep6_typ(
self,
) -> crate::common::RegisterField<
5,
0x1,
1,
0,
ep_type::Ep6Typ,
ep_type::Ep6Typ,
EpType_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
5,
0x1,
1,
0,
ep_type::Ep6Typ,
ep_type::Ep6Typ,
EpType_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Endpoint Type Indication."]
#[inline(always)]
pub fn ep7_typ(
self,
) -> crate::common::RegisterField<
6,
0x1,
1,
0,
ep_type::Ep7Typ,
ep_type::Ep7Typ,
EpType_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
6,
0x1,
1,
0,
ep_type::Ep7Typ,
ep_type::Ep7Typ,
EpType_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Endpoint Type Indication."]
#[inline(always)]
pub fn ep8_typ(
self,
) -> crate::common::RegisterField<
7,
0x1,
1,
0,
ep_type::Ep8Typ,
ep_type::Ep8Typ,
EpType_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
7,
0x1,
1,
0,
ep_type::Ep8Typ,
ep_type::Ep8Typ,
EpType_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for EpType {
#[inline(always)]
fn default() -> EpType {
<crate::RegValueT<EpType_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod ep_type {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Ep1Typ_SPEC;
pub type Ep1Typ = crate::EnumBitfieldStruct<u8, Ep1Typ_SPEC>;
impl Ep1Typ {
#[doc = "IN outpoint"]
pub const EP_IN: Self = Self::new(0);
#[doc = "OUT outpoint"]
pub const EP_OUT: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Ep2Typ_SPEC;
pub type Ep2Typ = crate::EnumBitfieldStruct<u8, Ep2Typ_SPEC>;
impl Ep2Typ {
#[doc = "IN outpoint"]
pub const EP_IN: Self = Self::new(0);
#[doc = "OUT outpoint"]
pub const EP_OUT: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Ep3Typ_SPEC;
pub type Ep3Typ = crate::EnumBitfieldStruct<u8, Ep3Typ_SPEC>;
impl Ep3Typ {
#[doc = "IN outpoint"]
pub const EP_IN: Self = Self::new(0);
#[doc = "OUT outpoint"]
pub const EP_OUT: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Ep4Typ_SPEC;
pub type Ep4Typ = crate::EnumBitfieldStruct<u8, Ep4Typ_SPEC>;
impl Ep4Typ {
#[doc = "IN outpoint"]
pub const EP_IN: Self = Self::new(0);
#[doc = "OUT outpoint"]
pub const EP_OUT: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Ep5Typ_SPEC;
pub type Ep5Typ = crate::EnumBitfieldStruct<u8, Ep5Typ_SPEC>;
impl Ep5Typ {
#[doc = "IN outpoint"]
pub const EP_IN: Self = Self::new(0);
#[doc = "OUT outpoint"]
pub const EP_OUT: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Ep6Typ_SPEC;
pub type Ep6Typ = crate::EnumBitfieldStruct<u8, Ep6Typ_SPEC>;
impl Ep6Typ {
#[doc = "IN outpoint"]
pub const EP_IN: Self = Self::new(0);
#[doc = "OUT outpoint"]
pub const EP_OUT: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Ep7Typ_SPEC;
pub type Ep7Typ = crate::EnumBitfieldStruct<u8, Ep7Typ_SPEC>;
impl Ep7Typ {
#[doc = "IN outpoint"]
pub const EP_IN: Self = Self::new(0);
#[doc = "OUT outpoint"]
pub const EP_OUT: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Ep8Typ_SPEC;
pub type Ep8Typ = crate::EnumBitfieldStruct<u8, Ep8Typ_SPEC>;
impl Ep8Typ {
#[doc = "IN outpoint"]
pub const EP_IN: Self = Self::new(0);
#[doc = "OUT outpoint"]
pub const EP_OUT: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp2Cfg_SPEC;
impl crate::sealed::RegSpec for ArbEp2Cfg_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Configuration Register *1"]
pub type ArbEp2Cfg = crate::RegValueT<ArbEp2Cfg_SPEC>;
impl ArbEp2Cfg {
#[doc = "Indication that Endpoint Packet Data is Ready in Main memory"]
#[inline(always)]
pub fn in_data_rdy(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp2Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbEp2Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated."]
#[inline(always)]
pub fn dma_req(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp2Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbEp2Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware"]
#[inline(always)]
pub fn crc_bypass(
self,
) -> crate::common::RegisterField<
2,
0x1,
1,
0,
arb_ep2_cfg::CrcBypass,
arb_ep2_cfg::CrcBypass,
ArbEp2Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0x1,
1,
0,
arb_ep2_cfg::CrcBypass,
arb_ep2_cfg::CrcBypass,
ArbEp2Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction."]
#[inline(always)]
pub fn reset_ptr(
self,
) -> crate::common::RegisterField<
3,
0x1,
1,
0,
arb_ep2_cfg::ResetPtr,
arb_ep2_cfg::ResetPtr,
ArbEp2Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
3,
0x1,
1,
0,
arb_ep2_cfg::ResetPtr,
arb_ep2_cfg::ResetPtr,
ArbEp2Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbEp2Cfg {
#[inline(always)]
fn default() -> ArbEp2Cfg {
<crate::RegValueT<ArbEp2Cfg_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod arb_ep2_cfg {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CrcBypass_SPEC;
pub type CrcBypass = crate::EnumBitfieldStruct<u8, CrcBypass_SPEC>;
impl CrcBypass {
#[doc = "No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s"]
pub const CRC_NORMAL: Self = Self::new(0);
#[doc = "CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s"]
pub const CRC_BYPASS: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ResetPtr_SPEC;
pub type ResetPtr = crate::EnumBitfieldStruct<u8, ResetPtr_SPEC>;
impl ResetPtr {
#[doc = "Do not Reset Pointer; Krypton Backward compatibility mode"]
pub const RESET_KRYPTON: Self = Self::new(0);
#[doc = "Reset Pointer; recommended value for reduction of CPU Configuration Writes."]
pub const RESET_NORMAL: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp2IntEn_SPEC;
impl crate::sealed::RegSpec for ArbEp2IntEn_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Interrupt Enable Register *1"]
pub type ArbEp2IntEn = crate::RegValueT<ArbEp2IntEn_SPEC>;
impl ArbEp2IntEn {
#[doc = "IN Endpoint Local Buffer Full Enable"]
#[inline(always)]
pub fn in_buf_full_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp2IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbEp2IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Grant Enable"]
#[inline(always)]
pub fn dma_gnt_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp2IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,ArbEp2IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Overflow Enable"]
#[inline(always)]
pub fn buf_over_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbEp2IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,ArbEp2IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Underflow Enable"]
#[inline(always)]
pub fn buf_under_en(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbEp2IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,ArbEp2IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Error in Transaction Interrupt Enable"]
#[inline(always)]
pub fn err_int_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ArbEp2IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,ArbEp2IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Terminated Enable"]
#[inline(always)]
pub fn dma_termin_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbEp2IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,ArbEp2IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbEp2IntEn {
#[inline(always)]
fn default() -> ArbEp2IntEn {
<crate::RegValueT<ArbEp2IntEn_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp2Sr_SPEC;
impl crate::sealed::RegSpec for ArbEp2Sr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Interrupt Enable Register *1"]
pub type ArbEp2Sr = crate::RegValueT<ArbEp2Sr_SPEC>;
impl ArbEp2Sr {
#[doc = "IN Endpoint Local Buffer Full Interrupt"]
#[inline(always)]
pub fn in_buf_full(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp2Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbEp2Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Grant Interrupt"]
#[inline(always)]
pub fn dma_gnt(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp2Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbEp2Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Overflow Interrupt"]
#[inline(always)]
pub fn buf_over(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbEp2Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,ArbEp2Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Underflow Interrupt"]
#[inline(always)]
pub fn buf_under(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbEp2Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,ArbEp2Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Terminated Interrupt"]
#[inline(always)]
pub fn dma_termin(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbEp2Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,ArbEp2Sr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbEp2Sr {
#[inline(always)]
fn default() -> ArbEp2Sr {
<crate::RegValueT<ArbEp2Sr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw2Wa_SPEC;
impl crate::sealed::RegSpec for ArbRw2Wa_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *1, *2"]
pub type ArbRw2Wa = crate::RegValueT<ArbRw2Wa_SPEC>;
impl ArbRw2Wa {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw2Wa_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw2Wa_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw2Wa {
#[inline(always)]
fn default() -> ArbRw2Wa {
<crate::RegValueT<ArbRw2Wa_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw2WaMsb_SPEC;
impl crate::sealed::RegSpec for ArbRw2WaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *1, *2"]
pub type ArbRw2WaMsb = crate::RegValueT<ArbRw2WaMsb_SPEC>;
impl ArbRw2WaMsb {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbRw2WaMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbRw2WaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw2WaMsb {
#[inline(always)]
fn default() -> ArbRw2WaMsb {
<crate::RegValueT<ArbRw2WaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw2Ra_SPEC;
impl crate::sealed::RegSpec for ArbRw2Ra_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1, *2"]
pub type ArbRw2Ra = crate::RegValueT<ArbRw2Ra_SPEC>;
impl ArbRw2Ra {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw2Ra_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw2Ra_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw2Ra {
#[inline(always)]
fn default() -> ArbRw2Ra {
<crate::RegValueT<ArbRw2Ra_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw2RaMsb_SPEC;
impl crate::sealed::RegSpec for ArbRw2RaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1, *2"]
pub type ArbRw2RaMsb = crate::RegValueT<ArbRw2RaMsb_SPEC>;
impl ArbRw2RaMsb {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbRw2RaMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbRw2RaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw2RaMsb {
#[inline(always)]
fn default() -> ArbRw2RaMsb {
<crate::RegValueT<ArbRw2RaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw2Dr_SPEC;
impl crate::sealed::RegSpec for ArbRw2Dr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Data Register"]
pub type ArbRw2Dr = crate::RegValueT<ArbRw2Dr_SPEC>;
impl ArbRw2Dr {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw2Dr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw2Dr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw2Dr {
#[inline(always)]
fn default() -> ArbRw2Dr {
<crate::RegValueT<ArbRw2Dr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbCfg_SPEC;
impl crate::sealed::RegSpec for ArbCfg_SPEC {
type DataType = u32;
}
#[doc = "Arbiter Configuration Register *1"]
pub type ArbCfg = crate::RegValueT<ArbCfg_SPEC>;
impl ArbCfg {
#[doc = "Enables Auto Memory Configuration. Manual memory configuration by default."]
#[inline(always)]
pub fn auto_mem(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ArbCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,ArbCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "DMA Access Configuration."]
#[inline(always)]
pub fn dma_cfg(
self,
) -> crate::common::RegisterField<
5,
0x3,
1,
0,
arb_cfg::DmaCfg,
arb_cfg::DmaCfg,
ArbCfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
5,
0x3,
1,
0,
arb_cfg::DmaCfg,
arb_cfg::DmaCfg,
ArbCfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required."]
#[inline(always)]
pub fn cfg_cmp(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, ArbCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,ArbCfg_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbCfg {
#[inline(always)]
fn default() -> ArbCfg {
<crate::RegValueT<ArbCfg_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod arb_cfg {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DmaCfg_SPEC;
pub type DmaCfg = crate::EnumBitfieldStruct<u8, DmaCfg_SPEC>;
impl DmaCfg {
#[doc = "No DMA"]
pub const DMA_NONE: Self = Self::new(0);
#[doc = "Manual DMA"]
pub const DMA_MANUAL: Self = Self::new(1);
#[doc = "Auto DMA"]
pub const DMA_AUTO: Self = Self::new(2);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UsbClkEn_SPEC;
impl crate::sealed::RegSpec for UsbClkEn_SPEC {
type DataType = u32;
}
#[doc = "USB Block Clock Enable Register"]
pub type UsbClkEn = crate::RegValueT<UsbClkEn_SPEC>;
impl UsbClkEn {
#[doc = "Clock Enable for Core Logic clocked by AHB bus clock"]
#[inline(always)]
pub fn csr_clk_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, UsbClkEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,UsbClkEn_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for UsbClkEn {
#[inline(always)]
fn default() -> UsbClkEn {
<crate::RegValueT<UsbClkEn_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbIntEn_SPEC;
impl crate::sealed::RegSpec for ArbIntEn_SPEC {
type DataType = u32;
}
#[doc = "Arbiter Interrupt Enable *1"]
pub type ArbIntEn = crate::RegValueT<ArbIntEn_SPEC>;
impl ArbIntEn {
#[doc = "Enables interrupt for EP1"]
#[inline(always)]
pub fn ep1_intr_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbIntEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbIntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables interrupt for EP2"]
#[inline(always)]
pub fn ep2_intr_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbIntEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbIntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables interrupt for EP3"]
#[inline(always)]
pub fn ep3_intr_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbIntEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,ArbIntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables interrupt for EP4"]
#[inline(always)]
pub fn ep4_intr_en(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbIntEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,ArbIntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables interrupt for EP5"]
#[inline(always)]
pub fn ep5_intr_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ArbIntEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,ArbIntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables interrupt for EP6"]
#[inline(always)]
pub fn ep6_intr_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbIntEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,ArbIntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables interrupt for EP7"]
#[inline(always)]
pub fn ep7_intr_en(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, ArbIntEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,ArbIntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables interrupt for EP8"]
#[inline(always)]
pub fn ep8_intr_en(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, ArbIntEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,ArbIntEn_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbIntEn {
#[inline(always)]
fn default() -> ArbIntEn {
<crate::RegValueT<ArbIntEn_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbIntSr_SPEC;
impl crate::sealed::RegSpec for ArbIntSr_SPEC {
type DataType = u32;
}
#[doc = "Arbiter Interrupt Status *1"]
pub type ArbIntSr = crate::RegValueT<ArbIntSr_SPEC>;
impl ArbIntSr {
#[doc = "Interrupt status for EP1"]
#[inline(always)]
pub fn ep1_intr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbIntSr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,ArbIntSr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Interrupt status for EP2"]
#[inline(always)]
pub fn ep2_intr(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbIntSr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,ArbIntSr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Interrupt status for EP3"]
#[inline(always)]
pub fn ep3_intr(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbIntSr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,ArbIntSr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Interrupt status for EP4"]
#[inline(always)]
pub fn ep4_intr(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbIntSr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3,1,0,ArbIntSr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Interrupt status for EP5"]
#[inline(always)]
pub fn ep5_intr(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ArbIntSr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4,1,0,ArbIntSr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Interrupt status for EP6"]
#[inline(always)]
pub fn ep6_intr(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbIntSr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5,1,0,ArbIntSr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Interrupt status for EP7"]
#[inline(always)]
pub fn ep7_intr(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, ArbIntSr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<6,1,0,ArbIntSr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Interrupt status for EP8"]
#[inline(always)]
pub fn ep8_intr(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, ArbIntSr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<7,1,0,ArbIntSr_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for ArbIntSr {
#[inline(always)]
fn default() -> ArbIntSr {
<crate::RegValueT<ArbIntSr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp3Cfg_SPEC;
impl crate::sealed::RegSpec for ArbEp3Cfg_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Configuration Register *1"]
pub type ArbEp3Cfg = crate::RegValueT<ArbEp3Cfg_SPEC>;
impl ArbEp3Cfg {
#[doc = "Indication that Endpoint Packet Data is Ready in Main memory"]
#[inline(always)]
pub fn in_data_rdy(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp3Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbEp3Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated."]
#[inline(always)]
pub fn dma_req(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp3Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbEp3Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware"]
#[inline(always)]
pub fn crc_bypass(
self,
) -> crate::common::RegisterField<
2,
0x1,
1,
0,
arb_ep3_cfg::CrcBypass,
arb_ep3_cfg::CrcBypass,
ArbEp3Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0x1,
1,
0,
arb_ep3_cfg::CrcBypass,
arb_ep3_cfg::CrcBypass,
ArbEp3Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction."]
#[inline(always)]
pub fn reset_ptr(
self,
) -> crate::common::RegisterField<
3,
0x1,
1,
0,
arb_ep3_cfg::ResetPtr,
arb_ep3_cfg::ResetPtr,
ArbEp3Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
3,
0x1,
1,
0,
arb_ep3_cfg::ResetPtr,
arb_ep3_cfg::ResetPtr,
ArbEp3Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbEp3Cfg {
#[inline(always)]
fn default() -> ArbEp3Cfg {
<crate::RegValueT<ArbEp3Cfg_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod arb_ep3_cfg {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CrcBypass_SPEC;
pub type CrcBypass = crate::EnumBitfieldStruct<u8, CrcBypass_SPEC>;
impl CrcBypass {
#[doc = "No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s"]
pub const CRC_NORMAL: Self = Self::new(0);
#[doc = "CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s"]
pub const CRC_BYPASS: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ResetPtr_SPEC;
pub type ResetPtr = crate::EnumBitfieldStruct<u8, ResetPtr_SPEC>;
impl ResetPtr {
#[doc = "Do not Reset Pointer; Krypton Backward compatibility mode"]
pub const RESET_KRYPTON: Self = Self::new(0);
#[doc = "Reset Pointer; recommended value for reduction of CPU Configuration Writes."]
pub const RESET_NORMAL: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp3IntEn_SPEC;
impl crate::sealed::RegSpec for ArbEp3IntEn_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Interrupt Enable Register *1"]
pub type ArbEp3IntEn = crate::RegValueT<ArbEp3IntEn_SPEC>;
impl ArbEp3IntEn {
#[doc = "IN Endpoint Local Buffer Full Enable"]
#[inline(always)]
pub fn in_buf_full_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp3IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbEp3IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Grant Enable"]
#[inline(always)]
pub fn dma_gnt_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp3IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,ArbEp3IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Overflow Enable"]
#[inline(always)]
pub fn buf_over_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbEp3IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,ArbEp3IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Underflow Enable"]
#[inline(always)]
pub fn buf_under_en(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbEp3IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,ArbEp3IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Error in Transaction Interrupt Enable"]
#[inline(always)]
pub fn err_int_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ArbEp3IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,ArbEp3IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Terminated Enable"]
#[inline(always)]
pub fn dma_termin_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbEp3IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,ArbEp3IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbEp3IntEn {
#[inline(always)]
fn default() -> ArbEp3IntEn {
<crate::RegValueT<ArbEp3IntEn_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp3Sr_SPEC;
impl crate::sealed::RegSpec for ArbEp3Sr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Interrupt Enable Register *1"]
pub type ArbEp3Sr = crate::RegValueT<ArbEp3Sr_SPEC>;
impl ArbEp3Sr {
#[doc = "IN Endpoint Local Buffer Full Interrupt"]
#[inline(always)]
pub fn in_buf_full(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp3Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbEp3Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Grant Interrupt"]
#[inline(always)]
pub fn dma_gnt(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp3Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbEp3Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Overflow Interrupt"]
#[inline(always)]
pub fn buf_over(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbEp3Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,ArbEp3Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Underflow Interrupt"]
#[inline(always)]
pub fn buf_under(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbEp3Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,ArbEp3Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Terminated Interrupt"]
#[inline(always)]
pub fn dma_termin(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbEp3Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,ArbEp3Sr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbEp3Sr {
#[inline(always)]
fn default() -> ArbEp3Sr {
<crate::RegValueT<ArbEp3Sr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw3Wa_SPEC;
impl crate::sealed::RegSpec for ArbRw3Wa_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *1, *2"]
pub type ArbRw3Wa = crate::RegValueT<ArbRw3Wa_SPEC>;
impl ArbRw3Wa {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw3Wa_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw3Wa_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw3Wa {
#[inline(always)]
fn default() -> ArbRw3Wa {
<crate::RegValueT<ArbRw3Wa_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw3WaMsb_SPEC;
impl crate::sealed::RegSpec for ArbRw3WaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *1, *2"]
pub type ArbRw3WaMsb = crate::RegValueT<ArbRw3WaMsb_SPEC>;
impl ArbRw3WaMsb {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbRw3WaMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbRw3WaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw3WaMsb {
#[inline(always)]
fn default() -> ArbRw3WaMsb {
<crate::RegValueT<ArbRw3WaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw3Ra_SPEC;
impl crate::sealed::RegSpec for ArbRw3Ra_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1, *2"]
pub type ArbRw3Ra = crate::RegValueT<ArbRw3Ra_SPEC>;
impl ArbRw3Ra {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw3Ra_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw3Ra_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw3Ra {
#[inline(always)]
fn default() -> ArbRw3Ra {
<crate::RegValueT<ArbRw3Ra_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw3RaMsb_SPEC;
impl crate::sealed::RegSpec for ArbRw3RaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1, *2"]
pub type ArbRw3RaMsb = crate::RegValueT<ArbRw3RaMsb_SPEC>;
impl ArbRw3RaMsb {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbRw3RaMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbRw3RaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw3RaMsb {
#[inline(always)]
fn default() -> ArbRw3RaMsb {
<crate::RegValueT<ArbRw3RaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw3Dr_SPEC;
impl crate::sealed::RegSpec for ArbRw3Dr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Data Register"]
pub type ArbRw3Dr = crate::RegValueT<ArbRw3Dr_SPEC>;
impl ArbRw3Dr {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw3Dr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw3Dr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw3Dr {
#[inline(always)]
fn default() -> ArbRw3Dr {
<crate::RegValueT<ArbRw3Dr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cwa_SPEC;
impl crate::sealed::RegSpec for Cwa_SPEC {
type DataType = u32;
}
#[doc = "Common Area Write Address *1"]
pub type Cwa = crate::RegValueT<Cwa_SPEC>;
impl Cwa {
#[doc = "Write Address for Common Area"]
#[inline(always)]
pub fn cwa(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Cwa_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Cwa_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cwa {
#[inline(always)]
fn default() -> Cwa {
<crate::RegValueT<Cwa_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CwaMsb_SPEC;
impl crate::sealed::RegSpec for CwaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1"]
pub type CwaMsb = crate::RegValueT<CwaMsb_SPEC>;
impl CwaMsb {
#[doc = "Write Address for Common Area"]
#[inline(always)]
pub fn cwa_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, CwaMsb_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,CwaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CwaMsb {
#[inline(always)]
fn default() -> CwaMsb {
<crate::RegValueT<CwaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp4Cfg_SPEC;
impl crate::sealed::RegSpec for ArbEp4Cfg_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Configuration Register *1"]
pub type ArbEp4Cfg = crate::RegValueT<ArbEp4Cfg_SPEC>;
impl ArbEp4Cfg {
#[doc = "Indication that Endpoint Packet Data is Ready in Main memory"]
#[inline(always)]
pub fn in_data_rdy(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp4Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbEp4Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated."]
#[inline(always)]
pub fn dma_req(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp4Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbEp4Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware"]
#[inline(always)]
pub fn crc_bypass(
self,
) -> crate::common::RegisterField<
2,
0x1,
1,
0,
arb_ep4_cfg::CrcBypass,
arb_ep4_cfg::CrcBypass,
ArbEp4Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0x1,
1,
0,
arb_ep4_cfg::CrcBypass,
arb_ep4_cfg::CrcBypass,
ArbEp4Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction."]
#[inline(always)]
pub fn reset_ptr(
self,
) -> crate::common::RegisterField<
3,
0x1,
1,
0,
arb_ep4_cfg::ResetPtr,
arb_ep4_cfg::ResetPtr,
ArbEp4Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
3,
0x1,
1,
0,
arb_ep4_cfg::ResetPtr,
arb_ep4_cfg::ResetPtr,
ArbEp4Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbEp4Cfg {
#[inline(always)]
fn default() -> ArbEp4Cfg {
<crate::RegValueT<ArbEp4Cfg_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod arb_ep4_cfg {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CrcBypass_SPEC;
pub type CrcBypass = crate::EnumBitfieldStruct<u8, CrcBypass_SPEC>;
impl CrcBypass {
#[doc = "No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s"]
pub const CRC_NORMAL: Self = Self::new(0);
#[doc = "CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s"]
pub const CRC_BYPASS: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ResetPtr_SPEC;
pub type ResetPtr = crate::EnumBitfieldStruct<u8, ResetPtr_SPEC>;
impl ResetPtr {
#[doc = "Do not Reset Pointer; Krypton Backward compatibility mode"]
pub const RESET_KRYPTON: Self = Self::new(0);
#[doc = "Reset Pointer; recommended value for reduction of CPU Configuration Writes."]
pub const RESET_NORMAL: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp4IntEn_SPEC;
impl crate::sealed::RegSpec for ArbEp4IntEn_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Interrupt Enable Register *1"]
pub type ArbEp4IntEn = crate::RegValueT<ArbEp4IntEn_SPEC>;
impl ArbEp4IntEn {
#[doc = "IN Endpoint Local Buffer Full Enable"]
#[inline(always)]
pub fn in_buf_full_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp4IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbEp4IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Grant Enable"]
#[inline(always)]
pub fn dma_gnt_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp4IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,ArbEp4IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Overflow Enable"]
#[inline(always)]
pub fn buf_over_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbEp4IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,ArbEp4IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Underflow Enable"]
#[inline(always)]
pub fn buf_under_en(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbEp4IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,ArbEp4IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Error in Transaction Interrupt Enable"]
#[inline(always)]
pub fn err_int_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ArbEp4IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,ArbEp4IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Terminated Enable"]
#[inline(always)]
pub fn dma_termin_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbEp4IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,ArbEp4IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbEp4IntEn {
#[inline(always)]
fn default() -> ArbEp4IntEn {
<crate::RegValueT<ArbEp4IntEn_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp4Sr_SPEC;
impl crate::sealed::RegSpec for ArbEp4Sr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Interrupt Enable Register *1"]
pub type ArbEp4Sr = crate::RegValueT<ArbEp4Sr_SPEC>;
impl ArbEp4Sr {
#[doc = "IN Endpoint Local Buffer Full Interrupt"]
#[inline(always)]
pub fn in_buf_full(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp4Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbEp4Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Grant Interrupt"]
#[inline(always)]
pub fn dma_gnt(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp4Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbEp4Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Overflow Interrupt"]
#[inline(always)]
pub fn buf_over(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbEp4Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,ArbEp4Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Underflow Interrupt"]
#[inline(always)]
pub fn buf_under(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbEp4Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,ArbEp4Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Terminated Interrupt"]
#[inline(always)]
pub fn dma_termin(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbEp4Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,ArbEp4Sr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbEp4Sr {
#[inline(always)]
fn default() -> ArbEp4Sr {
<crate::RegValueT<ArbEp4Sr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw4Wa_SPEC;
impl crate::sealed::RegSpec for ArbRw4Wa_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *1, *2"]
pub type ArbRw4Wa = crate::RegValueT<ArbRw4Wa_SPEC>;
impl ArbRw4Wa {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw4Wa_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw4Wa_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw4Wa {
#[inline(always)]
fn default() -> ArbRw4Wa {
<crate::RegValueT<ArbRw4Wa_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw4WaMsb_SPEC;
impl crate::sealed::RegSpec for ArbRw4WaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *1, *2"]
pub type ArbRw4WaMsb = crate::RegValueT<ArbRw4WaMsb_SPEC>;
impl ArbRw4WaMsb {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbRw4WaMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbRw4WaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw4WaMsb {
#[inline(always)]
fn default() -> ArbRw4WaMsb {
<crate::RegValueT<ArbRw4WaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw4Ra_SPEC;
impl crate::sealed::RegSpec for ArbRw4Ra_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1, *2"]
pub type ArbRw4Ra = crate::RegValueT<ArbRw4Ra_SPEC>;
impl ArbRw4Ra {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw4Ra_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw4Ra_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw4Ra {
#[inline(always)]
fn default() -> ArbRw4Ra {
<crate::RegValueT<ArbRw4Ra_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw4RaMsb_SPEC;
impl crate::sealed::RegSpec for ArbRw4RaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1, *2"]
pub type ArbRw4RaMsb = crate::RegValueT<ArbRw4RaMsb_SPEC>;
impl ArbRw4RaMsb {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbRw4RaMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbRw4RaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw4RaMsb {
#[inline(always)]
fn default() -> ArbRw4RaMsb {
<crate::RegValueT<ArbRw4RaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw4Dr_SPEC;
impl crate::sealed::RegSpec for ArbRw4Dr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Data Register"]
pub type ArbRw4Dr = crate::RegValueT<ArbRw4Dr_SPEC>;
impl ArbRw4Dr {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw4Dr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw4Dr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw4Dr {
#[inline(always)]
fn default() -> ArbRw4Dr {
<crate::RegValueT<ArbRw4Dr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DmaThres_SPEC;
impl crate::sealed::RegSpec for DmaThres_SPEC {
type DataType = u32;
}
#[doc = "DMA Burst / Threshold Configuration"]
pub type DmaThres = crate::RegValueT<DmaThres_SPEC>;
impl DmaThres {
#[doc = "DMA Threshold count"]
#[inline(always)]
pub fn dma_ths(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, DmaThres_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,DmaThres_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for DmaThres {
#[inline(always)]
fn default() -> DmaThres {
<crate::RegValueT<DmaThres_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DmaThresMsb_SPEC;
impl crate::sealed::RegSpec for DmaThresMsb_SPEC {
type DataType = u32;
}
#[doc = "DMA Burst / Threshold Configuration"]
pub type DmaThresMsb = crate::RegValueT<DmaThresMsb_SPEC>;
impl DmaThresMsb {
#[doc = "DMA Threshold count"]
#[inline(always)]
pub fn dma_ths_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, DmaThresMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,DmaThresMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for DmaThresMsb {
#[inline(always)]
fn default() -> DmaThresMsb {
<crate::RegValueT<DmaThresMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp5Cfg_SPEC;
impl crate::sealed::RegSpec for ArbEp5Cfg_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Configuration Register *1"]
pub type ArbEp5Cfg = crate::RegValueT<ArbEp5Cfg_SPEC>;
impl ArbEp5Cfg {
#[doc = "Indication that Endpoint Packet Data is Ready in Main memory"]
#[inline(always)]
pub fn in_data_rdy(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp5Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbEp5Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated."]
#[inline(always)]
pub fn dma_req(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp5Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbEp5Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware"]
#[inline(always)]
pub fn crc_bypass(
self,
) -> crate::common::RegisterField<
2,
0x1,
1,
0,
arb_ep5_cfg::CrcBypass,
arb_ep5_cfg::CrcBypass,
ArbEp5Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0x1,
1,
0,
arb_ep5_cfg::CrcBypass,
arb_ep5_cfg::CrcBypass,
ArbEp5Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction."]
#[inline(always)]
pub fn reset_ptr(
self,
) -> crate::common::RegisterField<
3,
0x1,
1,
0,
arb_ep5_cfg::ResetPtr,
arb_ep5_cfg::ResetPtr,
ArbEp5Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
3,
0x1,
1,
0,
arb_ep5_cfg::ResetPtr,
arb_ep5_cfg::ResetPtr,
ArbEp5Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbEp5Cfg {
#[inline(always)]
fn default() -> ArbEp5Cfg {
<crate::RegValueT<ArbEp5Cfg_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod arb_ep5_cfg {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CrcBypass_SPEC;
pub type CrcBypass = crate::EnumBitfieldStruct<u8, CrcBypass_SPEC>;
impl CrcBypass {
#[doc = "No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s"]
pub const CRC_NORMAL: Self = Self::new(0);
#[doc = "CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s"]
pub const CRC_BYPASS: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ResetPtr_SPEC;
pub type ResetPtr = crate::EnumBitfieldStruct<u8, ResetPtr_SPEC>;
impl ResetPtr {
#[doc = "Do not Reset Pointer; Krypton Backward compatibility mode"]
pub const RESET_KRYPTON: Self = Self::new(0);
#[doc = "Reset Pointer; recommended value for reduction of CPU Configuration Writes."]
pub const RESET_NORMAL: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp5IntEn_SPEC;
impl crate::sealed::RegSpec for ArbEp5IntEn_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Interrupt Enable Register *1"]
pub type ArbEp5IntEn = crate::RegValueT<ArbEp5IntEn_SPEC>;
impl ArbEp5IntEn {
#[doc = "IN Endpoint Local Buffer Full Enable"]
#[inline(always)]
pub fn in_buf_full_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp5IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbEp5IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Grant Enable"]
#[inline(always)]
pub fn dma_gnt_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp5IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,ArbEp5IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Overflow Enable"]
#[inline(always)]
pub fn buf_over_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbEp5IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,ArbEp5IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Underflow Enable"]
#[inline(always)]
pub fn buf_under_en(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbEp5IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,ArbEp5IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Error in Transaction Interrupt Enable"]
#[inline(always)]
pub fn err_int_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ArbEp5IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,ArbEp5IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Terminated Enable"]
#[inline(always)]
pub fn dma_termin_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbEp5IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,ArbEp5IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbEp5IntEn {
#[inline(always)]
fn default() -> ArbEp5IntEn {
<crate::RegValueT<ArbEp5IntEn_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp5Sr_SPEC;
impl crate::sealed::RegSpec for ArbEp5Sr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Interrupt Enable Register *1"]
pub type ArbEp5Sr = crate::RegValueT<ArbEp5Sr_SPEC>;
impl ArbEp5Sr {
#[doc = "IN Endpoint Local Buffer Full Interrupt"]
#[inline(always)]
pub fn in_buf_full(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp5Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbEp5Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Grant Interrupt"]
#[inline(always)]
pub fn dma_gnt(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp5Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbEp5Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Overflow Interrupt"]
#[inline(always)]
pub fn buf_over(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbEp5Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,ArbEp5Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Underflow Interrupt"]
#[inline(always)]
pub fn buf_under(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbEp5Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,ArbEp5Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Terminated Interrupt"]
#[inline(always)]
pub fn dma_termin(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbEp5Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,ArbEp5Sr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbEp5Sr {
#[inline(always)]
fn default() -> ArbEp5Sr {
<crate::RegValueT<ArbEp5Sr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw5Wa_SPEC;
impl crate::sealed::RegSpec for ArbRw5Wa_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *1, *2"]
pub type ArbRw5Wa = crate::RegValueT<ArbRw5Wa_SPEC>;
impl ArbRw5Wa {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw5Wa_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw5Wa_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw5Wa {
#[inline(always)]
fn default() -> ArbRw5Wa {
<crate::RegValueT<ArbRw5Wa_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw5WaMsb_SPEC;
impl crate::sealed::RegSpec for ArbRw5WaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *1, *2"]
pub type ArbRw5WaMsb = crate::RegValueT<ArbRw5WaMsb_SPEC>;
impl ArbRw5WaMsb {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbRw5WaMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbRw5WaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw5WaMsb {
#[inline(always)]
fn default() -> ArbRw5WaMsb {
<crate::RegValueT<ArbRw5WaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw5Ra_SPEC;
impl crate::sealed::RegSpec for ArbRw5Ra_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1, *2"]
pub type ArbRw5Ra = crate::RegValueT<ArbRw5Ra_SPEC>;
impl ArbRw5Ra {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw5Ra_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw5Ra_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw5Ra {
#[inline(always)]
fn default() -> ArbRw5Ra {
<crate::RegValueT<ArbRw5Ra_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw5RaMsb_SPEC;
impl crate::sealed::RegSpec for ArbRw5RaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1, *2"]
pub type ArbRw5RaMsb = crate::RegValueT<ArbRw5RaMsb_SPEC>;
impl ArbRw5RaMsb {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbRw5RaMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbRw5RaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw5RaMsb {
#[inline(always)]
fn default() -> ArbRw5RaMsb {
<crate::RegValueT<ArbRw5RaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw5Dr_SPEC;
impl crate::sealed::RegSpec for ArbRw5Dr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Data Register"]
pub type ArbRw5Dr = crate::RegValueT<ArbRw5Dr_SPEC>;
impl ArbRw5Dr {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw5Dr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw5Dr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw5Dr {
#[inline(always)]
fn default() -> ArbRw5Dr {
<crate::RegValueT<ArbRw5Dr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct BusRstCnt_SPEC;
impl crate::sealed::RegSpec for BusRstCnt_SPEC {
type DataType = u32;
}
#[doc = "Bus Reset Count Register"]
pub type BusRstCnt = crate::RegValueT<BusRstCnt_SPEC>;
impl BusRstCnt {
#[doc = "Bus Reset Count Length"]
#[inline(always)]
pub fn bus_rst_cnt(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, BusRstCnt_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,BusRstCnt_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for BusRstCnt {
#[inline(always)]
fn default() -> BusRstCnt {
<crate::RegValueT<BusRstCnt_SPEC> as RegisterValue<_>>::new(10)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp6Cfg_SPEC;
impl crate::sealed::RegSpec for ArbEp6Cfg_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Configuration Register *1"]
pub type ArbEp6Cfg = crate::RegValueT<ArbEp6Cfg_SPEC>;
impl ArbEp6Cfg {
#[doc = "Indication that Endpoint Packet Data is Ready in Main memory"]
#[inline(always)]
pub fn in_data_rdy(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp6Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbEp6Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated."]
#[inline(always)]
pub fn dma_req(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp6Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbEp6Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware"]
#[inline(always)]
pub fn crc_bypass(
self,
) -> crate::common::RegisterField<
2,
0x1,
1,
0,
arb_ep6_cfg::CrcBypass,
arb_ep6_cfg::CrcBypass,
ArbEp6Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0x1,
1,
0,
arb_ep6_cfg::CrcBypass,
arb_ep6_cfg::CrcBypass,
ArbEp6Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction."]
#[inline(always)]
pub fn reset_ptr(
self,
) -> crate::common::RegisterField<
3,
0x1,
1,
0,
arb_ep6_cfg::ResetPtr,
arb_ep6_cfg::ResetPtr,
ArbEp6Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
3,
0x1,
1,
0,
arb_ep6_cfg::ResetPtr,
arb_ep6_cfg::ResetPtr,
ArbEp6Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbEp6Cfg {
#[inline(always)]
fn default() -> ArbEp6Cfg {
<crate::RegValueT<ArbEp6Cfg_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod arb_ep6_cfg {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CrcBypass_SPEC;
pub type CrcBypass = crate::EnumBitfieldStruct<u8, CrcBypass_SPEC>;
impl CrcBypass {
#[doc = "No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s"]
pub const CRC_NORMAL: Self = Self::new(0);
#[doc = "CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s"]
pub const CRC_BYPASS: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ResetPtr_SPEC;
pub type ResetPtr = crate::EnumBitfieldStruct<u8, ResetPtr_SPEC>;
impl ResetPtr {
#[doc = "Do not Reset Pointer; Krypton Backward compatibility mode"]
pub const RESET_KRYPTON: Self = Self::new(0);
#[doc = "Reset Pointer; recommended value for reduction of CPU Configuration Writes."]
pub const RESET_NORMAL: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp6IntEn_SPEC;
impl crate::sealed::RegSpec for ArbEp6IntEn_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Interrupt Enable Register *1"]
pub type ArbEp6IntEn = crate::RegValueT<ArbEp6IntEn_SPEC>;
impl ArbEp6IntEn {
#[doc = "IN Endpoint Local Buffer Full Enable"]
#[inline(always)]
pub fn in_buf_full_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp6IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbEp6IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Grant Enable"]
#[inline(always)]
pub fn dma_gnt_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp6IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,ArbEp6IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Overflow Enable"]
#[inline(always)]
pub fn buf_over_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbEp6IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,ArbEp6IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Underflow Enable"]
#[inline(always)]
pub fn buf_under_en(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbEp6IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,ArbEp6IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Error in Transaction Interrupt Enable"]
#[inline(always)]
pub fn err_int_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ArbEp6IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,ArbEp6IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Terminated Enable"]
#[inline(always)]
pub fn dma_termin_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbEp6IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,ArbEp6IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbEp6IntEn {
#[inline(always)]
fn default() -> ArbEp6IntEn {
<crate::RegValueT<ArbEp6IntEn_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp6Sr_SPEC;
impl crate::sealed::RegSpec for ArbEp6Sr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Interrupt Enable Register *1"]
pub type ArbEp6Sr = crate::RegValueT<ArbEp6Sr_SPEC>;
impl ArbEp6Sr {
#[doc = "IN Endpoint Local Buffer Full Interrupt"]
#[inline(always)]
pub fn in_buf_full(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp6Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbEp6Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Grant Interrupt"]
#[inline(always)]
pub fn dma_gnt(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp6Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbEp6Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Overflow Interrupt"]
#[inline(always)]
pub fn buf_over(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbEp6Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,ArbEp6Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Underflow Interrupt"]
#[inline(always)]
pub fn buf_under(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbEp6Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,ArbEp6Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Terminated Interrupt"]
#[inline(always)]
pub fn dma_termin(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbEp6Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,ArbEp6Sr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbEp6Sr {
#[inline(always)]
fn default() -> ArbEp6Sr {
<crate::RegValueT<ArbEp6Sr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw6Wa_SPEC;
impl crate::sealed::RegSpec for ArbRw6Wa_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *1, *2"]
pub type ArbRw6Wa = crate::RegValueT<ArbRw6Wa_SPEC>;
impl ArbRw6Wa {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw6Wa_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw6Wa_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw6Wa {
#[inline(always)]
fn default() -> ArbRw6Wa {
<crate::RegValueT<ArbRw6Wa_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw6WaMsb_SPEC;
impl crate::sealed::RegSpec for ArbRw6WaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *1, *2"]
pub type ArbRw6WaMsb = crate::RegValueT<ArbRw6WaMsb_SPEC>;
impl ArbRw6WaMsb {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbRw6WaMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbRw6WaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw6WaMsb {
#[inline(always)]
fn default() -> ArbRw6WaMsb {
<crate::RegValueT<ArbRw6WaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw6Ra_SPEC;
impl crate::sealed::RegSpec for ArbRw6Ra_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1, *2"]
pub type ArbRw6Ra = crate::RegValueT<ArbRw6Ra_SPEC>;
impl ArbRw6Ra {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw6Ra_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw6Ra_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw6Ra {
#[inline(always)]
fn default() -> ArbRw6Ra {
<crate::RegValueT<ArbRw6Ra_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw6RaMsb_SPEC;
impl crate::sealed::RegSpec for ArbRw6RaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1, *2"]
pub type ArbRw6RaMsb = crate::RegValueT<ArbRw6RaMsb_SPEC>;
impl ArbRw6RaMsb {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbRw6RaMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbRw6RaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw6RaMsb {
#[inline(always)]
fn default() -> ArbRw6RaMsb {
<crate::RegValueT<ArbRw6RaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw6Dr_SPEC;
impl crate::sealed::RegSpec for ArbRw6Dr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Data Register"]
pub type ArbRw6Dr = crate::RegValueT<ArbRw6Dr_SPEC>;
impl ArbRw6Dr {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw6Dr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw6Dr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw6Dr {
#[inline(always)]
fn default() -> ArbRw6Dr {
<crate::RegValueT<ArbRw6Dr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp7Cfg_SPEC;
impl crate::sealed::RegSpec for ArbEp7Cfg_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Configuration Register *1"]
pub type ArbEp7Cfg = crate::RegValueT<ArbEp7Cfg_SPEC>;
impl ArbEp7Cfg {
#[doc = "Indication that Endpoint Packet Data is Ready in Main memory"]
#[inline(always)]
pub fn in_data_rdy(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp7Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbEp7Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated."]
#[inline(always)]
pub fn dma_req(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp7Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbEp7Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware"]
#[inline(always)]
pub fn crc_bypass(
self,
) -> crate::common::RegisterField<
2,
0x1,
1,
0,
arb_ep7_cfg::CrcBypass,
arb_ep7_cfg::CrcBypass,
ArbEp7Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0x1,
1,
0,
arb_ep7_cfg::CrcBypass,
arb_ep7_cfg::CrcBypass,
ArbEp7Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction."]
#[inline(always)]
pub fn reset_ptr(
self,
) -> crate::common::RegisterField<
3,
0x1,
1,
0,
arb_ep7_cfg::ResetPtr,
arb_ep7_cfg::ResetPtr,
ArbEp7Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
3,
0x1,
1,
0,
arb_ep7_cfg::ResetPtr,
arb_ep7_cfg::ResetPtr,
ArbEp7Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbEp7Cfg {
#[inline(always)]
fn default() -> ArbEp7Cfg {
<crate::RegValueT<ArbEp7Cfg_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod arb_ep7_cfg {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CrcBypass_SPEC;
pub type CrcBypass = crate::EnumBitfieldStruct<u8, CrcBypass_SPEC>;
impl CrcBypass {
#[doc = "No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s"]
pub const CRC_NORMAL: Self = Self::new(0);
#[doc = "CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s"]
pub const CRC_BYPASS: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ResetPtr_SPEC;
pub type ResetPtr = crate::EnumBitfieldStruct<u8, ResetPtr_SPEC>;
impl ResetPtr {
#[doc = "Do not Reset Pointer; Krypton Backward compatibility mode"]
pub const RESET_KRYPTON: Self = Self::new(0);
#[doc = "Reset Pointer; recommended value for reduction of CPU Configuration Writes."]
pub const RESET_NORMAL: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp7IntEn_SPEC;
impl crate::sealed::RegSpec for ArbEp7IntEn_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Interrupt Enable Register *1"]
pub type ArbEp7IntEn = crate::RegValueT<ArbEp7IntEn_SPEC>;
impl ArbEp7IntEn {
#[doc = "IN Endpoint Local Buffer Full Enable"]
#[inline(always)]
pub fn in_buf_full_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp7IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbEp7IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Grant Enable"]
#[inline(always)]
pub fn dma_gnt_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp7IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,ArbEp7IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Overflow Enable"]
#[inline(always)]
pub fn buf_over_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbEp7IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,ArbEp7IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Underflow Enable"]
#[inline(always)]
pub fn buf_under_en(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbEp7IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,ArbEp7IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Error in Transaction Interrupt Enable"]
#[inline(always)]
pub fn err_int_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ArbEp7IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,ArbEp7IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Terminated Enable"]
#[inline(always)]
pub fn dma_termin_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbEp7IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,ArbEp7IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbEp7IntEn {
#[inline(always)]
fn default() -> ArbEp7IntEn {
<crate::RegValueT<ArbEp7IntEn_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp7Sr_SPEC;
impl crate::sealed::RegSpec for ArbEp7Sr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Interrupt Enable Register *1"]
pub type ArbEp7Sr = crate::RegValueT<ArbEp7Sr_SPEC>;
impl ArbEp7Sr {
#[doc = "IN Endpoint Local Buffer Full Interrupt"]
#[inline(always)]
pub fn in_buf_full(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp7Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbEp7Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Grant Interrupt"]
#[inline(always)]
pub fn dma_gnt(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp7Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbEp7Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Overflow Interrupt"]
#[inline(always)]
pub fn buf_over(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbEp7Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,ArbEp7Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Underflow Interrupt"]
#[inline(always)]
pub fn buf_under(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbEp7Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,ArbEp7Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Terminated Interrupt"]
#[inline(always)]
pub fn dma_termin(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbEp7Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,ArbEp7Sr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbEp7Sr {
#[inline(always)]
fn default() -> ArbEp7Sr {
<crate::RegValueT<ArbEp7Sr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw7Wa_SPEC;
impl crate::sealed::RegSpec for ArbRw7Wa_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *1, *2"]
pub type ArbRw7Wa = crate::RegValueT<ArbRw7Wa_SPEC>;
impl ArbRw7Wa {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw7Wa_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw7Wa_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw7Wa {
#[inline(always)]
fn default() -> ArbRw7Wa {
<crate::RegValueT<ArbRw7Wa_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw7WaMsb_SPEC;
impl crate::sealed::RegSpec for ArbRw7WaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *1, *2"]
pub type ArbRw7WaMsb = crate::RegValueT<ArbRw7WaMsb_SPEC>;
impl ArbRw7WaMsb {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbRw7WaMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbRw7WaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw7WaMsb {
#[inline(always)]
fn default() -> ArbRw7WaMsb {
<crate::RegValueT<ArbRw7WaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw7Ra_SPEC;
impl crate::sealed::RegSpec for ArbRw7Ra_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1, *2"]
pub type ArbRw7Ra = crate::RegValueT<ArbRw7Ra_SPEC>;
impl ArbRw7Ra {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw7Ra_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw7Ra_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw7Ra {
#[inline(always)]
fn default() -> ArbRw7Ra {
<crate::RegValueT<ArbRw7Ra_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw7RaMsb_SPEC;
impl crate::sealed::RegSpec for ArbRw7RaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1, *2"]
pub type ArbRw7RaMsb = crate::RegValueT<ArbRw7RaMsb_SPEC>;
impl ArbRw7RaMsb {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbRw7RaMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbRw7RaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw7RaMsb {
#[inline(always)]
fn default() -> ArbRw7RaMsb {
<crate::RegValueT<ArbRw7RaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw7Dr_SPEC;
impl crate::sealed::RegSpec for ArbRw7Dr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Data Register"]
pub type ArbRw7Dr = crate::RegValueT<ArbRw7Dr_SPEC>;
impl ArbRw7Dr {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw7Dr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw7Dr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw7Dr {
#[inline(always)]
fn default() -> ArbRw7Dr {
<crate::RegValueT<ArbRw7Dr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp8Cfg_SPEC;
impl crate::sealed::RegSpec for ArbEp8Cfg_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Configuration Register *1"]
pub type ArbEp8Cfg = crate::RegValueT<ArbEp8Cfg_SPEC>;
impl ArbEp8Cfg {
#[doc = "Indication that Endpoint Packet Data is Ready in Main memory"]
#[inline(always)]
pub fn in_data_rdy(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp8Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbEp8Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated."]
#[inline(always)]
pub fn dma_req(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp8Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbEp8Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware"]
#[inline(always)]
pub fn crc_bypass(
self,
) -> crate::common::RegisterField<
2,
0x1,
1,
0,
arb_ep8_cfg::CrcBypass,
arb_ep8_cfg::CrcBypass,
ArbEp8Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0x1,
1,
0,
arb_ep8_cfg::CrcBypass,
arb_ep8_cfg::CrcBypass,
ArbEp8Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction."]
#[inline(always)]
pub fn reset_ptr(
self,
) -> crate::common::RegisterField<
3,
0x1,
1,
0,
arb_ep8_cfg::ResetPtr,
arb_ep8_cfg::ResetPtr,
ArbEp8Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
3,
0x1,
1,
0,
arb_ep8_cfg::ResetPtr,
arb_ep8_cfg::ResetPtr,
ArbEp8Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbEp8Cfg {
#[inline(always)]
fn default() -> ArbEp8Cfg {
<crate::RegValueT<ArbEp8Cfg_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod arb_ep8_cfg {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CrcBypass_SPEC;
pub type CrcBypass = crate::EnumBitfieldStruct<u8, CrcBypass_SPEC>;
impl CrcBypass {
#[doc = "No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s"]
pub const CRC_NORMAL: Self = Self::new(0);
#[doc = "CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s"]
pub const CRC_BYPASS: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ResetPtr_SPEC;
pub type ResetPtr = crate::EnumBitfieldStruct<u8, ResetPtr_SPEC>;
impl ResetPtr {
#[doc = "Do not Reset Pointer; Krypton Backward compatibility mode"]
pub const RESET_KRYPTON: Self = Self::new(0);
#[doc = "Reset Pointer; recommended value for reduction of CPU Configuration Writes."]
pub const RESET_NORMAL: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp8IntEn_SPEC;
impl crate::sealed::RegSpec for ArbEp8IntEn_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Interrupt Enable Register *1"]
pub type ArbEp8IntEn = crate::RegValueT<ArbEp8IntEn_SPEC>;
impl ArbEp8IntEn {
#[doc = "IN Endpoint Local Buffer Full Enable"]
#[inline(always)]
pub fn in_buf_full_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp8IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbEp8IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Grant Enable"]
#[inline(always)]
pub fn dma_gnt_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp8IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,ArbEp8IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Overflow Enable"]
#[inline(always)]
pub fn buf_over_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbEp8IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,ArbEp8IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Underflow Enable"]
#[inline(always)]
pub fn buf_under_en(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbEp8IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,ArbEp8IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Error in Transaction Interrupt Enable"]
#[inline(always)]
pub fn err_int_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ArbEp8IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,ArbEp8IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Terminated Enable"]
#[inline(always)]
pub fn dma_termin_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbEp8IntEn_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,ArbEp8IntEn_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbEp8IntEn {
#[inline(always)]
fn default() -> ArbEp8IntEn {
<crate::RegValueT<ArbEp8IntEn_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbEp8Sr_SPEC;
impl crate::sealed::RegSpec for ArbEp8Sr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Interrupt Enable Register *1"]
pub type ArbEp8Sr = crate::RegValueT<ArbEp8Sr_SPEC>;
impl ArbEp8Sr {
#[doc = "IN Endpoint Local Buffer Full Interrupt"]
#[inline(always)]
pub fn in_buf_full(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbEp8Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ArbEp8Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Grant Interrupt"]
#[inline(always)]
pub fn dma_gnt(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ArbEp8Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ArbEp8Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Overflow Interrupt"]
#[inline(always)]
pub fn buf_over(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ArbEp8Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,ArbEp8Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint Buffer Underflow Interrupt"]
#[inline(always)]
pub fn buf_under(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ArbEp8Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,ArbEp8Sr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Endpoint DMA Terminated Interrupt"]
#[inline(always)]
pub fn dma_termin(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ArbEp8Sr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,ArbEp8Sr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbEp8Sr {
#[inline(always)]
fn default() -> ArbEp8Sr {
<crate::RegValueT<ArbEp8Sr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw8Wa_SPEC;
impl crate::sealed::RegSpec for ArbRw8Wa_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *1, *2"]
pub type ArbRw8Wa = crate::RegValueT<ArbRw8Wa_SPEC>;
impl ArbRw8Wa {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw8Wa_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw8Wa_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw8Wa {
#[inline(always)]
fn default() -> ArbRw8Wa {
<crate::RegValueT<ArbRw8Wa_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw8WaMsb_SPEC;
impl crate::sealed::RegSpec for ArbRw8WaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *1, *2"]
pub type ArbRw8WaMsb = crate::RegValueT<ArbRw8WaMsb_SPEC>;
impl ArbRw8WaMsb {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbRw8WaMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbRw8WaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw8WaMsb {
#[inline(always)]
fn default() -> ArbRw8WaMsb {
<crate::RegValueT<ArbRw8WaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw8Ra_SPEC;
impl crate::sealed::RegSpec for ArbRw8Ra_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1, *2"]
pub type ArbRw8Ra = crate::RegValueT<ArbRw8Ra_SPEC>;
impl ArbRw8Ra {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw8Ra_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw8Ra_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw8Ra {
#[inline(always)]
fn default() -> ArbRw8Ra {
<crate::RegValueT<ArbRw8Ra_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw8RaMsb_SPEC;
impl crate::sealed::RegSpec for ArbRw8RaMsb_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *1, *2"]
pub type ArbRw8RaMsb = crate::RegValueT<ArbRw8RaMsb_SPEC>;
impl ArbRw8RaMsb {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra_msb(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ArbRw8RaMsb_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ArbRw8RaMsb_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw8RaMsb {
#[inline(always)]
fn default() -> ArbRw8RaMsb {
<crate::RegValueT<ArbRw8RaMsb_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw8Dr_SPEC;
impl crate::sealed::RegSpec for ArbRw8Dr_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Data Register"]
pub type ArbRw8Dr = crate::RegValueT<ArbRw8Dr_SPEC>;
impl ArbRw8Dr {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ArbRw8Dr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ArbRw8Dr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArbRw8Dr {
#[inline(always)]
fn default() -> ArbRw8Dr {
<crate::RegValueT<ArbRw8Dr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MemData_SPEC;
impl crate::sealed::RegSpec for MemData_SPEC {
type DataType = u32;
}
#[doc = "DATA"]
pub type MemData = crate::RegValueT<MemData_SPEC>;
impl MemData {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, MemData_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,MemData_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for MemData {
#[inline(always)]
fn default() -> MemData {
<crate::RegValueT<MemData_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Sof16_SPEC;
impl crate::sealed::RegSpec for Sof16_SPEC {
type DataType = u32;
}
#[doc = "Start Of Frame Register"]
pub type Sof16 = crate::RegValueT<Sof16_SPEC>;
impl Sof16 {
#[doc = "The frame number (11b)"]
#[inline(always)]
pub fn frame_number16(
self,
) -> crate::common::RegisterField<0, 0x7ff, 1, 0, u16, u16, Sof16_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x7ff,1,0,u16,u16,Sof16_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Sof16 {
#[inline(always)]
fn default() -> Sof16 {
<crate::RegValueT<Sof16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct OsclkDr16_SPEC;
impl crate::sealed::RegSpec for OsclkDr16_SPEC {
type DataType = u32;
}
#[doc = "Oscillator lock data register"]
pub type OsclkDr16 = crate::RegValueT<OsclkDr16_SPEC>;
impl OsclkDr16 {
#[doc = "These bits return the oscillator locking circuits adder output."]
#[inline(always)]
pub fn adder16(
self,
) -> crate::common::RegisterField<0, 0x7fff, 1, 0, u16, u16, OsclkDr16_SPEC, crate::common::R>
{
crate::common::RegisterField::<
0,
0x7fff,
1,
0,
u16,
u16,
OsclkDr16_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for OsclkDr16 {
#[inline(always)]
fn default() -> OsclkDr16 {
<crate::RegValueT<OsclkDr16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw1Wa16_SPEC;
impl crate::sealed::RegSpec for ArbRw1Wa16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *3"]
pub type ArbRw1Wa16 = crate::RegValueT<ArbRw1Wa16_SPEC>;
impl ArbRw1Wa16 {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw1Wa16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw1Wa16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw1Wa16 {
#[inline(always)]
fn default() -> ArbRw1Wa16 {
<crate::RegValueT<ArbRw1Wa16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw1Ra16_SPEC;
impl crate::sealed::RegSpec for ArbRw1Ra16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *3"]
pub type ArbRw1Ra16 = crate::RegValueT<ArbRw1Ra16_SPEC>;
impl ArbRw1Ra16 {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw1Ra16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw1Ra16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw1Ra16 {
#[inline(always)]
fn default() -> ArbRw1Ra16 {
<crate::RegValueT<ArbRw1Ra16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw1Dr16_SPEC;
impl crate::sealed::RegSpec for ArbRw1Dr16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Data Register"]
pub type ArbRw1Dr16 = crate::RegValueT<ArbRw1Dr16_SPEC>;
impl ArbRw1Dr16 {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr16(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ArbRw1Dr16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ArbRw1Dr16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw1Dr16 {
#[inline(always)]
fn default() -> ArbRw1Dr16 {
<crate::RegValueT<ArbRw1Dr16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw2Wa16_SPEC;
impl crate::sealed::RegSpec for ArbRw2Wa16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *3"]
pub type ArbRw2Wa16 = crate::RegValueT<ArbRw2Wa16_SPEC>;
impl ArbRw2Wa16 {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw2Wa16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw2Wa16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw2Wa16 {
#[inline(always)]
fn default() -> ArbRw2Wa16 {
<crate::RegValueT<ArbRw2Wa16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw2Ra16_SPEC;
impl crate::sealed::RegSpec for ArbRw2Ra16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *3"]
pub type ArbRw2Ra16 = crate::RegValueT<ArbRw2Ra16_SPEC>;
impl ArbRw2Ra16 {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw2Ra16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw2Ra16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw2Ra16 {
#[inline(always)]
fn default() -> ArbRw2Ra16 {
<crate::RegValueT<ArbRw2Ra16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw2Dr16_SPEC;
impl crate::sealed::RegSpec for ArbRw2Dr16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Data Register"]
pub type ArbRw2Dr16 = crate::RegValueT<ArbRw2Dr16_SPEC>;
impl ArbRw2Dr16 {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr16(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ArbRw2Dr16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ArbRw2Dr16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw2Dr16 {
#[inline(always)]
fn default() -> ArbRw2Dr16 {
<crate::RegValueT<ArbRw2Dr16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw3Wa16_SPEC;
impl crate::sealed::RegSpec for ArbRw3Wa16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *3"]
pub type ArbRw3Wa16 = crate::RegValueT<ArbRw3Wa16_SPEC>;
impl ArbRw3Wa16 {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw3Wa16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw3Wa16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw3Wa16 {
#[inline(always)]
fn default() -> ArbRw3Wa16 {
<crate::RegValueT<ArbRw3Wa16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw3Ra16_SPEC;
impl crate::sealed::RegSpec for ArbRw3Ra16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *3"]
pub type ArbRw3Ra16 = crate::RegValueT<ArbRw3Ra16_SPEC>;
impl ArbRw3Ra16 {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw3Ra16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw3Ra16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw3Ra16 {
#[inline(always)]
fn default() -> ArbRw3Ra16 {
<crate::RegValueT<ArbRw3Ra16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw3Dr16_SPEC;
impl crate::sealed::RegSpec for ArbRw3Dr16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Data Register"]
pub type ArbRw3Dr16 = crate::RegValueT<ArbRw3Dr16_SPEC>;
impl ArbRw3Dr16 {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr16(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ArbRw3Dr16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ArbRw3Dr16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw3Dr16 {
#[inline(always)]
fn default() -> ArbRw3Dr16 {
<crate::RegValueT<ArbRw3Dr16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cwa16_SPEC;
impl crate::sealed::RegSpec for Cwa16_SPEC {
type DataType = u32;
}
#[doc = "Common Area Write Address"]
pub type Cwa16 = crate::RegValueT<Cwa16_SPEC>;
impl Cwa16 {
#[doc = "Write Address for Common Area"]
#[inline(always)]
pub fn cwa16(
self,
) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, Cwa16_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,Cwa16_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cwa16 {
#[inline(always)]
fn default() -> Cwa16 {
<crate::RegValueT<Cwa16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw4Wa16_SPEC;
impl crate::sealed::RegSpec for ArbRw4Wa16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *3"]
pub type ArbRw4Wa16 = crate::RegValueT<ArbRw4Wa16_SPEC>;
impl ArbRw4Wa16 {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw4Wa16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw4Wa16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw4Wa16 {
#[inline(always)]
fn default() -> ArbRw4Wa16 {
<crate::RegValueT<ArbRw4Wa16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw4Ra16_SPEC;
impl crate::sealed::RegSpec for ArbRw4Ra16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *3"]
pub type ArbRw4Ra16 = crate::RegValueT<ArbRw4Ra16_SPEC>;
impl ArbRw4Ra16 {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw4Ra16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw4Ra16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw4Ra16 {
#[inline(always)]
fn default() -> ArbRw4Ra16 {
<crate::RegValueT<ArbRw4Ra16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw4Dr16_SPEC;
impl crate::sealed::RegSpec for ArbRw4Dr16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Data Register"]
pub type ArbRw4Dr16 = crate::RegValueT<ArbRw4Dr16_SPEC>;
impl ArbRw4Dr16 {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr16(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ArbRw4Dr16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ArbRw4Dr16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw4Dr16 {
#[inline(always)]
fn default() -> ArbRw4Dr16 {
<crate::RegValueT<ArbRw4Dr16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DmaThres16_SPEC;
impl crate::sealed::RegSpec for DmaThres16_SPEC {
type DataType = u32;
}
#[doc = "DMA Burst / Threshold Configuration"]
pub type DmaThres16 = crate::RegValueT<DmaThres16_SPEC>;
impl DmaThres16 {
#[doc = "DMA Threshold count"]
#[inline(always)]
pub fn dma_ths16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
DmaThres16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
DmaThres16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DmaThres16 {
#[inline(always)]
fn default() -> DmaThres16 {
<crate::RegValueT<DmaThres16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw5Wa16_SPEC;
impl crate::sealed::RegSpec for ArbRw5Wa16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *3"]
pub type ArbRw5Wa16 = crate::RegValueT<ArbRw5Wa16_SPEC>;
impl ArbRw5Wa16 {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw5Wa16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw5Wa16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw5Wa16 {
#[inline(always)]
fn default() -> ArbRw5Wa16 {
<crate::RegValueT<ArbRw5Wa16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw5Ra16_SPEC;
impl crate::sealed::RegSpec for ArbRw5Ra16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *3"]
pub type ArbRw5Ra16 = crate::RegValueT<ArbRw5Ra16_SPEC>;
impl ArbRw5Ra16 {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw5Ra16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw5Ra16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw5Ra16 {
#[inline(always)]
fn default() -> ArbRw5Ra16 {
<crate::RegValueT<ArbRw5Ra16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw5Dr16_SPEC;
impl crate::sealed::RegSpec for ArbRw5Dr16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Data Register"]
pub type ArbRw5Dr16 = crate::RegValueT<ArbRw5Dr16_SPEC>;
impl ArbRw5Dr16 {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr16(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ArbRw5Dr16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ArbRw5Dr16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw5Dr16 {
#[inline(always)]
fn default() -> ArbRw5Dr16 {
<crate::RegValueT<ArbRw5Dr16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw6Wa16_SPEC;
impl crate::sealed::RegSpec for ArbRw6Wa16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *3"]
pub type ArbRw6Wa16 = crate::RegValueT<ArbRw6Wa16_SPEC>;
impl ArbRw6Wa16 {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw6Wa16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw6Wa16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw6Wa16 {
#[inline(always)]
fn default() -> ArbRw6Wa16 {
<crate::RegValueT<ArbRw6Wa16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw6Ra16_SPEC;
impl crate::sealed::RegSpec for ArbRw6Ra16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *3"]
pub type ArbRw6Ra16 = crate::RegValueT<ArbRw6Ra16_SPEC>;
impl ArbRw6Ra16 {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw6Ra16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw6Ra16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw6Ra16 {
#[inline(always)]
fn default() -> ArbRw6Ra16 {
<crate::RegValueT<ArbRw6Ra16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw6Dr16_SPEC;
impl crate::sealed::RegSpec for ArbRw6Dr16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Data Register"]
pub type ArbRw6Dr16 = crate::RegValueT<ArbRw6Dr16_SPEC>;
impl ArbRw6Dr16 {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr16(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ArbRw6Dr16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ArbRw6Dr16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw6Dr16 {
#[inline(always)]
fn default() -> ArbRw6Dr16 {
<crate::RegValueT<ArbRw6Dr16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw7Wa16_SPEC;
impl crate::sealed::RegSpec for ArbRw7Wa16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *3"]
pub type ArbRw7Wa16 = crate::RegValueT<ArbRw7Wa16_SPEC>;
impl ArbRw7Wa16 {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw7Wa16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw7Wa16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw7Wa16 {
#[inline(always)]
fn default() -> ArbRw7Wa16 {
<crate::RegValueT<ArbRw7Wa16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw7Ra16_SPEC;
impl crate::sealed::RegSpec for ArbRw7Ra16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *3"]
pub type ArbRw7Ra16 = crate::RegValueT<ArbRw7Ra16_SPEC>;
impl ArbRw7Ra16 {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw7Ra16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw7Ra16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw7Ra16 {
#[inline(always)]
fn default() -> ArbRw7Ra16 {
<crate::RegValueT<ArbRw7Ra16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw7Dr16_SPEC;
impl crate::sealed::RegSpec for ArbRw7Dr16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Data Register"]
pub type ArbRw7Dr16 = crate::RegValueT<ArbRw7Dr16_SPEC>;
impl ArbRw7Dr16 {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr16(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ArbRw7Dr16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ArbRw7Dr16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw7Dr16 {
#[inline(always)]
fn default() -> ArbRw7Dr16 {
<crate::RegValueT<ArbRw7Dr16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw8Wa16_SPEC;
impl crate::sealed::RegSpec for ArbRw8Wa16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Write Address value *3"]
pub type ArbRw8Wa16 = crate::RegValueT<ArbRw8Wa16_SPEC>;
impl ArbRw8Wa16 {
#[doc = "Write Address for EP"]
#[inline(always)]
pub fn wa16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw8Wa16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw8Wa16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw8Wa16 {
#[inline(always)]
fn default() -> ArbRw8Wa16 {
<crate::RegValueT<ArbRw8Wa16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw8Ra16_SPEC;
impl crate::sealed::RegSpec for ArbRw8Ra16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Read Address value *3"]
pub type ArbRw8Ra16 = crate::RegValueT<ArbRw8Ra16_SPEC>;
impl ArbRw8Ra16 {
#[doc = "Read Address for EP"]
#[inline(always)]
pub fn ra16(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw8Ra16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
ArbRw8Ra16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw8Ra16 {
#[inline(always)]
fn default() -> ArbRw8Ra16 {
<crate::RegValueT<ArbRw8Ra16_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArbRw8Dr16_SPEC;
impl crate::sealed::RegSpec for ArbRw8Dr16_SPEC {
type DataType = u32;
}
#[doc = "Endpoint Data Register"]
pub type ArbRw8Dr16 = crate::RegValueT<ArbRw8Dr16_SPEC>;
impl ArbRw8Dr16 {
#[doc = "Data Register for EP ; This register is linked to the memory, hence reset value is undefined"]
#[inline(always)]
pub fn dr16(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ArbRw8Dr16_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ArbRw8Dr16_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ArbRw8Dr16 {
#[inline(always)]
fn default() -> ArbRw8Dr16 {
<crate::RegValueT<ArbRw8Dr16_SPEC> as RegisterValue<_>>::new(0)
}
}
}
#[doc = "USB Device LPM and PHY Test"]
#[non_exhaustive]
pub struct _Usblpm;
#[doc = "USB Device LPM and PHY Test"]
pub type Usblpm = &'static _Usblpm;
unsafe impl ::core::marker::Sync for _Usblpm {}
impl _Usblpm {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "Power Control Register"]
#[inline(always)]
pub const fn power_ctl(
&self,
) -> &'static crate::common::Reg<usblpm::PowerCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usblpm::PowerCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "USB IO Control Register"]
#[inline(always)]
pub const fn usbio_ctl(
&self,
) -> &'static crate::common::Reg<usblpm::UsbioCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usblpm::UsbioCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(8usize),
)
}
}
#[doc = "Flow Control Register"]
#[inline(always)]
pub const fn flow_ctl(
&self,
) -> &'static crate::common::Reg<usblpm::FlowCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usblpm::FlowCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(12usize),
)
}
}
#[doc = "LPM Control Register"]
#[inline(always)]
pub const fn lpm_ctl(
&self,
) -> &'static crate::common::Reg<usblpm::LpmCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usblpm::LpmCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16usize),
)
}
}
#[doc = "LPM Status register"]
#[inline(always)]
pub const fn lpm_stat(
&self,
) -> &'static crate::common::Reg<usblpm::LpmStat_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usblpm::LpmStat_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(20usize),
)
}
}
#[doc = "USB SOF, BUS RESET and EP0 Interrupt Status"]
#[inline(always)]
pub const fn intr_sie(
&self,
) -> &'static crate::common::Reg<usblpm::IntrSie_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usblpm::IntrSie_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "USB SOF, BUS RESET and EP0 Interrupt Set"]
#[inline(always)]
pub const fn intr_sie_set(
&self,
) -> &'static crate::common::Reg<usblpm::IntrSieSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usblpm::IntrSieSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
#[doc = "USB SOF, BUS RESET and EP0 Interrupt Mask"]
#[inline(always)]
pub const fn intr_sie_mask(
&self,
) -> &'static crate::common::Reg<usblpm::IntrSieMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usblpm::IntrSieMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(40usize),
)
}
}
#[doc = "USB SOF, BUS RESET and EP0 Interrupt Masked"]
#[inline(always)]
pub const fn intr_sie_masked(
&self,
) -> &'static crate::common::Reg<usblpm::IntrSieMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usblpm::IntrSieMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(44usize),
)
}
}
#[doc = "Select interrupt level for each interrupt source"]
#[inline(always)]
pub const fn intr_lvl_sel(
&self,
) -> &'static crate::common::Reg<usblpm::IntrLvlSel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usblpm::IntrLvlSel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(48usize),
)
}
}
#[doc = "High priority interrupt Cause register"]
#[inline(always)]
pub const fn intr_cause_hi(
&self,
) -> &'static crate::common::Reg<usblpm::IntrCauseHi_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usblpm::IntrCauseHi_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(52usize),
)
}
}
#[doc = "Medium priority interrupt Cause register"]
#[inline(always)]
pub const fn intr_cause_med(
&self,
) -> &'static crate::common::Reg<usblpm::IntrCauseMed_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usblpm::IntrCauseMed_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(56usize),
)
}
}
#[doc = "Low priority interrupt Cause register"]
#[inline(always)]
pub const fn intr_cause_lo(
&self,
) -> &'static crate::common::Reg<usblpm::IntrCauseLo_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usblpm::IntrCauseLo_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(60usize),
)
}
}
#[doc = "DFT control"]
#[inline(always)]
pub const fn dft_ctl(
&self,
) -> &'static crate::common::Reg<usblpm::DftCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usblpm::DftCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(112usize),
)
}
}
#[doc = "DDFT Select register"]
#[inline(always)]
pub const fn ddft0_sel(
&self,
) -> &'static crate::common::Reg<usblpm::Ddft0Sel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usblpm::Ddft0Sel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(116usize),
)
}
}
#[doc = "DDFT Select register"]
#[inline(always)]
pub const fn ddft1_sel(
&self,
) -> &'static crate::common::Reg<usblpm::Ddft1Sel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usblpm::Ddft1Sel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(120usize),
)
}
}
#[doc = "DDFT Select register"]
#[inline(always)]
pub const fn ddft2_sel(
&self,
) -> &'static crate::common::Reg<usblpm::Ddft2Sel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usblpm::Ddft2Sel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(124usize),
)
}
}
}
pub mod usblpm {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PowerCtl_SPEC;
impl crate::sealed::RegSpec for PowerCtl_SPEC {
type DataType = u32;
}
#[doc = "Power Control Register"]
pub type PowerCtl = crate::RegValueT<PowerCtl_SPEC>;
impl PowerCtl {
#[doc = "Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep).\nNote:\n- This bit is invalid if the HOST bit of the Host Control 0 Register (HOST_CTL0) is \'1\'."]
#[inline(always)]
pub fn suspend(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, PowerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,PowerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables the pull up on the DP.\n\'0\' : Disable.\n\'1\' : Enable."]
#[inline(always)]
pub fn dp_up_en(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, PowerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,PowerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select the resister value if POWER_CTL.DP_EN=\'1\'. This bit is valid in GPIO.\n\'0\' : The resister value is from 900 to1575Ohmpull up on the DP.\n\'1\' : The resister value is from 1425 to 3090Ohmpull up on the DP"]
#[inline(always)]
pub fn dp_big(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, PowerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,PowerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables the ~15k pull down on the DP."]
#[inline(always)]
pub fn dp_down_en(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, PowerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,PowerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO.\n\'0\' : Disable.\n\'1\' : Enable."]
#[inline(always)]
pub fn dm_up_en(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, PowerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,PowerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select the resister value if POWER_CTL.DM_EN=\'1\'. This bit is valid in GPIO.\n\'0\' : The resister value is from 900 to1575Ohmpull up on the DM.\n\'1\' : The resister value is from 1425 to 3090Ohmpull up on the DM"]
#[inline(always)]
pub fn dm_big(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, PowerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,PowerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables the ~15k pull down on the DP."]
#[inline(always)]
pub fn dm_down_en(
self,
) -> crate::common::RegisterFieldBool<21, 1, 0, PowerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<21,1,0,PowerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables the single ended receiver on D+."]
#[inline(always)]
pub fn enable_dpo(
self,
) -> crate::common::RegisterFieldBool<28, 1, 0, PowerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<28,1,0,PowerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables the signle ended receiver on D-."]
#[inline(always)]
pub fn enable_dmo(
self,
) -> crate::common::RegisterFieldBool<29, 1, 0, PowerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<29,1,0,PowerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for PowerCtl {
#[inline(always)]
fn default() -> PowerCtl {
<crate::RegValueT<PowerCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UsbioCtl_SPEC;
impl crate::sealed::RegSpec for UsbioCtl_SPEC {
type DataType = u32;
}
#[doc = "USB IO Control Register"]
pub type UsbioCtl = crate::RegValueT<UsbioCtl_SPEC>;
impl UsbioCtl {
#[doc = "The GPIO Drive Mode for DP IO pad. This field only applies if USBIO_CR1.IOMODE =1. Data comes from the corresponding GPIO.DR register."]
#[inline(always)]
pub fn dm_p(
self,
) -> crate::common::RegisterField<
0,
0x7,
1,
0,
usbio_ctl::DmP,
usbio_ctl::DmP,
UsbioCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x7,
1,
0,
usbio_ctl::DmP,
usbio_ctl::DmP,
UsbioCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "The GPIO Drive Mode for DM IO pad."]
#[inline(always)]
pub fn dm_m(
self,
) -> crate::common::RegisterField<3, 0x7, 1, 0, u8, u8, UsbioCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<3,0x7,1,0,u8,u8,UsbioCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for UsbioCtl {
#[inline(always)]
fn default() -> UsbioCtl {
<crate::RegValueT<UsbioCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod usbio_ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DmP_SPEC;
pub type DmP = crate::EnumBitfieldStruct<u8, DmP_SPEC>;
impl DmP {
#[doc = "Mode 0: Output buffer off (high Z). Input buffer off."]
pub const OFF: Self = Self::new(0);
#[doc = "Mode 1: Output buffer off (high Z). Input buffer on.\n\nOther values, not supported."]
pub const INPUT: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct FlowCtl_SPEC;
impl crate::sealed::RegSpec for FlowCtl_SPEC {
type DataType = u32;
}
#[doc = "Flow Control Register"]
pub type FlowCtl = crate::RegValueT<FlowCtl_SPEC>;
impl FlowCtl {
#[doc = "End Point 1 error response\n0: do nothing (backward compatibility mode)\n1: if this is an IN EP and an underflow occurs then cause a CRC error, if this is an OUT EP and an overflow occurs then send a NAK"]
#[inline(always)]
pub fn ep1_err_resp(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, FlowCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,FlowCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "End Point 2 error response"]
#[inline(always)]
pub fn ep2_err_resp(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, FlowCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,FlowCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "End Point 3 error response"]
#[inline(always)]
pub fn ep3_err_resp(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, FlowCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,FlowCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "End Point 4 error response"]
#[inline(always)]
pub fn ep4_err_resp(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, FlowCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,FlowCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "End Point 5 error response"]
#[inline(always)]
pub fn ep5_err_resp(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, FlowCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,FlowCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "End Point 6 error response"]
#[inline(always)]
pub fn ep6_err_resp(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, FlowCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,FlowCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "End Point 7 error response"]
#[inline(always)]
pub fn ep7_err_resp(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, FlowCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,FlowCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "End Point 8 error response"]
#[inline(always)]
pub fn ep8_err_resp(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, FlowCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,FlowCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for FlowCtl {
#[inline(always)]
fn default() -> FlowCtl {
<crate::RegValueT<FlowCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LpmCtl_SPEC;
impl crate::sealed::RegSpec for LpmCtl_SPEC {
type DataType = u32;
}
#[doc = "LPM Control Register"]
pub type LpmCtl = crate::RegValueT<LpmCtl_SPEC>;
impl LpmCtl {
#[doc = "LPM enable\n0: Disabled, LPM token will not get a response (backward compatibility mode) \n1: Enable, LPM token will get a handshake response (ACK, STALL, NYET or NAK)\n A STALL will be sent if the bLinkState is not 0001b\n A NYET, NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below"]
#[inline(always)]
pub fn lpm_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, LpmCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,LpmCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request \n0: a LPM token will get a NYET or NAK (depending on NYET_EN bit below) response and the device will NOT go to a low power mode \n1: a LPM token will get an ACK response and the device will go to the requested low power mode"]
#[inline(always)]
pub fn lpm_ack_resp(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, LpmCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,LpmCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0).\n0: a LPM token will get an NAK response (indicating a CRC error), the host is expected to repeat the LPM token.\n1: a LPM token will get a NYET response"]
#[inline(always)]
pub fn nyet_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, LpmCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,LpmCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs."]
#[inline(always)]
pub fn sub_resp(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, LpmCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,LpmCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for LpmCtl {
#[inline(always)]
fn default() -> LpmCtl {
<crate::RegValueT<LpmCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LpmStat_SPEC;
impl crate::sealed::RegSpec for LpmStat_SPEC {
type DataType = u32;
}
#[doc = "LPM Status register"]
pub type LpmStat = crate::RegValueT<LpmStat_SPEC>;
impl LpmStat {
#[doc = "Best Effort Service Latency\nThis value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor."]
#[inline(always)]
pub fn lpm_besl(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, LpmStat_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,LpmStat_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "0: Device is prohibited from initiating a remote wake\n1: Device is allow to wake the host"]
#[inline(always)]
pub fn lpm_remotewake(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, LpmStat_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4,1,0,LpmStat_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for LpmStat {
#[inline(always)]
fn default() -> LpmStat {
<crate::RegValueT<LpmStat_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSie_SPEC;
impl crate::sealed::RegSpec for IntrSie_SPEC {
type DataType = u32;
}
#[doc = "USB SOF, BUS RESET and EP0 Interrupt Status"]
pub type IntrSie = crate::RegValueT<IntrSie_SPEC>;
impl IntrSie {
#[doc = "Interrupt status for USB SOF"]
#[inline(always)]
pub fn sof_intr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSie_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrSie_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Interrupt status for BUS RESET"]
#[inline(always)]
pub fn bus_reset_intr(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSie_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,IntrSie_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Interrupt status for EP0"]
#[inline(always)]
pub fn ep0_intr(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrSie_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,IntrSie_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Interrupt status for LPM (Link Power Management, L1 entry)"]
#[inline(always)]
pub fn lpm_intr(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrSie_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,IntrSie_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Interrupt status for Resume"]
#[inline(always)]
pub fn resume_intr(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrSie_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,IntrSie_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrSie {
#[inline(always)]
fn default() -> IntrSie {
<crate::RegValueT<IntrSie_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSieSet_SPEC;
impl crate::sealed::RegSpec for IntrSieSet_SPEC {
type DataType = u32;
}
#[doc = "USB SOF, BUS RESET and EP0 Interrupt Set"]
pub type IntrSieSet = crate::RegValueT<IntrSieSet_SPEC>;
impl IntrSieSet {
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn sof_intr_set(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSieSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrSieSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn bus_reset_intr_set(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSieSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,IntrSieSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn ep0_intr_set(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrSieSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,IntrSieSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn lpm_intr_set(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrSieSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,IntrSieSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn resume_intr_set(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrSieSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,IntrSieSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrSieSet {
#[inline(always)]
fn default() -> IntrSieSet {
<crate::RegValueT<IntrSieSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSieMask_SPEC;
impl crate::sealed::RegSpec for IntrSieMask_SPEC {
type DataType = u32;
}
#[doc = "USB SOF, BUS RESET and EP0 Interrupt Mask"]
pub type IntrSieMask = crate::RegValueT<IntrSieMask_SPEC>;
impl IntrSieMask {
#[doc = "Set to 1 to enable interrupt corresponding to interrupt request register"]
#[inline(always)]
pub fn sof_intr_mask(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSieMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,IntrSieMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set to 1 to enable interrupt corresponding to interrupt request register"]
#[inline(always)]
pub fn bus_reset_intr_mask(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSieMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,IntrSieMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set to 1 to enable interrupt corresponding to interrupt request register"]
#[inline(always)]
pub fn ep0_intr_mask(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrSieMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,IntrSieMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set to 1 to enable interrupt corresponding to interrupt request register"]
#[inline(always)]
pub fn lpm_intr_mask(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrSieMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,IntrSieMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set to 1 to enable interrupt corresponding to interrupt request register"]
#[inline(always)]
pub fn resume_intr_mask(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrSieMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,IntrSieMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrSieMask {
#[inline(always)]
fn default() -> IntrSieMask {
<crate::RegValueT<IntrSieMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSieMasked_SPEC;
impl crate::sealed::RegSpec for IntrSieMasked_SPEC {
type DataType = u32;
}
#[doc = "USB SOF, BUS RESET and EP0 Interrupt Masked"]
pub type IntrSieMasked = crate::RegValueT<IntrSieMasked_SPEC>;
impl IntrSieMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn sof_intr_masked(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSieMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<0,1,0,IntrSieMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn bus_reset_intr_masked(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSieMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<1,1,0,IntrSieMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn ep0_intr_masked(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrSieMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<2,1,0,IntrSieMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn lpm_intr_masked(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrSieMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<3,1,0,IntrSieMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn resume_intr_masked(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrSieMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<4,1,0,IntrSieMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrSieMasked {
#[inline(always)]
fn default() -> IntrSieMasked {
<crate::RegValueT<IntrSieMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrLvlSel_SPEC;
impl crate::sealed::RegSpec for IntrLvlSel_SPEC {
type DataType = u32;
}
#[doc = "Select interrupt level for each interrupt source"]
pub type IntrLvlSel = crate::RegValueT<IntrLvlSel_SPEC>;
impl IntrLvlSel {
#[doc = "USB SOF Interrupt level select"]
#[inline(always)]
pub fn sof_lvl_sel(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
intr_lvl_sel::SofLvlSel,
intr_lvl_sel::SofLvlSel,
IntrLvlSel_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
intr_lvl_sel::SofLvlSel,
intr_lvl_sel::SofLvlSel,
IntrLvlSel_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "BUS RESET Interrupt level select"]
#[inline(always)]
pub fn bus_reset_lvl_sel(
self,
) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, IntrLvlSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<2,0x3,1,0,u8,u8,IntrLvlSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "EP0 Interrupt level select"]
#[inline(always)]
pub fn ep0_lvl_sel(
self,
) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, IntrLvlSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0x3,1,0,u8,u8,IntrLvlSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "LPM Interrupt level select"]
#[inline(always)]
pub fn lpm_lvl_sel(
self,
) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, IntrLvlSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<6,0x3,1,0,u8,u8,IntrLvlSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Resume Interrupt level select"]
#[inline(always)]
pub fn resume_lvl_sel(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, IntrLvlSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,IntrLvlSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Arbiter Endpoint Interrupt level select"]
#[inline(always)]
pub fn arb_ep_lvl_sel(
self,
) -> crate::common::RegisterField<14, 0x3, 1, 0, u8, u8, IntrLvlSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<14,0x3,1,0,u8,u8,IntrLvlSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "EP1 Interrupt level select"]
#[inline(always)]
pub fn ep1_lvl_sel(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, IntrLvlSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3,1,0,u8,u8,IntrLvlSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "EP2 Interrupt level select"]
#[inline(always)]
pub fn ep2_lvl_sel(
self,
) -> crate::common::RegisterField<18, 0x3, 1, 0, u8, u8, IntrLvlSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<18,0x3,1,0,u8,u8,IntrLvlSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "EP3 Interrupt level select"]
#[inline(always)]
pub fn ep3_lvl_sel(
self,
) -> crate::common::RegisterField<20, 0x3, 1, 0, u8, u8, IntrLvlSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<20,0x3,1,0,u8,u8,IntrLvlSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "EP4 Interrupt level select"]
#[inline(always)]
pub fn ep4_lvl_sel(
self,
) -> crate::common::RegisterField<22, 0x3, 1, 0, u8, u8, IntrLvlSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<22,0x3,1,0,u8,u8,IntrLvlSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "EP5 Interrupt level select"]
#[inline(always)]
pub fn ep5_lvl_sel(
self,
) -> crate::common::RegisterField<24, 0x3, 1, 0, u8, u8, IntrLvlSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0x3,1,0,u8,u8,IntrLvlSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "EP6 Interrupt level select"]
#[inline(always)]
pub fn ep6_lvl_sel(
self,
) -> crate::common::RegisterField<26, 0x3, 1, 0, u8, u8, IntrLvlSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<26,0x3,1,0,u8,u8,IntrLvlSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "EP7 Interrupt level select"]
#[inline(always)]
pub fn ep7_lvl_sel(
self,
) -> crate::common::RegisterField<28, 0x3, 1, 0, u8, u8, IntrLvlSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<28,0x3,1,0,u8,u8,IntrLvlSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "EP8 Interrupt level select"]
#[inline(always)]
pub fn ep8_lvl_sel(
self,
) -> crate::common::RegisterField<30, 0x3, 1, 0, u8, u8, IntrLvlSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<30,0x3,1,0,u8,u8,IntrLvlSel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrLvlSel {
#[inline(always)]
fn default() -> IntrLvlSel {
<crate::RegValueT<IntrLvlSel_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod intr_lvl_sel {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct SofLvlSel_SPEC;
pub type SofLvlSel = crate::EnumBitfieldStruct<u8, SofLvlSel_SPEC>;
impl SofLvlSel {
#[doc = "High priority interrupt"]
pub const HI: Self = Self::new(0);
#[doc = "Medium priority interrupt"]
pub const MED: Self = Self::new(1);
#[doc = "Low priority interrupt"]
pub const LO: Self = Self::new(2);
#[doc = "illegal"]
pub const RSVD: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrCauseHi_SPEC;
impl crate::sealed::RegSpec for IntrCauseHi_SPEC {
type DataType = u32;
}
#[doc = "High priority interrupt Cause register"]
pub type IntrCauseHi = crate::RegValueT<IntrCauseHi_SPEC>;
impl IntrCauseHi {
#[doc = "USB SOF Interrupt"]
#[inline(always)]
pub fn sof_intr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrCauseHi_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,IntrCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "BUS RESET Interrupt"]
#[inline(always)]
pub fn bus_reset_intr(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrCauseHi_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,IntrCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP0 Interrupt"]
#[inline(always)]
pub fn ep0_intr(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrCauseHi_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,IntrCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "LPM Interrupt"]
#[inline(always)]
pub fn lpm_intr(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrCauseHi_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3,1,0,IntrCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Resume Interrupt"]
#[inline(always)]
pub fn resume_intr(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrCauseHi_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4,1,0,IntrCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Arbiter Endpoint Interrupt"]
#[inline(always)]
pub fn arb_ep_intr(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrCauseHi_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<7,1,0,IntrCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP1 Interrupt"]
#[inline(always)]
pub fn ep1_intr(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrCauseHi_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8,1,0,IntrCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP2 Interrupt"]
#[inline(always)]
pub fn ep2_intr(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrCauseHi_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<9,1,0,IntrCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP3 Interrupt"]
#[inline(always)]
pub fn ep3_intr(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<10,1,0,IntrCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP4 Interrupt"]
#[inline(always)]
pub fn ep4_intr(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, IntrCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<11,1,0,IntrCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP5 Interrupt"]
#[inline(always)]
pub fn ep5_intr(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, IntrCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<12,1,0,IntrCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP6 Interrupt"]
#[inline(always)]
pub fn ep6_intr(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, IntrCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<13,1,0,IntrCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP7 Interrupt"]
#[inline(always)]
pub fn ep7_intr(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, IntrCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<14,1,0,IntrCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP8 Interrupt"]
#[inline(always)]
pub fn ep8_intr(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, IntrCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<15,1,0,IntrCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrCauseHi {
#[inline(always)]
fn default() -> IntrCauseHi {
<crate::RegValueT<IntrCauseHi_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrCauseMed_SPEC;
impl crate::sealed::RegSpec for IntrCauseMed_SPEC {
type DataType = u32;
}
#[doc = "Medium priority interrupt Cause register"]
pub type IntrCauseMed = crate::RegValueT<IntrCauseMed_SPEC>;
impl IntrCauseMed {
#[doc = "USB SOF Interrupt"]
#[inline(always)]
pub fn sof_intr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<0,1,0,IntrCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "BUS RESET Interrupt"]
#[inline(always)]
pub fn bus_reset_intr(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<1,1,0,IntrCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP0 Interrupt"]
#[inline(always)]
pub fn ep0_intr(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<2,1,0,IntrCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "LPM Interrupt"]
#[inline(always)]
pub fn lpm_intr(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<3,1,0,IntrCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Resume Interrupt"]
#[inline(always)]
pub fn resume_intr(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<4,1,0,IntrCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Arbiter Endpoint Interrupt"]
#[inline(always)]
pub fn arb_ep_intr(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<7,1,0,IntrCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP1 Interrupt"]
#[inline(always)]
pub fn ep1_intr(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<8,1,0,IntrCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP2 Interrupt"]
#[inline(always)]
pub fn ep2_intr(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<9,1,0,IntrCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP3 Interrupt"]
#[inline(always)]
pub fn ep3_intr(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<10,1,0,IntrCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP4 Interrupt"]
#[inline(always)]
pub fn ep4_intr(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, IntrCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<11,1,0,IntrCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP5 Interrupt"]
#[inline(always)]
pub fn ep5_intr(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, IntrCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<12,1,0,IntrCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP6 Interrupt"]
#[inline(always)]
pub fn ep6_intr(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, IntrCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<13,1,0,IntrCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP7 Interrupt"]
#[inline(always)]
pub fn ep7_intr(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, IntrCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<14,1,0,IntrCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP8 Interrupt"]
#[inline(always)]
pub fn ep8_intr(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, IntrCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<15,1,0,IntrCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrCauseMed {
#[inline(always)]
fn default() -> IntrCauseMed {
<crate::RegValueT<IntrCauseMed_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrCauseLo_SPEC;
impl crate::sealed::RegSpec for IntrCauseLo_SPEC {
type DataType = u32;
}
#[doc = "Low priority interrupt Cause register"]
pub type IntrCauseLo = crate::RegValueT<IntrCauseLo_SPEC>;
impl IntrCauseLo {
#[doc = "USB SOF Interrupt"]
#[inline(always)]
pub fn sof_intr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrCauseLo_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,IntrCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "BUS RESET Interrupt"]
#[inline(always)]
pub fn bus_reset_intr(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrCauseLo_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,IntrCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP0 Interrupt"]
#[inline(always)]
pub fn ep0_intr(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrCauseLo_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,IntrCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "LPM Interrupt"]
#[inline(always)]
pub fn lpm_intr(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrCauseLo_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3,1,0,IntrCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Resume Interrupt"]
#[inline(always)]
pub fn resume_intr(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrCauseLo_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4,1,0,IntrCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Arbiter Endpoint Interrupt"]
#[inline(always)]
pub fn arb_ep_intr(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrCauseLo_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<7,1,0,IntrCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP1 Interrupt"]
#[inline(always)]
pub fn ep1_intr(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrCauseLo_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8,1,0,IntrCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP2 Interrupt"]
#[inline(always)]
pub fn ep2_intr(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrCauseLo_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<9,1,0,IntrCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP3 Interrupt"]
#[inline(always)]
pub fn ep3_intr(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<10,1,0,IntrCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP4 Interrupt"]
#[inline(always)]
pub fn ep4_intr(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, IntrCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<11,1,0,IntrCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP5 Interrupt"]
#[inline(always)]
pub fn ep5_intr(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, IntrCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<12,1,0,IntrCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP6 Interrupt"]
#[inline(always)]
pub fn ep6_intr(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, IntrCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<13,1,0,IntrCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP7 Interrupt"]
#[inline(always)]
pub fn ep7_intr(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, IntrCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<14,1,0,IntrCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP8 Interrupt"]
#[inline(always)]
pub fn ep8_intr(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, IntrCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<15,1,0,IntrCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrCauseLo {
#[inline(always)]
fn default() -> IntrCauseLo {
<crate::RegValueT<IntrCauseLo_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DftCtl_SPEC;
impl crate::sealed::RegSpec for DftCtl_SPEC {
type DataType = u32;
}
#[doc = "DFT control"]
pub type DftCtl = crate::RegValueT<DftCtl_SPEC>;
impl DftCtl {
#[doc = "DDFT output select signal"]
#[inline(always)]
pub fn ddft_out_sel(
self,
) -> crate::common::RegisterField<
0,
0x7,
1,
0,
dft_ctl::DdftOutSel,
dft_ctl::DdftOutSel,
DftCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x7,
1,
0,
dft_ctl::DdftOutSel,
dft_ctl::DdftOutSel,
DftCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "DDFT input select signal"]
#[inline(always)]
pub fn ddft_in_sel(
self,
) -> crate::common::RegisterField<
3,
0x3,
1,
0,
dft_ctl::DdftInSel,
dft_ctl::DdftInSel,
DftCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
3,
0x3,
1,
0,
dft_ctl::DdftInSel,
dft_ctl::DdftInSel,
DftCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DftCtl {
#[inline(always)]
fn default() -> DftCtl {
<crate::RegValueT<DftCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod dft_ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DdftOutSel_SPEC;
pub type DdftOutSel = crate::EnumBitfieldStruct<u8, DdftOutSel_SPEC>;
impl DdftOutSel {
#[doc = "Nothing connected, output 0"]
pub const OFF: Self = Self::new(0);
#[doc = "Single Ended output of DP"]
pub const DP_SE: Self = Self::new(1);
#[doc = "Single Ended output of DM"]
pub const DM_SE: Self = Self::new(2);
#[doc = "Output Enable"]
pub const TXOE: Self = Self::new(3);
#[doc = "Differential Receiver output"]
pub const RCV_DF: Self = Self::new(4);
#[doc = "GPIO output of DP"]
pub const GPIO_DP_OUT: Self = Self::new(5);
#[doc = "GPIO output of DM"]
pub const GPIO_DM_OUT: Self = Self::new(6);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DdftInSel_SPEC;
pub type DdftInSel = crate::EnumBitfieldStruct<u8, DdftInSel_SPEC>;
impl DdftInSel {
#[doc = "Nothing connected, output 0"]
pub const OFF: Self = Self::new(0);
#[doc = "GPIO input of DP"]
pub const GPIO_DP_IN: Self = Self::new(1);
#[doc = "GPIO input of DM"]
pub const GPIO_DM_IN: Self = Self::new(2);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ddft0Sel_SPEC;
impl crate::sealed::RegSpec for Ddft0Sel_SPEC {
type DataType = u32;
}
#[doc = "DDFT Select register"]
pub type Ddft0Sel = crate::RegValueT<Ddft0Sel_SPEC>;
impl Ddft0Sel {
#[doc = "Selects internal DUT signal that need to be observed on pin-0 of DDFT pair"]
#[inline(always)]
pub fn ddft0_mux_sel(
self,
) -> crate::common::RegisterField<0, 0xfff, 1, 0, u16, u16, Ddft0Sel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xfff,1,0,u16,u16,Ddft0Sel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Selects internal DUT signal that need to be observed on pin-1 of DDFT pair"]
#[inline(always)]
pub fn ddft1_mux_sel(
self,
) -> crate::common::RegisterField<15, 0xfff, 1, 0, u16, u16, Ddft0Sel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
15,
0xfff,
1,
0,
u16,
u16,
Ddft0Sel_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Ddft0Sel {
#[inline(always)]
fn default() -> Ddft0Sel {
<crate::RegValueT<Ddft0Sel_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ddft1Sel_SPEC;
impl crate::sealed::RegSpec for Ddft1Sel_SPEC {
type DataType = u32;
}
#[doc = "DDFT Select register"]
pub type Ddft1Sel = crate::RegValueT<Ddft1Sel_SPEC>;
impl Ddft1Sel {
#[doc = "Selects internal DUT signal that need to be observed on pin-0 of DDFT pair"]
#[inline(always)]
pub fn ddft0_mux_sel(
self,
) -> crate::common::RegisterField<0, 0xfff, 1, 0, u16, u16, Ddft1Sel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xfff,1,0,u16,u16,Ddft1Sel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Selects internal DUT signal that need to be observed on pin-1 of DDFT pair"]
#[inline(always)]
pub fn ddft1_mux_sel(
self,
) -> crate::common::RegisterField<15, 0xfff, 1, 0, u16, u16, Ddft1Sel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
15,
0xfff,
1,
0,
u16,
u16,
Ddft1Sel_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Ddft1Sel {
#[inline(always)]
fn default() -> Ddft1Sel {
<crate::RegValueT<Ddft1Sel_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ddft2Sel_SPEC;
impl crate::sealed::RegSpec for Ddft2Sel_SPEC {
type DataType = u32;
}
#[doc = "DDFT Select register"]
pub type Ddft2Sel = crate::RegValueT<Ddft2Sel_SPEC>;
impl Ddft2Sel {
#[doc = "Selects internal DUT signal that need to be observed on pin-0 of DDFT pair"]
#[inline(always)]
pub fn ddft0_mux_sel(
self,
) -> crate::common::RegisterField<0, 0xfff, 1, 0, u16, u16, Ddft2Sel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xfff,1,0,u16,u16,Ddft2Sel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Selects internal DUT signal that need to be observed on pin-1 of DDFT pair"]
#[inline(always)]
pub fn ddft1_mux_sel(
self,
) -> crate::common::RegisterField<15, 0xfff, 1, 0, u16, u16, Ddft2Sel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
15,
0xfff,
1,
0,
u16,
u16,
Ddft2Sel_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Ddft2Sel {
#[inline(always)]
fn default() -> Ddft2Sel {
<crate::RegValueT<Ddft2Sel_SPEC> as RegisterValue<_>>::new(0)
}
}
}
#[doc = "USB Host Controller"]
#[non_exhaustive]
pub struct _Usbhost;
#[doc = "USB Host Controller"]
pub type Usbhost = &'static _Usbhost;
unsafe impl ::core::marker::Sync for _Usbhost {}
impl _Usbhost {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "Host Control 0 Register."]
#[inline(always)]
pub const fn host_ctl0(
&self,
) -> &'static crate::common::Reg<usbhost::HostCtl0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostCtl0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Host Control 1 Register."]
#[inline(always)]
pub const fn host_ctl1(
&self,
) -> &'static crate::common::Reg<usbhost::HostCtl1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostCtl1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16usize),
)
}
}
#[doc = "Host Control 2 Register."]
#[inline(always)]
pub const fn host_ctl2(
&self,
) -> &'static crate::common::Reg<usbhost::HostCtl2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostCtl2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(256usize),
)
}
}
#[doc = "Host Error Status Register."]
#[inline(always)]
pub const fn host_err(
&self,
) -> &'static crate::common::Reg<usbhost::HostErr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostErr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(260usize),
)
}
}
#[doc = "Host Status Register."]
#[inline(always)]
pub const fn host_status(
&self,
) -> &'static crate::common::Reg<usbhost::HostStatus_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostStatus_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(264usize),
)
}
}
#[doc = "Host SOF Interrupt Frame Compare Register"]
#[inline(always)]
pub const fn host_fcomp(
&self,
) -> &'static crate::common::Reg<usbhost::HostFcomp_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostFcomp_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(268usize),
)
}
}
#[doc = "Host Retry Timer Setup Register"]
#[inline(always)]
pub const fn host_rtimer(
&self,
) -> &'static crate::common::Reg<usbhost::HostRtimer_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostRtimer_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(272usize),
)
}
}
#[doc = "Host Address Register"]
#[inline(always)]
pub const fn host_addr(
&self,
) -> &'static crate::common::Reg<usbhost::HostAddr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostAddr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(276usize),
)
}
}
#[doc = "Host EOF Setup Register"]
#[inline(always)]
pub const fn host_eof(
&self,
) -> &'static crate::common::Reg<usbhost::HostEof_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostEof_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(280usize),
)
}
}
#[doc = "Host Frame Setup Register"]
#[inline(always)]
pub const fn host_frame(
&self,
) -> &'static crate::common::Reg<usbhost::HostFrame_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostFrame_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(284usize),
)
}
}
#[doc = "Host Token Endpoint Register"]
#[inline(always)]
pub const fn host_token(
&self,
) -> &'static crate::common::Reg<usbhost::HostToken_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostToken_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(288usize),
)
}
}
#[doc = "Host Endpoint 1 Control Register"]
#[inline(always)]
pub const fn host_ep1_ctl(
&self,
) -> &'static crate::common::Reg<usbhost::HostEp1Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostEp1Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1024usize),
)
}
}
#[doc = "Host Endpoint 1 Status Register"]
#[inline(always)]
pub const fn host_ep1_status(
&self,
) -> &'static crate::common::Reg<usbhost::HostEp1Status_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbhost::HostEp1Status_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1028usize),
)
}
}
#[doc = "Host Endpoint 1 Data 1-Byte Register"]
#[inline(always)]
pub const fn host_ep1_rw1_dr(
&self,
) -> &'static crate::common::Reg<usbhost::HostEp1Rw1Dr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostEp1Rw1Dr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1032usize),
)
}
}
#[doc = "Host Endpoint 1 Data 2-Byte Register"]
#[inline(always)]
pub const fn host_ep1_rw2_dr(
&self,
) -> &'static crate::common::Reg<usbhost::HostEp1Rw2Dr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostEp1Rw2Dr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1036usize),
)
}
}
#[doc = "Host Endpoint 2 Control Register"]
#[inline(always)]
pub const fn host_ep2_ctl(
&self,
) -> &'static crate::common::Reg<usbhost::HostEp2Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostEp2Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1280usize),
)
}
}
#[doc = "Host Endpoint 2 Status Register"]
#[inline(always)]
pub const fn host_ep2_status(
&self,
) -> &'static crate::common::Reg<usbhost::HostEp2Status_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbhost::HostEp2Status_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1284usize),
)
}
}
#[doc = "Host Endpoint 2 Data 1-Byte Register"]
#[inline(always)]
pub const fn host_ep2_rw1_dr(
&self,
) -> &'static crate::common::Reg<usbhost::HostEp2Rw1Dr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostEp2Rw1Dr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1288usize),
)
}
}
#[doc = "Host Endpoint 2 Data 2-Byte Register"]
#[inline(always)]
pub const fn host_ep2_rw2_dr(
&self,
) -> &'static crate::common::Reg<usbhost::HostEp2Rw2Dr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostEp2Rw2Dr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1292usize),
)
}
}
#[doc = "Host Interrupt Level 1 Selection Register"]
#[inline(always)]
pub const fn host_lvl1_sel(
&self,
) -> &'static crate::common::Reg<usbhost::HostLvl1Sel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostLvl1Sel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2048usize),
)
}
}
#[doc = "Host Interrupt Level 2 Selection Register"]
#[inline(always)]
pub const fn host_lvl2_sel(
&self,
) -> &'static crate::common::Reg<usbhost::HostLvl2Sel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostLvl2Sel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2052usize),
)
}
}
#[doc = "Interrupt USB Host Cause High Register"]
#[inline(always)]
pub const fn intr_usbhost_cause_hi(
&self,
) -> &'static crate::common::Reg<usbhost::IntrUsbhostCauseHi_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbhost::IntrUsbhostCauseHi_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(2304usize),
)
}
}
#[doc = "Interrupt USB Host Cause Medium Register"]
#[inline(always)]
pub const fn intr_usbhost_cause_med(
&self,
) -> &'static crate::common::Reg<usbhost::IntrUsbhostCauseMed_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbhost::IntrUsbhostCauseMed_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(2308usize),
)
}
}
#[doc = "Interrupt USB Host Cause Low Register"]
#[inline(always)]
pub const fn intr_usbhost_cause_lo(
&self,
) -> &'static crate::common::Reg<usbhost::IntrUsbhostCauseLo_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbhost::IntrUsbhostCauseLo_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(2312usize),
)
}
}
#[doc = "Interrupt USB Host Endpoint Cause High Register"]
#[inline(always)]
pub const fn intr_host_ep_cause_hi(
&self,
) -> &'static crate::common::Reg<usbhost::IntrHostEpCauseHi_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbhost::IntrHostEpCauseHi_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(2336usize),
)
}
}
#[doc = "Interrupt USB Host Endpoint Cause Medium Register"]
#[inline(always)]
pub const fn intr_host_ep_cause_med(
&self,
) -> &'static crate::common::Reg<usbhost::IntrHostEpCauseMed_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbhost::IntrHostEpCauseMed_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(2340usize),
)
}
}
#[doc = "Interrupt USB Host Endpoint Cause Low Register"]
#[inline(always)]
pub const fn intr_host_ep_cause_lo(
&self,
) -> &'static crate::common::Reg<usbhost::IntrHostEpCauseLo_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbhost::IntrHostEpCauseLo_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(2344usize),
)
}
}
#[doc = "Interrupt USB Host Register"]
#[inline(always)]
pub const fn intr_usbhost(
&self,
) -> &'static crate::common::Reg<usbhost::IntrUsbhost_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::IntrUsbhost_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2368usize),
)
}
}
#[doc = "Interrupt USB Host Set Register"]
#[inline(always)]
pub const fn intr_usbhost_set(
&self,
) -> &'static crate::common::Reg<usbhost::IntrUsbhostSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::IntrUsbhostSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2372usize),
)
}
}
#[doc = "Interrupt USB Host Mask Register"]
#[inline(always)]
pub const fn intr_usbhost_mask(
&self,
) -> &'static crate::common::Reg<usbhost::IntrUsbhostMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::IntrUsbhostMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2376usize),
)
}
}
#[doc = "Interrupt USB Host Masked Register"]
#[inline(always)]
pub const fn intr_usbhost_masked(
&self,
) -> &'static crate::common::Reg<usbhost::IntrUsbhostMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbhost::IntrUsbhostMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(2380usize),
)
}
}
#[doc = "Interrupt USB Host Endpoint Register"]
#[inline(always)]
pub const fn intr_host_ep(
&self,
) -> &'static crate::common::Reg<usbhost::IntrHostEp_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::IntrHostEp_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2560usize),
)
}
}
#[doc = "Interrupt USB Host Endpoint Set Register"]
#[inline(always)]
pub const fn intr_host_ep_set(
&self,
) -> &'static crate::common::Reg<usbhost::IntrHostEpSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::IntrHostEpSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2564usize),
)
}
}
#[doc = "Interrupt USB Host Endpoint Mask Register"]
#[inline(always)]
pub const fn intr_host_ep_mask(
&self,
) -> &'static crate::common::Reg<usbhost::IntrHostEpMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::IntrHostEpMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2568usize),
)
}
}
#[doc = "Interrupt USB Host Endpoint Masked Register"]
#[inline(always)]
pub const fn intr_host_ep_masked(
&self,
) -> &'static crate::common::Reg<usbhost::IntrHostEpMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<usbhost::IntrHostEpMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(2572usize),
)
}
}
#[doc = "Host DMA Enable Register"]
#[inline(always)]
pub const fn host_dma_enbl(
&self,
) -> &'static crate::common::Reg<usbhost::HostDmaEnbl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostDmaEnbl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2816usize),
)
}
}
#[doc = "Host Endpoint 1 Block Register"]
#[inline(always)]
pub const fn host_ep1_blk(
&self,
) -> &'static crate::common::Reg<usbhost::HostEp1Blk_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostEp1Blk_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2848usize),
)
}
}
#[doc = "Host Endpoint 2 Block Register"]
#[inline(always)]
pub const fn host_ep2_blk(
&self,
) -> &'static crate::common::Reg<usbhost::HostEp2Blk_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<usbhost::HostEp2Blk_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2864usize),
)
}
}
}
pub mod usbhost {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostCtl0_SPEC;
impl crate::sealed::RegSpec for HostCtl0_SPEC {
type DataType = u32;
}
#[doc = "Host Control 0 Register."]
pub type HostCtl0 = crate::RegValueT<HostCtl0_SPEC>;
impl HostCtl0 {
#[doc = "This bit selects an operating mode of this IP.\n\'0\' : USB Device\n\'1\' : USB Host\nNotes:\n- The mode of operation mode does not transition immediately after setting this bit. Read this bit to confirm that the operation mode has changed.\n- This bit is reset to \'0\' if the ENABLE bit in this register changes from \'1\' to \'0\'.\n- Before changing from the USB Host to the USB Device, check that the following conditions are satisfied and also set the RST bit of the Host Control 1 Register (HOST_CTL1). to \'1\'.\n * The SOFBUSY bit of the Host Status Register (HOST_STATUS) is set to \'0\'.\n * The TKNEN bits of the Host Token Endpoint Register (HOST_TOKEN) is set to \'000\'.\n * The SUSP bit of the Host Status Register (HOST_STATUS) is set to \'0\'."]
#[inline(always)]
pub fn host(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, HostCtl0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,HostCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit enables the operation of this IP.\n\'0\' : Disable USB Host\n\'1\' : Enable USB Host\nNote:\n- This bit doesn\'t affect the USB Device."]
#[inline(always)]
pub fn enable(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, HostCtl0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,HostCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for HostCtl0 {
#[inline(always)]
fn default() -> HostCtl0 {
<crate::RegValueT<HostCtl0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostCtl1_SPEC;
impl crate::sealed::RegSpec for HostCtl1_SPEC {
type DataType = u32;
}
#[doc = "Host Control 1 Register."]
pub type HostCtl1 = crate::RegValueT<HostCtl1_SPEC>;
impl HostCtl1 {
#[doc = "This bit selects the operating clock of USB Host.\n\'0\' : Low-speed clock\n\'1\' : Full-speed clock\nNotes:\n- This bit is set to it\'s default vaulue \'1\' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from \'1\' to \'0\'.\n- This bit must always be set to \'1\' in the USB Device mode."]
#[inline(always)]
pub fn clksel(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, HostCtl1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,HostCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit stops the clock for the USB Host operating unit. When this bit is \'1\', power consumption can be reduced by configuring this bit.\n\'0\' : Normal operating mode.\n\'1\' : Stops the clock for the USB Host operating unit.\nNotes:\n- If this bit is set to \'1\', the function of USB Host can\'t be used because internal clock is stopped.\n- This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from \'1\' to \'0\'."]
#[inline(always)]
pub fn ustp(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, HostCtl1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,HostCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit resets the USB Host.\n\'0\' : Normal operating mode.\n\'1\' : USB Host is reset.\nNotes:\n- This bit is to it\'s default value \'1\' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from \'1\' to \'0\'.\n- If this bit is set to \'1\', both the BFINI bits of the Host Endpoint 1 Control Register (HOST_EP1_CTL) and Host Endpoint 2 Control Register (HOST_EP2_CTL) are set to \'1\'."]
#[inline(always)]
pub fn rst(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, HostCtl1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,HostCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for HostCtl1 {
#[inline(always)]
fn default() -> HostCtl1 {
<crate::RegValueT<HostCtl1_SPEC> as RegisterValue<_>>::new(131)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostCtl2_SPEC;
impl crate::sealed::RegSpec for HostCtl2_SPEC {
type DataType = u32;
}
#[doc = "Host Control 2 Register."]
pub type HostCtl2 = crate::RegValueT<HostCtl2_SPEC>;
impl HostCtl2 {
#[doc = "If this bit is set to \'1\', the target token is retried if a NAK or error* occurs. Retry processing is performed after the time that is specified in the Host Retry Timer Setup Register (HOST_RTIMER).\n* : HOST_ERR.RERR=\'1\', HOST_ERR.TOUT=\'1\', HOST_ERR.CRC=\'1\', HOST_ERR.TGERR=\'1\', HOST_ERR.STUFF=\'1\'\n\'0\' : Doesn\'t retry token sending.\n\'1\' : Retries token sending\nNote:\n- This bit isn\'t initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn retry(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, HostCtl2_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,HostCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When this bit is set to \'1\', if the target token is written to the Host Token Endpoint Register (HOST_TOKEN) in the EOF area (specified in the Host EOF Setup Register), its sending is canceled. When this bit is set to \'0\', token sending is not canceled even if the target token is written to the register. The cancellation of token sending is detected by reading the TCAN bit of the Interrupt USB Host Register (INTR_USBHOST).\n\'0\' : Continues a token.\n\'1\' : Cancels a token."]
#[inline(always)]
pub fn cancel(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, HostCtl2_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,HostCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set to \'1\', the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to \'1\' each time SOF is sent.\nIf this bit is set to \'0\', the set value of the Host SOF Interrupt Frame Compare Register (HOST_FCOMP) is compared with the low-order eight bits of the SOF frame number. If they match, the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to \'1\'.\n\'0\' : An interrupt occurred due to the HOST_HFCOMP setting.\n\'1\' : An interrupt occurred.\nNotes:\n- If a SOF token (TKNEN=\'001\') is sent by the setting of the Host Token Endpoint Register (HOST_TOKEN), the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is not set to \'1\' regardless of the setting of this bit."]
#[inline(always)]
pub fn sofstep(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, HostCtl2_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,HostCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to \'1\' while the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is \'0\', SE0 is output instead of SOF. This bit is only effective when the CLKSEL bit is \'0\'. If the CLKSEL bit is \'1\' (Full-Speed mode), SOF is output regardless of the setting of the ALIVE bit. \n\'0\' : SOF output.\n\'1\' : SE0 output (Keep alive)"]
#[inline(always)]
pub fn alive(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, HostCtl2_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,HostCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_4(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, HostCtl2_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,HostCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_5(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, HostCtl2_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,HostCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn ttest(
self,
) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, HostCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<6,0x3,1,0,u8,u8,HostCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for HostCtl2 {
#[inline(always)]
fn default() -> HostCtl2 {
<crate::RegValueT<HostCtl2_SPEC> as RegisterValue<_>>::new(1)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostErr_SPEC;
impl crate::sealed::RegSpec for HostErr_SPEC {
type DataType = u32;
}
#[doc = "Host Error Status Register."]
pub type HostErr = crate::RegValueT<HostErr_SPEC>;
impl HostErr {
#[doc = "These flags indicate the status of a handshake packet to be sent or received.\nThese flags are set to \'NULL\' when no handshake occurs due to an error or when a SOF token has been ended with the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN).\nThese bits are updated when sending or receiving has been ended. \nWrite \'11\' to set the status back to \'NULL\', all other write values are ignored. \nNote:\nThis bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn hs(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
host_err::Hs,
host_err::Hs,
HostErr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
host_err::Hs,
host_err::Hs,
HostErr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "If this bit is set to \'1\', it means that a bit stuffing error has been detected. When this bit is \'0\', it means that no error is detected. If a stuffing error is detected, bit5 (TOUT) of this register is also set to \'1\'. Write \'1\' to clear, a write of \'0\' is ignored.\n\'0\' : No stuffing error.\n\'1\' : Stuffing error detected.\nNote:\n- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn stuff(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, HostErr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,HostErr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set to \'1\', it means that the data does not match the TGGL data. When this bit is \'0\', it means that no error is detected. Write \'1\' to clear, a write of \'0\' is ignored.\n\'0\' : No toggle error.\n\'1\' : Toggle error detected.\nNote:\n- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn tgerr(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, HostErr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,HostErr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set to \'1\', it means that a CRC error is detected in the USB Host. When this bit is \'0\', it means that no error is detected. If a CRC error is detected, bit5 (TOUT) of this register is also set to \'1\'. Write \'1\' to clear, a write of \'0\' is ignored.\n\'0\' : No CRC error.\n\'1\' : CRC error detected.\nNote:\n- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn crc(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, HostErr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,HostErr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set to \'1\', it means that no response is returned from the device within the specified time after a token has been sent in the USB Host. When this bit is \'0\', it means that no timeout is detected. Write \'1\' to clear, a write of \'0\' is ignored.\n\'0\' : No timeout.\n\'1\' : Timeout has detected.\nNote:\n- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn tout(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, HostErr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,HostErr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When this bit is set to \'1\', it means that the received data exceeds the specified maximum number of packets in the USB Host. If a receive error is detected, bit5 (TOUT) of this register is also set to \'1\'. When this bit is \'0\', it means that no error is detected. Write \'1\' to clear, a write of \'0\' is ignored.\n\'0\' : No receive error.\n\'1\' : Maximum packet receive error detected.\n- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn rerr(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, HostErr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,HostErr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set to \'1\', it means that the SOF token can\'t be sent in the USB Host because other token is in process. When this bit is \'0\', it means that SOF token was sent with no error. Write \'1\' to clear, a write of \'0\' is ignored.\n\'0\' : SOF sent without error.\n\'1\' : SOF error detected.\nNote:\n- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn lstsof(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, HostErr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,HostErr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for HostErr {
#[inline(always)]
fn default() -> HostErr {
<crate::RegValueT<HostErr_SPEC> as RegisterValue<_>>::new(3)
}
}
pub mod host_err {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Hs_SPEC;
pub type Hs = crate::EnumBitfieldStruct<u8, Hs_SPEC>;
impl Hs {
#[doc = "Acknowledge Packet"]
pub const ACK: Self = Self::new(0);
#[doc = "Non-Acknowledge Packet"]
pub const NAK: Self = Self::new(1);
#[doc = "Stall Packet"]
pub const STALL: Self = Self::new(2);
#[doc = "Null Packet"]
pub const NULL: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostStatus_SPEC;
impl crate::sealed::RegSpec for HostStatus_SPEC {
type DataType = u32;
}
#[doc = "Host Status Register."]
pub type HostStatus = crate::RegValueT<HostStatus_SPEC>;
impl HostStatus {
#[doc = "When this bit is \'1\', it means that the device is connected. When this bit is \'0\', it means that the device is disconnected.\n\'0\' : Device is disconnected.\n\'1\' : Device is connected.\nNotes:\n- This bit is set to the default value if the RST bit of the Host Control 1 Register (Host_CTL1) is set to \'1\'.\n- The transition to disconnected on RST isn\'t immediate. Read this bit to confirm the transition is complete."]
#[inline(always)]
pub fn cstat(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, HostStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,HostStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "If this bit is \'1\', it means that the device is connected in the full-speed mode. When this bit is \'0\', it means that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status Register (HOST_STATUS) is \'1\'.\n\'0\' : Low-speed.\n\'1\' : Full-speed.\nNotes:\n- This bit is set to the default value if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'. \n- The transition to disconnected on RST isn\'t immediate. Read this bit to confirm the transition is complete."]
#[inline(always)]
pub fn tmode(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, HostStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,HostStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "If this bit is set to \'1\', the USB Host is placed into the suspend state. If this bit is set to \'0\' while it is \'1\' or the USB bus is placed into the k-state mode, then suspend state is released, and the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to \'1\'.\nSet to \'1\' : Suspend.\nSet \'0\' when this bit is \'1\' : Resume.\nOther conditions : Holds the status.\nNotes:\n- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'.\n- The transition to disconnected on RST isn\'t immediate. Read this bit to confirm the transition is complete.\n- If this bit is set to \'1\', this bit must not be set to \'1\' until the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to \'1\'.\n- Do not set this bit to \'1\' while the USB is active (during USB bus resetting, data transfer, or SOF timer running).\n- If the value of this bit is changed, it is not immediately reflected on the state of the USB bus. To check whether or not the state is updated, read this bit."]
#[inline(always)]
pub fn susp(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, HostStatus_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,HostStatus_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN), this bit is set to \'1\', which means that the SOF timer is active. When this bit is \'0\', it means that the SOF timer is under suspension. To stop the active SOF timer, write \'0\' to this bit. However, if this bit is written with \'1\', its value is ignored. \n\'0\' : The SOF timer is stopped.\n\'1\' : The SOF timer is active.\nNotes:\n- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'.\n- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).\n- The SOF timer does not stop immediately after this bit has been set to \'0\' to stop the SOF timer. To check whether or not the SOF timer is stopped, read this bit."]
#[inline(always)]
pub fn sofbusy(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, HostStatus_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,HostStatus_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When this bit is set to \'1\', the USB bus is reset. This bit remains a \'1\' during USB bus resetting, and changes to \'0\' when USB bus resetting is ended. If this bit is set to \'0\', the USB bus reset is complete"]
#[inline(always)]
pub fn urst(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, HostStatus_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,HostStatus_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_5(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, HostStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5,1,0,HostStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit shows that USB Host is being reset internally. If the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\', this bit is set to \'1\'.\nIf the RST bit of Host Control 1 Register (HOST_CTL1) is set to \'0\', this bit is set to \'0\'.\n\'0\' : USB Host isn\'t being reset.\n\'1\' : USB Host is being reset.\nNotes:\n- If this bit is \'1\', the a token must not be executed.\n- This bit isn\'t set to \'0\' or \'1\' immediately even if the RST bit of Host Control 1 Register (HOST_CTL1) is set to \'0\' or \'1\'. Read this bit to confirm the operation is complete."]
#[inline(always)]
pub fn rstbusy(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, HostStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<6,1,0,HostStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\', this bit is set to \'1\'.\n\'0\' : Low speed\n\'1\' : Full speed\nNote:\n- If this bit is different from the CLKSEL bit, The execution of the token and bus reset must wait these bits match.\n- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete."]
#[inline(always)]
pub fn clksel_st(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, HostStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<7,1,0,HostStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit shows whether the device is in USB Host mode. If the HOST bit of the Host Control Register (HOST_CTL0) is set to \'1\', this bit is set to \'1\'.\n\'0\' : USB Device\n\'1\' : USB Host\nNotes:\n- If this bit is different from the HOST bit, The execution of a token must wait these bits match.\n- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete."]
#[inline(always)]
pub fn host_st(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, HostStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8,1,0,HostStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for HostStatus {
#[inline(always)]
fn default() -> HostStatus {
<crate::RegValueT<HostStatus_SPEC> as RegisterValue<_>>::new(194)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostFcomp_SPEC;
impl crate::sealed::RegSpec for HostFcomp_SPEC {
type DataType = u32;
}
#[doc = "Host SOF Interrupt Frame Compare Register"]
pub type HostFcomp = crate::RegValueT<HostFcomp_SPEC>;
impl HostFcomp {
#[doc = "These bits are used to specify the data to be compared with the low-order eight bits of a frame number when sending a SOF token.\nIf the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is \'0\', the frame number of SOF is compared with the value of this register when sending a SOF token. If they match, the SOFIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to \'1\'.\nThe setting of this register is invalid when the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is \'1\'.\nNote:\n- This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn framecomp(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, HostFcomp_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,HostFcomp_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for HostFcomp {
#[inline(always)]
fn default() -> HostFcomp {
<crate::RegValueT<HostFcomp_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostRtimer_SPEC;
impl crate::sealed::RegSpec for HostRtimer_SPEC {
type DataType = u32;
}
#[doc = "Host Retry Timer Setup Register"]
pub type HostRtimer = crate::RegValueT<HostRtimer_SPEC>;
impl HostRtimer {
#[doc = "These bits are used to specify the retry time in this register. The retry timer is activated when token sending starts while the RETRY bit of Host Control 2 Register (HOST_CTL2) is \'1\'. The retry time is then decremented by one when a 1-bit transfer clock (12 MHz in the full-speed mode) is output. When the retry timer reaches 0, the target token is sent, and processing ends.\nIf a token retry occurs in the EOF area, the retry timer is stopped until SOF sending is ended. After SOF sending has been completed, the retry timer restarts with the value that is set when the timer stopped."]
#[inline(always)]
pub fn rtimer(
self,
) -> crate::common::RegisterField<
0,
0x3ffff,
1,
0,
u32,
u32,
HostRtimer_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3ffff,
1,
0,
u32,
u32,
HostRtimer_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for HostRtimer {
#[inline(always)]
fn default() -> HostRtimer {
<crate::RegValueT<HostRtimer_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostAddr_SPEC;
impl crate::sealed::RegSpec for HostAddr_SPEC {
type DataType = u32;
}
#[doc = "Host Address Register"]
pub type HostAddr = crate::RegValueT<HostAddr_SPEC>;
impl HostAddr {
#[doc = "These bits are used to specify a token address.\nNote:\n- This bit is reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn address(
self,
) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, HostAddr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7f,1,0,u8,u8,HostAddr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for HostAddr {
#[inline(always)]
fn default() -> HostAddr {
<crate::RegValueT<HostAddr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostEof_SPEC;
impl crate::sealed::RegSpec for HostEof_SPEC {
type DataType = u32;
}
#[doc = "Host EOF Setup Register"]
pub type HostEof = crate::RegValueT<HostEof_SPEC>;
impl HostEof {
#[doc = "These bits are used to specify the time to disable token sending before transferring SOF. Specify the time with a margin, which is longer than the one-packet length. The time unit is the 1-bit transfer time.\nSetting example: MAXPKT = 64 bytes, full-speed mode\n (Token_length + packet_length + header + CRC)*7/6 + Turn_around_time\n =(34 bit + 546 bit)*7/6 + 36 bit = 712.7 bit\n Therefore, set 0x2C9.\nNote:\n- This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn eof(
self,
) -> crate::common::RegisterField<0, 0x3fff, 1, 0, u16, u16, HostEof_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x3fff,1,0,u16,u16,HostEof_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for HostEof {
#[inline(always)]
fn default() -> HostEof {
<crate::RegValueT<HostEof_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostFrame_SPEC;
impl crate::sealed::RegSpec for HostFrame_SPEC {
type DataType = u32;
}
#[doc = "Host Frame Setup Register"]
pub type HostFrame = crate::RegValueT<HostFrame_SPEC>;
impl HostFrame {
#[doc = "These bits are used to specify a frame number of SOF.\nNotes:\n- This bit isn\'t reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'.\n- Specify a frame number in this register before setting SOF in the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN).\n- This register cannot be written while the SOFBUSY bit of the Host Status Register (HOST_STATUS) is \'1\' and a SOF token is in process."]
#[inline(always)]
pub fn frame(
self,
) -> crate::common::RegisterField<0, 0x7ff, 1, 0, u16, u16, HostFrame_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0x7ff,
1,
0,
u16,
u16,
HostFrame_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for HostFrame {
#[inline(always)]
fn default() -> HostFrame {
<crate::RegValueT<HostFrame_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostToken_SPEC;
impl crate::sealed::RegSpec for HostToken_SPEC {
type DataType = u32;
}
#[doc = "Host Token Endpoint Register"]
pub type HostToken = crate::RegValueT<HostToken_SPEC>;
impl HostToken {
#[doc = "These bits are used to specify an endpoint to send or receive data to or from the device.\nNote:\n- This bit isn\'t reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn endpt(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, HostToken_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,HostToken_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "These bits send a token according to the current settings. After operation is complete, the TKNEN bit is set to \'000\', and the CMPIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to \'1\'.\nThe settings of the TGGL and ENDPT bits are ignored when sending a SOF token.\nNotes:\n- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'.\n- The PRE packet isn\'t supported.\n- Do not set \'100\' to the TKNEN bit when the SOFBUSY bit of the Host Status Register (HOST_STATUS) is \'1\'\n- Mode should be USB Host before writing data to this bit.\n- When issuing a token again after the token interrupt flag (CMPIRQ) has been set to \'1\', wait for 3 cycles or more after a USB transfer clock (12 MHz in the full-speed mode, 1.5 MHz in the low-speed mode) was output, then write data to this bit.\n- Read the value of TKNEN bit if a new value is written in it .Continue writing in this bit until a retrieved value equals a new value written in. During this checking process, it is needed to prevent any interrupt.\n- Take the following steps when CMPIRQ bit of Interrupt USB Host Register (INTR_USBHOST) is set to \'1\' by finishing IN token or Isochronous IN token.\n1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to \'0\'.\n2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to \'1\' if HS bit of Host Error Status Register (HOST_ERR) is equal to \'00\' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to \'1\'. Finish the IN token processing if HS bit is not equal to \'00\'.\n3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to \'1\'."]
#[inline(always)]
pub fn tknen(
self,
) -> crate::common::RegisterField<
4,
0x7,
1,
0,
host_token::Tknen,
host_token::Tknen,
HostToken_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x7,
1,
0,
host_token::Tknen,
host_token::Tknen,
HostToken_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving toggle data, received toggle data is compared with the toggle data of this bit to verify whether or not an error occurs.\n\'0\' : DATA0\n\'1\' : DATA1\nNotes:\n- This bit isn\'t reset to the default value even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'.\n- Set this bit when the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN) is \'000\'."]
#[inline(always)]
pub fn tggl(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, HostToken_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,HostToken_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for HostToken {
#[inline(always)]
fn default() -> HostToken {
<crate::RegValueT<HostToken_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod host_token {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Tknen_SPEC;
pub type Tknen = crate::EnumBitfieldStruct<u8, Tknen_SPEC>;
impl Tknen {
#[doc = "Sends no data."]
pub const NONE: Self = Self::new(0);
#[doc = "Sends SETUP token."]
pub const SETUP: Self = Self::new(1);
#[doc = "Sends IN token."]
pub const IN: Self = Self::new(2);
#[doc = "Sends OUT token."]
pub const OUT: Self = Self::new(3);
#[doc = "Sends SOF token."]
pub const SOF: Self = Self::new(4);
#[doc = "Sends Isochronous IN."]
pub const ISO_IN: Self = Self::new(5);
#[doc = "Sends Isochronous OUT."]
pub const ISO_OUT: Self = Self::new(6);
#[doc = "N/A"]
pub const RSV: Self = Self::new(7);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostEp1Ctl_SPEC;
impl crate::sealed::RegSpec for HostEp1Ctl_SPEC {
type DataType = u32;
}
#[doc = "Host Endpoint 1 Control Register"]
pub type HostEp1Ctl = crate::RegValueT<HostEp1Ctl_SPEC>;
impl HostEp1Ctl {
#[doc = "This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x100.\n- If automatic buffer transfer mode (DMAE=\'1\') is used, Endpoint 0,1, or 2 cannot be used,"]
#[inline(always)]
pub fn pks1(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
HostEp1Ctl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
HostEp1Ctl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer.\n\'0\' : Releases the NULL automatic transfer mode.\n\'1\' : Sets the NULL automatic transfer mode.\nNote :\n- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication."]
#[inline(always)]
pub fn nulle(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, HostEp1Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<10,1,0,HostEp1Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred.\n\'0\' : Releases the packet transfer mode.\n\'1\' : Sets the packet transfer mode.\nNote :\n- The CPU must not access the send/receive buffer while the DMAE bit is set to \'1\'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS1 bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR)."]
#[inline(always)]
pub fn dmae(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, HostEp1Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<11,1,0,HostEp1Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit specifies the transfer direction the Endpoint support.\n\'0\' : IN Endpoint.\n\'1\' : OUT Endpoint\nNote:\n- This bit must be changed when INI_ST bit of the Host Endpoint 1 Status Register (HOST_EP1_STATUS) is \'1\'."]
#[inline(always)]
pub fn dir(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, HostEp1Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<12,1,0,HostEp1Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to \'0\' before clearing the BFINI bit.\n\'0\' : Clears the initialization.\n\'1\' : Initializes the send/receive buffer\nNote :\n- The EP1 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP1DRQ and EP1SPK bits."]
#[inline(always)]
pub fn bfini(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, HostEp1Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<15,1,0,HostEp1Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for HostEp1Ctl {
#[inline(always)]
fn default() -> HostEp1Ctl {
<crate::RegValueT<HostEp1Ctl_SPEC> as RegisterValue<_>>::new(33024)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostEp1Status_SPEC;
impl crate::sealed::RegSpec for HostEp1Status_SPEC {
type DataType = u32;
}
#[doc = "Host Endpoint 1 Status Register"]
pub type HostEp1Status = crate::RegValueT<HostEp1Status_SPEC>;
impl HostEp1Status {
#[doc = "These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP1 has finished.\nThe indication range is from 0x000 to 0x100.\nNote :\n- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect."]
#[inline(always)]
pub fn size1(
self,
) -> crate::common::RegisterField<
0,
0x1ff,
1,
0,
u16,
u16,
HostEp1Status_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0x1ff,
1,
0,
u16,
u16,
HostEp1Status_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "This bit shows that there is valid data in the EP1 buffer.\n\'0\' : Invalid data in the buffer\n\'1\' : Valid data in the buffer"]
#[inline(always)]
pub fn val_data(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, HostEp1Status_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<16,1,0,HostEp1Status_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit shows that EP1 is initialized. If the init bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to \'1\' and EP1 is initialized, this bit is to \'1\'.\n\'0\' : Not initiatialized\n\'1\' : Initialized\nNote:\n- This bit isn\'t set to \'0\' or \'1\' immediately even if BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to \'0\' or \'1\'. Read this bit to confirm the transition."]
#[inline(always)]
pub fn ini_st(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, HostEp1Status_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<17,1,0,HostEp1Status_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_18(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, HostEp1Status_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<18,1,0,HostEp1Status_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for HostEp1Status {
#[inline(always)]
fn default() -> HostEp1Status {
<crate::RegValueT<HostEp1Status_SPEC> as RegisterValue<_>>::new(393216)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostEp1Rw1Dr_SPEC;
impl crate::sealed::RegSpec for HostEp1Rw1Dr_SPEC {
type DataType = u32;
}
#[doc = "Host Endpoint 1 Data 1-Byte Register"]
pub type HostEp1Rw1Dr = crate::RegValueT<HostEp1Rw1Dr_SPEC>;
impl HostEp1Rw1Dr {
#[doc = "Data Register for EP1 for 1-byte data"]
#[inline(always)]
pub fn bfdt8(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, HostEp1Rw1Dr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xff,
1,
0,
u8,
u8,
HostEp1Rw1Dr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for HostEp1Rw1Dr {
#[inline(always)]
fn default() -> HostEp1Rw1Dr {
<crate::RegValueT<HostEp1Rw1Dr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostEp1Rw2Dr_SPEC;
impl crate::sealed::RegSpec for HostEp1Rw2Dr_SPEC {
type DataType = u32;
}
#[doc = "Host Endpoint 1 Data 2-Byte Register"]
pub type HostEp1Rw2Dr = crate::RegValueT<HostEp1Rw2Dr_SPEC>;
impl HostEp1Rw2Dr {
#[doc = "Data Register for EP1 for 2-byte data"]
#[inline(always)]
pub fn bfdt16(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
HostEp1Rw2Dr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
HostEp1Rw2Dr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for HostEp1Rw2Dr {
#[inline(always)]
fn default() -> HostEp1Rw2Dr {
<crate::RegValueT<HostEp1Rw2Dr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostEp2Ctl_SPEC;
impl crate::sealed::RegSpec for HostEp2Ctl_SPEC {
type DataType = u32;
}
#[doc = "Host Endpoint 2 Control Register"]
pub type HostEp2Ctl = crate::RegValueT<HostEp2Ctl_SPEC>;
impl HostEp2Ctl {
#[doc = "This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x40.\n- If automatic buffer transfer mode (DMAE=\'1\') is used, this Endpoint must not set from 0 to 2."]
#[inline(always)]
pub fn pks2(
self,
) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, HostEp2Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7f,1,0,u8,u8,HostEp2Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When a data transfer request in the OUT direction transmitted while packet transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer.\n\'0\' : Releases the NULL automatic transfer mode.\n\'1\' : Sets the NULL automatic transfer mode.\nNote :\n- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication."]
#[inline(always)]
pub fn nulle(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, HostEp2Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<10,1,0,HostEp2Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred.\n\'0\' : Releases the automatic buffer transfer mode.\n\'1\' : Sets the automatic buffer transfer mode.\nNote :\n- The CPU must not access the send/receive buffer while the DMAE bit is set to \'1\'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR)."]
#[inline(always)]
pub fn dmae(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, HostEp2Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<11,1,0,HostEp2Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit specifies the transfer direction the Endpoint support.\n\'0\' : IN Endpoint.\n\'1\' : OUT Endpoint\nNote:\n- This bit must be changed when INI_ST bit of the Host Endpoint 2 Status Register (HOST_EP2_STATUS) is \'1\'."]
#[inline(always)]
pub fn dir(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, HostEp2Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<12,1,0,HostEp2Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to \'0\' before clearing the BFINI bit.\n\'0\' : Clears the initialization.\n\'1\' : Initializes the send/receive buffer\nNote :\n- The EP2 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP2DRQ and EP2SPK bits."]
#[inline(always)]
pub fn bfini(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, HostEp2Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<15,1,0,HostEp2Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for HostEp2Ctl {
#[inline(always)]
fn default() -> HostEp2Ctl {
<crate::RegValueT<HostEp2Ctl_SPEC> as RegisterValue<_>>::new(32832)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostEp2Status_SPEC;
impl crate::sealed::RegSpec for HostEp2Status_SPEC {
type DataType = u32;
}
#[doc = "Host Endpoint 2 Status Register"]
pub type HostEp2Status = crate::RegValueT<HostEp2Status_SPEC>;
impl HostEp2Status {
#[doc = "These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP2 has finished.\nThe indication range is from 0x000 to 0x40.\nNote :\n- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect."]
#[inline(always)]
pub fn size2(
self,
) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, HostEp2Status_SPEC, crate::common::R>
{
crate::common::RegisterField::<
0,
0x7f,
1,
0,
u8,
u8,
HostEp2Status_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "This bit shows that there is valid data in the EP2 buffer.\n\'0\' : Invalid data in the buffer\n\'1\' : Valid data in the buffer"]
#[inline(always)]
pub fn val_data(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, HostEp2Status_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<16,1,0,HostEp2Status_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit shows that EP2 is initialized. If the BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to \'1\' and EP2 is initialized, this bit is to \'1\'.\n\'0\' : Not Initialized\n\'1\' : Initialized\nNote:\n- This bit isn\'t set to \'0\' or \'1\' immediately evne if BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to \'0\' or \'1\'."]
#[inline(always)]
pub fn ini_st(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, HostEp2Status_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<17,1,0,HostEp2Status_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_18(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, HostEp2Status_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<18,1,0,HostEp2Status_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for HostEp2Status {
#[inline(always)]
fn default() -> HostEp2Status {
<crate::RegValueT<HostEp2Status_SPEC> as RegisterValue<_>>::new(393216)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostEp2Rw1Dr_SPEC;
impl crate::sealed::RegSpec for HostEp2Rw1Dr_SPEC {
type DataType = u32;
}
#[doc = "Host Endpoint 2 Data 1-Byte Register"]
pub type HostEp2Rw1Dr = crate::RegValueT<HostEp2Rw1Dr_SPEC>;
impl HostEp2Rw1Dr {
#[doc = "Data Register for EP2 for 1-byte data."]
#[inline(always)]
pub fn bfdt8(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, HostEp2Rw1Dr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xff,
1,
0,
u8,
u8,
HostEp2Rw1Dr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for HostEp2Rw1Dr {
#[inline(always)]
fn default() -> HostEp2Rw1Dr {
<crate::RegValueT<HostEp2Rw1Dr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostEp2Rw2Dr_SPEC;
impl crate::sealed::RegSpec for HostEp2Rw2Dr_SPEC {
type DataType = u32;
}
#[doc = "Host Endpoint 2 Data 2-Byte Register"]
pub type HostEp2Rw2Dr = crate::RegValueT<HostEp2Rw2Dr_SPEC>;
impl HostEp2Rw2Dr {
#[doc = "Data Register for EP2 for 2 byte data."]
#[inline(always)]
pub fn bfdt16(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
HostEp2Rw2Dr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
HostEp2Rw2Dr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for HostEp2Rw2Dr {
#[inline(always)]
fn default() -> HostEp2Rw2Dr {
<crate::RegValueT<HostEp2Rw2Dr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostLvl1Sel_SPEC;
impl crate::sealed::RegSpec for HostLvl1Sel_SPEC {
type DataType = u32;
}
#[doc = "Host Interrupt Level 1 Selection Register"]
pub type HostLvl1Sel = crate::RegValueT<HostLvl1Sel_SPEC>;
impl HostLvl1Sel {
#[doc = "These bits assign SOFIRQ interrupt flag to selected interrupt signals."]
#[inline(always)]
pub fn sofirq_sel(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
host_lvl1_sel::SofirqSel,
host_lvl1_sel::SofirqSel,
HostLvl1Sel_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
host_lvl1_sel::SofirqSel,
host_lvl1_sel::SofirqSel,
HostLvl1Sel_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "These bits assign DIRQ interrupt flag to selected interrupt signals."]
#[inline(always)]
pub fn dirq_sel(
self,
) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, HostLvl1Sel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<2,0x3,1,0,u8,u8,HostLvl1Sel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "These bits assign CNNIRQ interrupt flag to selected interrupt signals."]
#[inline(always)]
pub fn cnnirq_sel(
self,
) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, HostLvl1Sel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0x3,1,0,u8,u8,HostLvl1Sel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "These bits assign URIRQ interrupt flag to selected interrupt signals."]
#[inline(always)]
pub fn cmpirq_sel(
self,
) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, HostLvl1Sel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<6,0x3,1,0,u8,u8,HostLvl1Sel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "These bits assign URIRQ interrupt flag to selected interrupt signals."]
#[inline(always)]
pub fn urirq_sel(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, HostLvl1Sel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,HostLvl1Sel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "These bits assign RWKIRQ interrupt flag to selected interrupt signals."]
#[inline(always)]
pub fn rwkirq_sel(
self,
) -> crate::common::RegisterField<10, 0x3, 1, 0, u8, u8, HostLvl1Sel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<10,0x3,1,0,u8,u8,HostLvl1Sel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_13_12(
self,
) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, HostLvl1Sel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<12,0x3,1,0,u8,u8,HostLvl1Sel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "These bits assign TCAN interrupt flag to selected interrupt signals."]
#[inline(always)]
pub fn tcan_sel(
self,
) -> crate::common::RegisterField<14, 0x3, 1, 0, u8, u8, HostLvl1Sel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<14,0x3,1,0,u8,u8,HostLvl1Sel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for HostLvl1Sel {
#[inline(always)]
fn default() -> HostLvl1Sel {
<crate::RegValueT<HostLvl1Sel_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod host_lvl1_sel {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct SofirqSel_SPEC;
pub type SofirqSel = crate::EnumBitfieldStruct<u8, SofirqSel_SPEC>;
impl SofirqSel {
#[doc = "High priority interrupt"]
pub const HI: Self = Self::new(0);
#[doc = "Medium priority interrupt"]
pub const MED: Self = Self::new(1);
#[doc = "Low priority interrupt"]
pub const LO: Self = Self::new(2);
#[doc = "N/A"]
pub const RSVD: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostLvl2Sel_SPEC;
impl crate::sealed::RegSpec for HostLvl2Sel_SPEC {
type DataType = u32;
}
#[doc = "Host Interrupt Level 2 Selection Register"]
pub type HostLvl2Sel = crate::RegValueT<HostLvl2Sel_SPEC>;
impl HostLvl2Sel {
#[doc = "These bits assign EP1_DRQ interrupt flag to selected interrupt signals."]
#[inline(always)]
pub fn ep1_drq_sel(
self,
) -> crate::common::RegisterField<
4,
0x3,
1,
0,
host_lvl2_sel::Ep1DrqSel,
host_lvl2_sel::Ep1DrqSel,
HostLvl2Sel_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x3,
1,
0,
host_lvl2_sel::Ep1DrqSel,
host_lvl2_sel::Ep1DrqSel,
HostLvl2Sel_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "These bits assign EP1_SPK interrupt flag to selected interrupt signals."]
#[inline(always)]
pub fn ep1_spk_sel(
self,
) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, HostLvl2Sel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<6,0x3,1,0,u8,u8,HostLvl2Sel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "These bits assign EP2_DRQ interrupt flag to selected interrupt signals."]
#[inline(always)]
pub fn ep2_drq_sel(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, HostLvl2Sel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,HostLvl2Sel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "These bits assign EP2_SPK interrupt flag to selected interrupt signals."]
#[inline(always)]
pub fn ep2_spk_sel(
self,
) -> crate::common::RegisterField<10, 0x3, 1, 0, u8, u8, HostLvl2Sel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<10,0x3,1,0,u8,u8,HostLvl2Sel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for HostLvl2Sel {
#[inline(always)]
fn default() -> HostLvl2Sel {
<crate::RegValueT<HostLvl2Sel_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod host_lvl2_sel {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Ep1DrqSel_SPEC;
pub type Ep1DrqSel = crate::EnumBitfieldStruct<u8, Ep1DrqSel_SPEC>;
impl Ep1DrqSel {
#[doc = "High priority interrupt"]
pub const HI: Self = Self::new(0);
#[doc = "Medium priority interrupt"]
pub const MED: Self = Self::new(1);
#[doc = "Low priority interrupt"]
pub const LO: Self = Self::new(2);
#[doc = "N/A"]
pub const RSVD: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrUsbhostCauseHi_SPEC;
impl crate::sealed::RegSpec for IntrUsbhostCauseHi_SPEC {
type DataType = u32;
}
#[doc = "Interrupt USB Host Cause High Register"]
pub type IntrUsbhostCauseHi = crate::RegValueT<IntrUsbhostCauseHi_SPEC>;
impl IntrUsbhostCauseHi {
#[doc = "SOFIRQ interrupt"]
#[inline(always)]
pub fn sofirq_int(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrUsbhostCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<0,1,0,IntrUsbhostCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "DIRQ interrupt"]
#[inline(always)]
pub fn dirq_int(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrUsbhostCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<1,1,0,IntrUsbhostCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "CNNIRQ interrupt"]
#[inline(always)]
pub fn cnnirq_int(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrUsbhostCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<2,1,0,IntrUsbhostCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "CMPIRQ interrupt"]
#[inline(always)]
pub fn cmpirq_int(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrUsbhostCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<3,1,0,IntrUsbhostCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "URIRQ interrupt"]
#[inline(always)]
pub fn urirq_int(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrUsbhostCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<4,1,0,IntrUsbhostCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "RWKIRQ interrupt"]
#[inline(always)]
pub fn rwkirq_int(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrUsbhostCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<5,1,0,IntrUsbhostCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrUsbhostCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<6,1,0,IntrUsbhostCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "TCAN interrupt"]
#[inline(always)]
pub fn tcan_int(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrUsbhostCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<7,1,0,IntrUsbhostCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrUsbhostCauseHi {
#[inline(always)]
fn default() -> IntrUsbhostCauseHi {
<crate::RegValueT<IntrUsbhostCauseHi_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrUsbhostCauseMed_SPEC;
impl crate::sealed::RegSpec for IntrUsbhostCauseMed_SPEC {
type DataType = u32;
}
#[doc = "Interrupt USB Host Cause Medium Register"]
pub type IntrUsbhostCauseMed = crate::RegValueT<IntrUsbhostCauseMed_SPEC>;
impl IntrUsbhostCauseMed {
#[doc = "SOFIRQ interrupt"]
#[inline(always)]
pub fn sofirq_int(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrUsbhostCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<0,1,0,IntrUsbhostCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "DIRQ interrupt"]
#[inline(always)]
pub fn dirq_int(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrUsbhostCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<1,1,0,IntrUsbhostCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "CNNIRQ interrupt"]
#[inline(always)]
pub fn cnnirq_int(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrUsbhostCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<2,1,0,IntrUsbhostCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "CMPIRQ interrupt"]
#[inline(always)]
pub fn cmpirq_int(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrUsbhostCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<3,1,0,IntrUsbhostCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "URIRQ interrupt"]
#[inline(always)]
pub fn urirq_int(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrUsbhostCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<4,1,0,IntrUsbhostCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "RWKIRQ interrupt"]
#[inline(always)]
pub fn rwkirq_int(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrUsbhostCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<5,1,0,IntrUsbhostCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrUsbhostCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<6,1,0,IntrUsbhostCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "TCAN interrupt"]
#[inline(always)]
pub fn tcan_int(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrUsbhostCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<7,1,0,IntrUsbhostCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrUsbhostCauseMed {
#[inline(always)]
fn default() -> IntrUsbhostCauseMed {
<crate::RegValueT<IntrUsbhostCauseMed_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrUsbhostCauseLo_SPEC;
impl crate::sealed::RegSpec for IntrUsbhostCauseLo_SPEC {
type DataType = u32;
}
#[doc = "Interrupt USB Host Cause Low Register"]
pub type IntrUsbhostCauseLo = crate::RegValueT<IntrUsbhostCauseLo_SPEC>;
impl IntrUsbhostCauseLo {
#[doc = "SOFIRQ interrupt"]
#[inline(always)]
pub fn sofirq_int(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrUsbhostCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<0,1,0,IntrUsbhostCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "DIRQ interrupt"]
#[inline(always)]
pub fn dirq_int(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrUsbhostCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<1,1,0,IntrUsbhostCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "CNNIRQ interrupt"]
#[inline(always)]
pub fn cnnirq_int(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrUsbhostCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<2,1,0,IntrUsbhostCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "CMPIRQ interrupt"]
#[inline(always)]
pub fn cmpirq_int(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrUsbhostCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<3,1,0,IntrUsbhostCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "URIRQ interrupt"]
#[inline(always)]
pub fn urirq_int(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrUsbhostCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<4,1,0,IntrUsbhostCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "RWKIRQ interrupt"]
#[inline(always)]
pub fn rwkirq_int(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrUsbhostCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<5,1,0,IntrUsbhostCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrUsbhostCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<6,1,0,IntrUsbhostCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "TCAN interrupt"]
#[inline(always)]
pub fn tcan_int(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrUsbhostCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<7,1,0,IntrUsbhostCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrUsbhostCauseLo {
#[inline(always)]
fn default() -> IntrUsbhostCauseLo {
<crate::RegValueT<IntrUsbhostCauseLo_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrHostEpCauseHi_SPEC;
impl crate::sealed::RegSpec for IntrHostEpCauseHi_SPEC {
type DataType = u32;
}
#[doc = "Interrupt USB Host Endpoint Cause High Register"]
pub type IntrHostEpCauseHi = crate::RegValueT<IntrHostEpCauseHi_SPEC>;
impl IntrHostEpCauseHi {
#[doc = "EP1DRQ interrupt"]
#[inline(always)]
pub fn ep1drq_int(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrHostEpCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<2,1,0,IntrHostEpCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP1SPK interrupt"]
#[inline(always)]
pub fn ep1spk_int(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrHostEpCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<3,1,0,IntrHostEpCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP2DRQ interrupt"]
#[inline(always)]
pub fn ep2drq_int(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrHostEpCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<4,1,0,IntrHostEpCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP2SPK interrupt"]
#[inline(always)]
pub fn ep2spk_int(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrHostEpCauseHi_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<5,1,0,IntrHostEpCauseHi_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrHostEpCauseHi {
#[inline(always)]
fn default() -> IntrHostEpCauseHi {
<crate::RegValueT<IntrHostEpCauseHi_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrHostEpCauseMed_SPEC;
impl crate::sealed::RegSpec for IntrHostEpCauseMed_SPEC {
type DataType = u32;
}
#[doc = "Interrupt USB Host Endpoint Cause Medium Register"]
pub type IntrHostEpCauseMed = crate::RegValueT<IntrHostEpCauseMed_SPEC>;
impl IntrHostEpCauseMed {
#[doc = "EP1DRQ interrupt"]
#[inline(always)]
pub fn ep1drq_int(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrHostEpCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<2,1,0,IntrHostEpCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP1SPK interrupt"]
#[inline(always)]
pub fn ep1spk_int(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrHostEpCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<3,1,0,IntrHostEpCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP2DRQ interrupt"]
#[inline(always)]
pub fn ep2drq_int(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrHostEpCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<4,1,0,IntrHostEpCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP2SPK interrupt"]
#[inline(always)]
pub fn ep2spk_int(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrHostEpCauseMed_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<5,1,0,IntrHostEpCauseMed_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrHostEpCauseMed {
#[inline(always)]
fn default() -> IntrHostEpCauseMed {
<crate::RegValueT<IntrHostEpCauseMed_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrHostEpCauseLo_SPEC;
impl crate::sealed::RegSpec for IntrHostEpCauseLo_SPEC {
type DataType = u32;
}
#[doc = "Interrupt USB Host Endpoint Cause Low Register"]
pub type IntrHostEpCauseLo = crate::RegValueT<IntrHostEpCauseLo_SPEC>;
impl IntrHostEpCauseLo {
#[doc = "EP1DRQ interrupt"]
#[inline(always)]
pub fn ep1drq_int(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrHostEpCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<2,1,0,IntrHostEpCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP1SPK interrupt"]
#[inline(always)]
pub fn ep1spk_int(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrHostEpCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<3,1,0,IntrHostEpCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP2DRQ interrupt"]
#[inline(always)]
pub fn ep2drq_int(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrHostEpCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<4,1,0,IntrHostEpCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "EP2SPK interrupt"]
#[inline(always)]
pub fn ep2spk_int(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrHostEpCauseLo_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<5,1,0,IntrHostEpCauseLo_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrHostEpCauseLo {
#[inline(always)]
fn default() -> IntrHostEpCauseLo {
<crate::RegValueT<IntrHostEpCauseLo_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrUsbhost_SPEC;
impl crate::sealed::RegSpec for IntrUsbhost_SPEC {
type DataType = u32;
}
#[doc = "Interrupt USB Host Register"]
pub type IntrUsbhost = crate::RegValueT<IntrUsbhost_SPEC>;
impl IntrUsbhost {
#[doc = "If this bit is set to \'1\', it means that SOF token sending is started. When this bit is \'0\', it has no meaning. Write \'1\' to clear, a write of \'0\' is ignored.\n\'0\' : Does not issue an interrupt request by starting a SOF token.\n\'1\' : Issues an interrupt request by starting a SOF token.\nNote :\n- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn sofirq(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrUsbhost_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,IntrUsbhost_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set to \'1\', it means that a device disconnection is detected. When this bit is \'0\', it has no meaning. Write \'1\' to clear, a write of \'0\' is ignored.\n\'0\' : Issues no interrupt request by detecting a device disconnection.\n\'1\' : Issues an interrupt request by detecting a device disconnection.\nNote :\n- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn dirq(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrUsbhost_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,IntrUsbhost_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set to \'1\', it means that a device connection is detected. When this bit is \'0\', it has no meaning. Write \'1\' to clear, a write of \'0\' is ignored.\n\'0\' : Issues no interrupt request by detecting a device connection.\n\'1\' : Issues an interrupt request by detecting a device connection.\nNote :\n- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn cnnirq(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrUsbhost_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,IntrUsbhost_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set to \'1\', it means that a token is completed. When this bit is \'0\', it has no meaning. Write \'1\' to clear, a write of \'0\' is ignored.\n\'0\' : Issues no interrupt request by token completion.\n\'1\' : Issues an interrupt request by token completion.\nNote :\n- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'.\n- This bit is not set to \'1\' even if the TCAN bit of the Interrupt USBHost Register (INTR_USBHOST) changes to \'1\'.\n- Take the following steps when this bit is set to \'1\' by finishing IN token or Isochronous IN token.\n1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to \'0\'.\n2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to \'1\' if HS bit of Host Error Status Register (HOST_ERR) is equal to \'00\' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to \'1\'. Finish the IN token processing if HS bit is not equal to \'00\'.\n3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to \'1\'."]
#[inline(always)]
pub fn cmpirq(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrUsbhost_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,IntrUsbhost_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set to \'1\', it means that USB bus resetting is ended. When this bit is \'0\', it has no meaning. If this bit is written with \'1\', it is set to \'0\'. However, if this bit is written with \'0\', its value is ignored.\n\'0\' : Issues no interrupt request by USB bus resetting.\n\'1\' : Issues an interrupt request by USB bus resetting.\nNote :\n- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn urirq(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrUsbhost_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,IntrUsbhost_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set to \'1\', it means that remote Wake-up is ended. When this bit is \'0\', it has no meaning. Write \'1\' to clear, a write of \'0\' is ignored.\n\'0\' : Issues no interrupt request by restart.\n\'1\' : Issues an interrupt request by restart.\nNote :\n- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn rwkirq(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrUsbhost_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,IntrUsbhost_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrUsbhost_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,IntrUsbhost_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set to \'1\', it means that token sending is canceled based on the setting of the CANCEL bit of Host Control 2 Register (HOST_CTL2). When this bit is \'0\', it means that token sending is not canceled. Write \'1\' to clear, a write of \'0\' is ignored.\n\'0\' : Does not cancel token sending.\n\'1\' : Cancels token sending.\nNote :\n- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to \'1\'."]
#[inline(always)]
pub fn tcan(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrUsbhost_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<7,1,0,IntrUsbhost_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrUsbhost {
#[inline(always)]
fn default() -> IntrUsbhost {
<crate::RegValueT<IntrUsbhost_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrUsbhostSet_SPEC;
impl crate::sealed::RegSpec for IntrUsbhostSet_SPEC {
type DataType = u32;
}
#[doc = "Interrupt USB Host Set Register"]
pub type IntrUsbhostSet = crate::RegValueT<IntrUsbhostSet_SPEC>;
impl IntrUsbhostSet {
#[doc = "This bit sets SOFIRQ bit. If this bit is written to \'1\', SOFIRQ is set to \'1\'. However, if this bit is written with \'0\', its value is ignored."]
#[inline(always)]
pub fn sofirqs(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrUsbhostSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,IntrUsbhostSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit sets DIRQ bit. If this bit is written to \'1\', DIRQ is set to \'1\'. However, if this bit is written with \'0\', its value is ignored."]
#[inline(always)]
pub fn dirqs(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrUsbhostSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,IntrUsbhostSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit sets CNNIRQ bit. If this bit is written to \'1\', CNNIRQ is set to \'1\'. However, if this bit is written with \'0\', its value is ignored."]
#[inline(always)]
pub fn cnnirqs(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrUsbhostSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,IntrUsbhostSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit sets CMPIRQ bit. If this bit is written to \'1\', CMPIRQ is set to \'1\'. However, if this bit is written with \'0\', its value is ignored."]
#[inline(always)]
pub fn cmpirqs(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrUsbhostSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,IntrUsbhostSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit sets URIRQ bit. If this bit is written to \'1\', URIRQ is set to \'1\'. However, if this bit is written with \'0\', its value is ignored."]
#[inline(always)]
pub fn urirqs(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrUsbhostSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,IntrUsbhostSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit sets RWKIRQ bit. If this bit is written to \'1\', RWKIRQ is set to \'1\'. However, if this bit is written with \'0\', its value is ignored."]
#[inline(always)]
pub fn rwkirqs(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrUsbhostSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,IntrUsbhostSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrUsbhostSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,IntrUsbhostSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit sets TCAN bit. If this bit is written to \'1\', TCAN is set to \'1\'. However, if this bit is written with \'0\', its value is ignored."]
#[inline(always)]
pub fn tcans(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrUsbhostSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<7,1,0,IntrUsbhostSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrUsbhostSet {
#[inline(always)]
fn default() -> IntrUsbhostSet {
<crate::RegValueT<IntrUsbhostSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrUsbhostMask_SPEC;
impl crate::sealed::RegSpec for IntrUsbhostMask_SPEC {
type DataType = u32;
}
#[doc = "Interrupt USB Host Mask Register"]
pub type IntrUsbhostMask = crate::RegValueT<IntrUsbhostMask_SPEC>;
impl IntrUsbhostMask {
#[doc = "This bit masks the interrupt by SOF flag.\n\'0\' : Disables\n\'1\' : Enables"]
#[inline(always)]
pub fn sofirqm(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrUsbhostMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,IntrUsbhostMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit masks the interrupt by DIRQ flag.\n\'0\' : Disables\n\'1\' : Enables"]
#[inline(always)]
pub fn dirqm(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrUsbhostMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,IntrUsbhostMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit masks the interrupt by CNNIRQ flag.\n\'0\' : Disables\n\'1\' : Enables"]
#[inline(always)]
pub fn cnnirqm(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrUsbhostMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,IntrUsbhostMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit masks the interrupt by CMPIRQ flag.\n\'0\' : Disables\n\'1\' : Enables"]
#[inline(always)]
pub fn cmpirqm(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrUsbhostMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,IntrUsbhostMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit masks the interrupt by URIRQ flag.\n\'0\' : Disables\n\'1\' : Enables"]
#[inline(always)]
pub fn urirqm(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrUsbhostMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,IntrUsbhostMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit masks the interrupt by RWKIRQ flag.\n\'0\' : Disables\n\'1\' : Enables"]
#[inline(always)]
pub fn rwkirqm(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrUsbhostMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,IntrUsbhostMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrUsbhostMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,IntrUsbhostMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit masks the interrupt by TCAN flag.\n\'0\' : Disables\n\'1\' : Enables"]
#[inline(always)]
pub fn tcanm(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrUsbhostMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<7,1,0,IntrUsbhostMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrUsbhostMask {
#[inline(always)]
fn default() -> IntrUsbhostMask {
<crate::RegValueT<IntrUsbhostMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrUsbhostMasked_SPEC;
impl crate::sealed::RegSpec for IntrUsbhostMasked_SPEC {
type DataType = u32;
}
#[doc = "Interrupt USB Host Masked Register"]
pub type IntrUsbhostMasked = crate::RegValueT<IntrUsbhostMasked_SPEC>;
impl IntrUsbhostMasked {
#[doc = "This bit indicates the interrupt by SOF flag.\n\'0\' : Doesn\'t request the interrupt by SOF\n\'1\' : Request the interrupt by SOF"]
#[inline(always)]
pub fn sofirqed(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrUsbhostMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<0,1,0,IntrUsbhostMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit indicates the interrupt by DIRQ flag.\n\'0\' : Doesn\'t request the interrupt by DIRQ\n\'1\' : Request the interrupt by DIRQ"]
#[inline(always)]
pub fn dirqed(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrUsbhostMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<1,1,0,IntrUsbhostMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit indicates the interrupt by CNNIRQ flag.\n\'0\' : Doesn\'t request the interrupt by CNNIRQ\n\'1\' : Request the interrupt by CNNIRQ"]
#[inline(always)]
pub fn cnnirqed(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrUsbhostMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<2,1,0,IntrUsbhostMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit indicates the interrupt by CMPIRQ flag.\n\'0\' : Doesn\'t request the interrupt by CMPIRQ\n\'1\' : Request the interrupt by CMPIRQ"]
#[inline(always)]
pub fn cmpirqed(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrUsbhostMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<3,1,0,IntrUsbhostMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit indicates the interrupt by URIRQ flag.\n\'0\' : Doesn\'t request the interrupt by URIRQ\n\'1\' : Request the interrupt by URIRQ"]
#[inline(always)]
pub fn urirqed(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrUsbhostMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<4,1,0,IntrUsbhostMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit indicates the interrupt by RWKIRQ flag.\n\'0\' : Doesn\'t request the interrupt by RWKIRQ\n\'1\' : Request the interrupt by RWKIRQ"]
#[inline(always)]
pub fn rwkirqed(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrUsbhostMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<5,1,0,IntrUsbhostMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd_6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrUsbhostMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<6,1,0,IntrUsbhostMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit indicates the interrupt by TCAN flag.\n\'0\' : Doesn\'t request the interrupt by TCAN\n\'1\' : Request the interrupt by TCAN"]
#[inline(always)]
pub fn tcaned(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrUsbhostMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<7,1,0,IntrUsbhostMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrUsbhostMasked {
#[inline(always)]
fn default() -> IntrUsbhostMasked {
<crate::RegValueT<IntrUsbhostMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrHostEp_SPEC;
impl crate::sealed::RegSpec for IntrHostEp_SPEC {
type DataType = u32;
}
#[doc = "Interrupt USB Host Endpoint Register"]
pub type IntrHostEp = crate::RegValueT<IntrHostEp_SPEC>;
impl IntrHostEp {
#[doc = "This bit indicates that the EP1 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing \'0\' is ignored. Clear the DRQ bit by writing \'1\'.\n\'0\' : Clears the interrupt cause\n\'1\' : Packet transfer normally ended\nNote :\n- If automatic buffer transfer mode (DMAE = \'1\') is not used, \'1\' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = \'0\' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is \'1\', it implies that 0-byte data is set. If DIR of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to \'1\' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, \'1\' must not be written."]
#[inline(always)]
pub fn ep1drq(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrHostEp_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,IntrHostEp_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 1 Control Register (HOST_EP1_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing \'0\' is ignored. Clear it by writing \'1\'.\n\'0\' : Received data size satisfies the maximum packet size\n\'1\' : Received data size does not satisfy the maximum packet size\nNote :\n- The EP1SPK bit is not set during data transfer in the OUT direction."]
#[inline(always)]
pub fn ep1spk(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrHostEp_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,IntrHostEp_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit indicates that the EP2 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing \'0\' is ignored. Clear the DRQ bit by writing \'1\'.\n\'0\' : Clears the interrupt cause\n\'1\' : Packet transfer normally ended\nNote :\n- If packet transfer mode (DMAE = \'1\') is not used, \'1\' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = \'0\' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is \'1\', it implies that 0-byte data is set. If DIR of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to \'1\' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, \'1\' must not be written."]
#[inline(always)]
pub fn ep2drq(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrHostEp_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,IntrHostEp_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS1 in the Host Endpoint 2 Control Register (HOST_EP2_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing \'0\' is ignored. Clear it by writing \'1\'.\n\'0\' : Received data size satisfies the maximum packet size\n\'1\' : Received data size does not satisfy the maximum packet size\nNote :\n- The SPK bit is not set during data transfer in the OUT direction."]
#[inline(always)]
pub fn ep2spk(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrHostEp_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,IntrHostEp_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrHostEp {
#[inline(always)]
fn default() -> IntrHostEp {
<crate::RegValueT<IntrHostEp_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrHostEpSet_SPEC;
impl crate::sealed::RegSpec for IntrHostEpSet_SPEC {
type DataType = u32;
}
#[doc = "Interrupt USB Host Endpoint Set Register"]
pub type IntrHostEpSet = crate::RegValueT<IntrHostEpSet_SPEC>;
impl IntrHostEpSet {
#[doc = "This bit sets EP1DRQ bit. If this bit is written to \'1\', EP1DRQ is set to \'1\'. However, if this bit is written with \'0\', its value is ignored.\nNote:\nIf BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is \'1\', EP1DRQ can\'t be set to \'1\'."]
#[inline(always)]
pub fn ep1drqs(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrHostEpSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,IntrHostEpSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit sets EP1SPK bit. If this bit is written to \'1\', EP1SPK is set to \'1\'. However, if this bit is written with \'0\', its value is ignored.\nNote:\nIf BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is \'1\', EP1SPK can\'t be set to \'1\'."]
#[inline(always)]
pub fn ep1spks(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrHostEpSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,IntrHostEpSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit sets EP2DRQ bit. If this bit is written to \'1\', EP2DRQ is set to \'1\'. However, if this bit is written with \'0\', its value is ignored.\nNote:\nIf BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is \'1\', EP2DRQ can\'t be set to \'1\'."]
#[inline(always)]
pub fn ep2drqs(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrHostEpSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,IntrHostEpSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit sets EP2SPK bit. If this bit is written to \'1\', EP2SPK is set to \'1\'. However, if this bit is written with \'0\', its value is ignored.\nNote:\nIf BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is \'1\', EP2SPK can\'t be set to \'1\'."]
#[inline(always)]
pub fn ep2spks(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrHostEpSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,IntrHostEpSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrHostEpSet {
#[inline(always)]
fn default() -> IntrHostEpSet {
<crate::RegValueT<IntrHostEpSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrHostEpMask_SPEC;
impl crate::sealed::RegSpec for IntrHostEpMask_SPEC {
type DataType = u32;
}
#[doc = "Interrupt USB Host Endpoint Mask Register"]
pub type IntrHostEpMask = crate::RegValueT<IntrHostEpMask_SPEC>;
impl IntrHostEpMask {
#[doc = "This bit masks the interrupt by EP1DRQ flag.\n\'0\' : Disables\n\'1\' : Enables"]
#[inline(always)]
pub fn ep1drqm(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrHostEpMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,IntrHostEpMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit masks the interrupt by EP1SPK flag.\n\'0\' : Disables\n\'1\' : Enables"]
#[inline(always)]
pub fn ep1spkm(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrHostEpMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,IntrHostEpMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit masks the interrupt by EP2DRQ flag.\n\'0\' : Disables\n\'1\' : Enables"]
#[inline(always)]
pub fn ep2drqm(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrHostEpMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,IntrHostEpMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit masks the interrupt by EP2SPK flag.\n\'0\' : Disables\n\'1\' : Enables"]
#[inline(always)]
pub fn ep2spkm(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrHostEpMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,IntrHostEpMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrHostEpMask {
#[inline(always)]
fn default() -> IntrHostEpMask {
<crate::RegValueT<IntrHostEpMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrHostEpMasked_SPEC;
impl crate::sealed::RegSpec for IntrHostEpMasked_SPEC {
type DataType = u32;
}
#[doc = "Interrupt USB Host Endpoint Masked Register"]
pub type IntrHostEpMasked = crate::RegValueT<IntrHostEpMasked_SPEC>;
impl IntrHostEpMasked {
#[doc = "This bit indicates the interrupt by EP1DRQ flag.\n\'0\' : Doesn\'t request the interrupt by EP1DRQ\n\'1\' : Request the interrupt by EP1DRQ"]
#[inline(always)]
pub fn ep1drqed(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrHostEpMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<2,1,0,IntrHostEpMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit indicates the interrupt by EP1SPK flag.\n\'0\' : Doesn\'t request the interrupt by EP1SPK\n\'1\' : Request the interrupt by EP1SPK"]
#[inline(always)]
pub fn ep1spked(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrHostEpMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<3,1,0,IntrHostEpMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit indicates the interrupt by EP2DRQ flag.\n\'0\' : Doesn\'t request the interrupt by EP2DRQ\n\'1\' : Request the interrupt by EP2DRQ"]
#[inline(always)]
pub fn ep2drqed(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrHostEpMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<4,1,0,IntrHostEpMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit indicates the interrupt by EP2SPK flag.\n\'0\' : Doesn\'t request the interrupt by EP2SPK\n\'1\' : Request the interrupt by EP2SPK"]
#[inline(always)]
pub fn ep2spked(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrHostEpMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<5,1,0,IntrHostEpMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrHostEpMasked {
#[inline(always)]
fn default() -> IntrHostEpMasked {
<crate::RegValueT<IntrHostEpMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostDmaEnbl_SPEC;
impl crate::sealed::RegSpec for HostDmaEnbl_SPEC {
type DataType = u32;
}
#[doc = "Host DMA Enable Register"]
pub type HostDmaEnbl = crate::RegValueT<HostDmaEnbl_SPEC>;
impl HostDmaEnbl {
#[doc = "This bit enables DMA Request by EP1DRQ.\n\'0\' : Disable\n\'1\' : Enable"]
#[inline(always)]
pub fn dm_ep1drqe(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, HostDmaEnbl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,HostDmaEnbl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit enables DMA Request by EP2DRQ.\n\'0\' : Disable\n\'1\' : Enable"]
#[inline(always)]
pub fn dm_ep2drqe(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, HostDmaEnbl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,HostDmaEnbl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for HostDmaEnbl {
#[inline(always)]
fn default() -> HostDmaEnbl {
<crate::RegValueT<HostDmaEnbl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostEp1Blk_SPEC;
impl crate::sealed::RegSpec for HostEp1Blk_SPEC {
type DataType = u32;
}
#[doc = "Host Endpoint 1 Block Register"]
pub type HostEp1Blk = crate::RegValueT<HostEp1Blk_SPEC>;
impl HostEp1Blk {
#[doc = "Set the total byte number for DMA transfer. If HOST_EP1_RW1_DR or HOST_EP1_RW2_DR is written, the block number counter is decremented when DMAE=\'1\'.\n- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP1DRQE=\'1\')"]
#[inline(always)]
pub fn blk_num(
self,
) -> crate::common::RegisterField<
16,
0xffff,
1,
0,
u16,
u16,
HostEp1Blk_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0xffff,
1,
0,
u16,
u16,
HostEp1Blk_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for HostEp1Blk {
#[inline(always)]
fn default() -> HostEp1Blk {
<crate::RegValueT<HostEp1Blk_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HostEp2Blk_SPEC;
impl crate::sealed::RegSpec for HostEp2Blk_SPEC {
type DataType = u32;
}
#[doc = "Host Endpoint 2 Block Register"]
pub type HostEp2Blk = crate::RegValueT<HostEp2Blk_SPEC>;
impl HostEp2Blk {
#[doc = "Set the total byte number for DMA transfer. If HOST_EP2_RW1_DR or HOST_EP2_RW2_DR is written, the block number counter is decremented when DMAE=\'1\'.\n- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP2DRQE=\'1\')"]
#[inline(always)]
pub fn blk_num(
self,
) -> crate::common::RegisterField<
16,
0xffff,
1,
0,
u16,
u16,
HostEp2Blk_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0xffff,
1,
0,
u16,
u16,
HostEp2Blk_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for HostEp2Blk {
#[inline(always)]
fn default() -> HostEp2Blk {
<crate::RegValueT<HostEp2Blk_SPEC> as RegisterValue<_>>::new(0)
}
}
}