/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"PASS top-level MMIO (DSABv2, INTR)"]
unsafe impl ::core::marker::Send for super::Pass {}
unsafe impl ::core::marker::Sync for super::Pass {}
impl super::Pass {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "Interrupt cause register"]
#[inline(always)]
pub const fn intr_cause(
&self,
) -> &'static crate::common::Reg<self::IntrCause_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrCause_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "VREF Trim bits"]
#[inline(always)]
pub const fn vref_trim0(
&self,
) -> &'static crate::common::Reg<self::VrefTrim0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::VrefTrim0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3840usize),
)
}
}
#[doc = "VREF Trim bits"]
#[inline(always)]
pub const fn vref_trim1(
&self,
) -> &'static crate::common::Reg<self::VrefTrim1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::VrefTrim1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3844usize),
)
}
}
#[doc = "VREF Trim bits"]
#[inline(always)]
pub const fn vref_trim2(
&self,
) -> &'static crate::common::Reg<self::VrefTrim2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::VrefTrim2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3848usize),
)
}
}
#[doc = "VREF Trim bits"]
#[inline(always)]
pub const fn vref_trim3(
&self,
) -> &'static crate::common::Reg<self::VrefTrim3_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::VrefTrim3_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3852usize),
)
}
}
#[doc = "IZTAT Trim bits"]
#[inline(always)]
pub const fn iztat_trim0(
&self,
) -> &'static crate::common::Reg<self::IztatTrim0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IztatTrim0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3856usize),
)
}
}
#[doc = "IZTAT Trim bits"]
#[inline(always)]
pub const fn iztat_trim1(
&self,
) -> &'static crate::common::Reg<self::IztatTrim1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IztatTrim1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3860usize),
)
}
}
#[doc = "IPTAT Trim bits"]
#[inline(always)]
pub const fn iptat_trim0(
&self,
) -> &'static crate::common::Reg<self::IptatTrim0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IptatTrim0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3864usize),
)
}
}
#[doc = "ICTAT Trim bits"]
#[inline(always)]
pub const fn ictat_trim0(
&self,
) -> &'static crate::common::Reg<self::IctatTrim0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IctatTrim0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3868usize),
)
}
}
#[doc = "AREF configuration"]
#[inline(always)]
pub const fn aref(self) -> crate::pass::Aref {
unsafe { crate::pass::_Aref::_svd2pac_from_ptr(self._svd2pac_as_ptr().add(3584usize)) }
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrCause_SPEC;
impl crate::sealed::RegSpec for IntrCause_SPEC {
type DataType = u32;
}
#[doc = "Interrupt cause register"]
pub type IntrCause = crate::RegValueT<IntrCause_SPEC>;
impl IntrCause {
#[doc = "CTB0 interrupt pending"]
#[inline(always)]
pub fn ctb0_int(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "CTB1 interrupt pending"]
#[inline(always)]
pub fn ctb1_int(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "CTB2 interrupt pending"]
#[inline(always)]
pub fn ctb2_int(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "CTB3 interrupt pending"]
#[inline(always)]
pub fn ctb3_int(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "CTDAC0 interrupt pending"]
#[inline(always)]
pub fn ctdac0_int(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "CTDAC1 interrupt pending"]
#[inline(always)]
pub fn ctdac1_int(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "CTDAC2 interrupt pending"]
#[inline(always)]
pub fn ctdac2_int(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<6, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "CTDAC3 interrupt pending"]
#[inline(always)]
pub fn ctdac3_int(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<7, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for IntrCause {
#[inline(always)]
fn default() -> IntrCause {
<crate::RegValueT<IntrCause_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct VrefTrim0_SPEC;
impl crate::sealed::RegSpec for VrefTrim0_SPEC {
type DataType = u32;
}
#[doc = "VREF Trim bits"]
pub type VrefTrim0 = crate::RegValueT<VrefTrim0_SPEC>;
impl VrefTrim0 {
#[doc = "N/A"]
#[inline(always)]
pub fn vref_abs_trim(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, VrefTrim0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,VrefTrim0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for VrefTrim0 {
#[inline(always)]
fn default() -> VrefTrim0 {
<crate::RegValueT<VrefTrim0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct VrefTrim1_SPEC;
impl crate::sealed::RegSpec for VrefTrim1_SPEC {
type DataType = u32;
}
#[doc = "VREF Trim bits"]
pub type VrefTrim1 = crate::RegValueT<VrefTrim1_SPEC>;
impl VrefTrim1 {
#[doc = "N/A"]
#[inline(always)]
pub fn vref_tempco_trim(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, VrefTrim1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,VrefTrim1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for VrefTrim1 {
#[inline(always)]
fn default() -> VrefTrim1 {
<crate::RegValueT<VrefTrim1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct VrefTrim2_SPEC;
impl crate::sealed::RegSpec for VrefTrim2_SPEC {
type DataType = u32;
}
#[doc = "VREF Trim bits"]
pub type VrefTrim2 = crate::RegValueT<VrefTrim2_SPEC>;
impl VrefTrim2 {
#[doc = "N/A"]
#[inline(always)]
pub fn vref_curv_trim(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, VrefTrim2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,VrefTrim2_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for VrefTrim2 {
#[inline(always)]
fn default() -> VrefTrim2 {
<crate::RegValueT<VrefTrim2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct VrefTrim3_SPEC;
impl crate::sealed::RegSpec for VrefTrim3_SPEC {
type DataType = u32;
}
#[doc = "VREF Trim bits"]
pub type VrefTrim3 = crate::RegValueT<VrefTrim3_SPEC>;
impl VrefTrim3 {
#[doc = "Obsolete"]
#[inline(always)]
pub fn vref_atten_trim(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, VrefTrim3_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0xf,1,0,u8,u8,VrefTrim3_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for VrefTrim3 {
#[inline(always)]
fn default() -> VrefTrim3 {
<crate::RegValueT<VrefTrim3_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IztatTrim0_SPEC;
impl crate::sealed::RegSpec for IztatTrim0_SPEC {
type DataType = u32;
}
#[doc = "IZTAT Trim bits"]
pub type IztatTrim0 = crate::RegValueT<IztatTrim0_SPEC>;
impl IztatTrim0 {
#[doc = "N/A"]
#[inline(always)]
pub fn iztat_abs_trim(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, IztatTrim0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,IztatTrim0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IztatTrim0 {
#[inline(always)]
fn default() -> IztatTrim0 {
<crate::RegValueT<IztatTrim0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IztatTrim1_SPEC;
impl crate::sealed::RegSpec for IztatTrim1_SPEC {
type DataType = u32;
}
#[doc = "IZTAT Trim bits"]
pub type IztatTrim1 = crate::RegValueT<IztatTrim1_SPEC>;
impl IztatTrim1 {
#[doc = "IZTAT temperature correction trim (RMB)\n0x00 : No IZTAT temperature correction\n0xFF : Maximum IZTAT temperature correction\n\nAs this is a Risk Mitigation Register, it should be loaded with 0x08."]
#[inline(always)]
pub fn iztat_tc_trim(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, IztatTrim1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,IztatTrim1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IztatTrim1 {
#[inline(always)]
fn default() -> IztatTrim1 {
<crate::RegValueT<IztatTrim1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IptatTrim0_SPEC;
impl crate::sealed::RegSpec for IptatTrim0_SPEC {
type DataType = u32;
}
#[doc = "IPTAT Trim bits"]
pub type IptatTrim0 = crate::RegValueT<IptatTrim0_SPEC>;
impl IptatTrim0 {
#[doc = "IPTAT trim\n0x0 : Minimum IPTAT current (~150nA at room)\n0xF : Maximum IPTAT current (~350nA at room)"]
#[inline(always)]
pub fn iptat_core_trim(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, IptatTrim0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,IptatTrim0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "CTMB PTAT Current Trim\n0x0 : Minimum CTMB IPTAT Current (~875nA)\n0xF : Maximum CTMB IPTAT Current (~1.1uA)"]
#[inline(always)]
pub fn iptat_ctbm_trim(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, IptatTrim0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0xf,1,0,u8,u8,IptatTrim0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IptatTrim0 {
#[inline(always)]
fn default() -> IptatTrim0 {
<crate::RegValueT<IptatTrim0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IctatTrim0_SPEC;
impl crate::sealed::RegSpec for IctatTrim0_SPEC {
type DataType = u32;
}
#[doc = "ICTAT Trim bits"]
pub type IctatTrim0 = crate::RegValueT<IctatTrim0_SPEC>;
impl IctatTrim0 {
#[doc = "ICTAT trim\n0x00 : Minimum ICTAT current (~150nA at room)\n0x0F : Maximum ICTAT current (~350nA at room)"]
#[inline(always)]
pub fn ictat_trim(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, IctatTrim0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,IctatTrim0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IctatTrim0 {
#[inline(always)]
fn default() -> IctatTrim0 {
<crate::RegValueT<IctatTrim0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc = "AREF configuration"]
#[non_exhaustive]
pub struct _Aref;
#[doc = "AREF configuration"]
pub type Aref = &'static _Aref;
unsafe impl ::core::marker::Sync for _Aref {}
impl _Aref {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "global AREF control"]
#[inline(always)]
pub const fn aref_ctrl(
&self,
) -> &'static crate::common::Reg<aref::ArefCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<aref::ArefCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
}
pub mod aref {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ArefCtrl_SPEC;
impl crate::sealed::RegSpec for ArefCtrl_SPEC {
type DataType = u32;
}
#[doc = "global AREF control"]
pub type ArefCtrl = crate::RegValueT<ArefCtrl_SPEC>;
impl ArefCtrl {
#[doc = "Control bit to trade off AREF settling and noise performance"]
#[inline(always)]
pub fn aref_mode(
self,
) -> crate::common::RegisterField<
0,
0x1,
1,
0,
aref_ctrl::ArefMode,
aref_ctrl::ArefMode,
ArefCtrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1,
1,
0,
aref_ctrl::ArefMode,
aref_ctrl::ArefMode,
ArefCtrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "BIAS Current Control for all AREF Amplifiers. (These are risk mitigation bits that should not be touched by the customer: the impact on IDDA/noise/startup still needs to be characterized)\n0: 125nA (reduced bias: reduction in total AREF IDDA, higher noise and longer startup times)\n1: 250nA (\'default\' setting to meet bandgap performance (noise/startup) and IDDA specifications)\n2: 375nA (increased bias: increase in total AREF IDDA, lower noise and shorter startup times)\n3: 500nA (further increased bias: increase in total AREF IDDA, lower noise and shorter startup times)"]
#[inline(always)]
pub fn aref_bias_scale(
self,
) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, ArefCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<2,0x3,1,0,u8,u8,ArefCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "AREF control signals (RMB).\n\nBit 0: Manual VBG startup circuit enable\n 0: normal VBG startup circuit operation\n 1: VBG startup circuit is forced \'always on\'\n\nBit 1: Manual disable of IPTAT2 DAC\n 0: normal IPTAT2 DAC operation\n 1: PTAT2 DAC is disabled while VBG startup is active\n\nBit 2: Manual enable of VBG offset correction DAC\n 0: normal VBG offset correction DAC operation\n 1: VBG offset correction DAC is enabled while VBG startup is active"]
#[inline(always)]
pub fn aref_rmb(
self,
) -> crate::common::RegisterField<4, 0x7, 1, 0, u8, u8, ArefCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0x7,1,0,u8,u8,ArefCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "CTB IPTAT current scaler. This bit must be set in order to operate the CTB amplifiers in the lowest power mode. This bit is chip-wide (controls all CTB amplifiers).\n0: 1uA\n1: 100nA"]
#[inline(always)]
pub fn ctb_iptat_scale(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, ArefCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,ArefCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Re-direct the CTB IPTAT output current. This can be used to reduce amplifier bias glitches during power mode transitions (for PSoC4A/B DSAB backwards compatibility).\n0: Opamp<n>.IPTAT = AREF.IPTAT and Opamp<n>.IZTAT= AREF.IZTAT\n1: Opamp<n>.IPTAT = HiZ and Opamp<n>.IZTAT= AREF.IPTAT\n\n*Note that in Deep Sleep, the AREF IZTAT and/or IPTAT currents can be disabled and therefore the corresponding Opamp<n>.IZTAT/IPTAT will be HiZ."]
#[inline(always)]
pub fn ctb_iptat_redirect(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, ArefCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,ArefCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "iztat current select control"]
#[inline(always)]
pub fn iztat_sel(
self,
) -> crate::common::RegisterField<
16,
0x1,
1,
0,
aref_ctrl::IztatSel,
aref_ctrl::IztatSel,
ArefCtrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0x1,
1,
0,
aref_ctrl::IztatSel,
aref_ctrl::IztatSel,
ArefCtrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "CTBm charge pump clock source select. This field has nothing to do with the AREF.\n0: Use the dedicated pump clock from SRSS (default)\n1: Use one of the CLK_PERI dividers"]
#[inline(always)]
pub fn clock_pump_peri_sel(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, ArefCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,ArefCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "bandgap voltage select control"]
#[inline(always)]
pub fn vref_sel(
self,
) -> crate::common::RegisterField<
20,
0x3,
1,
0,
aref_ctrl::VrefSel,
aref_ctrl::VrefSel,
ArefCtrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
20,
0x3,
1,
0,
aref_ctrl::VrefSel,
aref_ctrl::VrefSel,
ArefCtrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "AREF DeepSleep Operation Modes (only applies if DEEPSLEEP_ON = 1)"]
#[inline(always)]
pub fn deepsleep_mode(
self,
) -> crate::common::RegisterField<
28,
0x3,
1,
0,
aref_ctrl::DeepsleepMode,
aref_ctrl::DeepsleepMode,
ArefCtrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
28,
0x3,
1,
0,
aref_ctrl::DeepsleepMode,
aref_ctrl::DeepsleepMode,
ArefCtrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "- 0: AREF IP disabled/off during DeepSleep power mode\n- 1: AREF IP remains enabled during DeepSleep power mode (if ENABLED=1)"]
#[inline(always)]
pub fn deepsleep_on(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, ArefCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,ArefCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Disable AREF"]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ArefCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,ArefCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ArefCtrl {
#[inline(always)]
fn default() -> ArefCtrl {
<crate::RegValueT<ArefCtrl_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod aref_ctrl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ArefMode_SPEC;
pub type ArefMode = crate::EnumBitfieldStruct<u8, ArefMode_SPEC>;
impl ArefMode {
#[doc = "Nominal noise normal startup mode (meets normal mode settling and noise specifications)"]
pub const NORMAL: Self = Self::new(0);
#[doc = "High noise fast startup mode (meets fast mode settling and noise specifications)"]
pub const FAST_START: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct IztatSel_SPEC;
pub type IztatSel = crate::EnumBitfieldStruct<u8, IztatSel_SPEC>;
impl IztatSel {
#[doc = "Use 250nA IZTAT from SRSS"]
pub const SRSS: Self = Self::new(0);
#[doc = "Use locally generated 250nA"]
pub const LOCAL: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct VrefSel_SPEC;
pub type VrefSel = crate::EnumBitfieldStruct<u8, VrefSel_SPEC>;
impl VrefSel {
#[doc = "Use 0.8V Vref from SRSS"]
pub const SRSS: Self = Self::new(0);
#[doc = "Use locally generated Vref"]
pub const LOCAL: Self = Self::new(1);
#[doc = "Use externally supplied Vref (aref_ext_vref)"]
pub const EXTERNAL: Self = Self::new(2);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DeepsleepMode_SPEC;
pub type DeepsleepMode = crate::EnumBitfieldStruct<u8, DeepsleepMode_SPEC>;
impl DeepsleepMode {
#[doc = "All blocks \'OFF\' in DeepSleep"]
pub const OFF: Self = Self::new(0);
#[doc = "IPTAT bias generator \'ON\' in DeepSleep (used for fast AREF wakeup only: IPTAT outputs not available)"]
pub const IPTAT: Self = Self::new(1);
#[doc = "IPTAT bias generator and outputs \'ON\' in DeepSleep (used for biasing the CTBm with a PTAT current only in deep sleep)\n\n*Note that this mode also requires that the CTB_IPTAT_REDIRECT be set if the CTBm opamp is to operate in DeepSleep"]
pub const IPTAT_IZTAT: Self = Self::new(2);
#[doc = "IPTAT, VREF, and IZTAT generators \'ON\' in DeepSleep. This mode provides identical AREF functionality in DeepSleep as in the Active mode."]
pub const IPTAT_IZTAT_VREF: Self = Self::new(3);
}
}
}