mtb_pac_psoc6_01 0.1.1

/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)

    or an affiliate of Cypress Semiconductor Corporation.



    SPDX-License-Identifier: Apache-2.0



    Licensed under the Apache License, Version 2.0 (the "License");

    you may not use this file except in compliance with the License.

    You may obtain a copy of the License at



      http://www.apache.org/licenses/LICENSE-2.0



    Unless required by applicable law or agreed to in writing, software

    distributed under the License is distributed on an "AS IS" BASIS,

    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

    See the License for the specific language governing permissions and

    limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000

#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"PDM registers"]
unsafe impl ::core::marker::Send for super::Pdm {}
unsafe impl ::core::marker::Sync for super::Pdm {}
impl super::Pdm {
    #[allow(unused)]
    #[inline(always)]
    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
        self.ptr
    }

    #[doc = "Control"]
    #[inline(always)]
    pub const fn ctl(&self) -> &'static crate::common::Reg<self::Ctl_SPEC, crate::common::RW> {
        unsafe {
            crate::common::Reg::<self::Ctl_SPEC, crate::common::RW>::from_ptr(
                self._svd2pac_as_ptr().add(0usize),
            )
        }
    }

    #[doc = "Clock control"]
    #[inline(always)]
    pub const fn clock_ctl(
        &self,
    ) -> &'static crate::common::Reg<self::ClockCtl_SPEC, crate::common::RW> {
        unsafe {
            crate::common::Reg::<self::ClockCtl_SPEC, crate::common::RW>::from_ptr(
                self._svd2pac_as_ptr().add(16usize),
            )
        }
    }

    #[doc = "Mode control"]
    #[inline(always)]
    pub const fn mode_ctl(
        &self,
    ) -> &'static crate::common::Reg<self::ModeCtl_SPEC, crate::common::RW> {
        unsafe {
            crate::common::Reg::<self::ModeCtl_SPEC, crate::common::RW>::from_ptr(
                self._svd2pac_as_ptr().add(20usize),
            )
        }
    }

    #[doc = "Data control"]
    #[inline(always)]
    pub const fn data_ctl(
        &self,
    ) -> &'static crate::common::Reg<self::DataCtl_SPEC, crate::common::RW> {
        unsafe {
            crate::common::Reg::<self::DataCtl_SPEC, crate::common::RW>::from_ptr(
                self._svd2pac_as_ptr().add(24usize),
            )
        }
    }

    #[doc = "Command"]
    #[inline(always)]
    pub const fn cmd(&self) -> &'static crate::common::Reg<self::Cmd_SPEC, crate::common::RW> {
        unsafe {
            crate::common::Reg::<self::Cmd_SPEC, crate::common::RW>::from_ptr(
                self._svd2pac_as_ptr().add(32usize),
            )
        }
    }

    #[doc = "Trigger control"]
    #[inline(always)]
    pub const fn tr_ctl(&self) -> &'static crate::common::Reg<self::TrCtl_SPEC, crate::common::RW> {
        unsafe {
            crate::common::Reg::<self::TrCtl_SPEC, crate::common::RW>::from_ptr(
                self._svd2pac_as_ptr().add(64usize),
            )
        }
    }

    #[doc = "RX FIFO control"]
    #[inline(always)]
    pub const fn rx_fifo_ctl(
        &self,
    ) -> &'static crate::common::Reg<self::RxFifoCtl_SPEC, crate::common::RW> {
        unsafe {
            crate::common::Reg::<self::RxFifoCtl_SPEC, crate::common::RW>::from_ptr(
                self._svd2pac_as_ptr().add(768usize),
            )
        }
    }

    #[doc = "RX FIFO status"]
    #[inline(always)]
    pub const fn rx_fifo_status(
        &self,
    ) -> &'static crate::common::Reg<self::RxFifoStatus_SPEC, crate::common::R> {
        unsafe {
            crate::common::Reg::<self::RxFifoStatus_SPEC, crate::common::R>::from_ptr(
                self._svd2pac_as_ptr().add(772usize),
            )
        }
    }

    #[doc = "RX FIFO read"]
    #[inline(always)]
    pub const fn rx_fifo_rd(
        &self,
    ) -> &'static crate::common::Reg<self::RxFifoRd_SPEC, crate::common::R> {
        unsafe {
            crate::common::Reg::<self::RxFifoRd_SPEC, crate::common::R>::from_ptr(
                self._svd2pac_as_ptr().add(776usize),
            )
        }
    }

    #[doc = "RX FIFO silent read"]
    #[inline(always)]
    pub const fn rx_fifo_rd_silent(
        &self,
    ) -> &'static crate::common::Reg<self::RxFifoRdSilent_SPEC, crate::common::R> {
        unsafe {
            crate::common::Reg::<self::RxFifoRdSilent_SPEC, crate::common::R>::from_ptr(
                self._svd2pac_as_ptr().add(780usize),
            )
        }
    }

    #[doc = "Interrupt register"]
    #[inline(always)]
    pub const fn intr(&self) -> &'static crate::common::Reg<self::Intr_SPEC, crate::common::RW> {
        unsafe {
            crate::common::Reg::<self::Intr_SPEC, crate::common::RW>::from_ptr(
                self._svd2pac_as_ptr().add(3840usize),
            )
        }
    }

    #[doc = "Interrupt set register"]
    #[inline(always)]
    pub const fn intr_set(
        &self,
    ) -> &'static crate::common::Reg<self::IntrSet_SPEC, crate::common::RW> {
        unsafe {
            crate::common::Reg::<self::IntrSet_SPEC, crate::common::RW>::from_ptr(
                self._svd2pac_as_ptr().add(3844usize),
            )
        }
    }

    #[doc = "Interrupt mask register"]
    #[inline(always)]
    pub const fn intr_mask(
        &self,
    ) -> &'static crate::common::Reg<self::IntrMask_SPEC, crate::common::RW> {
        unsafe {
            crate::common::Reg::<self::IntrMask_SPEC, crate::common::RW>::from_ptr(
                self._svd2pac_as_ptr().add(3848usize),
            )
        }
    }

    #[doc = "Interrupt masked register"]
    #[inline(always)]
    pub const fn intr_masked(
        &self,
    ) -> &'static crate::common::Reg<self::IntrMasked_SPEC, crate::common::R> {
        unsafe {
            crate::common::Reg::<self::IntrMasked_SPEC, crate::common::R>::from_ptr(
                self._svd2pac_as_ptr().add(3852usize),
            )
        }
    }
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctl_SPEC;
impl crate::sealed::RegSpec for Ctl_SPEC {
    type DataType = u32;
}

#[doc = "Control"]
pub type Ctl = crate::RegValueT<Ctl_SPEC>;

impl Ctl {
    #[doc = "Right channel PGA gain:\n+1.5dB/step, -12dB ~ +10.5dB\n\'0\': -12 dB\n\'1\': -10.5 dB \n...\n\'15\' +10.5 dB\n(Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_R)"]
    #[inline(always)]
    pub fn pga_r(
        self,
    ) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, Ctl_SPEC, crate::common::RW> {
        crate::common::RegisterField::<0,0xf,1,0,u8,u8,Ctl_SPEC,crate::common::RW>::from_register(self,0)
    }

    #[doc = "Left channel PGA gain:\n+1.5dB/step, -12dB ~ +10.5dB\n\'0\': -12 dB\n\'1\': -10.5 dB \n...\n\'15\': +10.5 dB\n(Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_L)"]
    #[inline(always)]
    pub fn pga_l(
        self,
    ) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, Ctl_SPEC, crate::common::RW> {
        crate::common::RegisterField::<8,0xf,1,0,u8,u8,Ctl_SPEC,crate::common::RW>::from_register(self,0)
    }

    #[doc = "Soft mute function to mute the volume smoothly\n\'0\': Disabled.\n\'1\': Enabled.\n(Note: This bit is connected to AR36U12.PDM_CORE_CFG.SOFT_MUTE)"]
    #[inline(always)]
    pub fn soft_mute(
        self,
    ) -> crate::common::RegisterFieldBool<16, 1, 0, Ctl_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<16, 1, 0, Ctl_SPEC, crate::common::RW>::from_register(
            self, 0,
        )
    }

    #[doc = "Set fine gain step for smooth PGA or Soft-Mute attenuation transition.\n\'0\': 0.13dB\n\'1\': 0.26dB\n(Note: This bit is connected to AR36U12.PDM_CORE2_CFG.SEL_STEP)"]
    #[inline(always)]
    pub fn step_sel(
        self,
    ) -> crate::common::RegisterFieldBool<17, 1, 0, Ctl_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<17, 1, 0, Ctl_SPEC, crate::common::RW>::from_register(
            self, 0,
        )
    }

    #[doc = "Enables the PDM component:\n\'0\': Disabled.\n\'1\': Enabled."]
    #[inline(always)]
    pub fn enabled(
        self,
    ) -> crate::common::RegisterFieldBool<31, 1, 0, Ctl_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<31, 1, 0, Ctl_SPEC, crate::common::RW>::from_register(
            self, 0,
        )
    }
}
impl ::core::default::Default for Ctl {
    #[inline(always)]
    fn default() -> Ctl {
        <crate::RegValueT<Ctl_SPEC> as RegisterValue<_>>::new(133128)
    }
}

#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClockCtl_SPEC;
impl crate::sealed::RegSpec for ClockCtl_SPEC {
    type DataType = u32;
}

#[doc = "Clock control"]
pub type ClockCtl = crate::RegValueT<ClockCtl_SPEC>;

impl ClockCtl {
    #[doc = "PDM CLK (FPDM_CLK) (1st divider):\nThis configures a frequency of PDM CLK. The configured frequency is used to operate PDM core. I.e. the frequency is input to MCLKQ_CLOCK_DIV register.\n\nNote: configure a frequency of PDM CLK as lower than or equal 50MHz with this divider."]
    #[inline(always)]
    pub fn clk_clock_div(
        self,
    ) -> crate::common::RegisterField<
        0,
        0x3,
        1,
        0,
        clock_ctl::ClkClockDiv,
        clock_ctl::ClkClockDiv,
        ClockCtl_SPEC,
        crate::common::RW,
    > {
        crate::common::RegisterField::<
            0,
            0x3,
            1,
            0,
            clock_ctl::ClkClockDiv,
            clock_ctl::ClkClockDiv,
            ClockCtl_SPEC,
            crate::common::RW,
        >::from_register(self, 0)
    }

    #[doc = "MCLKQ divider (2nd divider)\n\n(Note: These bits are connected to \nAR36U12.PDM_CORE2_CFG.DIV_MCLKQ)"]
    #[inline(always)]
    pub fn mclkq_clock_div(
        self,
    ) -> crate::common::RegisterField<
        4,
        0x3,
        1,
        0,
        clock_ctl::MclkqClockDiv,
        clock_ctl::MclkqClockDiv,
        ClockCtl_SPEC,
        crate::common::RW,
    > {
        crate::common::RegisterField::<
            4,
            0x3,
            1,
            0,
            clock_ctl::MclkqClockDiv,
            clock_ctl::MclkqClockDiv,
            ClockCtl_SPEC,
            crate::common::RW,
        >::from_register(self, 0)
    }

    #[doc = "PDM CKO (FPDM_CKO) clock divider (3rd divider):\nFPDM_CKO = MCLKQ / (CKO_CLOCK_DIV + 1)\n\nNote: To configure \'0\' to this field is prohibited.\n(Note: PDM_CKO is configured by MCLKQ_CLOCK_DIV,  CLK_CLOCK_DIV and CKO_CLOCK_DIV. )\n(Note: These bits are connected to \nAR36U12.PDM_CORE_CFG.MCLKDIV)"]
    #[inline(always)]
    pub fn cko_clock_div(
        self,
    ) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, ClockCtl_SPEC, crate::common::RW> {
        crate::common::RegisterField::<8,0xf,1,0,u8,u8,ClockCtl_SPEC,crate::common::RW>::from_register(self,0)
    }

    #[doc = "SINC Decimation Rate. For details, see the data sheet provided by Archband.\nOversampling Ratio = Decimation Rate = 2 X SINC_RATE\n(Note: These bits are connected to AR36U12.PDM_CORE_CFG.SINC_RATE)"]
    #[inline(always)]
    pub fn sinc_rate(
        self,
    ) -> crate::common::RegisterField<16, 0x7f, 1, 0, u8, u8, ClockCtl_SPEC, crate::common::RW>
    {
        crate::common::RegisterField::<16,0x7f,1,0,u8,u8,ClockCtl_SPEC,crate::common::RW>::from_register(self,0)
    }
}
impl ::core::default::Default for ClockCtl {
    #[inline(always)]
    fn default() -> ClockCtl {
        <crate::RegValueT<ClockCtl_SPEC> as RegisterValue<_>>::new(2097936)
    }
}
pub mod clock_ctl {

    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
    pub struct ClkClockDiv_SPEC;
    pub type ClkClockDiv = crate::EnumBitfieldStruct<u8, ClkClockDiv_SPEC>;
    impl ClkClockDiv {
        #[doc = "Divide by 1"]
        pub const DIVBY_1: Self = Self::new(0);

        #[doc = "Divide by 2 (no 50 percent duty cycle)"]
        pub const DIVBY_2: Self = Self::new(1);

        #[doc = "Divide by 3 (no 50 percent duty cycle)"]
        pub const DIVBY_3: Self = Self::new(2);

        #[doc = "Divide by 4 (no 50 percent duty cycle)"]
        pub const DIVBY_4: Self = Self::new(3);
    }
    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
    pub struct MclkqClockDiv_SPEC;
    pub type MclkqClockDiv = crate::EnumBitfieldStruct<u8, MclkqClockDiv_SPEC>;
    impl MclkqClockDiv {
        #[doc = "Divide by 1"]
        pub const DIVBY_1: Self = Self::new(0);

        #[doc = "Divide by 2 (no 50 percent duty cycle)"]
        pub const DIVBY_2: Self = Self::new(1);

        #[doc = "Divide by 3 (no 50 percent duty cycle)"]
        pub const DIVBY_3: Self = Self::new(2);

        #[doc = "Divide by 4 (no 50 percent duty cycle)"]
        pub const DIVBY_4: Self = Self::new(3);
    }
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ModeCtl_SPEC;
impl crate::sealed::RegSpec for ModeCtl_SPEC {
    type DataType = u32;
}

#[doc = "Mode control"]
pub type ModeCtl = crate::RegValueT<ModeCtl_SPEC>;

impl ModeCtl {
    #[doc = "Specifies PCM output channels as mono or stereo:\n\n(Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_CHSET)"]
    #[inline(always)]
    pub fn pcm_ch_set(
        self,
    ) -> crate::common::RegisterField<
        0,
        0x3,
        1,
        0,
        mode_ctl::PcmChSet,
        mode_ctl::PcmChSet,
        ModeCtl_SPEC,
        crate::common::RW,
    > {
        crate::common::RegisterField::<
            0,
            0x3,
            1,
            0,
            mode_ctl::PcmChSet,
            mode_ctl::PcmChSet,
            ModeCtl_SPEC,
            crate::common::RW,
        >::from_register(self, 0)
    }

    #[doc = "Input data L/R channel swap:\n\'1\': Right/Left channel recording swap\n\'0\': No Swap\n(Note: This bit is connected to AR36U12.PDM_CORE_CFG.LRSWAP)"]
    #[inline(always)]
    pub fn swap_lr(
        self,
    ) -> crate::common::RegisterFieldBool<2, 1, 0, ModeCtl_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<2, 1, 0, ModeCtl_SPEC, crate::common::RW>::from_register(
            self, 0,
        )
    }

    #[doc = "Set time step for gain change during PGA or soft mute operation in\nnumber of 1/a sampling rate.\n(Note: These bits are connected to AR36U12.PDM_CORE_CFG.S_CYCLES)"]
    #[inline(always)]
    pub fn s_cycles(
        self,
    ) -> crate::common::RegisterField<
        8,
        0x7,
        1,
        0,
        mode_ctl::SCycles,
        mode_ctl::SCycles,
        ModeCtl_SPEC,
        crate::common::RW,
    > {
        crate::common::RegisterField::<
            8,
            0x7,
            1,
            0,
            mode_ctl::SCycles,
            mode_ctl::SCycles,
            ModeCtl_SPEC,
            crate::common::RW,
        >::from_register(self, 0)
    }

    #[doc = "Phase difference from the rising edge of internal sampler clock (CLK_IS) to that of PDM_CKO clock:\n\n(Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PDMCKO_DLY)"]
    #[inline(always)]
    pub fn cko_delay(
        self,
    ) -> crate::common::RegisterField<
        16,
        0x7,
        1,
        0,
        mode_ctl::CkoDelay,
        mode_ctl::CkoDelay,
        ModeCtl_SPEC,
        crate::common::RW,
    > {
        crate::common::RegisterField::<
            16,
            0x7,
            1,
            0,
            mode_ctl::CkoDelay,
            mode_ctl::CkoDelay,
            ModeCtl_SPEC,
            crate::common::RW,
        >::from_register(self, 0)
    }

    #[doc = "Adjust high pass filter coefficients. \nH(Z) = (1 - Z-1 ) / \\[1 - (1- 2 -HPF_GAIN) Z-1 \\]\n(Note: These bits are connected to AR36U12.PDM_CORE_CFG.HPGAIN)"]
    #[inline(always)]
    pub fn hpf_gain(
        self,
    ) -> crate::common::RegisterField<24, 0xf, 1, 0, u8, u8, ModeCtl_SPEC, crate::common::RW> {
        crate::common::RegisterField::<24,0xf,1,0,u8,u8,ModeCtl_SPEC,crate::common::RW>::from_register(self,0)
    }

    #[doc = "Enable high pass filter (active low)\n\'1\': Disabled.\n\'0\': Enabled.\n(Note: This bit is connected to AR36U12.PDM_CORE_CFG.ADCHPD)"]
    #[inline(always)]
    pub fn hpf_en_n(
        self,
    ) -> crate::common::RegisterFieldBool<28, 1, 0, ModeCtl_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<28, 1, 0, ModeCtl_SPEC, crate::common::RW>::from_register(
            self, 0,
        )
    }
}
impl ::core::default::Default for ModeCtl {
    #[inline(always)]
    fn default() -> ModeCtl {
        <crate::RegValueT<ModeCtl_SPEC> as RegisterValue<_>>::new(452985091)
    }
}
pub mod mode_ctl {

    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
    pub struct PcmChSet_SPEC;
    pub type PcmChSet = crate::EnumBitfieldStruct<u8, PcmChSet_SPEC>;
    impl PcmChSet {
        #[doc = "Channel disabled"]
        pub const DISABLED: Self = Self::new(0);

        #[doc = "Mono left channel enable"]
        pub const MONO_L: Self = Self::new(1);

        #[doc = "Mono right channel enable"]
        pub const MONO_R: Self = Self::new(2);

        #[doc = "Stereo channel enable"]
        pub const STEREO: Self = Self::new(3);
    }
    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
    pub struct SCycles_SPEC;
    pub type SCycles = crate::EnumBitfieldStruct<u8, SCycles_SPEC>;
    impl SCycles {
        #[doc = "64steps"]
        pub const STEP_NUM_64: Self = Self::new(0);

        #[doc = "96steps"]
        pub const STEP_NUM_96: Self = Self::new(1);

        #[doc = "128steps"]
        pub const STEP_NUM_128: Self = Self::new(2);

        #[doc = "160steps"]
        pub const STEP_NUM_160: Self = Self::new(3);

        #[doc = "192steps"]
        pub const STEP_NUM_192: Self = Self::new(4);

        #[doc = "256steps"]
        pub const STEP_NUM_256: Self = Self::new(5);

        #[doc = "384steps"]
        pub const STEP_NUM_384: Self = Self::new(6);

        #[doc = "512steps"]
        pub const STEP_NUM_512: Self = Self::new(7);
    }
    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
    pub struct CkoDelay_SPEC;
    pub type CkoDelay = crate::EnumBitfieldStruct<u8, CkoDelay_SPEC>;
    impl CkoDelay {
        #[doc = "CLK_IS is 3*PDM_CLK period early"]
        pub const ADV_3: Self = Self::new(0);

        #[doc = "CLK_IS is 2*PDM_CLK period early"]
        pub const ADV_2: Self = Self::new(1);

        #[doc = "CLK_IS is 1*PDM_CLK period early"]
        pub const ADV_1: Self = Self::new(2);

        #[doc = "CLK_IS is the same as PDM_CKO"]
        pub const NO_DELAY: Self = Self::new(3);

        #[doc = "CLK_IS is 1*PDM_CLK period late"]
        pub const DLY_1: Self = Self::new(4);

        #[doc = "CLK_IS is 2*PDM_CLK period late"]
        pub const DLY_2: Self = Self::new(5);

        #[doc = "CLK_IS is 3*PDM_CLK period late"]
        pub const DLY_3: Self = Self::new(6);

        #[doc = "CLK_IS is 4*PDM_CLK period late"]
        pub const DLY_4: Self = Self::new(7);
    }
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DataCtl_SPEC;
impl crate::sealed::RegSpec for DataCtl_SPEC {
    type DataType = u32;
}

#[doc = "Data control"]
pub type DataCtl = crate::RegValueT<DataCtl_SPEC>;

impl DataCtl {
    #[doc = "PCM Word Length in number of bits:\n\n(Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_IWL)"]
    #[inline(always)]
    pub fn word_len(
        self,
    ) -> crate::common::RegisterField<
        0,
        0x3,
        1,
        0,
        data_ctl::WordLen,
        data_ctl::WordLen,
        DataCtl_SPEC,
        crate::common::RW,
    > {
        crate::common::RegisterField::<
            0,
            0x3,
            1,
            0,
            data_ctl::WordLen,
            data_ctl::WordLen,
            DataCtl_SPEC,
            crate::common::RW,
        >::from_register(self, 0)
    }

    #[doc = "When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set.\n\'0\': Extended by \'0\'\n\'1\': Extended by sign bit (if MSB word is \'1\', then it is extended by \'1\', if MSB is \'0\' then it is extended by \'0\')"]
    #[inline(always)]
    pub fn bit_extension(
        self,
    ) -> crate::common::RegisterFieldBool<8, 1, 0, DataCtl_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<8, 1, 0, DataCtl_SPEC, crate::common::RW>::from_register(
            self, 0,
        )
    }
}
impl ::core::default::Default for DataCtl {
    #[inline(always)]
    fn default() -> DataCtl {
        <crate::RegValueT<DataCtl_SPEC> as RegisterValue<_>>::new(0)
    }
}
pub mod data_ctl {

    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
    pub struct WordLen_SPEC;
    pub type WordLen = crate::EnumBitfieldStruct<u8, WordLen_SPEC>;
    impl WordLen {
        #[doc = "16-bit"]
        pub const BIT_LEN_16: Self = Self::new(0);

        #[doc = "18-bit"]
        pub const BIT_LEN_18: Self = Self::new(1);

        #[doc = "20-bit"]
        pub const BIT_LEN_20: Self = Self::new(2);

        #[doc = "24-bit"]
        pub const BIT_LEN_24: Self = Self::new(3);
    }
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cmd_SPEC;
impl crate::sealed::RegSpec for Cmd_SPEC {
    type DataType = u32;
}

#[doc = "Command"]
pub type Cmd = crate::RegValueT<Cmd_SPEC>;

impl Cmd {
    #[doc = "Enable data streaming flow:\n\'0\': Disabled.\n\'1\': Enabled.\n(Note: This bit is connected to AR36U12.PDM_CORE_CFG.PDMA_EN)"]
    #[inline(always)]
    pub fn stream_en(
        self,
    ) -> crate::common::RegisterFieldBool<0, 1, 0, Cmd_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<0, 1, 0, Cmd_SPEC, crate::common::RW>::from_register(
            self, 0,
        )
    }
}
impl ::core::default::Default for Cmd {
    #[inline(always)]
    fn default() -> Cmd {
        <crate::RegValueT<Cmd_SPEC> as RegisterValue<_>>::new(0)
    }
}

#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrCtl_SPEC;
impl crate::sealed::RegSpec for TrCtl_SPEC {
    type DataType = u32;
}

#[doc = "Trigger control"]
pub type TrCtl = crate::RegValueT<TrCtl_SPEC>;

impl TrCtl {
    #[doc = "Trigger output (\'tr_pdm_rx_req\') enable for requests of DMA transfer\n\'0\': Disabled.\n\'1\': Enabled."]
    #[inline(always)]
    pub fn rx_req_en(
        self,
    ) -> crate::common::RegisterFieldBool<16, 1, 0, TrCtl_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<16, 1, 0, TrCtl_SPEC, crate::common::RW>::from_register(
            self, 0,
        )
    }
}
impl ::core::default::Default for TrCtl {
    #[inline(always)]
    fn default() -> TrCtl {
        <crate::RegValueT<TrCtl_SPEC> as RegisterValue<_>>::new(0)
    }
}

#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxFifoCtl_SPEC;
impl crate::sealed::RegSpec for RxFifoCtl_SPEC {
    type DataType = u32;
}

#[doc = "RX FIFO control"]
pub type RxFifoCtl = crate::RegValueT<RxFifoCtl_SPEC>;

impl RxFifoCtl {
    #[doc = "Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated.\nNote: software can configure up to 254 in Mono channel enabled (MODE_CTL.PCM_CH_SET = \'1\' or \'2\'), up to 253 in Stereo channel enabled (MODE_CTL.PCM_CH_SET = \'3\')."]
    #[inline(always)]
    pub fn trigger_level(
        self,
    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, RxFifoCtl_SPEC, crate::common::RW>
    {
        crate::common::RegisterField::<0,0xff,1,0,u8,u8,RxFifoCtl_SPEC,crate::common::RW>::from_register(self,0)
    }

    #[doc = "When \'1\', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is \'1\'. If a quick clear/invalidation is required, the field should be set to \'1\' and be followed by a set to \'0\'. If a clear/invalidation is required for an extended time period, the field should be set to \'1\' during the complete time period."]
    #[inline(always)]
    pub fn clear(
        self,
    ) -> crate::common::RegisterFieldBool<16, 1, 0, RxFifoCtl_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<16,1,0,RxFifoCtl_SPEC,crate::common::RW>::from_register(self,0)
    }

    #[doc = "When \'1\', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer.This field is used only for debugging purposes."]
    #[inline(always)]
    pub fn freeze(
        self,
    ) -> crate::common::RegisterFieldBool<17, 1, 0, RxFifoCtl_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<17,1,0,RxFifoCtl_SPEC,crate::common::RW>::from_register(self,0)
    }
}
impl ::core::default::Default for RxFifoCtl {
    #[inline(always)]
    fn default() -> RxFifoCtl {
        <crate::RegValueT<RxFifoCtl_SPEC> as RegisterValue<_>>::new(0)
    }
}

#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxFifoStatus_SPEC;
impl crate::sealed::RegSpec for RxFifoStatus_SPEC {
    type DataType = u32;
}

#[doc = "RX FIFO status"]
pub type RxFifoStatus = crate::RegValueT<RxFifoStatus_SPEC>;

impl RxFifoStatus {
    #[doc = "Number of entries in the RX FIFO. The field value is in the range \\[0, 255\\]. When this is zero, the RX FIFO is empty."]
    #[inline(always)]
    pub fn used(
        self,
    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, RxFifoStatus_SPEC, crate::common::R>
    {
        crate::common::RegisterField::<0,0xff,1,0,u8,u8,RxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
    }

    #[doc = "RX FIFO read pointer: RX FIFO location from which a data frame is read by the host.This field is used only for debugging purposes."]
    #[inline(always)]
    pub fn rd_ptr(
        self,
    ) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, RxFifoStatus_SPEC, crate::common::R>
    {
        crate::common::RegisterField::<16,0xff,1,0,u8,u8,RxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
    }

    #[doc = "RX FIFO write pointer: RX FIFO location at which a new data frame is written by the hardware.This field is used only for debugging purposes."]
    #[inline(always)]
    pub fn wr_ptr(
        self,
    ) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, RxFifoStatus_SPEC, crate::common::R>
    {
        crate::common::RegisterField::<24,0xff,1,0,u8,u8,RxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
    }
}
impl ::core::default::Default for RxFifoStatus {
    #[inline(always)]
    fn default() -> RxFifoStatus {
        <crate::RegValueT<RxFifoStatus_SPEC> as RegisterValue<_>>::new(0)
    }
}

#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxFifoRd_SPEC;
impl crate::sealed::RegSpec for RxFifoRd_SPEC {
    type DataType = u32;
}

#[doc = "RX FIFO read"]
pub type RxFifoRd = crate::RegValueT<RxFifoRd_SPEC>;

impl RxFifoRd {
    #[doc = "Data read from the RX FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. \nNote: Don\'t access to this bit while RX_FIFO_CTL.CLEAR is \'1\'."]
    #[inline(always)]
    pub fn data(
        self,
    ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, RxFifoRd_SPEC, crate::common::R>
    {
        crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,RxFifoRd_SPEC,crate::common::R>::from_register(self,0)
    }
}
impl ::core::default::Default for RxFifoRd {
    #[inline(always)]
    fn default() -> RxFifoRd {
        <crate::RegValueT<RxFifoRd_SPEC> as RegisterValue<_>>::new(0)
    }
}

#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxFifoRdSilent_SPEC;
impl crate::sealed::RegSpec for RxFifoRdSilent_SPEC {
    type DataType = u32;
}

#[doc = "RX FIFO silent read"]
pub type RxFifoRdSilent = crate::RegValueT<RxFifoRdSilent_SPEC>;

impl RxFifoRdSilent {
    #[doc = "Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes.\nNote: Don\'t access to this bit while RX_FIFO_CTL.CLEAR is \'1\'."]
    #[inline(always)]
    pub fn data(
        self,
    ) -> crate::common::RegisterField<
        0,
        0xffffffff,
        1,
        0,
        u32,
        u32,
        RxFifoRdSilent_SPEC,
        crate::common::R,
    > {
        crate::common::RegisterField::<
            0,
            0xffffffff,
            1,
            0,
            u32,
            u32,
            RxFifoRdSilent_SPEC,
            crate::common::R,
        >::from_register(self, 0)
    }
}
impl ::core::default::Default for RxFifoRdSilent {
    #[inline(always)]
    fn default() -> RxFifoRdSilent {
        <crate::RegValueT<RxFifoRdSilent_SPEC> as RegisterValue<_>>::new(0)
    }
}

#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Intr_SPEC;
impl crate::sealed::RegSpec for Intr_SPEC {
    type DataType = u32;
}

#[doc = "Interrupt register"]
pub type Intr = crate::RegValueT<Intr_SPEC>;

impl Intr {
    #[doc = "More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTL."]
    #[inline(always)]
    pub fn rx_trigger(
        self,
    ) -> crate::common::RegisterFieldBool<16, 1, 0, Intr_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<16, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
            self, 0,
        )
    }

    #[doc = "RX FIFO is not empty."]
    #[inline(always)]
    pub fn rx_not_empty(
        self,
    ) -> crate::common::RegisterFieldBool<18, 1, 0, Intr_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<18, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
            self, 0,
        )
    }

    #[doc = "Attempt to write to a full RX FIFO"]
    #[inline(always)]
    pub fn rx_overflow(
        self,
    ) -> crate::common::RegisterFieldBool<21, 1, 0, Intr_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<21, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
            self, 0,
        )
    }

    #[doc = "Attempt to read from an empty RX FIFO"]
    #[inline(always)]
    pub fn rx_underflow(
        self,
    ) -> crate::common::RegisterFieldBool<22, 1, 0, Intr_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<22, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
            self, 0,
        )
    }
}
impl ::core::default::Default for Intr {
    #[inline(always)]
    fn default() -> Intr {
        <crate::RegValueT<Intr_SPEC> as RegisterValue<_>>::new(0)
    }
}

#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSet_SPEC;
impl crate::sealed::RegSpec for IntrSet_SPEC {
    type DataType = u32;
}

#[doc = "Interrupt set register"]
pub type IntrSet = crate::RegValueT<IntrSet_SPEC>;

impl IntrSet {
    #[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
    #[inline(always)]
    pub fn rx_trigger(
        self,
    ) -> crate::common::RegisterFieldBool<16, 1, 0, IntrSet_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<16, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
            self, 0,
        )
    }

    #[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
    #[inline(always)]
    pub fn rx_not_empty(
        self,
    ) -> crate::common::RegisterFieldBool<18, 1, 0, IntrSet_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<18, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
            self, 0,
        )
    }

    #[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
    #[inline(always)]
    pub fn rx_overflow(
        self,
    ) -> crate::common::RegisterFieldBool<21, 1, 0, IntrSet_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<21, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
            self, 0,
        )
    }

    #[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
    #[inline(always)]
    pub fn rx_underflow(
        self,
    ) -> crate::common::RegisterFieldBool<22, 1, 0, IntrSet_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<22, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
            self, 0,
        )
    }
}
impl ::core::default::Default for IntrSet {
    #[inline(always)]
    fn default() -> IntrSet {
        <crate::RegValueT<IntrSet_SPEC> as RegisterValue<_>>::new(0)
    }
}

#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMask_SPEC;
impl crate::sealed::RegSpec for IntrMask_SPEC {
    type DataType = u32;
}

#[doc = "Interrupt mask register"]
pub type IntrMask = crate::RegValueT<IntrMask_SPEC>;

impl IntrMask {
    #[doc = "Mask bit for corresponding bit in interrupt request register."]
    #[inline(always)]
    pub fn rx_trigger(
        self,
    ) -> crate::common::RegisterFieldBool<16, 1, 0, IntrMask_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<16,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
    }

    #[doc = "Mask bit for corresponding bit in interrupt request register."]
    #[inline(always)]
    pub fn rx_not_empty(
        self,
    ) -> crate::common::RegisterFieldBool<18, 1, 0, IntrMask_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<18,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
    }

    #[doc = "Mask bit for corresponding bit in interrupt request register."]
    #[inline(always)]
    pub fn rx_overflow(
        self,
    ) -> crate::common::RegisterFieldBool<21, 1, 0, IntrMask_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<21,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
    }

    #[doc = "Mask bit for corresponding bit in interrupt request register."]
    #[inline(always)]
    pub fn rx_underflow(
        self,
    ) -> crate::common::RegisterFieldBool<22, 1, 0, IntrMask_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<22,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
    }
}
impl ::core::default::Default for IntrMask {
    #[inline(always)]
    fn default() -> IntrMask {
        <crate::RegValueT<IntrMask_SPEC> as RegisterValue<_>>::new(0)
    }
}

#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMasked_SPEC;
impl crate::sealed::RegSpec for IntrMasked_SPEC {
    type DataType = u32;
}

#[doc = "Interrupt masked register"]
pub type IntrMasked = crate::RegValueT<IntrMasked_SPEC>;

impl IntrMasked {
    #[doc = "Logical and of corresponding request and mask bits."]
    #[inline(always)]
    pub fn rx_trigger(
        self,
    ) -> crate::common::RegisterFieldBool<16, 1, 0, IntrMasked_SPEC, crate::common::R> {
        crate::common::RegisterFieldBool::<16,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
    }

    #[doc = "Logical and of corresponding request and mask bits."]
    #[inline(always)]
    pub fn rx_not_empty(
        self,
    ) -> crate::common::RegisterFieldBool<18, 1, 0, IntrMasked_SPEC, crate::common::R> {
        crate::common::RegisterFieldBool::<18,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
    }

    #[doc = "Logical and of corresponding request and mask bits."]
    #[inline(always)]
    pub fn rx_overflow(
        self,
    ) -> crate::common::RegisterFieldBool<21, 1, 0, IntrMasked_SPEC, crate::common::R> {
        crate::common::RegisterFieldBool::<21,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
    }

    #[doc = "Logical and of corresponding request and mask bits."]
    #[inline(always)]
    pub fn rx_underflow(
        self,
    ) -> crate::common::RegisterFieldBool<22, 1, 0, IntrMasked_SPEC, crate::common::R> {
        crate::common::RegisterFieldBool::<22,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
    }
}
impl ::core::default::Default for IntrMasked {
    #[inline(always)]
    fn default() -> IntrMasked {
        <crate::RegValueT<IntrMasked_SPEC> as RegisterValue<_>>::new(0)
    }
}