/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"SRSS Core Registers"]
unsafe impl ::core::marker::Send for super::Srss {}
unsafe impl ::core::marker::Sync for super::Srss {}
impl super::Srss {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "Power Mode Control"]
#[inline(always)]
pub const fn pwr_ctl(
&self,
) -> &'static crate::common::Reg<self::PwrCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::PwrCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "HIBERNATE Mode Register"]
#[inline(always)]
pub const fn pwr_hibernate(
&self,
) -> &'static crate::common::Reg<self::PwrHibernate_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::PwrHibernate_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "Low Voltage Detector (LVD) Configuration Register"]
#[inline(always)]
pub const fn pwr_lvd_ctl(
&self,
) -> &'static crate::common::Reg<self::PwrLvdCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::PwrLvdCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(8usize),
)
}
}
#[doc = "Buck Control Register"]
#[inline(always)]
pub const fn pwr_buck_ctl(
&self,
) -> &'static crate::common::Reg<self::PwrBuckCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::PwrBuckCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(20usize),
)
}
}
#[doc = "Buck Control Register 2"]
#[inline(always)]
pub const fn pwr_buck_ctl2(
&self,
) -> &'static crate::common::Reg<self::PwrBuckCtl2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::PwrBuckCtl2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(24usize),
)
}
}
#[doc = "Low Voltage Detector (LVD) Status Register"]
#[inline(always)]
pub const fn pwr_lvd_status(
&self,
) -> &'static crate::common::Reg<self::PwrLvdStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::PwrLvdStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(28usize),
)
}
}
#[doc = "HIBERNATE Data Register"]
#[inline(always)]
pub const fn pwr_hib_data(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::PwrHibData_SPEC, crate::common::RW>,
16,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x80usize))
}
}
#[doc = "Watchdog Counter Control Register"]
#[inline(always)]
pub const fn wdt_ctl(
&self,
) -> &'static crate::common::Reg<self::WdtCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::WdtCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(384usize),
)
}
}
#[doc = "Watchdog Counter Count Register"]
#[inline(always)]
pub const fn wdt_cnt(
&self,
) -> &'static crate::common::Reg<self::WdtCnt_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::WdtCnt_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(388usize),
)
}
}
#[doc = "Watchdog Counter Match Register"]
#[inline(always)]
pub const fn wdt_match(
&self,
) -> &'static crate::common::Reg<self::WdtMatch_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::WdtMatch_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(392usize),
)
}
}
#[doc = "Clock DSI Select Register"]
#[inline(always)]
pub const fn clk_dsi_select(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::ClkDsiSelect_SPEC, crate::common::RW>,
16,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x300usize))
}
}
#[doc = "Clock Path Select Register"]
#[inline(always)]
pub const fn clk_path_select(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::ClkPathSelect_SPEC, crate::common::RW>,
16,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x340usize))
}
}
#[doc = "Clock Root Select Register"]
#[inline(always)]
pub const fn clk_root_select(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::ClkRootSelect_SPEC, crate::common::RW>,
16,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x380usize))
}
}
#[doc = "Clock selection register"]
#[inline(always)]
pub const fn clk_select(
&self,
) -> &'static crate::common::Reg<self::ClkSelect_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkSelect_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1280usize),
)
}
}
#[doc = "Timer Clock Control Register"]
#[inline(always)]
pub const fn clk_timer_ctl(
&self,
) -> &'static crate::common::Reg<self::ClkTimerCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkTimerCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1284usize),
)
}
}
#[doc = "ILO Configuration"]
#[inline(always)]
pub const fn clk_ilo_config(
&self,
) -> &'static crate::common::Reg<self::ClkIloConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkIloConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1292usize),
)
}
}
#[doc = "IMO Configuration"]
#[inline(always)]
pub const fn clk_imo_config(
&self,
) -> &'static crate::common::Reg<self::ClkImoConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkImoConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1296usize),
)
}
}
#[doc = "Fast Clock Output Select Register"]
#[inline(always)]
pub const fn clk_output_fast(
&self,
) -> &'static crate::common::Reg<self::ClkOutputFast_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkOutputFast_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1300usize),
)
}
}
#[doc = "Slow Clock Output Select Register"]
#[inline(always)]
pub const fn clk_output_slow(
&self,
) -> &'static crate::common::Reg<self::ClkOutputSlow_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkOutputSlow_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1304usize),
)
}
}
#[doc = "Clock Calibration Counter 1"]
#[inline(always)]
pub const fn clk_cal_cnt1(
&self,
) -> &'static crate::common::Reg<self::ClkCalCnt1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkCalCnt1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1308usize),
)
}
}
#[doc = "Clock Calibration Counter 2"]
#[inline(always)]
pub const fn clk_cal_cnt2(
&self,
) -> &'static crate::common::Reg<self::ClkCalCnt2_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::ClkCalCnt2_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1312usize),
)
}
}
#[doc = "ECO Configuration Register"]
#[inline(always)]
pub const fn clk_eco_config(
&self,
) -> &'static crate::common::Reg<self::ClkEcoConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkEcoConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1324usize),
)
}
}
#[doc = "ECO Status Register"]
#[inline(always)]
pub const fn clk_eco_status(
&self,
) -> &'static crate::common::Reg<self::ClkEcoStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::ClkEcoStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1328usize),
)
}
}
#[doc = "Precision ILO Configuration Register"]
#[inline(always)]
pub const fn clk_pilo_config(
&self,
) -> &'static crate::common::Reg<self::ClkPiloConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkPiloConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1340usize),
)
}
}
#[doc = "FLL Configuration Register"]
#[inline(always)]
pub const fn clk_fll_config(
&self,
) -> &'static crate::common::Reg<self::ClkFllConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkFllConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1408usize),
)
}
}
#[doc = "FLL Configuration Register 2"]
#[inline(always)]
pub const fn clk_fll_config2(
&self,
) -> &'static crate::common::Reg<self::ClkFllConfig2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkFllConfig2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1412usize),
)
}
}
#[doc = "FLL Configuration Register 3"]
#[inline(always)]
pub const fn clk_fll_config3(
&self,
) -> &'static crate::common::Reg<self::ClkFllConfig3_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkFllConfig3_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1416usize),
)
}
}
#[doc = "FLL Configuration Register 4"]
#[inline(always)]
pub const fn clk_fll_config4(
&self,
) -> &'static crate::common::Reg<self::ClkFllConfig4_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkFllConfig4_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1420usize),
)
}
}
#[doc = "FLL Status Register"]
#[inline(always)]
pub const fn clk_fll_status(
&self,
) -> &'static crate::common::Reg<self::ClkFllStatus_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkFllStatus_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1424usize),
)
}
}
#[doc = "PLL Configuration Register"]
#[inline(always)]
pub const fn clk_pll_config(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::ClkPllConfig_SPEC, crate::common::RW>,
15,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x600usize))
}
}
#[doc = "PLL Status Register"]
#[inline(always)]
pub const fn clk_pll_status(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::ClkPllStatus_SPEC, crate::common::RW>,
15,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x640usize))
}
}
#[doc = "SRSS Interrupt Register"]
#[inline(always)]
pub const fn srss_intr(
&self,
) -> &'static crate::common::Reg<self::SrssIntr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SrssIntr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1792usize),
)
}
}
#[doc = "SRSS Interrupt Set Register"]
#[inline(always)]
pub const fn srss_intr_set(
&self,
) -> &'static crate::common::Reg<self::SrssIntrSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SrssIntrSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1796usize),
)
}
}
#[doc = "SRSS Interrupt Mask Register"]
#[inline(always)]
pub const fn srss_intr_mask(
&self,
) -> &'static crate::common::Reg<self::SrssIntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SrssIntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1800usize),
)
}
}
#[doc = "SRSS Interrupt Masked Register"]
#[inline(always)]
pub const fn srss_intr_masked(
&self,
) -> &'static crate::common::Reg<self::SrssIntrMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::SrssIntrMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1804usize),
)
}
}
#[doc = "SRSS Interrupt Configuration Register"]
#[inline(always)]
pub const fn srss_intr_cfg(
&self,
) -> &'static crate::common::Reg<self::SrssIntrCfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SrssIntrCfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1808usize),
)
}
}
#[doc = "Reset Cause Observation Register"]
#[inline(always)]
pub const fn res_cause(
&self,
) -> &'static crate::common::Reg<self::ResCause_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ResCause_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2048usize),
)
}
}
#[doc = "Reset Cause Observation Register 2"]
#[inline(always)]
pub const fn res_cause2(
&self,
) -> &'static crate::common::Reg<self::ResCause2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ResCause2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2052usize),
)
}
}
#[doc = "Reference Trim Register"]
#[inline(always)]
pub const fn pwr_trim_ref_ctl(
&self,
) -> &'static crate::common::Reg<self::PwrTrimRefCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::PwrTrimRefCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32512usize),
)
}
}
#[doc = "BOD/OVP Trim Register"]
#[inline(always)]
pub const fn pwr_trim_bodovp_ctl(
&self,
) -> &'static crate::common::Reg<self::PwrTrimBodovpCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::PwrTrimBodovpCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32516usize),
)
}
}
#[doc = "CCO Trim Register"]
#[inline(always)]
pub const fn clk_trim_cco_ctl(
&self,
) -> &'static crate::common::Reg<self::ClkTrimCcoCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkTrimCcoCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32520usize),
)
}
}
#[doc = "CCO Trim Register 2"]
#[inline(always)]
pub const fn clk_trim_cco_ctl2(
&self,
) -> &'static crate::common::Reg<self::ClkTrimCcoCtl2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkTrimCcoCtl2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32524usize),
)
}
}
#[doc = "Wakeup Trim Register"]
#[inline(always)]
pub const fn pwr_trim_wake_ctl(
&self,
) -> &'static crate::common::Reg<self::PwrTrimWakeCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::PwrTrimWakeCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32560usize),
)
}
}
#[doc = "LVD Trim Register"]
#[inline(always)]
pub const fn pwr_trim_lvd_ctl(
&self,
) -> &'static crate::common::Reg<self::PwrTrimLvdCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::PwrTrimLvdCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(65296usize),
)
}
}
#[doc = "ILO Trim Register"]
#[inline(always)]
pub const fn clk_trim_ilo_ctl(
&self,
) -> &'static crate::common::Reg<self::ClkTrimIloCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkTrimIloCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(65304usize),
)
}
}
#[doc = "Power System Trim Register"]
#[inline(always)]
pub const fn pwr_trim_pwrsys_ctl(
&self,
) -> &'static crate::common::Reg<self::PwrTrimPwrsysCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::PwrTrimPwrsysCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(65308usize),
)
}
}
#[doc = "ECO Trim Register"]
#[inline(always)]
pub const fn clk_trim_eco_ctl(
&self,
) -> &'static crate::common::Reg<self::ClkTrimEcoCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkTrimEcoCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(65312usize),
)
}
}
#[doc = "PILO Trim Register"]
#[inline(always)]
pub const fn clk_trim_pilo_ctl(
&self,
) -> &'static crate::common::Reg<self::ClkTrimPiloCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkTrimPiloCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(65316usize),
)
}
}
#[doc = "PILO Trim Register 2"]
#[inline(always)]
pub const fn clk_trim_pilo_ctl2(
&self,
) -> &'static crate::common::Reg<self::ClkTrimPiloCtl2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkTrimPiloCtl2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(65320usize),
)
}
}
#[doc = "PILO Trim Register 3"]
#[inline(always)]
pub const fn clk_trim_pilo_ctl3(
&self,
) -> &'static crate::common::Reg<self::ClkTrimPiloCtl3_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClkTrimPiloCtl3_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(65324usize),
)
}
}
#[doc = "Multi-Counter Watchdog Timer"]
#[inline(always)]
pub fn mcwdt_struct(
self,
) -> &'static crate::common::ClusterRegisterArray<crate::srss::_McwdtStruct, 2, 0x40> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x200usize))
}
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PwrCtl_SPEC;
impl crate::sealed::RegSpec for PwrCtl_SPEC {
type DataType = u32;
}
#[doc = "Power Mode Control"]
pub type PwrCtl = crate::RegValueT<PwrCtl_SPEC>;
impl PwrCtl {
#[doc = "Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon."]
#[inline(always)]
pub fn power_mode(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
pwr_ctl::PowerMode,
pwr_ctl::PowerMode,
PwrCtl_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
pwr_ctl::PowerMode,
pwr_ctl::PowerMode,
PwrCtl_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)"]
#[inline(always)]
pub fn debug_session(
self,
) -> crate::common::RegisterField<
4,
0x1,
1,
0,
pwr_ctl::DebugSession,
pwr_ctl::DebugSession,
PwrCtl_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
4,
0x1,
1,
0,
pwr_ctl::DebugSession,
pwr_ctl::DebugSession,
PwrCtl_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES/POR/BOD/HIBERNATE wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register is only reset by XRES/POR/BOD/HIBERNATE.\n0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode.\n1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers."]
#[inline(always)]
pub fn lpm_ready(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, PwrCtl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5, 1, 0, PwrCtl_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE.\n0: Current reference generator operates in normal mode. It works for vddd ramp rates of 100mV/us or less.\n1: Current reference generator operates in low power mode. Response time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less."]
#[inline(always)]
pub fn iref_lpmode(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, PwrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18, 1, 0, PwrCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1."]
#[inline(always)]
pub fn vrefbuf_ok(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, PwrCtl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<19, 1, 0, PwrCtl_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Disable the DeepSleep regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE.\n0: DeepSleep Regulator is on.\n1: DeepSleep Regulator is off."]
#[inline(always)]
pub fn dpslp_reg_dis(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, PwrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20, 1, 0, PwrCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Disable the Retention regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE.\n0: Retention Regulator is on.\n1: Retention Regulator is off."]
#[inline(always)]
pub fn ret_reg_dis(
self,
) -> crate::common::RegisterFieldBool<21, 1, 0, PwrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<21, 1, 0, PwrCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Disable the Nwell regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE.\n0: Nwell Regulator is on.\n1: Nwell Regulator is off."]
#[inline(always)]
pub fn nwell_reg_dis(
self,
) -> crate::common::RegisterFieldBool<22, 1, 0, PwrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<22, 1, 0, PwrCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Disable the linear Core Regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE.\n0: Linear regulator is on.\n1: Linear regulator is off."]
#[inline(always)]
pub fn linreg_dis(
self,
) -> crate::common::RegisterFieldBool<23, 1, 0, PwrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<23, 1, 0, PwrCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE.\n0: Linear Regulator operates in normal mode. Internal current consumption is 50uA and load current capability is 50mA to 300mA, depending on the number of regulator modules present in the product.\n1: Linear Regulator operates in low power mode. Internal current consumption is 5uA and load current capability is 25mA. Firmware must ensure the current is kept within the limit."]
#[inline(always)]
pub fn linreg_lpmode(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, PwrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24, 1, 0, PwrCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE.\n0: POR/BOD circuits operate in normal mode. They work for vddd ramp rates of 100mV/us or less.\n1: POR/BOD circuits operate in low power mode. Response time is reduced to save current, and they work for vddd ramp rates of 10mV/us or less."]
#[inline(always)]
pub fn porbod_lpmode(
self,
) -> crate::common::RegisterFieldBool<25, 1, 0, PwrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<25, 1, 0, PwrCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Control the power mode of the Bandgap Voltage and Current References. This applies to voltage and current generation and is different than the reference voltage buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. When lower power mode is used, the Active Reference circuit can be disabled to reduce current. Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode. This register is only reset by XRES/POR/BOD/HIBERNATE.\n0: Active Bandgap Voltage and Current Reference operates in normal mode. They work for vddd ramp rates of 100mV/us or less.\n1: Active Bandgap Voltage and Current Reference operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. The Active Reference may be disabled using ACT_REF_DIS=0."]
#[inline(always)]
pub fn bgref_lpmode(
self,
) -> crate::common::RegisterFieldBool<26, 1, 0, PwrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<26, 1, 0, PwrCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Bypass level shifter inside the PLL. \n0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage.\n1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current."]
#[inline(always)]
pub fn pll_ls_bypass(
self,
) -> crate::common::RegisterFieldBool<27, 1, 0, PwrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<27, 1, 0, PwrCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1.\n0: Voltage Reference Buffer operates in normal mode. They work for vddd ramp rates of 100mV/us or less. This register is only reset by XRES/POR/BOD/HIBERNATE.\n1: Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less."]
#[inline(always)]
pub fn vrefbuf_lpmode(
self,
) -> crate::common::RegisterFieldBool<28, 1, 0, PwrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<28, 1, 0, PwrCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Disable the 800mV voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES/POR/BOD/HIBERNATE."]
#[inline(always)]
pub fn vrefbuf_dis(
self,
) -> crate::common::RegisterFieldBool<29, 1, 0, PwrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<29, 1, 0, PwrCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference. When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready. This register is only reset by XRES/POR/BOD/HIBERNATE.\n0: Active Reference is enabled\n1: Active Reference is disabled"]
#[inline(always)]
pub fn act_ref_dis(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, PwrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30, 1, 0, PwrCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Indicates that the normal mode of the Active Reference is ready."]
#[inline(always)]
pub fn act_ref_ok(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, PwrCtl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31, 1, 0, PwrCtl_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for PwrCtl {
#[inline(always)]
fn default() -> PwrCtl {
<crate::RegValueT<PwrCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod pwr_ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PowerMode_SPEC;
pub type PowerMode = crate::EnumBitfieldStruct<u8, PowerMode_SPEC>;
impl PowerMode {
#[doc = "System is resetting."]
pub const RESET: Self = Self::new(0);
#[doc = "At least one CPU is running."]
pub const ACTIVE: Self = Self::new(1);
#[doc = "No CPUs are running. Peripherals may be running."]
pub const SLEEP: Self = Self::new(2);
#[doc = "Main high-frequency clock is off; low speed clocks are available. Communication interface clocks may be present."]
pub const DEEPSLEEP: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DebugSession_SPEC;
pub type DebugSession = crate::EnumBitfieldStruct<u8, DebugSession_SPEC>;
impl DebugSession {
#[doc = "No debug session active"]
pub const NO_SESSION: Self = Self::new(0);
#[doc = "Debug session is active. Power modes behave differently to keep the debug session active."]
pub const SESSION_ACTIVE: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PwrHibernate_SPEC;
impl crate::sealed::RegSpec for PwrHibernate_SPEC {
type DataType = u32;
}
#[doc = "HIBERNATE Mode Register"]
pub type PwrHibernate = crate::RegValueT<PwrHibernate_SPEC>;
impl PwrHibernate {
#[doc = "Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register."]
#[inline(always)]
pub fn token(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, PwrHibernate_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,PwrHibernate_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description."]
#[inline(always)]
pub fn unlock(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, PwrHibernate_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,PwrHibernate_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Firmware sets this bit to freeze the configuration, mode and state of all GPIOs and SIOs in the system. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write."]
#[inline(always)]
pub fn freeze(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, PwrHibernate_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,PwrHibernate_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When set, HIBERNATE will wakeup for a RTC interrupt"]
#[inline(always)]
pub fn mask_hibalarm(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, PwrHibernate_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,PwrHibernate_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When set, HIBERNATE will wakeup if WDT matches"]
#[inline(always)]
pub fn mask_hibwdt(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, PwrHibernate_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,PwrHibernate_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Each bit sets the active polarity of the corresponding wakeup pin.\n0: Pin input of 0 will wakeup the part from HIBERNATE\n1: Pin input of 1 will wakeup the part from HIBERNATE"]
#[inline(always)]
pub fn polarity_hibpin(
self,
) -> crate::common::RegisterField<20, 0xf, 1, 0, u8, u8, PwrHibernate_SPEC, crate::common::RW>
{
crate::common::RegisterField::<20,0xf,1,0,u8,u8,PwrHibernate_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the wakeup pins."]
#[inline(always)]
pub fn mask_hibpin(
self,
) -> crate::common::RegisterField<24, 0xf, 1, 0, u8, u8, PwrHibernate_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0xf,1,0,u8,u8,PwrHibernate_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Hibernate disable bit.\n0: Normal operation, HIBERNATE works as described\n1: Further writes to this register are ignored\nNote: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written.."]
#[inline(always)]
pub fn hibernate_disable(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, PwrHibernate_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,PwrHibernate_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode."]
#[inline(always)]
pub fn hibernate(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, PwrHibernate_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,PwrHibernate_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for PwrHibernate {
#[inline(always)]
fn default() -> PwrHibernate {
<crate::RegValueT<PwrHibernate_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PwrLvdCtl_SPEC;
impl crate::sealed::RegSpec for PwrLvdCtl_SPEC {
type DataType = u32;
}
#[doc = "Low Voltage Detector (LVD) Configuration Register"]
pub type PwrLvdCtl = crate::RegValueT<PwrLvdCtl_SPEC>;
impl PwrLvdCtl {
#[doc = "Threshold selection for HVLVD1. Disable the LVD (HVLVD1_EN=0) before changing the threshold.\n0: rise=1.225V (nom), fall=1.2V (nom)\n1: rise=1.425V (nom), fall=1.4V (nom)\n2: rise=1.625V (nom), fall=1.6V (nom)\n3: rise=1.825V (nom), fall=1.8V (nom)\n4: rise=2.025V (nom), fall=2V (nom)\n5: rise=2.125V (nom), fall=2.1V (nom)\n6: rise=2.225V (nom), fall=2.2V (nom)\n7: rise=2.325V (nom), fall=2.3V (nom)\n8: rise=2.425V (nom), fall=2.4V (nom)\n9: rise=2.525V (nom), fall=2.5V (nom)\n10: rise=2.625V (nom), fall=2.6V (nom)\n11: rise=2.725V (nom), fall=2.7V (nom)\n12: rise=2.825V (nom), fall=2.8V (nom)\n13: rise=2.925V (nom), fall=2.9V (nom)\n14: rise=3.025V (nom), fall=3.0V (nom)\n15: rise=3.125V (nom), fall=3.1V (nom)"]
#[inline(always)]
pub fn hvlvd1_tripsel(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, PwrLvdCtl_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0xf,1,0,u8,u8,PwrLvdCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Source selection for HVLVD1"]
#[inline(always)]
pub fn hvlvd1_srcsel(
self,
) -> crate::common::RegisterField<
4,
0x7,
1,
0,
pwr_lvd_ctl::Hvlvd1Srcsel,
pwr_lvd_ctl::Hvlvd1Srcsel,
PwrLvdCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x7,
1,
0,
pwr_lvd_ctl::Hvlvd1Srcsel,
pwr_lvd_ctl::Hvlvd1Srcsel,
PwrLvdCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Enable HVLVD1 voltage monitor. When the LVD is enabled, it takes 20us for it to settle. There is no hardware stabilization counter, and it may falsely trigger during settling. It is recommended that firmware keep the interrupt masked for at least 8us, write a 1\'b1 to the corresponding SRSS_INTR field to any falsely pended interrupt, and then optionally unmask the interrupt. After enabling, it is further recommended to read the related PWR_LVD_STATUS field, since the interrupt only triggers on edges. This bit is cleared (LVD is disabled) when entering DEEPSLEEP to prevent false interrupts during wakeup."]
#[inline(always)]
pub fn hvlvd1_en(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, PwrLvdCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,PwrLvdCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for PwrLvdCtl {
#[inline(always)]
fn default() -> PwrLvdCtl {
<crate::RegValueT<PwrLvdCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod pwr_lvd_ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Hvlvd1Srcsel_SPEC;
pub type Hvlvd1Srcsel = crate::EnumBitfieldStruct<u8, Hvlvd1Srcsel_SPEC>;
impl Hvlvd1Srcsel {
#[doc = "Select VDDD"]
pub const VDDD: Self = Self::new(0);
#[doc = "Select AMUXBUSA (VDDD branch)"]
pub const AMUXBUSA: Self = Self::new(1);
#[doc = "N/A"]
pub const RSVD: Self = Self::new(2);
#[doc = "N/A"]
pub const VDDIO: Self = Self::new(3);
#[doc = "Select AMUXBUSB (VDDD branch)"]
pub const AMUXBUSB: Self = Self::new(4);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PwrBuckCtl_SPEC;
impl crate::sealed::RegSpec for PwrBuckCtl_SPEC {
type DataType = u32;
}
#[doc = "Buck Control Register"]
pub type PwrBuckCtl = crate::RegValueT<PwrBuckCtl_SPEC>;
impl PwrBuckCtl {
#[doc = "N/A"]
#[inline(always)]
pub fn buck_out1_sel(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, PwrBuckCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,PwrBuckCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn buck_en(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, PwrBuckCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,PwrBuckCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES/POR/BOD/HIBERNATE. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1."]
#[inline(always)]
pub fn buck_out1_en(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, PwrBuckCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,PwrBuckCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for PwrBuckCtl {
#[inline(always)]
fn default() -> PwrBuckCtl {
<crate::RegValueT<PwrBuckCtl_SPEC> as RegisterValue<_>>::new(5)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PwrBuckCtl2_SPEC;
impl crate::sealed::RegSpec for PwrBuckCtl2_SPEC {
type DataType = u32;
}
#[doc = "Buck Control Register 2"]
pub type PwrBuckCtl2 = crate::RegValueT<PwrBuckCtl2_SPEC>;
impl PwrBuckCtl2 {
#[doc = "Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current.\n0: 1.15V\n1: 1.20V\n2: 1.25V\n3: 1.30V\n4: 1.35V\n5: 1.40V\n6: 1.45V\n7: 1.50V"]
#[inline(always)]
pub fn buck_out2_sel(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, PwrBuckCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,PwrBuckCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware, it can directly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN applies."]
#[inline(always)]
pub fn buck_out2_hw_sel(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, PwrBuckCtl2_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,PwrBuckCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time."]
#[inline(always)]
pub fn buck_out2_en(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, PwrBuckCtl2_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,PwrBuckCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for PwrBuckCtl2 {
#[inline(always)]
fn default() -> PwrBuckCtl2 {
<crate::RegValueT<PwrBuckCtl2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PwrLvdStatus_SPEC;
impl crate::sealed::RegSpec for PwrLvdStatus_SPEC {
type DataType = u32;
}
#[doc = "Low Voltage Detector (LVD) Status Register"]
pub type PwrLvdStatus = crate::RegValueT<PwrLvdStatus_SPEC>;
impl PwrLvdStatus {
#[doc = "HVLVD1 output.\n0: below voltage threshold\n1: above voltage threshold"]
#[inline(always)]
pub fn hvlvd1_ok(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, PwrLvdStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,PwrLvdStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for PwrLvdStatus {
#[inline(always)]
fn default() -> PwrLvdStatus {
<crate::RegValueT<PwrLvdStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PwrHibData_SPEC;
impl crate::sealed::RegSpec for PwrHibData_SPEC {
type DataType = u32;
}
#[doc = "HIBERNATE Data Register"]
pub type PwrHibData = crate::RegValueT<PwrHibData_SPEC>;
impl PwrHibData {
#[doc = "Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register."]
#[inline(always)]
pub fn hib_data(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
PwrHibData_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
PwrHibData_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PwrHibData {
#[inline(always)]
fn default() -> PwrHibData {
<crate::RegValueT<PwrHibData_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WdtCtl_SPEC;
impl crate::sealed::RegSpec for WdtCtl_SPEC {
type DataType = u32;
}
#[doc = "Watchdog Counter Control Register"]
pub type WdtCtl = crate::RegValueT<WdtCtl_SPEC>;
impl WdtCtl {
#[doc = "Enable this watchdog timer. This field is retained during Deep Sleep and Hibernate modes. Even though the default value is 1, in most cases the Cortex-M0+ executing the SROM code will change the value of this bit to 0. So effectively the user code starts with the WDT disabled."]
#[inline(always)]
pub fn wdt_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, WdtCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, WdtCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0. Requires at least two different writes to unlock. A change in WDT_LOCK takes effect beginning with the next write cycle.\nNote that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all those registers at the same time. WDT will lock on any reset. This field is not retained during Deep Sleep or Hibernate mode, so the WDT will be locked after wakeup from these modes."]
#[inline(always)]
pub fn wdt_lock(
self,
) -> crate::common::RegisterField<
30,
0x3,
1,
0,
wdt_ctl::WdtLock,
wdt_ctl::WdtLock,
WdtCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
30,
0x3,
1,
0,
wdt_ctl::WdtLock,
wdt_ctl::WdtLock,
WdtCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for WdtCtl {
#[inline(always)]
fn default() -> WdtCtl {
<crate::RegValueT<WdtCtl_SPEC> as RegisterValue<_>>::new(3221225473)
}
}
pub mod wdt_ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct WdtLock_SPEC;
pub type WdtLock = crate::EnumBitfieldStruct<u8, WdtLock_SPEC>;
impl WdtLock {
#[doc = "No effect"]
pub const NO_CHG: Self = Self::new(0);
#[doc = "Clears bit 0"]
pub const CLR_0: Self = Self::new(1);
#[doc = "Clears bit 1"]
pub const CLR_1: Self = Self::new(2);
#[doc = "Sets both bits 0 and 1"]
pub const SET_01: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WdtCnt_SPEC;
impl crate::sealed::RegSpec for WdtCnt_SPEC {
type DataType = u32;
}
#[doc = "Watchdog Counter Count Register"]
pub type WdtCnt = crate::RegValueT<WdtCnt_SPEC>;
impl WdtCnt {
#[doc = "Current value of WDT Counter. The write feature of this register is for verification purposes, has no synchronization, and can only be applied when the WDT is off. When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negative edge of ILO. Writes will be ignored if they occur when the WDT is enabled."]
#[inline(always)]
pub fn counter(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, WdtCnt_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,WdtCnt_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for WdtCnt {
#[inline(always)]
fn default() -> WdtCnt {
<crate::RegValueT<WdtCnt_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WdtMatch_SPEC;
impl crate::sealed::RegSpec for WdtMatch_SPEC {
type DataType = u32;
}
#[doc = "Watchdog Counter Match Register"]
pub type WdtMatch = crate::RegValueT<WdtMatch_SPEC>;
impl WdtMatch {
#[doc = "Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match)."]
#[inline(always)]
pub fn r#match(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, WdtMatch_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,WdtMatch_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Up to 12 MSB can be ignored. Settings >12 behave like a setting of 12."]
#[inline(always)]
pub fn ignore_bits(
self,
) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, WdtMatch_SPEC, crate::common::RW> {
crate::common::RegisterField::<16,0xf,1,0,u8,u8,WdtMatch_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for WdtMatch {
#[inline(always)]
fn default() -> WdtMatch {
<crate::RegValueT<WdtMatch_SPEC> as RegisterValue<_>>::new(4096)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkDsiSelect_SPEC;
impl crate::sealed::RegSpec for ClkDsiSelect_SPEC {
type DataType = u32;
}
#[doc = "Clock DSI Select Register"]
pub type ClkDsiSelect = crate::RegValueT<ClkDsiSelect_SPEC>;
impl ClkDsiSelect {
#[doc = "Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock."]
#[inline(always)]
pub fn dsi_mux(
self,
) -> crate::common::RegisterField<
0,
0x1f,
1,
0,
clk_dsi_select::DsiMux,
clk_dsi_select::DsiMux,
ClkDsiSelect_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1f,
1,
0,
clk_dsi_select::DsiMux,
clk_dsi_select::DsiMux,
ClkDsiSelect_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ClkDsiSelect {
#[inline(always)]
fn default() -> ClkDsiSelect {
<crate::RegValueT<ClkDsiSelect_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod clk_dsi_select {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DsiMux_SPEC;
pub type DsiMux = crate::EnumBitfieldStruct<u8, DsiMux_SPEC>;
impl DsiMux {
#[doc = "DSI0 - dsi_out\\[0\\]"]
pub const DSI_OUT_0: Self = Self::new(0);
#[doc = "DSI1 - dsi_out\\[1\\]"]
pub const DSI_OUT_1: Self = Self::new(1);
#[doc = "DSI2 - dsi_out\\[2\\]"]
pub const DSI_OUT_2: Self = Self::new(2);
#[doc = "DSI3 - dsi_out\\[3\\]"]
pub const DSI_OUT_3: Self = Self::new(3);
#[doc = "DSI4 - dsi_out\\[4\\]"]
pub const DSI_OUT_4: Self = Self::new(4);
#[doc = "DSI5 - dsi_out\\[5\\]"]
pub const DSI_OUT_5: Self = Self::new(5);
#[doc = "DSI6 - dsi_out\\[6\\]"]
pub const DSI_OUT_6: Self = Self::new(6);
#[doc = "DSI7 - dsi_out\\[7\\]"]
pub const DSI_OUT_7: Self = Self::new(7);
#[doc = "DSI8 - dsi_out\\[8\\]"]
pub const DSI_OUT_8: Self = Self::new(8);
#[doc = "DSI9 - dsi_out\\[9\\]"]
pub const DSI_OUT_9: Self = Self::new(9);
#[doc = "DSI10 - dsi_out\\[10\\]"]
pub const DSI_OUT_10: Self = Self::new(10);
#[doc = "DSI11 - dsi_out\\[11\\]"]
pub const DSI_OUT_11: Self = Self::new(11);
#[doc = "DSI12 - dsi_out\\[12\\]"]
pub const DSI_OUT_12: Self = Self::new(12);
#[doc = "DSI13 - dsi_out\\[13\\]"]
pub const DSI_OUT_13: Self = Self::new(13);
#[doc = "DSI14 - dsi_out\\[14\\]"]
pub const DSI_OUT_14: Self = Self::new(14);
#[doc = "DSI15 - dsi_out\\[15\\]"]
pub const DSI_OUT_15: Self = Self::new(15);
#[doc = "ILO - Internal Low-speed Oscillator"]
pub const ILO: Self = Self::new(16);
#[doc = "WCO - Watch-Crystal Oscillator"]
pub const WCO: Self = Self::new(17);
#[doc = "ALTLF - Alternate Low-Frequency Clock"]
pub const ALTLF: Self = Self::new(18);
#[doc = "PILO - Precision Internal Low-speed Oscillator"]
pub const PILO: Self = Self::new(19);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkPathSelect_SPEC;
impl crate::sealed::RegSpec for ClkPathSelect_SPEC {
type DataType = u32;
}
#[doc = "Clock Path Select Register"]
pub type ClkPathSelect = crate::RegValueT<ClkPathSelect_SPEC>;
impl ClkPathSelect {
#[doc = "Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior."]
#[inline(always)]
pub fn path_mux(
self,
) -> crate::common::RegisterField<
0,
0x7,
1,
0,
clk_path_select::PathMux,
clk_path_select::PathMux,
ClkPathSelect_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x7,
1,
0,
clk_path_select::PathMux,
clk_path_select::PathMux,
ClkPathSelect_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ClkPathSelect {
#[inline(always)]
fn default() -> ClkPathSelect {
<crate::RegValueT<ClkPathSelect_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod clk_path_select {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PathMux_SPEC;
pub type PathMux = crate::EnumBitfieldStruct<u8, PathMux_SPEC>;
impl PathMux {
#[doc = "IMO - Internal R/C Oscillator"]
pub const IMO: Self = Self::new(0);
#[doc = "EXTCLK - External Clock Pin"]
pub const EXTCLK: Self = Self::new(1);
#[doc = "ECO - External-Crystal Oscillator"]
pub const ECO: Self = Self::new(2);
#[doc = "ALTHF - Alternate High-Frequency clock input (product-specific clock)"]
pub const ALTHF: Self = Self::new(3);
#[doc = "DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior."]
pub const DSI_MUX: Self = Self::new(4);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkRootSelect_SPEC;
impl crate::sealed::RegSpec for ClkRootSelect_SPEC {
type DataType = u32;
}
#[doc = "Clock Root Select Register"]
pub type ClkRootSelect = crate::RegValueT<ClkRootSelect_SPEC>;
impl ClkRootSelect {
#[doc = "Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_PATH_SELECT\\[i\\] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG\\[k\\] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior."]
#[inline(always)]
pub fn root_mux(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
clk_root_select::RootMux,
clk_root_select::RootMux,
ClkRootSelect_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
clk_root_select::RootMux,
clk_root_select::RootMux,
ClkRootSelect_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Selects predivider value for this clock root and DSI input."]
#[inline(always)]
pub fn root_div(
self,
) -> crate::common::RegisterField<
4,
0x3,
1,
0,
clk_root_select::RootDiv,
clk_root_select::RootDiv,
ClkRootSelect_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x3,
1,
0,
clk_root_select::RootDiv,
clk_root_select::RootDiv,
ClkRootSelect_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled."]
#[inline(always)]
pub fn enable(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ClkRootSelect_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,ClkRootSelect_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkRootSelect {
#[inline(always)]
fn default() -> ClkRootSelect {
<crate::RegValueT<ClkRootSelect_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod clk_root_select {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct RootMux_SPEC;
pub type RootMux = crate::EnumBitfieldStruct<u8, RootMux_SPEC>;
impl RootMux {
#[doc = "Select PATH0 (can be configured for FLL)"]
pub const PATH_0: Self = Self::new(0);
#[doc = "Select PATH1 (can be configured for PLL0, if available in the product)"]
pub const PATH_1: Self = Self::new(1);
#[doc = "Select PATH2 (can be configured for PLL1, if available in the product)"]
pub const PATH_2: Self = Self::new(2);
#[doc = "Select PATH3 (can be configured for PLL2, if available in the product)"]
pub const PATH_3: Self = Self::new(3);
#[doc = "Select PATH4 (can be configured for PLL3, if available in the product)"]
pub const PATH_4: Self = Self::new(4);
#[doc = "Select PATH5 (can be configured for PLL4, if available in the product)"]
pub const PATH_5: Self = Self::new(5);
#[doc = "Select PATH6 (can be configured for PLL5, if available in the product)"]
pub const PATH_6: Self = Self::new(6);
#[doc = "Select PATH7 (can be configured for PLL6, if available in the product)"]
pub const PATH_7: Self = Self::new(7);
#[doc = "Select PATH8 (can be configured for PLL7, if available in the product)"]
pub const PATH_8: Self = Self::new(8);
#[doc = "Select PATH9 (can be configured for PLL8, if available in the product)"]
pub const PATH_9: Self = Self::new(9);
#[doc = "Select PATH10 (can be configured for PLL9, if available in the product)"]
pub const PATH_10: Self = Self::new(10);
#[doc = "Select PATH11 (can be configured for PLL10, if available in the product)"]
pub const PATH_11: Self = Self::new(11);
#[doc = "Select PATH12 (can be configured for PLL11, if available in the product)"]
pub const PATH_12: Self = Self::new(12);
#[doc = "Select PATH13 (can be configured for PLL12, if available in the product)"]
pub const PATH_13: Self = Self::new(13);
#[doc = "Select PATH14 (can be configured for PLL13, if available in the product)"]
pub const PATH_14: Self = Self::new(14);
#[doc = "Select PATH15 (can be configured for PLL14, if available in the product)"]
pub const PATH_15: Self = Self::new(15);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct RootDiv_SPEC;
pub type RootDiv = crate::EnumBitfieldStruct<u8, RootDiv_SPEC>;
impl RootDiv {
#[doc = "Transparent mode, feed through selected clock source w/o dividing."]
pub const NO_DIV: Self = Self::new(0);
#[doc = "Divide selected clock source by 2"]
pub const DIV_BY_2: Self = Self::new(1);
#[doc = "Divide selected clock source by 4"]
pub const DIV_BY_4: Self = Self::new(2);
#[doc = "Divide selected clock source by 8"]
pub const DIV_BY_8: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkSelect_SPEC;
impl crate::sealed::RegSpec for ClkSelect_SPEC {
type DataType = u32;
}
#[doc = "Clock selection register"]
pub type ClkSelect = crate::RegValueT<ClkSelect_SPEC>;
impl ClkSelect {
#[doc = "Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register."]
#[inline(always)]
pub fn lfclk_sel(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
clk_select::LfclkSel,
clk_select::LfclkSel,
ClkSelect_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
clk_select::LfclkSel,
clk_select::LfclkSel,
ClkSelect_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Selects clock PATH<k>, where k=PUMP_SEL. The output of this mux goes to the PUMP_DIV to make PUMPCLK Each product has a specific number of available clock paths. Selecting a path that is not implemented on a product will result in undefined behavior. Note that this is not a glitch free mux."]
#[inline(always)]
pub fn pump_sel(
self,
) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, ClkSelect_SPEC, crate::common::RW> {
crate::common::RegisterField::<8,0xf,1,0,u8,u8,ClkSelect_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source."]
#[inline(always)]
pub fn pump_div(
self,
) -> crate::common::RegisterField<
12,
0x7,
1,
0,
clk_select::PumpDiv,
clk_select::PumpDiv,
ClkSelect_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
12,
0x7,
1,
0,
clk_select::PumpDiv,
clk_select::PumpDiv,
ClkSelect_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings, do the following: \n1) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV. \n2) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0. \n3) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV."]
#[inline(always)]
pub fn pump_enable(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, ClkSelect_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<15,1,0,ClkSelect_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkSelect {
#[inline(always)]
fn default() -> ClkSelect {
<crate::RegValueT<ClkSelect_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod clk_select {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct LfclkSel_SPEC;
pub type LfclkSel = crate::EnumBitfieldStruct<u8, LfclkSel_SPEC>;
impl LfclkSel {
#[doc = "ILO - Internal Low-speed Oscillator"]
pub const ILO: Self = Self::new(0);
#[doc = "WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used)."]
pub const WCO: Self = Self::new(1);
#[doc = "ALTLF - Alternate Low-Frequency Clock. Capability is product-specific"]
pub const ALTLF: Self = Self::new(2);
#[doc = "PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode."]
pub const PILO: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PumpDiv_SPEC;
pub type PumpDiv = crate::EnumBitfieldStruct<u8, PumpDiv_SPEC>;
impl PumpDiv {
#[doc = "Transparent mode, feed through selected clock source w/o dividing."]
pub const NO_DIV: Self = Self::new(0);
#[doc = "Divide selected clock source by 2"]
pub const DIV_BY_2: Self = Self::new(1);
#[doc = "Divide selected clock source by 4"]
pub const DIV_BY_4: Self = Self::new(2);
#[doc = "Divide selected clock source by 8"]
pub const DIV_BY_8: Self = Self::new(3);
#[doc = "Divide selected clock source by 16"]
pub const DIV_BY_16: Self = Self::new(4);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkTimerCtl_SPEC;
impl crate::sealed::RegSpec for ClkTimerCtl_SPEC {
type DataType = u32;
}
#[doc = "Timer Clock Control Register"]
pub type ClkTimerCtl = crate::RegValueT<ClkTimerCtl_SPEC>;
impl ClkTimerCtl {
#[doc = "Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV."]
#[inline(always)]
pub fn timer_sel(
self,
) -> crate::common::RegisterField<
0,
0x1,
1,
0,
clk_timer_ctl::TimerSel,
clk_timer_ctl::TimerSel,
ClkTimerCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1,
1,
0,
clk_timer_ctl::TimerSel,
clk_timer_ctl::TimerSel,
ClkTimerCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV). Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock."]
#[inline(always)]
pub fn timer_hf0_div(
self,
) -> crate::common::RegisterField<
8,
0x3,
1,
0,
clk_timer_ctl::TimerHf0Div,
clk_timer_ctl::TimerHf0Div,
ClkTimerCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0x3,
1,
0,
clk_timer_ctl::TimerHf0Div,
clk_timer_ctl::TimerHf0Div,
ClkTimerCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range \\[1, 256\\]. Do not change this setting while the timer is enabled."]
#[inline(always)]
pub fn timer_div(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, ClkTimerCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,ClkTimerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable for TIMERCLK.\n0: TIMERCLK is off\n1: TIMERCLK is enabled"]
#[inline(always)]
pub fn enable(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ClkTimerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,ClkTimerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkTimerCtl {
#[inline(always)]
fn default() -> ClkTimerCtl {
<crate::RegValueT<ClkTimerCtl_SPEC> as RegisterValue<_>>::new(458752)
}
}
pub mod clk_timer_ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct TimerSel_SPEC;
pub type TimerSel = crate::EnumBitfieldStruct<u8, TimerSel_SPEC>;
impl TimerSel {
#[doc = "IMO - Internal Main Oscillator"]
pub const IMO: Self = Self::new(0);
#[doc = "Select the output of the predivider configured by TIMER_HF0_DIV."]
pub const HF_0_DIV: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct TimerHf0Div_SPEC;
pub type TimerHf0Div = crate::EnumBitfieldStruct<u8, TimerHf0Div_SPEC>;
impl TimerHf0Div {
#[doc = "Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle."]
pub const NO_DIV: Self = Self::new(0);
#[doc = "Divide HFCLK0 by 2."]
pub const DIV_BY_2: Self = Self::new(1);
#[doc = "Divide HFCLK0 by 4."]
pub const DIV_BY_4: Self = Self::new(2);
#[doc = "Divide HFCLK0 by 8."]
pub const DIV_BY_8: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkIloConfig_SPEC;
impl crate::sealed::RegSpec for ClkIloConfig_SPEC {
type DataType = u32;
}
#[doc = "ILO Configuration"]
pub type ClkIloConfig = crate::RegValueT<ClkIloConfig_SPEC>;
impl ClkIloConfig {
#[doc = "If backup domain is present on this product, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD on VDDD/VCCD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.\n0: ILO turns off at XRES/BOD event or HIBERNATE entry.\n1: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry."]
#[inline(always)]
pub fn ilo_backup(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ClkIloConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ClkIloConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. After enabling, it takes at most two cycles to reach the accuracy spec."]
#[inline(always)]
pub fn enable(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ClkIloConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,ClkIloConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkIloConfig {
#[inline(always)]
fn default() -> ClkIloConfig {
<crate::RegValueT<ClkIloConfig_SPEC> as RegisterValue<_>>::new(2147483648)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkImoConfig_SPEC;
impl crate::sealed::RegSpec for ClkImoConfig_SPEC {
type DataType = u32;
}
#[doc = "IMO Configuration"]
pub type ClkImoConfig = crate::RegValueT<ClkImoConfig_SPEC>;
impl ClkImoConfig {
#[doc = "Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during HIBERNATE and XRES. It will automatically disable during DEEPSLEEP if DPSLP_ENABLE==0."]
#[inline(always)]
pub fn enable(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ClkImoConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,ClkImoConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkImoConfig {
#[inline(always)]
fn default() -> ClkImoConfig {
<crate::RegValueT<ClkImoConfig_SPEC> as RegisterValue<_>>::new(2147483648)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkOutputFast_SPEC;
impl crate::sealed::RegSpec for ClkOutputFast_SPEC {
type DataType = u32;
}
#[doc = "Fast Clock Output Select Register"]
pub type ClkOutputFast = crate::RegValueT<ClkOutputFast_SPEC>;
impl ClkOutputFast {
#[doc = "Select signal for fast clock output #0"]
#[inline(always)]
pub fn fast_sel0(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
clk_output_fast::FastSel0,
clk_output_fast::FastSel0,
ClkOutputFast_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
clk_output_fast::FastSel0,
clk_output_fast::FastSel0,
ClkOutputFast_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Selects a clock path to use in fast clock output #0 logic. 0: FLL output\n1-15: PLL output on path1-path15 (if available)"]
#[inline(always)]
pub fn path_sel0(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, ClkOutputFast_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0xf,1,0,u8,u8,ClkOutputFast_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Selects a HFCLK tree for use in fast clock output #0"]
#[inline(always)]
pub fn hfclk_sel0(
self,
) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, ClkOutputFast_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xf,1,0,u8,u8,ClkOutputFast_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select signal for fast clock output #1"]
#[inline(always)]
pub fn fast_sel1(
self,
) -> crate::common::RegisterField<
16,
0xf,
1,
0,
clk_output_fast::FastSel1,
clk_output_fast::FastSel1,
ClkOutputFast_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0xf,
1,
0,
clk_output_fast::FastSel1,
clk_output_fast::FastSel1,
ClkOutputFast_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Selects a clock path to use in fast clock output #1 logic. 0: FLL output\n1-15: PLL output on path1-path15 (if available)"]
#[inline(always)]
pub fn path_sel1(
self,
) -> crate::common::RegisterField<20, 0xf, 1, 0, u8, u8, ClkOutputFast_SPEC, crate::common::RW>
{
crate::common::RegisterField::<20,0xf,1,0,u8,u8,ClkOutputFast_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Selects a HFCLK tree for use in fast clock output #1 logic"]
#[inline(always)]
pub fn hfclk_sel1(
self,
) -> crate::common::RegisterField<24, 0xf, 1, 0, u8, u8, ClkOutputFast_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0xf,1,0,u8,u8,ClkOutputFast_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkOutputFast {
#[inline(always)]
fn default() -> ClkOutputFast {
<crate::RegValueT<ClkOutputFast_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod clk_output_fast {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct FastSel0_SPEC;
pub type FastSel0 = crate::EnumBitfieldStruct<u8, FastSel0_SPEC>;
impl FastSel0 {
#[doc = "Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0."]
pub const NC: Self = Self::new(0);
#[doc = "External Crystal Oscillator (ECO)"]
pub const ECO: Self = Self::new(1);
#[doc = "External clock input (EXTCLK)"]
pub const EXTCLK: Self = Self::new(2);
#[doc = "Alternate High-Frequency (ALTHF) clock input to SRSS"]
pub const ALTHF: Self = Self::new(3);
#[doc = "Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse."]
pub const TIMERCLK: Self = Self::new(4);
#[doc = "Selects the clock path chosen by PATH_SEL0 field"]
pub const PATH_SEL_0: Self = Self::new(5);
#[doc = "Selects the output of the HFCLK_SEL0 mux"]
pub const HFCLK_SEL_0: Self = Self::new(6);
#[doc = "Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0"]
pub const SLOW_SEL_0: Self = Self::new(7);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct FastSel1_SPEC;
pub type FastSel1 = crate::EnumBitfieldStruct<u8, FastSel1_SPEC>;
impl FastSel1 {
#[doc = "Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1."]
pub const NC: Self = Self::new(0);
#[doc = "External Crystal Oscillator (ECO)"]
pub const ECO: Self = Self::new(1);
#[doc = "External clock input (EXTCLK)"]
pub const EXTCLK: Self = Self::new(2);
#[doc = "Alternate High-Frequency (ALTHF) clock input to SRSS"]
pub const ALTHF: Self = Self::new(3);
#[doc = "Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse."]
pub const TIMERCLK: Self = Self::new(4);
#[doc = "Selects the clock path chosen by PATH_SEL1 field"]
pub const PATH_SEL_1: Self = Self::new(5);
#[doc = "Selects the output of the HFCLK_SEL1 mux"]
pub const HFCLK_SEL_1: Self = Self::new(6);
#[doc = "Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1"]
pub const SLOW_SEL_1: Self = Self::new(7);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkOutputSlow_SPEC;
impl crate::sealed::RegSpec for ClkOutputSlow_SPEC {
type DataType = u32;
}
#[doc = "Slow Clock Output Select Register"]
pub type ClkOutputSlow = crate::RegValueT<ClkOutputSlow_SPEC>;
impl ClkOutputSlow {
#[doc = "Select signal for slow clock output #0"]
#[inline(always)]
pub fn slow_sel0(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
clk_output_slow::SlowSel0,
clk_output_slow::SlowSel0,
ClkOutputSlow_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
clk_output_slow::SlowSel0,
clk_output_slow::SlowSel0,
ClkOutputSlow_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Select signal for slow clock output #1"]
#[inline(always)]
pub fn slow_sel1(
self,
) -> crate::common::RegisterField<
4,
0xf,
1,
0,
clk_output_slow::SlowSel1,
clk_output_slow::SlowSel1,
ClkOutputSlow_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0xf,
1,
0,
clk_output_slow::SlowSel1,
clk_output_slow::SlowSel1,
ClkOutputSlow_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ClkOutputSlow {
#[inline(always)]
fn default() -> ClkOutputSlow {
<crate::RegValueT<ClkOutputSlow_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod clk_output_slow {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct SlowSel0_SPEC;
pub type SlowSel0 = crate::EnumBitfieldStruct<u8, SlowSel0_SPEC>;
impl SlowSel0 {
#[doc = "Disabled - output is 0. For power savings, clocks are blocked before entering any muxes."]
pub const NC: Self = Self::new(0);
#[doc = "Internal Low Speed Oscillator (ILO)"]
pub const ILO: Self = Self::new(1);
#[doc = "Watch-Crystal Oscillator (WCO)"]
pub const WCO: Self = Self::new(2);
#[doc = "Root of the Backup domain clock tree (BAK)"]
pub const BAK: Self = Self::new(3);
#[doc = "Alternate low-frequency clock input to SRSS (ALTLF)"]
pub const ALTLF: Self = Self::new(4);
#[doc = "Root of the low-speed clock tree (LFCLK)"]
pub const LFCLK: Self = Self::new(5);
#[doc = "Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit."]
pub const IMO: Self = Self::new(6);
#[doc = "Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit."]
pub const SLPCTRL: Self = Self::new(7);
#[doc = "Precision Internal Low Speed Oscillator (PILO)"]
pub const PILO: Self = Self::new(8);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct SlowSel1_SPEC;
pub type SlowSel1 = crate::EnumBitfieldStruct<u8, SlowSel1_SPEC>;
impl SlowSel1 {
#[doc = "Disabled - output is 0. For power savings, clocks are blocked before entering any muxes."]
pub const NC: Self = Self::new(0);
#[doc = "Internal Low Speed Oscillator (ILO)"]
pub const ILO: Self = Self::new(1);
#[doc = "Watch-Crystal Oscillator (WCO)"]
pub const WCO: Self = Self::new(2);
#[doc = "Root of the Backup domain clock tree (BAK)"]
pub const BAK: Self = Self::new(3);
#[doc = "Alternate low-frequency clock input to SRSS (ALTLF)"]
pub const ALTLF: Self = Self::new(4);
#[doc = "Root of the low-speed clock tree (LFCLK)"]
pub const LFCLK: Self = Self::new(5);
#[doc = "Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit."]
pub const IMO: Self = Self::new(6);
#[doc = "Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit."]
pub const SLPCTRL: Self = Self::new(7);
#[doc = "Precision Internal Low Speed Oscillator (PILO)"]
pub const PILO: Self = Self::new(8);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkCalCnt1_SPEC;
impl crate::sealed::RegSpec for ClkCalCnt1_SPEC {
type DataType = u32;
}
#[doc = "Clock Calibration Counter 1"]
pub type ClkCalCnt1 = crate::RegValueT<ClkCalCnt1_SPEC>;
impl ClkCalCnt1 {
#[doc = "Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1. Both clocks must be running or the measurement will not complete. A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result."]
#[inline(always)]
pub fn cal_counter1(
self,
) -> crate::common::RegisterField<0, 0xffffff, 1, 0, u32, u32, ClkCalCnt1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xffffff,
1,
0,
u32,
u32,
ClkCalCnt1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up"]
#[inline(always)]
pub fn cal_counter_done(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ClkCalCnt1_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31,1,0,ClkCalCnt1_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for ClkCalCnt1 {
#[inline(always)]
fn default() -> ClkCalCnt1 {
<crate::RegValueT<ClkCalCnt1_SPEC> as RegisterValue<_>>::new(2147483648)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkCalCnt2_SPEC;
impl crate::sealed::RegSpec for ClkCalCnt2_SPEC {
type DataType = u32;
}
#[doc = "Clock Calibration Counter 2"]
pub type ClkCalCnt2 = crate::RegValueT<ClkCalCnt2_SPEC>;
impl ClkCalCnt2 {
#[doc = "Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER)"]
#[inline(always)]
pub fn cal_counter2(
self,
) -> crate::common::RegisterField<0, 0xffffff, 1, 0, u32, u32, ClkCalCnt2_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffffff,1,0,u32,u32,ClkCalCnt2_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for ClkCalCnt2 {
#[inline(always)]
fn default() -> ClkCalCnt2 {
<crate::RegValueT<ClkCalCnt2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkEcoConfig_SPEC;
impl crate::sealed::RegSpec for ClkEcoConfig_SPEC {
type DataType = u32;
}
#[doc = "ECO Configuration Register"]
pub type ClkEcoConfig = crate::RegValueT<ClkEcoConfig_SPEC>;
impl ClkEcoConfig {
#[doc = "Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM. When low, the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal."]
#[inline(always)]
pub fn agc_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ClkEcoConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ClkEcoConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Master enable for ECO oscillator."]
#[inline(always)]
pub fn eco_en(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ClkEcoConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,ClkEcoConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkEcoConfig {
#[inline(always)]
fn default() -> ClkEcoConfig {
<crate::RegValueT<ClkEcoConfig_SPEC> as RegisterValue<_>>::new(2)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkEcoStatus_SPEC;
impl crate::sealed::RegSpec for ClkEcoStatus_SPEC {
type DataType = u32;
}
#[doc = "ECO Status Register"]
pub type ClkEcoStatus = crate::RegValueT<ClkEcoStatus_SPEC>;
impl ClkEcoStatus {
#[doc = "Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec."]
#[inline(always)]
pub fn eco_ok(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ClkEcoStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,ClkEcoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled, and it does not check the ECO output. It is recommended to also confirm ECO_OK==1."]
#[inline(always)]
pub fn eco_ready(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ClkEcoStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,ClkEcoStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for ClkEcoStatus {
#[inline(always)]
fn default() -> ClkEcoStatus {
<crate::RegValueT<ClkEcoStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkPiloConfig_SPEC;
impl crate::sealed::RegSpec for ClkPiloConfig_SPEC {
type DataType = u32;
}
#[doc = "Precision ILO Configuration Register"]
pub type ClkPiloConfig = crate::RegValueT<ClkPiloConfig_SPEC>;
impl ClkPiloConfig {
#[doc = "Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz."]
#[inline(always)]
pub fn pilo_ffreq(
self,
) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, ClkPiloConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0x3ff,
1,
0,
u16,
u16,
ClkPiloConfig_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Enable the PILO clock output. See PILO_EN field for required sequencing."]
#[inline(always)]
pub fn pilo_clk_en(
self,
) -> crate::common::RegisterFieldBool<29, 1, 0, ClkPiloConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<29,1,0,ClkPiloConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Reset the PILO. See PILO_EN field for required sequencing."]
#[inline(always)]
pub fn pilo_reset_n(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, ClkPiloConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,ClkPiloConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle."]
#[inline(always)]
pub fn pilo_en(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ClkPiloConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,ClkPiloConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkPiloConfig {
#[inline(always)]
fn default() -> ClkPiloConfig {
<crate::RegValueT<ClkPiloConfig_SPEC> as RegisterValue<_>>::new(128)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkFllConfig_SPEC;
impl crate::sealed::RegSpec for ClkFllConfig_SPEC {
type DataType = u32;
}
#[doc = "FLL Configuration Register"]
pub type ClkFllConfig = crate::RegValueT<ClkFllConfig_SPEC>;
impl ClkFllConfig {
#[doc = "Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref).\n\nFfll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1)"]
#[inline(always)]
pub fn fll_mult(
self,
) -> crate::common::RegisterField<
0,
0x3ffff,
1,
0,
u32,
u32,
ClkFllConfig_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3ffff,
1,
0,
u32,
u32,
ClkFllConfig_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled.\n0: no division\n1: divide by 2"]
#[inline(always)]
pub fn fll_output_div(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, ClkFllConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,ClkFllConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Master enable for FLL. The FLL requires firmware sequencing when enabling, disabling, and entering/exiting DEEPSLEEP.\n\nTo enable the FLL, first enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1 and wait until CLK_FLL_STATUS.CCO_READY==1. Next, ensure the reference clock has stabilized and CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF. Next, write FLL_ENABLE=1 and wait until CLK_FLL_STATUS.LOCKED==1. Finally, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. It takes seven reference clock cycles plus four FLL output cycles to switch to the FLL output. Do not disable the FLL before this time completes.\n\nTo disable the FLL, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF and (optionally) read the same register to ensure the write completes. Then, wait at least seven FLL reference clock cycles before disabling it with FLL_ENABLE=0. Lastly, disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0.\n\nBefore entering DEEPSLEEP, either disable the FLL using above sequence or use the following procedure to deselect/select it before/after DEEPSLEEP. Before entering DEEPSLEEP, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF to change the FLL to use its reference clock. After DEEPSLEEP wakeup, wait until CLK_FLL_STATUS.LOCKED==1 and then write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output.\n\n0: Block is powered off\n1: Block is powered on"]
#[inline(always)]
pub fn fll_enable(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ClkFllConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,ClkFllConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkFllConfig {
#[inline(always)]
fn default() -> ClkFllConfig {
<crate::RegValueT<ClkFllConfig_SPEC> as RegisterValue<_>>::new(16777216)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkFllConfig2_SPEC;
impl crate::sealed::RegSpec for ClkFllConfig2_SPEC {
type DataType = u32;
}
#[doc = "FLL Configuration Register 2"]
pub type ClkFllConfig2 = crate::RegValueT<ClkFllConfig2_SPEC>;
impl ClkFllConfig2 {
#[doc = "Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled.\n0: illegal (undefined behavior)\n1: divide by 1\n...\n8191: divide by 8191"]
#[inline(always)]
pub fn fll_ref_div(
self,
) -> crate::common::RegisterField<
0,
0x1fff,
1,
0,
u16,
u16,
ClkFllConfig2_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1fff,
1,
0,
u16,
u16,
ClkFllConfig2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or to track a less accurate source. The tolerance should be set so that the FLL does not unlock under normal conditions. The tolerance is the allowed difference between the count value for the ideal formula and the measured value. \n0: tolerate error of 1 count value\n1: tolerate error of 2 count values\n...\n511: tolerate error of 512 count values"]
#[inline(always)]
pub fn lock_tol(
self,
) -> crate::common::RegisterField<
16,
0x1ff,
1,
0,
u16,
u16,
ClkFllConfig2_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0x1ff,
1,
0,
u16,
u16,
ClkFllConfig2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ClkFllConfig2 {
#[inline(always)]
fn default() -> ClkFllConfig2 {
<crate::RegValueT<ClkFllConfig2_SPEC> as RegisterValue<_>>::new(131073)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkFllConfig3_SPEC;
impl crate::sealed::RegSpec for ClkFllConfig3_SPEC {
type DataType = u32;
}
#[doc = "FLL Configuration Register 3"]
pub type ClkFllConfig3 = crate::RegValueT<ClkFllConfig3_SPEC>;
impl ClkFllConfig3 {
#[doc = "FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN.\n0: 1/256\n1: 1/128\n2: 1/64\n3: 1/32\n4: 1/16\n5: 1/8\n6: 1/4\n7: 1/2\n8: 1.0\n9: 2.0\n10: 4.0\n11: 8.0\n>=12: illegal"]
#[inline(always)]
pub fn fll_lf_igain(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, ClkFllConfig3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,ClkFllConfig3_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN.\n0: 1/256\n1: 1/128\n2: 1/64\n3: 1/32\n4: 1/16\n5: 1/8\n6: 1/4\n7: 1/2\n8: 1.0\n9: 2.0\n10: 4.0\n11: 8.0\n>=12: illegal"]
#[inline(always)]
pub fn fll_lf_pgain(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, ClkFllConfig3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0xf,1,0,u8,u8,ClkFllConfig3_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case.\n0: no settling time\n1: wait one reference clock cycle\n...\n8191: wait 8191 reference clock cycles"]
#[inline(always)]
pub fn settling_count(
self,
) -> crate::common::RegisterField<
8,
0x1fff,
1,
0,
u16,
u16,
ClkFllConfig3_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0x1fff,
1,
0,
u16,
u16,
ClkFllConfig3_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Bypass mux located just after FLL output. See FLL_ENABLE description for instructions on how to use this field when enabling/disabling the FLL."]
#[inline(always)]
pub fn bypass_sel(
self,
) -> crate::common::RegisterField<
28,
0x3,
1,
0,
clk_fll_config3::BypassSel,
clk_fll_config3::BypassSel,
ClkFllConfig3_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
28,
0x3,
1,
0,
clk_fll_config3::BypassSel,
clk_fll_config3::BypassSel,
ClkFllConfig3_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ClkFllConfig3 {
#[inline(always)]
fn default() -> ClkFllConfig3 {
<crate::RegValueT<ClkFllConfig3_SPEC> as RegisterValue<_>>::new(10240)
}
}
pub mod clk_fll_config3 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct BypassSel_SPEC;
pub type BypassSel = crate::EnumBitfieldStruct<u8, BypassSel_SPEC>;
impl BypassSel {
#[doc = "N/A"]
pub const AUTO: Self = Self::new(0);
#[doc = "N/A"]
pub const AUTO_1: Self = Self::new(1);
#[doc = "Select FLL reference input (bypass mode). Ignores lock indicator"]
pub const FLL_REF: Self = Self::new(2);
#[doc = "Select FLL output. Ignores lock indicator."]
pub const FLL_OUT: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkFllConfig4_SPEC;
impl crate::sealed::RegSpec for ClkFllConfig4_SPEC {
type DataType = u32;
}
#[doc = "FLL Configuration Register 4"]
pub type ClkFllConfig4 = crate::RegValueT<ClkFllConfig4_SPEC>;
impl ClkFllConfig4 {
#[doc = "Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support)"]
#[inline(always)]
pub fn cco_limit(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ClkFllConfig4_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ClkFllConfig4_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Frequency range of CCO"]
#[inline(always)]
pub fn cco_range(
self,
) -> crate::common::RegisterField<
8,
0x7,
1,
0,
clk_fll_config4::CcoRange,
clk_fll_config4::CcoRange,
ClkFllConfig4_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0x7,
1,
0,
clk_fll_config4::CcoRange,
clk_fll_config4::CcoRange,
ClkFllConfig4_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range."]
#[inline(always)]
pub fn cco_freq(
self,
) -> crate::common::RegisterField<
16,
0x1ff,
1,
0,
u16,
u16,
ClkFllConfig4_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0x1ff,
1,
0,
u16,
u16,
ClkFllConfig4_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Disable CCO frequency update by FLL hardware\n0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation.\n1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation."]
#[inline(always)]
pub fn cco_hw_update_dis(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, ClkFllConfig4_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,ClkFllConfig4_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable the CCO. It is required to enable the CCO before using the FLL. \n0: Block is powered off\n1: Block is powered on"]
#[inline(always)]
pub fn cco_enable(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ClkFllConfig4_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,ClkFllConfig4_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkFllConfig4 {
#[inline(always)]
fn default() -> ClkFllConfig4 {
<crate::RegValueT<ClkFllConfig4_SPEC> as RegisterValue<_>>::new(255)
}
}
pub mod clk_fll_config4 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CcoRange_SPEC;
pub type CcoRange = crate::EnumBitfieldStruct<u8, CcoRange_SPEC>;
impl CcoRange {
#[doc = "Target frequency is in range \\[48, 64) MHz"]
pub const RANGE_0: Self = Self::new(0);
#[doc = "Target frequency is in range \\[64, 85) MHz"]
pub const RANGE_1: Self = Self::new(1);
#[doc = "Target frequency is in range \\[85, 113) MHz"]
pub const RANGE_2: Self = Self::new(2);
#[doc = "Target frequency is in range \\[113, 150) MHz"]
pub const RANGE_3: Self = Self::new(3);
#[doc = "Target frequency is in range \\[150, 200\\] MHz"]
pub const RANGE_4: Self = Self::new(4);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkFllStatus_SPEC;
impl crate::sealed::RegSpec for ClkFllStatus_SPEC {
type DataType = u32;
}
#[doc = "FLL Status Register"]
pub type ClkFllStatus = crate::RegValueT<ClkFllStatus_SPEC>;
impl ClkFllStatus {
#[doc = "FLL Lock Indicator. LOCKED is high when FLL is within CLK_FLL_CONFIG2.LOCK_TOL. If FLL is outside LOCK_TOL, LOCKED goes low. Note that this can happen during normal operation, if FLL needs to recalculate due to a change in the reference clock, change in voltage, or change in temperature."]
#[inline(always)]
pub fn locked(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ClkFllStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,ClkFllStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn unlock_occurred(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ClkFllStatus_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ClkFllStatus_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This indicates that the CCO is internally settled and ready to use."]
#[inline(always)]
pub fn cco_ready(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ClkFllStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,ClkFllStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for ClkFllStatus {
#[inline(always)]
fn default() -> ClkFllStatus {
<crate::RegValueT<ClkFllStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkPllConfig_SPEC;
impl crate::sealed::RegSpec for ClkPllConfig_SPEC {
type DataType = u32;
}
#[doc = "PLL Configuration Register"]
pub type ClkPllConfig = crate::RegValueT<ClkPllConfig_SPEC>;
impl ClkPllConfig {
#[doc = "Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled.\n0-21: illegal (undefined behavior)\n22: divide by 22\n...\n112: divide by 112\n>112: illegal (undefined behavior)"]
#[inline(always)]
pub fn feedback_div(
self,
) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, ClkPllConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7f,1,0,u8,u8,ClkPllConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled.\n0: illegal (undefined behavior)\n1: divide by 1\n...\n20: divide by 20\nothers: illegal (undefined behavior)"]
#[inline(always)]
pub fn reference_div(
self,
) -> crate::common::RegisterField<8, 0x1f, 1, 0, u8, u8, ClkPllConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x1f,1,0,u8,u8,ClkPllConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled.\n0: illegal (undefined behavior)\n1: illegal (undefined behavior) \n2: divide by 2. Suitable for direct usage as HFCLK source.\n...\n16: divide by 16. Suitable for direct usage as HFCLK source.\n>16: illegal (undefined behavior)"]
#[inline(always)]
pub fn output_div(
self,
) -> crate::common::RegisterField<16, 0x1f, 1, 0, u8, u8, ClkPllConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x1f,1,0,u8,u8,ClkPllConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled.\n0: VCO frequency is \\[200MHz, 400MHz\\]\n1: VCO frequency is \\[170MHz, 200MHz)"]
#[inline(always)]
pub fn pll_lf_mode(
self,
) -> crate::common::RegisterFieldBool<27, 1, 0, ClkPllConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<27,1,0,ClkPllConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running."]
#[inline(always)]
pub fn bypass_sel(
self,
) -> crate::common::RegisterField<
28,
0x3,
1,
0,
clk_pll_config::BypassSel,
clk_pll_config::BypassSel,
ClkPllConfig_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
28,
0x3,
1,
0,
clk_pll_config::BypassSel,
clk_pll_config::BypassSel,
ClkPllConfig_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0.\n\nFpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV)\n\n0: Block is disabled\n1: Block is enabled"]
#[inline(always)]
pub fn enable(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ClkPllConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,ClkPllConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkPllConfig {
#[inline(always)]
fn default() -> ClkPllConfig {
<crate::RegValueT<ClkPllConfig_SPEC> as RegisterValue<_>>::new(131350)
}
}
pub mod clk_pll_config {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct BypassSel_SPEC;
pub type BypassSel = crate::EnumBitfieldStruct<u8, BypassSel_SPEC>;
impl BypassSel {
#[doc = "Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output."]
pub const AUTO: Self = Self::new(0);
#[doc = "Same as AUTO"]
pub const AUTO_1: Self = Self::new(1);
#[doc = "Select PLL reference input (bypass mode). Ignores lock indicator"]
pub const PLL_REF: Self = Self::new(2);
#[doc = "Select PLL output. Ignores lock indicator."]
pub const PLL_OUT: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkPllStatus_SPEC;
impl crate::sealed::RegSpec for ClkPllStatus_SPEC {
type DataType = u32;
}
#[doc = "PLL Status Register"]
pub type ClkPllStatus = crate::RegValueT<ClkPllStatus_SPEC>;
impl ClkPllStatus {
#[doc = "PLL Lock Indicator"]
#[inline(always)]
pub fn locked(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ClkPllStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,ClkPllStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware."]
#[inline(always)]
pub fn unlock_occurred(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ClkPllStatus_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ClkPllStatus_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkPllStatus {
#[inline(always)]
fn default() -> ClkPllStatus {
<crate::RegValueT<ClkPllStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SrssIntr_SPEC;
impl crate::sealed::RegSpec for SrssIntr_SPEC {
type DataType = u32;
}
#[doc = "SRSS Interrupt Register"]
pub type SrssIntr = crate::RegValueT<SrssIntr_SPEC>;
impl SrssIntr {
#[doc = "WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also feeds the watch dog. Missing 2 interrupts in a row will generate a reset. Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C."]
#[inline(always)]
pub fn wdt_match(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, SrssIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, SrssIntr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Interrupt for low voltage detector HVLVD1"]
#[inline(always)]
pub fn hvlvd1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, SrssIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, SrssIntr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Clock calibration counter is done. This field is reset during DEEPSLEEP mode."]
#[inline(always)]
pub fn clk_cal(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, SrssIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, SrssIntr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for SrssIntr {
#[inline(always)]
fn default() -> SrssIntr {
<crate::RegValueT<SrssIntr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SrssIntrSet_SPEC;
impl crate::sealed::RegSpec for SrssIntrSet_SPEC {
type DataType = u32;
}
#[doc = "SRSS Interrupt Set Register"]
pub type SrssIntrSet = crate::RegValueT<SrssIntrSet_SPEC>;
impl SrssIntrSet {
#[doc = "Set interrupt for low voltage detector WDT_MATCH"]
#[inline(always)]
pub fn wdt_match(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, SrssIntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,SrssIntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set interrupt for low voltage detector HVLVD1"]
#[inline(always)]
pub fn hvlvd1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, SrssIntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,SrssIntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode."]
#[inline(always)]
pub fn clk_cal(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, SrssIntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,SrssIntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SrssIntrSet {
#[inline(always)]
fn default() -> SrssIntrSet {
<crate::RegValueT<SrssIntrSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SrssIntrMask_SPEC;
impl crate::sealed::RegSpec for SrssIntrMask_SPEC {
type DataType = u32;
}
#[doc = "SRSS Interrupt Mask Register"]
pub type SrssIntrMask = crate::RegValueT<SrssIntrMask_SPEC>;
impl SrssIntrMask {
#[doc = "Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. It will not, however, disable the WDT reset generation on 2 missed interrupts. When WDT resets the chip, it also internally pends an interrupt that survives the reset. To prevent unintended ISR execution, clear SRSS_INTR.WDT_MATCH before setting this bit."]
#[inline(always)]
pub fn wdt_match(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, SrssIntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,SrssIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask for low voltage detector HVLVD1"]
#[inline(always)]
pub fn hvlvd1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, SrssIntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,SrssIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask for clock calibration done"]
#[inline(always)]
pub fn clk_cal(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, SrssIntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,SrssIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SrssIntrMask {
#[inline(always)]
fn default() -> SrssIntrMask {
<crate::RegValueT<SrssIntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SrssIntrMasked_SPEC;
impl crate::sealed::RegSpec for SrssIntrMasked_SPEC {
type DataType = u32;
}
#[doc = "SRSS Interrupt Masked Register"]
pub type SrssIntrMasked = crate::RegValueT<SrssIntrMasked_SPEC>;
impl SrssIntrMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn wdt_match(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, SrssIntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,SrssIntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn hvlvd1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, SrssIntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,SrssIntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn clk_cal(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, SrssIntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5,1,0,SrssIntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for SrssIntrMasked {
#[inline(always)]
fn default() -> SrssIntrMasked {
<crate::RegValueT<SrssIntrMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SrssIntrCfg_SPEC;
impl crate::sealed::RegSpec for SrssIntrCfg_SPEC {
type DataType = u32;
}
#[doc = "SRSS Interrupt Configuration Register"]
pub type SrssIntrCfg = crate::RegValueT<SrssIntrCfg_SPEC>;
impl SrssIntrCfg {
#[doc = "Sets which edge(s) will trigger an IRQ for HVLVD1"]
#[inline(always)]
pub fn hvlvd1_edge_sel(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
srss_intr_cfg::Hvlvd1EdgeSel,
srss_intr_cfg::Hvlvd1EdgeSel,
SrssIntrCfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
srss_intr_cfg::Hvlvd1EdgeSel,
srss_intr_cfg::Hvlvd1EdgeSel,
SrssIntrCfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for SrssIntrCfg {
#[inline(always)]
fn default() -> SrssIntrCfg {
<crate::RegValueT<SrssIntrCfg_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod srss_intr_cfg {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Hvlvd1EdgeSel_SPEC;
pub type Hvlvd1EdgeSel = crate::EnumBitfieldStruct<u8, Hvlvd1EdgeSel_SPEC>;
impl Hvlvd1EdgeSel {
#[doc = "Disabled"]
pub const DISABLE: Self = Self::new(0);
#[doc = "Rising edge"]
pub const RISING: Self = Self::new(1);
#[doc = "Falling edge"]
pub const FALLING: Self = Self::new(2);
#[doc = "Both rising and falling edges"]
pub const BOTH: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ResCause_SPEC;
impl crate::sealed::RegSpec for ResCause_SPEC {
type DataType = u32;
}
#[doc = "Reset Cause Observation Register"]
pub type ResCause = crate::RegValueT<ResCause_SPEC>;
impl ResCause {
#[doc = "N/A"]
#[inline(always)]
pub fn reset_wdt(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ResCause_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, ResCause_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn reset_act_fault(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ResCause_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, ResCause_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn reset_dpslp_fault(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ResCause_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, ResCause_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn reset_csv_wco_loss(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ResCause_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, ResCause_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn reset_soft(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ResCause_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, ResCause_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn reset_mcwdt0(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ResCause_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, ResCause_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn reset_mcwdt1(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, ResCause_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, ResCause_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Multi-Counter Watchdog timer reset #2 has occurred since last power cycle. This hardware is not present in PSoC6 devices."]
#[inline(always)]
pub fn reset_mcwdt2(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, ResCause_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7, 1, 0, ResCause_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Multi-Counter Watchdog timer reset #3 has occurred since last power cycle. This hardware is not present in PSoC6 devices."]
#[inline(always)]
pub fn reset_mcwdt3(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, ResCause_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, ResCause_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for ResCause {
#[inline(always)]
fn default() -> ResCause {
<crate::RegValueT<ResCause_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ResCause2_SPEC;
impl crate::sealed::RegSpec for ResCause2_SPEC {
type DataType = u32;
}
#[doc = "Reset Cause Observation Register 2"]
pub type ResCause2 = crate::RegValueT<ResCause2_SPEC>;
impl ResCause2 {
#[doc = "Clock supervision logic requested a reset due to loss of a high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero."]
#[inline(always)]
pub fn reset_csv_hf_loss(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, ResCause2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,ResCause2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Clock supervision logic requested a reset due to frequency error of high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero."]
#[inline(always)]
pub fn reset_csv_hf_freq(
self,
) -> crate::common::RegisterField<16, 0xffff, 1, 0, u16, u16, ResCause2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xffff,1,0,u16,u16,ResCause2_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ResCause2 {
#[inline(always)]
fn default() -> ResCause2 {
<crate::RegValueT<ResCause2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PwrTrimRefCtl_SPEC;
impl crate::sealed::RegSpec for PwrTrimRefCtl_SPEC {
type DataType = u32;
}
#[doc = "Reference Trim Register"]
pub type PwrTrimRefCtl = crate::RegValueT<PwrTrimRefCtl_SPEC>;
impl PwrTrimRefCtl {
#[doc = "Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE.\n0 -> default setting at POR; not for trimming use\nothers -> normal trim range"]
#[inline(always)]
pub fn act_ref_tctrim(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, PwrTrimRefCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,PwrTrimRefCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Active-Reference current trim. This register is only reset by XRES/POR/BOD/HIBERNATE.\n0 -> default setting at POR; not for trimming use\nothers -> normal trim range"]
#[inline(always)]
pub fn act_ref_itrim(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, PwrTrimRefCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0xf,1,0,u8,u8,PwrTrimRefCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE.\n0 -> default setting at POR; not for trimming use\nothers -> normal trim range"]
#[inline(always)]
pub fn act_ref_abstrim(
self,
) -> crate::common::RegisterField<8, 0x1f, 1, 0, u8, u8, PwrTrimRefCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x1f,1,0,u8,u8,PwrTrimRefCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Active-Reference current boost. This register is only reset by XRES/POR/BOD/HIBERNATE.\n0: normal operation\nothers: risk mitigation"]
#[inline(always)]
pub fn act_ref_iboost(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, PwrTrimRefCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<14,1,0,PwrTrimRefCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE.\n0 -> default setting at POR; not for trimming use\nothers -> normal trim range"]
#[inline(always)]
pub fn dpslp_ref_tctrim(
self,
) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, PwrTrimRefCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xf,1,0,u8,u8,PwrTrimRefCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE."]
#[inline(always)]
pub fn dpslp_ref_abstrim(
self,
) -> crate::common::RegisterField<20, 0x1f, 1, 0, u8, u8, PwrTrimRefCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<20,0x1f,1,0,u8,u8,PwrTrimRefCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/HIBERNATE."]
#[inline(always)]
pub fn dpslp_ref_itrim(
self,
) -> crate::common::RegisterField<28, 0xf, 1, 0, u8, u8, PwrTrimRefCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<28,0xf,1,0,u8,u8,PwrTrimRefCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for PwrTrimRefCtl {
#[inline(always)]
fn default() -> PwrTrimRefCtl {
<crate::RegValueT<PwrTrimRefCtl_SPEC> as RegisterValue<_>>::new(1894776832)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PwrTrimBodovpCtl_SPEC;
impl crate::sealed::RegSpec for PwrTrimBodovpCtl_SPEC {
type DataType = u32;
}
#[doc = "BOD/OVP Trim Register"]
pub type PwrTrimBodovpCtl = crate::RegValueT<PwrTrimBodovpCtl_SPEC>;
impl PwrTrimBodovpCtl {
#[doc = "HVPORBOD trip point selection. Monitors vddd. This register is only reset by XRES/POR/BOD/HIBERNATE."]
#[inline(always)]
pub fn hvporbod_tripsel(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, PwrTrimBodovpCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,PwrTrimBodovpCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "HVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE."]
#[inline(always)]
pub fn hvporbod_ofstrim(
self,
) -> crate::common::RegisterField<4, 0x7, 1, 0, u8, u8, PwrTrimBodovpCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0x7,1,0,u8,u8,PwrTrimBodovpCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "HVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE."]
#[inline(always)]
pub fn hvporbod_itrim(
self,
) -> crate::common::RegisterField<7, 0x7, 1, 0, u8, u8, PwrTrimBodovpCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<7,0x7,1,0,u8,u8,PwrTrimBodovpCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "LVPORBOD trip point selection. Monitors vccd. This register is only reset by XRES/POR/BOD/HIBERNATE."]
#[inline(always)]
pub fn lvporbod_tripsel(
self,
) -> crate::common::RegisterField<10, 0x7, 1, 0, u8, u8, PwrTrimBodovpCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
10,
0x7,
1,
0,
u8,
u8,
PwrTrimBodovpCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "LVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE."]
#[inline(always)]
pub fn lvporbod_ofstrim(
self,
) -> crate::common::RegisterField<14, 0x7, 1, 0, u8, u8, PwrTrimBodovpCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
14,
0x7,
1,
0,
u8,
u8,
PwrTrimBodovpCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "LVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE."]
#[inline(always)]
pub fn lvporbod_itrim(
self,
) -> crate::common::RegisterField<17, 0x7, 1, 0, u8, u8, PwrTrimBodovpCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
17,
0x7,
1,
0,
u8,
u8,
PwrTrimBodovpCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PwrTrimBodovpCtl {
#[inline(always)]
fn default() -> PwrTrimBodovpCtl {
<crate::RegValueT<PwrTrimBodovpCtl_SPEC> as RegisterValue<_>>::new(265476)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkTrimCcoCtl_SPEC;
impl crate::sealed::RegSpec for ClkTrimCcoCtl_SPEC {
type DataType = u32;
}
#[doc = "CCO Trim Register"]
pub type ClkTrimCcoCtl = crate::RegValueT<ClkTrimCcoCtl_SPEC>;
impl ClkTrimCcoCtl {
#[doc = "CCO reference current source trim."]
#[inline(always)]
pub fn cco_rcstrim(
self,
) -> crate::common::RegisterField<0, 0x3f, 1, 0, u8, u8, ClkTrimCcoCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x3f,1,0,u8,u8,ClkTrimCcoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Terminal count for the stabilization counter from CCO_ENABLE until stable."]
#[inline(always)]
pub fn cco_stable_cnt(
self,
) -> crate::common::RegisterField<24, 0x3f, 1, 0, u8, u8, ClkTrimCcoCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0x3f,1,0,u8,u8,ClkTrimCcoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables the automatic stabilization counter."]
#[inline(always)]
pub fn enable_cnt(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ClkTrimCcoCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,ClkTrimCcoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkTrimCcoCtl {
#[inline(always)]
fn default() -> ClkTrimCcoCtl {
<crate::RegValueT<ClkTrimCcoCtl_SPEC> as RegisterValue<_>>::new(2801795104)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkTrimCcoCtl2_SPEC;
impl crate::sealed::RegSpec for ClkTrimCcoCtl2_SPEC {
type DataType = u32;
}
#[doc = "CCO Trim Register 2"]
pub type ClkTrimCcoCtl2 = crate::RegValueT<ClkTrimCcoCtl2_SPEC>;
impl ClkTrimCcoCtl2 {
#[doc = "CCO frequency 1st range calibration"]
#[inline(always)]
pub fn cco_fctrim1(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, ClkTrimCcoCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,ClkTrimCcoCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "CCO frequency 2nd range calibration"]
#[inline(always)]
pub fn cco_fctrim2(
self,
) -> crate::common::RegisterField<5, 0x1f, 1, 0, u8, u8, ClkTrimCcoCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<5,0x1f,1,0,u8,u8,ClkTrimCcoCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "CCO frequency 3rd range calibration"]
#[inline(always)]
pub fn cco_fctrim3(
self,
) -> crate::common::RegisterField<10, 0x1f, 1, 0, u8, u8, ClkTrimCcoCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<10,0x1f,1,0,u8,u8,ClkTrimCcoCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "CCO frequency 4th range calibration"]
#[inline(always)]
pub fn cco_fctrim4(
self,
) -> crate::common::RegisterField<15, 0x1f, 1, 0, u8, u8, ClkTrimCcoCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<15,0x1f,1,0,u8,u8,ClkTrimCcoCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "CCO frequency 5th range calibration"]
#[inline(always)]
pub fn cco_fctrim5(
self,
) -> crate::common::RegisterField<20, 0x1f, 1, 0, u8, u8, ClkTrimCcoCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<20,0x1f,1,0,u8,u8,ClkTrimCcoCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkTrimCcoCtl2 {
#[inline(always)]
fn default() -> ClkTrimCcoCtl2 {
<crate::RegValueT<ClkTrimCcoCtl2_SPEC> as RegisterValue<_>>::new(8929552)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PwrTrimWakeCtl_SPEC;
impl crate::sealed::RegSpec for PwrTrimWakeCtl_SPEC {
type DataType = u32;
}
#[doc = "Wakeup Trim Register"]
pub type PwrTrimWakeCtl = crate::RegValueT<PwrTrimWakeCtl_SPEC>;
impl PwrTrimWakeCtl {
#[doc = "Wakeup holdoff. Spec (fastest) wake time is achieved with a setting of 0. Additional delay can be added for debugging or workaround. The delay is counted by the IMO."]
#[inline(always)]
pub fn wake_delay(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, PwrTrimWakeCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,PwrTrimWakeCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for PwrTrimWakeCtl {
#[inline(always)]
fn default() -> PwrTrimWakeCtl {
<crate::RegValueT<PwrTrimWakeCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PwrTrimLvdCtl_SPEC;
impl crate::sealed::RegSpec for PwrTrimLvdCtl_SPEC {
type DataType = u32;
}
#[doc = "LVD Trim Register"]
pub type PwrTrimLvdCtl = crate::RegValueT<PwrTrimLvdCtl_SPEC>;
impl PwrTrimLvdCtl {
#[doc = "HVLVD1 offset trim"]
#[inline(always)]
pub fn hvlvd1_ofstrim(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, PwrTrimLvdCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,PwrTrimLvdCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "HVLVD1 current trim"]
#[inline(always)]
pub fn hvlvd1_itrim(
self,
) -> crate::common::RegisterField<4, 0x7, 1, 0, u8, u8, PwrTrimLvdCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0x7,1,0,u8,u8,PwrTrimLvdCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for PwrTrimLvdCtl {
#[inline(always)]
fn default() -> PwrTrimLvdCtl {
<crate::RegValueT<PwrTrimLvdCtl_SPEC> as RegisterValue<_>>::new(32)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkTrimIloCtl_SPEC;
impl crate::sealed::RegSpec for ClkTrimIloCtl_SPEC {
type DataType = u32;
}
#[doc = "ILO Trim Register"]
pub type ClkTrimIloCtl = crate::RegValueT<ClkTrimIloCtl_SPEC>;
impl ClkTrimIloCtl {
#[doc = "ILO frequency trims. LSB step size is 1.5 percent (typical) of the frequency."]
#[inline(always)]
pub fn ilo_ftrim(
self,
) -> crate::common::RegisterField<0, 0x3f, 1, 0, u8, u8, ClkTrimIloCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x3f,1,0,u8,u8,ClkTrimIloCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkTrimIloCtl {
#[inline(always)]
fn default() -> ClkTrimIloCtl {
<crate::RegValueT<ClkTrimIloCtl_SPEC> as RegisterValue<_>>::new(44)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PwrTrimPwrsysCtl_SPEC;
impl crate::sealed::RegSpec for PwrTrimPwrsysCtl_SPEC {
type DataType = u32;
}
#[doc = "Power System Trim Register"]
pub type PwrTrimPwrsysCtl = crate::RegValueT<PwrTrimPwrsysCtl_SPEC>;
impl PwrTrimPwrsysCtl {
#[doc = "Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES/POR/BOD/HIBERNATE. Two voltages are supported: 0.9V and 1.1V. The codes for these are stored in SFLASH_LDO_0P9V_TRIM and SFLASH_LDO_1P1V_TRIM, respectively."]
#[inline(always)]
pub fn act_reg_trim(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, PwrTrimPwrsysCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0x1f,
1,
0,
u8,
u8,
PwrTrimPwrsysCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting:\n2\'b00: 50uA\n2\'b01: 100uA\n2\'b10: 150uA\n2\'b11: 200uA\n\nThe allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip.\n50mA chip: 2\'b00 (default);\n100mA chip: 2\'b00 (default);\n150mA chip: 50..100mA app => 2\'b00, 150mA app => 2\'b01 (default);\n200mA chip: 50mA app => 2\'b00, 100..150mA app => 2\'b01, 200mA app => 2\'b10 (default);\n250mA chip: 50mA app => 2\'b00, 100..150mA app => 2\'b01, 200..250mA app => 2\'b10 (default);\n300mA chip: 50mA app => 2\'b00, 100..150mA app => 2\'b01, 200..250mA app => 2\'b10, 300mA app => 2\'b11 (default);\n\nThis register is only reset by XRES/POR/BOD/HIBERNATE."]
#[inline(always)]
pub fn act_reg_boost(
self,
) -> crate::common::RegisterField<30, 0x3, 1, 0, u8, u8, PwrTrimPwrsysCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
30,
0x3,
1,
0,
u8,
u8,
PwrTrimPwrsysCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PwrTrimPwrsysCtl {
#[inline(always)]
fn default() -> PwrTrimPwrsysCtl {
<crate::RegValueT<PwrTrimPwrsysCtl_SPEC> as RegisterValue<_>>::new(23)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkTrimEcoCtl_SPEC;
impl crate::sealed::RegSpec for ClkTrimEcoCtl_SPEC {
type DataType = u32;
}
#[doc = "ECO Trim Register"]
pub type ClkTrimEcoCtl = crate::RegValueT<ClkTrimEcoCtl_SPEC>;
impl ClkTrimEcoCtl {
#[doc = "Watch Dog Trim - Delta voltage below steady state level\n0x0 - 50mV\n0x1 - 75mV\n0x2 - 100mV\n0x3 - 125mV\n0x4 - 150mV\n0x5 - 175mV\n0x6 - 200mV\n0x7 - 225mV"]
#[inline(always)]
pub fn wdtrim(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, ClkTrimEcoCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,ClkTrimEcoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal.\n0x0 - 150mV\n0x1 - 175mV\n0x2 - 200mV\n0x3 - 225mV\n0x4 - 250mV\n0x5 - 275mV\n0x6 - 300mV\n0x7 - 325mV\n0x8 - 350mV\n0x9 - 375mV\n0xA - 400mV\n0xB - 425mV\n0xC - 450mV\n0xD - 475mV\n0xE - 500mV\n0xF - 525mV"]
#[inline(always)]
pub fn atrim(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, ClkTrimEcoCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0xf,1,0,u8,u8,ClkTrimEcoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Filter Trim - 3rd harmonic oscillation"]
#[inline(always)]
pub fn ftrim(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, ClkTrimEcoCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,ClkTrimEcoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Feedback resistor Trim"]
#[inline(always)]
pub fn rtrim(
self,
) -> crate::common::RegisterField<10, 0x3, 1, 0, u8, u8, ClkTrimEcoCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<10,0x3,1,0,u8,u8,ClkTrimEcoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Gain Trim - Startup time"]
#[inline(always)]
pub fn gtrim(
self,
) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, ClkTrimEcoCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<12,0x3,1,0,u8,u8,ClkTrimEcoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Current Trim"]
#[inline(always)]
pub fn itrim(
self,
) -> crate::common::RegisterField<16, 0x3f, 1, 0, u8, u8, ClkTrimEcoCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3f,1,0,u8,u8,ClkTrimEcoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkTrimEcoCtl {
#[inline(always)]
fn default() -> ClkTrimEcoCtl {
<crate::RegValueT<ClkTrimEcoCtl_SPEC> as RegisterValue<_>>::new(2031619)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkTrimPiloCtl_SPEC;
impl crate::sealed::RegSpec for ClkTrimPiloCtl_SPEC {
type DataType = u32;
}
#[doc = "PILO Trim Register"]
pub type ClkTrimPiloCtl = crate::RegValueT<ClkTrimPiloCtl_SPEC>;
impl ClkTrimPiloCtl {
#[doc = "Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz."]
#[inline(always)]
pub fn pilo_cfreq(
self,
) -> crate::common::RegisterField<0, 0x3f, 1, 0, u8, u8, ClkTrimPiloCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x3f,1,0,u8,u8,ClkTrimPiloCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Trim for current in oscillator block."]
#[inline(always)]
pub fn pilo_osc_trim(
self,
) -> crate::common::RegisterField<12, 0x7, 1, 0, u8, u8, ClkTrimPiloCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<12,0x7,1,0,u8,u8,ClkTrimPiloCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Trim for comparator bias current."]
#[inline(always)]
pub fn pilo_comp_trim(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, ClkTrimPiloCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3,1,0,u8,u8,ClkTrimPiloCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier"]
#[inline(always)]
pub fn pilo_nbias_trim(
self,
) -> crate::common::RegisterField<18, 0x3, 1, 0, u8, u8, ClkTrimPiloCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<18,0x3,1,0,u8,u8,ClkTrimPiloCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Trim for beta-multiplier branch current"]
#[inline(always)]
pub fn pilo_res_trim(
self,
) -> crate::common::RegisterField<20, 0x1f, 1, 0, u8, u8, ClkTrimPiloCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<20,0x1f,1,0,u8,u8,ClkTrimPiloCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Trim for beta-multiplier current slope"]
#[inline(always)]
pub fn pilo_islope_trim(
self,
) -> crate::common::RegisterField<26, 0x3, 1, 0, u8, u8, ClkTrimPiloCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<26,0x3,1,0,u8,u8,ClkTrimPiloCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Trim for VT-DIFF output (internal power supply)"]
#[inline(always)]
pub fn pilo_vtdiff_trim(
self,
) -> crate::common::RegisterField<28, 0x7, 1, 0, u8, u8, ClkTrimPiloCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<28,0x7,1,0,u8,u8,ClkTrimPiloCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClkTrimPiloCtl {
#[inline(always)]
fn default() -> ClkTrimPiloCtl {
<crate::RegValueT<ClkTrimPiloCtl_SPEC> as RegisterValue<_>>::new(17321999)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkTrimPiloCtl2_SPEC;
impl crate::sealed::RegSpec for ClkTrimPiloCtl2_SPEC {
type DataType = u32;
}
#[doc = "PILO Trim Register 2"]
pub type ClkTrimPiloCtl2 = crate::RegValueT<ClkTrimPiloCtl2_SPEC>;
impl ClkTrimPiloCtl2 {
#[doc = "Trim for voltage reference"]
#[inline(always)]
pub fn pilo_vref_trim(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ClkTrimPiloCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,ClkTrimPiloCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Trim for beta-multiplier current reference"]
#[inline(always)]
pub fn pilo_irefbm_trim(
self,
) -> crate::common::RegisterField<8, 0x1f, 1, 0, u8, u8, ClkTrimPiloCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x1f,1,0,u8,u8,ClkTrimPiloCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Trim for current reference"]
#[inline(always)]
pub fn pilo_iref_trim(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, ClkTrimPiloCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
16,
0xff,
1,
0,
u8,
u8,
ClkTrimPiloCtl2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ClkTrimPiloCtl2 {
#[inline(always)]
fn default() -> ClkTrimPiloCtl2 {
<crate::RegValueT<ClkTrimPiloCtl2_SPEC> as RegisterValue<_>>::new(14291168)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClkTrimPiloCtl3_SPEC;
impl crate::sealed::RegSpec for ClkTrimPiloCtl3_SPEC {
type DataType = u32;
}
#[doc = "PILO Trim Register 3"]
pub type ClkTrimPiloCtl3 = crate::RegValueT<ClkTrimPiloCtl3_SPEC>;
impl ClkTrimPiloCtl3 {
#[doc = "Engineering options for PILO circuits\n0: Short vdda to vpwr\n1: Beta:mult current change\n2: Iref generation Ptat current addition\n3: Disable current path in secondary Beta:mult startup circuit\n4: Double oscillator current\n5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block\n6: Spare\n7: Ptat component increase in Iref\n8: vpwr_rc and vpwr_dig_rc shorting testmode\n9: Switch b/w psub connection for cascode nfet for vref generation\n10: Switch between sub:threshold and deep:sub:threshold stacks in comparator.\n15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy."]
#[inline(always)]
pub fn pilo_engopt(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ClkTrimPiloCtl3_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ClkTrimPiloCtl3_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ClkTrimPiloCtl3 {
#[inline(always)]
fn default() -> ClkTrimPiloCtl3 {
<crate::RegValueT<ClkTrimPiloCtl3_SPEC> as RegisterValue<_>>::new(18432)
}
}
#[doc = "Multi-Counter Watchdog Timer"]
#[non_exhaustive]
pub struct _McwdtStruct;
#[doc = "Multi-Counter Watchdog Timer"]
pub type McwdtStruct = &'static _McwdtStruct;
unsafe impl ::core::marker::Sync for _McwdtStruct {}
impl _McwdtStruct {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "Multi-Counter Watchdog Sub-counters 0/1"]
#[inline(always)]
pub const fn mcwdt_cntlow(
&self,
) -> &'static crate::common::Reg<mcwdt_struct::McwdtCntlow_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<mcwdt_struct::McwdtCntlow_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "Multi-Counter Watchdog Sub-counter 2"]
#[inline(always)]
pub const fn mcwdt_cnthigh(
&self,
) -> &'static crate::common::Reg<mcwdt_struct::McwdtCnthigh_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<mcwdt_struct::McwdtCnthigh_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(8usize),
)
}
}
#[doc = "Multi-Counter Watchdog Counter Match Register"]
#[inline(always)]
pub const fn mcwdt_match(
&self,
) -> &'static crate::common::Reg<mcwdt_struct::McwdtMatch_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<mcwdt_struct::McwdtMatch_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(12usize),
)
}
}
#[doc = "Multi-Counter Watchdog Counter Configuration"]
#[inline(always)]
pub const fn mcwdt_config(
&self,
) -> &'static crate::common::Reg<mcwdt_struct::McwdtConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<mcwdt_struct::McwdtConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16usize),
)
}
}
#[doc = "Multi-Counter Watchdog Counter Control"]
#[inline(always)]
pub const fn mcwdt_ctl(
&self,
) -> &'static crate::common::Reg<mcwdt_struct::McwdtCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<mcwdt_struct::McwdtCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(20usize),
)
}
}
#[doc = "Multi-Counter Watchdog Counter Interrupt Register"]
#[inline(always)]
pub const fn mcwdt_intr(
&self,
) -> &'static crate::common::Reg<mcwdt_struct::McwdtIntr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<mcwdt_struct::McwdtIntr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(24usize),
)
}
}
#[doc = "Multi-Counter Watchdog Counter Interrupt Set Register"]
#[inline(always)]
pub const fn mcwdt_intr_set(
&self,
) -> &'static crate::common::Reg<mcwdt_struct::McwdtIntrSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<mcwdt_struct::McwdtIntrSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(28usize),
)
}
}
#[doc = "Multi-Counter Watchdog Counter Interrupt Mask Register"]
#[inline(always)]
pub const fn mcwdt_intr_mask(
&self,
) -> &'static crate::common::Reg<mcwdt_struct::McwdtIntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<mcwdt_struct::McwdtIntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "Multi-Counter Watchdog Counter Interrupt Masked Register"]
#[inline(always)]
pub const fn mcwdt_intr_masked(
&self,
) -> &'static crate::common::Reg<mcwdt_struct::McwdtIntrMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<mcwdt_struct::McwdtIntrMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
#[doc = "Multi-Counter Watchdog Counter Lock Register"]
#[inline(always)]
pub const fn mcwdt_lock(
&self,
) -> &'static crate::common::Reg<mcwdt_struct::McwdtLock_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<mcwdt_struct::McwdtLock_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(40usize),
)
}
}
}
pub mod mcwdt_struct {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct McwdtCntlow_SPEC;
impl crate::sealed::RegSpec for McwdtCntlow_SPEC {
type DataType = u32;
}
#[doc = "Multi-Counter Watchdog Sub-counters 0/1"]
pub type McwdtCntlow = crate::RegValueT<McwdtCntlow_SPEC>;
impl McwdtCntlow {
#[doc = "Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled."]
#[inline(always)]
pub fn wdt_ctr0(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
McwdtCntlow_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
McwdtCntlow_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled"]
#[inline(always)]
pub fn wdt_ctr1(
self,
) -> crate::common::RegisterField<
16,
0xffff,
1,
0,
u16,
u16,
McwdtCntlow_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0xffff,
1,
0,
u16,
u16,
McwdtCntlow_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for McwdtCntlow {
#[inline(always)]
fn default() -> McwdtCntlow {
<crate::RegValueT<McwdtCntlow_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct McwdtCnthigh_SPEC;
impl crate::sealed::RegSpec for McwdtCnthigh_SPEC {
type DataType = u32;
}
#[doc = "Multi-Counter Watchdog Sub-counter 2"]
pub type McwdtCnthigh = crate::RegValueT<McwdtCnthigh_SPEC>;
impl McwdtCnthigh {
#[doc = "Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled"]
#[inline(always)]
pub fn wdt_ctr2(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
McwdtCnthigh_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
McwdtCnthigh_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for McwdtCnthigh {
#[inline(always)]
fn default() -> McwdtCnthigh {
<crate::RegValueT<McwdtCnthigh_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct McwdtMatch_SPEC;
impl crate::sealed::RegSpec for McwdtMatch_SPEC {
type DataType = u32;
}
#[doc = "Multi-Counter Watchdog Counter Match Register"]
pub type McwdtMatch = crate::RegValueT<McwdtMatch_SPEC>;
impl McwdtMatch {
#[doc = "Match value for sub-counter 0 of this MCWDT"]
#[inline(always)]
pub fn wdt_match0(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
McwdtMatch_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
McwdtMatch_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Match value for sub-counter 1 of this MCWDT"]
#[inline(always)]
pub fn wdt_match1(
self,
) -> crate::common::RegisterField<
16,
0xffff,
1,
0,
u16,
u16,
McwdtMatch_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0xffff,
1,
0,
u16,
u16,
McwdtMatch_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for McwdtMatch {
#[inline(always)]
fn default() -> McwdtMatch {
<crate::RegValueT<McwdtMatch_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct McwdtConfig_SPEC;
impl crate::sealed::RegSpec for McwdtConfig_SPEC {
type DataType = u32;
}
#[doc = "Multi-Counter Watchdog Counter Configuration"]
pub type McwdtConfig = crate::RegValueT<McwdtConfig_SPEC>;
impl McwdtConfig {
#[doc = "Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0)."]
#[inline(always)]
pub fn wdt_mode0(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
mcwdt_config::WdtMode0,
mcwdt_config::WdtMode0,
McwdtConfig_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
mcwdt_config::WdtMode0,
mcwdt_config::WdtMode0,
McwdtConfig_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1).\n0: Free running counter\n1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1."]
#[inline(always)]
pub fn wdt_clear0(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, McwdtConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,McwdtConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0.\n0: Independent counters\n1: Cascaded counters"]
#[inline(always)]
pub fn wdt_cascade0_1(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, McwdtConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,McwdtConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1)."]
#[inline(always)]
pub fn wdt_mode1(
self,
) -> crate::common::RegisterField<
8,
0x3,
1,
0,
mcwdt_config::WdtMode1,
mcwdt_config::WdtMode1,
McwdtConfig_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0x3,
1,
0,
mcwdt_config::WdtMode1,
mcwdt_config::WdtMode1,
McwdtConfig_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1).\n0: Free running counter\n1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1."]
#[inline(always)]
pub fn wdt_clear1(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, McwdtConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<10,1,0,McwdtConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters.\n0: Independent counters\n1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1."]
#[inline(always)]
pub fn wdt_cascade1_2(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, McwdtConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<11,1,0,McwdtConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Watchdog Counter 2 Mode."]
#[inline(always)]
pub fn wdt_mode2(
self,
) -> crate::common::RegisterField<
16,
0x1,
1,
0,
mcwdt_config::WdtMode2,
mcwdt_config::WdtMode2,
McwdtConfig_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0x1,
1,
0,
mcwdt_config::WdtMode2,
mcwdt_config::WdtMode2,
McwdtConfig_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Bit to observe for WDT_INT2:\n0: Assert after bit0 of WDT_CTR2 toggles (one int every tick)\n...\n31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks)"]
#[inline(always)]
pub fn wdt_bits2(
self,
) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, McwdtConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
24,
0x1f,
1,
0,
u8,
u8,
McwdtConfig_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for McwdtConfig {
#[inline(always)]
fn default() -> McwdtConfig {
<crate::RegValueT<McwdtConfig_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod mcwdt_config {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct WdtMode0_SPEC;
pub type WdtMode0 = crate::EnumBitfieldStruct<u8, WdtMode0_SPEC>;
impl WdtMode0 {
#[doc = "Do nothing"]
pub const NOTHING: Self = Self::new(0);
#[doc = "Assert WDT_INTx"]
pub const INT: Self = Self::new(1);
#[doc = "Assert WDT Reset"]
pub const RESET: Self = Self::new(2);
#[doc = "Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt"]
pub const INT_THEN_RESET: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct WdtMode1_SPEC;
pub type WdtMode1 = crate::EnumBitfieldStruct<u8, WdtMode1_SPEC>;
impl WdtMode1 {
#[doc = "Do nothing"]
pub const NOTHING: Self = Self::new(0);
#[doc = "Assert WDT_INTx"]
pub const INT: Self = Self::new(1);
#[doc = "Assert WDT Reset"]
pub const RESET: Self = Self::new(2);
#[doc = "Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt"]
pub const INT_THEN_RESET: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct WdtMode2_SPEC;
pub type WdtMode2 = crate::EnumBitfieldStruct<u8, WdtMode2_SPEC>;
impl WdtMode2 {
#[doc = "Free running counter with no interrupt requests"]
pub const NOTHING: Self = Self::new(0);
#[doc = "Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2)."]
pub const INT: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct McwdtCtl_SPEC;
impl crate::sealed::RegSpec for McwdtCtl_SPEC {
type DataType = u32;
}
#[doc = "Multi-Counter Watchdog Counter Control"]
pub type McwdtCtl = crate::RegValueT<McwdtCtl_SPEC>;
impl McwdtCtl {
#[doc = "Enable subcounter 0. May take up to 2 LFCLK cycles to take effect.\n0: Counter is disabled (not clocked)\n1: Counter is enabled (counting up)"]
#[inline(always)]
pub fn wdt_enable0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, McwdtCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,McwdtCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles."]
#[inline(always)]
pub fn wdt_enabled0(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, McwdtCtl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,McwdtCtl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect."]
#[inline(always)]
pub fn wdt_reset0(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, McwdtCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,McwdtCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable subcounter 1. May take up to 2 LFCLK cycles to take effect.\n0: Counter is disabled (not clocked)\n1: Counter is enabled (counting up)"]
#[inline(always)]
pub fn wdt_enable1(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, McwdtCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,McwdtCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles."]
#[inline(always)]
pub fn wdt_enabled1(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, McwdtCtl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<9,1,0,McwdtCtl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect."]
#[inline(always)]
pub fn wdt_reset1(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, McwdtCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,McwdtCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable subcounter 2. May take up to 2 LFCLK cycles to take effect.\n0: Counter is disabled (not clocked)\n1: Counter is enabled (counting up)"]
#[inline(always)]
pub fn wdt_enable2(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, McwdtCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,McwdtCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles."]
#[inline(always)]
pub fn wdt_enabled2(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, McwdtCtl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<17,1,0,McwdtCtl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Resets counter 2 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect."]
#[inline(always)]
pub fn wdt_reset2(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, McwdtCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,McwdtCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for McwdtCtl {
#[inline(always)]
fn default() -> McwdtCtl {
<crate::RegValueT<McwdtCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct McwdtIntr_SPEC;
impl crate::sealed::RegSpec for McwdtIntr_SPEC {
type DataType = u32;
}
#[doc = "Multi-Counter Watchdog Counter Interrupt Register"]
pub type McwdtIntr = crate::RegValueT<McwdtIntr_SPEC>;
impl McwdtIntr {
#[doc = "MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3."]
#[inline(always)]
pub fn mcwdt_int0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, McwdtIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,McwdtIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3."]
#[inline(always)]
pub fn mcwdt_int1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, McwdtIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,McwdtIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3."]
#[inline(always)]
pub fn mcwdt_int2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, McwdtIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,McwdtIntr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for McwdtIntr {
#[inline(always)]
fn default() -> McwdtIntr {
<crate::RegValueT<McwdtIntr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct McwdtIntrSet_SPEC;
impl crate::sealed::RegSpec for McwdtIntrSet_SPEC {
type DataType = u32;
}
#[doc = "Multi-Counter Watchdog Counter Interrupt Set Register"]
pub type McwdtIntrSet = crate::RegValueT<McwdtIntrSet_SPEC>;
impl McwdtIntrSet {
#[doc = "Set interrupt for MCWDT_INT0"]
#[inline(always)]
pub fn mcwdt_int0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, McwdtIntrSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,McwdtIntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set interrupt for MCWDT_INT1"]
#[inline(always)]
pub fn mcwdt_int1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, McwdtIntrSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,McwdtIntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set interrupt for MCWDT_INT2"]
#[inline(always)]
pub fn mcwdt_int2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, McwdtIntrSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,McwdtIntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for McwdtIntrSet {
#[inline(always)]
fn default() -> McwdtIntrSet {
<crate::RegValueT<McwdtIntrSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct McwdtIntrMask_SPEC;
impl crate::sealed::RegSpec for McwdtIntrMask_SPEC {
type DataType = u32;
}
#[doc = "Multi-Counter Watchdog Counter Interrupt Mask Register"]
pub type McwdtIntrMask = crate::RegValueT<McwdtIntrMask_SPEC>;
impl McwdtIntrMask {
#[doc = "Interrupt Mask for sub-counter 0. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1."]
#[inline(always)]
pub fn mcwdt_int0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, McwdtIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,McwdtIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Interrupt Mask for sub-counter 1. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1."]
#[inline(always)]
pub fn mcwdt_int1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, McwdtIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,McwdtIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Interrupt Mask for sub-counter 2. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1."]
#[inline(always)]
pub fn mcwdt_int2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, McwdtIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,McwdtIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for McwdtIntrMask {
#[inline(always)]
fn default() -> McwdtIntrMask {
<crate::RegValueT<McwdtIntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct McwdtIntrMasked_SPEC;
impl crate::sealed::RegSpec for McwdtIntrMasked_SPEC {
type DataType = u32;
}
#[doc = "Multi-Counter Watchdog Counter Interrupt Masked Register"]
pub type McwdtIntrMasked = crate::RegValueT<McwdtIntrMasked_SPEC>;
impl McwdtIntrMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn mcwdt_int0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, McwdtIntrMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<0,1,0,McwdtIntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn mcwdt_int1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, McwdtIntrMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<1,1,0,McwdtIntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn mcwdt_int2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, McwdtIntrMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<2,1,0,McwdtIntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for McwdtIntrMasked {
#[inline(always)]
fn default() -> McwdtIntrMasked {
<crate::RegValueT<McwdtIntrMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct McwdtLock_SPEC;
impl crate::sealed::RegSpec for McwdtLock_SPEC {
type DataType = u32;
}
#[doc = "Multi-Counter Watchdog Counter Lock Register"]
pub type McwdtLock = crate::RegValueT<McwdtLock_SPEC>;
impl McwdtLock {
#[doc = "Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock.\nNote that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that."]
#[inline(always)]
pub fn mcwdt_lock(
self,
) -> crate::common::RegisterField<
30,
0x3,
1,
0,
mcwdt_lock::McwdtLock,
mcwdt_lock::McwdtLock,
McwdtLock_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
30,
0x3,
1,
0,
mcwdt_lock::McwdtLock,
mcwdt_lock::McwdtLock,
McwdtLock_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for McwdtLock {
#[inline(always)]
fn default() -> McwdtLock {
<crate::RegValueT<McwdtLock_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod mcwdt_lock {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct McwdtLock_SPEC;
pub type McwdtLock = crate::EnumBitfieldStruct<u8, McwdtLock_SPEC>;
impl McwdtLock {
#[doc = "No effect"]
pub const NO_CHG: Self = Self::new(0);
#[doc = "Clears bit 0"]
pub const CLR_0: Self = Self::new(1);
#[doc = "Clears bit 1"]
pub const CLR_1: Self = Self::new(2);
#[doc = "Sets both bits 0 and 1"]
pub const SET_01: Self = Self::new(3);
}
}
}