/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"Programmable IO configuration"]
unsafe impl ::core::marker::Send for super::Smartio {}
unsafe impl ::core::marker::Sync for super::Smartio {}
impl super::Smartio {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "Programmable IO port registers"]
#[inline(always)]
pub fn prt(
self,
) -> &'static crate::common::ClusterRegisterArray<crate::smartio::_Prt, 10, 0x100> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x0usize))
}
}
}
#[doc = "Programmable IO port registers"]
#[non_exhaustive]
pub struct _Prt;
#[doc = "Programmable IO port registers"]
pub type Prt = &'static _Prt;
unsafe impl ::core::marker::Sync for _Prt {}
impl _Prt {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "Control register"]
#[inline(always)]
pub const fn ctl(&self) -> &'static crate::common::Reg<prt::Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Synchronization control register"]
#[inline(always)]
pub const fn sync_ctl(
&self,
) -> &'static crate::common::Reg<prt::SyncCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::SyncCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16usize),
)
}
}
#[doc = "LUT component input selection"]
#[inline(always)]
pub const fn lut_sel(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<prt::LutSel_SPEC, crate::common::RW>,
8,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x20usize))
}
}
#[doc = "LUT component control register"]
#[inline(always)]
pub const fn lut_ctl(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<prt::LutCtl_SPEC, crate::common::RW>,
8,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x40usize))
}
}
#[doc = "Data unit component input selection"]
#[inline(always)]
pub const fn du_sel(&self) -> &'static crate::common::Reg<prt::DuSel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::DuSel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(192usize),
)
}
}
#[doc = "Data unit component control register"]
#[inline(always)]
pub const fn du_ctl(&self) -> &'static crate::common::Reg<prt::DuCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::DuCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(196usize),
)
}
}
#[doc = "Data register"]
#[inline(always)]
pub const fn data(&self) -> &'static crate::common::Reg<prt::Data_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::Data_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(240usize),
)
}
}
}
pub mod prt {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctl_SPEC;
impl crate::sealed::RegSpec for Ctl_SPEC {
type DataType = u32;
}
#[doc = "Control register"]
pub type Ctl = crate::RegValueT<Ctl_SPEC>;
impl Ctl {
#[doc = "Bypass of the programmable IO, one bit for each IO pin: BYPASS\\[i\\] is for IO pin i. When ENABLED is \'1\', this field is used. When ENABLED is \'0\', this field is NOT used and SMARTIO fabric is always bypassed.\n\'0\': No bypass (programmable SMARTIO fabric is exposed). \n\'1\': Bypass (programmable SMARTIOIO fabric is hidden)."]
#[inline(always)]
pub fn bypass(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Clock (\'clk_fabric\') and reset (\'rst_fabric_n\') source selection:\n\'0\': io_data_in\\[0\\]/\'1\'.\n...\n\'7\': io_data_in\\[7\\]/\'1\'.\n\'8\': chip_data\\[0\\]/\'1\'.\n...\n\'15\': chip_data\\[7\\]/\'1\'.\n\'16\': clk_smartio/rst_sys_act_n. Used for both Active functionality synchronous logic on \'clk_smartio\'. This selection is intended for synchronous operation on a PCLK specified clock frequency (\'clock_smartio_pos_en\'). Note that the fabric\'s clocked elements are frequency aligned, but NOT phase aligned to \'clk_sys\'. \n\'17\': clk_smartio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on \'clk_smartio\' (note that \'clk_smartio\' is NOT available in DeepSleep and Hibernate power modes). This selection is intended for synchronous operation on a PCLK specified clock frequency (\'clock_smartio_pos_en\'). Note that the fabric\'s clocked elements are frequency aligned, but NOT phase aligned to \'clk_sys\'. \n\'18\': Same as \'17\'. Note that the M0S8 SMARTIO version used the Hibernate reset for this value, but the MXS40 SMARTIO version does not support Hibernate functionality. \n\'19\': clk_lf/rst_lf_dpslp_n (note that \'clk_lf\' is available in DeepSleep power mode). This selection is intended for synchronous operation on\'clk_lf\'. Note that the fabric\'s clocked elements are frequency aligned, but NOT phase aligned to other \'clk_lf\' clocked elements.\n\'20\'-\'30\': Clock source is constant \'0\'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption.\n\'31\': asynchronous mode/\'1\'. Select this when clockless operation is configured.\n\nNOTE: Two positive edges of the selected clock are required for the block to be enabled (to deactivate reset). In asynchronous (clockless) mode clk_sys is used to enable the block, but is not available for clocking."]
#[inline(always)]
pub fn clock_src(
self,
) -> crate::common::RegisterField<8, 0x1f, 1, 0, u8, u8, Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x1f,1,0,u8,u8,Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep output functionality on these IO pads. This field is used to control the hold override functionality from the SMARTIO:\n\'0\': The HSIOM controls the IO cell hold override functionality (\'hsiom_hld_ovr\').\n\'1\': The SMARTIO controls the IO cel hold override functionality:\n- In bypass mode (ENABLED is \'0\' or BYPASS\\[i\\] is \'1\'), the HSIOM control is used.\n- In NON bypass mode (ENABLED is \'1\' and BYPASS\\[i\\] is \'0\'), the SMARTIO sets hold override to \'pwr_hld_ovr_hib\' to enable SMARTIO functionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode)."]
#[inline(always)]
pub fn hld_ovr(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24, 1, 0, Ctl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Enable for pipeline register:\n\'0\': Disabled (register is bypassed).\n\'1\': Enabled."]
#[inline(always)]
pub fn pipeline_en(
self,
) -> crate::common::RegisterFieldBool<25, 1, 0, Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<25, 1, 0, Ctl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Enable for programmable IO. Should only be set to \'1\' when the programmable IO is completely configured:\n\'0\': Disabled (signals are bypassed; behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated.\n\nIf the IP is disabled:\n- The PIPELINE_EN register field should be set to \'1\', to ensure low power consumption by preventing combinatorial loops.\n- The CLOCK_SRC register field should be set to \'20\'-\'30\' (clock is constant \'0\'), to ensure low power consumption.\n\n\'1\': Enabled. Once enabled, it takes 3 \'clk_fabric\' clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins\' input synchronizer states are flushed when the fabric is fully functional."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31, 1, 0, Ctl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Ctl {
#[inline(always)]
fn default() -> Ctl {
<crate::RegValueT<Ctl_SPEC> as RegisterValue<_>>::new(33559552)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SyncCtl_SPEC;
impl crate::sealed::RegSpec for SyncCtl_SPEC {
type DataType = u32;
}
#[doc = "Synchronization control register"]
pub type SyncCtl = crate::RegValueT<SyncCtl_SPEC>;
impl SyncCtl {
#[doc = "Synchronization of the IO pin input signals to \'clk_fabric\', one bit for each IO pin: IO_SYNC_EN\\[i\\] is for IO pin i.\n\'0\': No synchronization.\n\'1\': Synchronization."]
#[inline(always)]
pub fn io_sync_en(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, SyncCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,SyncCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Synchronization of the chip input signals to \'clk_fabric\', one bit for each input: CHIP_SYNC_EN\\[i\\] is for input i.\n\'0\': No synchronization.\n\'1\': Synchronization."]
#[inline(always)]
pub fn chip_sync_en(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, SyncCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,SyncCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SyncCtl {
#[inline(always)]
fn default() -> SyncCtl {
<crate::RegValueT<SyncCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LutSel_SPEC;
impl crate::sealed::RegSpec for LutSel_SPEC {
type DataType = u32;
}
#[doc = "LUT component input selection"]
pub type LutSel = crate::RegValueT<LutSel_SPEC>;
impl LutSel {
#[doc = "LUT input signal \'tr0_in\' source selection:\n\'0\': Data unit output.\n\'1\': LUT 1 output.\n\'2\': LUT 2 output.\n\'3\': LUT 3 output.\n\'4\': LUT 4 output.\n\'5\': LUT 5 output.\n\'6\': LUT 6 output.\n\'7\': LUT 7 output.\n\'8\': chip_data\\[0\\] (for LUTs 0, 1, 2, 3); chip_data\\[4\\] (for LUTs 4, 5, 6, 7).\n\'9\': chip_data\\[1\\] (for LUTs 0, 1, 2, 3); chip_data\\[5\\] (for LUTs 4, 5, 6, 7).\n\'10\': chip_data\\[2\\] (for LUTs 0, 1, 2, 3); chip_data\\[6\\] (for LUTs 4, 5, 6, 7).\n\'11\': chip_data\\[3\\] (for LUTs 0, 1, 2, 3); chip_data\\[7\\] (for LUTs 4, 5, 6, 7).\n\'12\': io_data_in\\[0\\] (for LUTs 0, 1, 2, 3); io_data_in\\[4\\] (for LUTs 4, 5, 6, 7).\n\'13\': io_data_in\\[1\\] (for LUTs 0, 1, 2, 3); io_data_in\\[5\\] (for LUTs 4, 5, 6, 7).\n\'14\': io_data_in\\[2\\] (for LUTs 0, 1, 2, 3); io_data_in\\[6\\] (for LUTs 4, 5, 6, 7).\n\'15\': io_data_in\\[3\\] (for LUTs 0, 1, 2, 3); io_data_in\\[7\\] (for LUTs 4, 5, 6, 7)."]
#[inline(always)]
pub fn lut_tr0_sel(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, LutSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,LutSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "LUT input signal \'tr1_in\' source selection:\n\'0\': LUT 0 output.\n\'1\': LUT 1 output.\n\'2\': LUT 2 output.\n\'3\': LUT 3 output.\n\'4\': LUT 4 output.\n\'5\': LUT 5 output.\n\'6\': LUT 6 output.\n\'7\': LUT 7 output.\n\'8\': chip_data\\[0\\] (for LUTs 0, 1, 2, 3); chip_data\\[4\\] (for LUTs 4, 5, 6, 7).\n\'9\': chip_data\\[1\\] (for LUTs 0, 1, 2, 3); chip_data\\[5\\] (for LUTs 4, 5, 6, 7).\n\'10\': chip_data\\[2\\] (for LUTs 0, 1, 2, 3); chip_data\\[6\\] (for LUTs 4, 5, 6, 7).\n\'11\': chip_data\\[3\\] (for LUTs 0, 1, 2, 3); chip_data\\[7\\] (for LUTs 4, 5, 6, 7).\n\'12\': io_data_in\\[0\\] (for LUTs 0, 1, 2, 3); io_data_in\\[4\\] (for LUTs 4, 5, 6, 7).\n\'13\': io_data_in\\[1\\] (for LUTs 0, 1, 2, 3); io_data_in\\[5\\] (for LUTs 4, 5, 6, 7).\n\'14\': io_data_in\\[2\\] (for LUTs 0, 1, 2, 3); io_data_in\\[6\\] (for LUTs 4, 5, 6, 7).\n\'15\': io_data_in\\[3\\] (for LUTs 0, 1, 2, 3); io_data_in\\[7\\] (for LUTs 4, 5, 6, 7)."]
#[inline(always)]
pub fn lut_tr1_sel(
self,
) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, LutSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xf,1,0,u8,u8,LutSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "LUT input signal \'tr2_in\' source selection. Encoding is the same as for LUT_TR1_SEL."]
#[inline(always)]
pub fn lut_tr2_sel(
self,
) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, LutSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xf,1,0,u8,u8,LutSel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for LutSel {
#[inline(always)]
fn default() -> LutSel {
<crate::RegValueT<LutSel_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LutCtl_SPEC;
impl crate::sealed::RegSpec for LutCtl_SPEC {
type DataType = u32;
}
#[doc = "LUT component control register"]
pub type LutCtl = crate::RegValueT<LutCtl_SPEC>;
impl LutCtl {
#[doc = "LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg)."]
#[inline(always)]
pub fn lut(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, LutCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,LutCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "LUT opcode specifies the LUT operation:\n\'0\': Combinatoral output, no feedback.\n tr_out = LUT\\[{tr2_in, tr1_in, tr0_in}\\].\n\'1\': Combinatorial output, feedback.\n tr_out = LUT\\[{lut_reg, tr1_in, tr0_in}\\].\nOn clock:\n lut_reg <= tr_in2.\n\'2\': Sequential output, no feedback.\n temp = LUT\\[{tr2_in, tr1_in, tr0_in}\\].\n tr_out = lut_reg.\nOn clock:\n lut_reg <= temp.\n\'3\': Register with asynchronous set and reset.\n tr_out = lut_reg.\n enable = (tr2_in ^ LUT\\[4\\]) | LUT\\[5\\].\n set = enable & (tr1_in ^ LUT\\[2\\]) & LUT\\[3\\].\n clr = enable & (tr0_in ^ LUT\\[0\\]) & LUT\\[1\\].\nAsynchronously (no clock required):\n lut_reg <= if (clr) \'0\' else if (set) \'1\'"]
#[inline(always)]
pub fn lut_opc(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, LutCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,LutCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for LutCtl {
#[inline(always)]
fn default() -> LutCtl {
<crate::RegValueT<LutCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DuSel_SPEC;
impl crate::sealed::RegSpec for DuSel_SPEC {
type DataType = u32;
}
#[doc = "Data unit component input selection"]
pub type DuSel = crate::RegValueT<DuSel_SPEC>;
impl DuSel {
#[doc = "Data unit input signal \'tr0_in\' source selection:\n\'0\': Constant \'0\'.\n\'1\': Constant \'1\'.\n\'2\': Data unit output.\n\'10-3\': LUT 7 - 0 outputs.\nOtherwise: Undefined."]
#[inline(always)]
pub fn du_tr0_sel(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, DuSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,DuSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Data unit input signal \'tr1_in\' source selection. Encoding is the same as for DU_TR0_SEL."]
#[inline(always)]
pub fn du_tr1_sel(
self,
) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, DuSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xf,1,0,u8,u8,DuSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Data unit input signal \'tr2_in\' source selection. Encoding is the same as for DU_TR0_SEL."]
#[inline(always)]
pub fn du_tr2_sel(
self,
) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, DuSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xf,1,0,u8,u8,DuSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Data unit input data \'data0_in\' source selection:\n\'0\': Constant \'0\'.\n\'1\': chip_data\\[7:0\\].\n\'2\': io_data_in\\[7:0\\].\n\'3\': DATA.DATA MMIO register field."]
#[inline(always)]
pub fn du_data0_sel(
self,
) -> crate::common::RegisterField<24, 0x3, 1, 0, u8, u8, DuSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0x3,1,0,u8,u8,DuSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Data unit input data \'data1_in\' source selection. Encoding is the same as for DU_DATA0_SEL."]
#[inline(always)]
pub fn du_data1_sel(
self,
) -> crate::common::RegisterField<28, 0x3, 1, 0, u8, u8, DuSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<28,0x3,1,0,u8,u8,DuSel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for DuSel {
#[inline(always)]
fn default() -> DuSel {
<crate::RegValueT<DuSel_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DuCtl_SPEC;
impl crate::sealed::RegSpec for DuCtl_SPEC {
type DataType = u32;
}
#[doc = "Data unit component control register"]
pub type DuCtl = crate::RegValueT<DuCtl_SPEC>;
impl DuCtl {
#[doc = "Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits."]
#[inline(always)]
pub fn du_size(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, DuCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,DuCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Data unit opcode specifies the data unit operation:\n\'1\': INCR\n\'2\': DECR\n\'3\': INCR_WRAP\n\'4\': DECR_WRAP\n\'5\': INCR_DECR\n\'6\': INCR_DECR_WRAP\n\'7\': ROR\n\'8\': SHR\n\'9\': AND_OR\n\'10\': SHR_MAJ3\n\'11\': SHR_EQL.\nOtherwise: Undefined."]
#[inline(always)]
pub fn du_opc(
self,
) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, DuCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xf,1,0,u8,u8,DuCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for DuCtl {
#[inline(always)]
fn default() -> DuCtl {
<crate::RegValueT<DuCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Data_SPEC;
impl crate::sealed::RegSpec for Data_SPEC {
type DataType = u32;
}
#[doc = "Data register"]
pub type Data = crate::RegValueT<Data_SPEC>;
impl Data {
#[doc = "Data unit input data source."]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Data_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Data_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Data {
#[inline(always)]
fn default() -> Data {
<crate::RegValueT<Data_SPEC> as RegisterValue<_>>::new(0)
}
}
}