/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"Timer/Counter/PWM"]
unsafe impl ::core::marker::Send for super::Tcpwm {}
unsafe impl ::core::marker::Sync for super::Tcpwm {}
impl super::Tcpwm {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "TCPWM control register"]
#[inline(always)]
pub const fn ctrl(&self) -> &'static crate::common::Reg<self::Ctrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Ctrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "TCPWM control clear register"]
#[inline(always)]
pub const fn ctrl_clr(
&self,
) -> &'static crate::common::Reg<self::CtrlClr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CtrlClr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "TCPWM control set register"]
#[inline(always)]
pub const fn ctrl_set(
&self,
) -> &'static crate::common::Reg<self::CtrlSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CtrlSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(8usize),
)
}
}
#[doc = "TCPWM capture command register"]
#[inline(always)]
pub const fn cmd_capture(
&self,
) -> &'static crate::common::Reg<self::CmdCapture_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CmdCapture_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(12usize),
)
}
}
#[doc = "TCPWM reload command register"]
#[inline(always)]
pub const fn cmd_reload(
&self,
) -> &'static crate::common::Reg<self::CmdReload_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CmdReload_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16usize),
)
}
}
#[doc = "TCPWM stop command register"]
#[inline(always)]
pub const fn cmd_stop(
&self,
) -> &'static crate::common::Reg<self::CmdStop_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CmdStop_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(20usize),
)
}
}
#[doc = "TCPWM start command register"]
#[inline(always)]
pub const fn cmd_start(
&self,
) -> &'static crate::common::Reg<self::CmdStart_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CmdStart_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(24usize),
)
}
}
#[doc = "TCPWM Counter interrupt cause register"]
#[inline(always)]
pub const fn intr_cause(
&self,
) -> &'static crate::common::Reg<self::IntrCause_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrCause_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(28usize),
)
}
}
#[doc = "Timer/Counter/PWM Counter Module"]
#[inline(always)]
pub fn cnt(self) -> &'static crate::common::ClusterRegisterArray<crate::tcpwm::_Cnt, 24, 0x40> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x100usize))
}
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctrl_SPEC;
impl crate::sealed::RegSpec for Ctrl_SPEC {
type DataType = u32;
}
#[doc = "TCPWM control register"]
pub type Ctrl = crate::RegValueT<Ctrl_SPEC>;
impl Ctrl {
#[doc = "Counter enables for counters 0 up to CNT_NR-1.\n\'0\': counter disabled.\n\'1\': counter enabled.\nCounter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes:\n- the associated counter triggers in the CMD register are set to \'0\'.\n- the counter\'s interrupt cause fields in counter\'s INTR register.\n- the counter\'s status fields in counter\'s STATUS register..\n- the counter\'s trigger outputs (\'tr_overflow\', \'tr_underflow\' and \'tr_compare_match\').\n- the counter\'s line outputs (\'line_out\' and \'line_compl_out\').\nIn multi-core environments, use the CTRL_SET/CTRL_CLR registers to avoid race-conditions on read-modify-write attempts to this register."]
#[inline(always)]
pub fn counter_enabled(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Ctrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ctrl {
#[inline(always)]
fn default() -> Ctrl {
<crate::RegValueT<Ctrl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CtrlClr_SPEC;
impl crate::sealed::RegSpec for CtrlClr_SPEC {
type DataType = u32;
}
#[doc = "TCPWM control clear register"]
pub type CtrlClr = crate::RegValueT<CtrlClr_SPEC>;
impl CtrlClr {
#[doc = "Alias of CTRL that only allows disabling of counters. A write access:\n\'0\': Does nothing.\n\'1\': Clears respective COUNTER_ENABLED field.\n\nA read access returns CTRL.COUNTER_ENABLED."]
#[inline(always)]
pub fn counter_enabled(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, CtrlClr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,CtrlClr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CtrlClr {
#[inline(always)]
fn default() -> CtrlClr {
<crate::RegValueT<CtrlClr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CtrlSet_SPEC;
impl crate::sealed::RegSpec for CtrlSet_SPEC {
type DataType = u32;
}
#[doc = "TCPWM control set register"]
pub type CtrlSet = crate::RegValueT<CtrlSet_SPEC>;
impl CtrlSet {
#[doc = "Alias of CTRL that only allows enabling of counters. A write access:\n\'0\': Does nothing.\n\'1\': Sets respective COUNTER_ENABLED field.\n\nA read access returns CTRL.COUNTER_ENABLED."]
#[inline(always)]
pub fn counter_enabled(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, CtrlSet_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,CtrlSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CtrlSet {
#[inline(always)]
fn default() -> CtrlSet {
<crate::RegValueT<CtrlSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CmdCapture_SPEC;
impl crate::sealed::RegSpec for CmdCapture_SPEC {
type DataType = u32;
}
#[doc = "TCPWM capture command register"]
pub type CmdCapture = crate::RegValueT<CmdCapture_SPEC>;
impl CmdCapture {
#[doc = "Counters SW capture trigger. When written with \'1\', a capture trigger is generated and the HW sets the field to \'0\' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.COUNTER_ENABLED, the field is immediately set to \'0\'."]
#[inline(always)]
pub fn counter_capture(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CmdCapture_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CmdCapture_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CmdCapture {
#[inline(always)]
fn default() -> CmdCapture {
<crate::RegValueT<CmdCapture_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CmdReload_SPEC;
impl crate::sealed::RegSpec for CmdReload_SPEC {
type DataType = u32;
}
#[doc = "TCPWM reload command register"]
pub type CmdReload = crate::RegValueT<CmdReload_SPEC>;
impl CmdReload {
#[doc = "Counters SW reload trigger. For HW behavior, see COUNTER_CAPTURE field."]
#[inline(always)]
pub fn counter_reload(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CmdReload_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CmdReload_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CmdReload {
#[inline(always)]
fn default() -> CmdReload {
<crate::RegValueT<CmdReload_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CmdStop_SPEC;
impl crate::sealed::RegSpec for CmdStop_SPEC {
type DataType = u32;
}
#[doc = "TCPWM stop command register"]
pub type CmdStop = crate::RegValueT<CmdStop_SPEC>;
impl CmdStop {
#[doc = "Counters SW stop trigger. For HW behavior, see COUNTER_CAPTURE field."]
#[inline(always)]
pub fn counter_stop(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, CmdStop_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,CmdStop_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CmdStop {
#[inline(always)]
fn default() -> CmdStop {
<crate::RegValueT<CmdStop_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CmdStart_SPEC;
impl crate::sealed::RegSpec for CmdStart_SPEC {
type DataType = u32;
}
#[doc = "TCPWM start command register"]
pub type CmdStart = crate::RegValueT<CmdStart_SPEC>;
impl CmdStart {
#[doc = "Counters SW start trigger. For HW behavior, see COUNTER_CAPTURE field."]
#[inline(always)]
pub fn counter_start(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, CmdStart_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CmdStart_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CmdStart {
#[inline(always)]
fn default() -> CmdStart {
<crate::RegValueT<CmdStart_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrCause_SPEC;
impl crate::sealed::RegSpec for IntrCause_SPEC {
type DataType = u32;
}
#[doc = "TCPWM Counter interrupt cause register"]
pub type IntrCause = crate::RegValueT<IntrCause_SPEC>;
impl IntrCause {
#[doc = "Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED, the associated interrupt field is immediately set to \'0\'."]
#[inline(always)]
pub fn counter_int(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, IntrCause_SPEC, crate::common::R>
{
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
IntrCause_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for IntrCause {
#[inline(always)]
fn default() -> IntrCause {
<crate::RegValueT<IntrCause_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc = "Timer/Counter/PWM Counter Module"]
#[non_exhaustive]
pub struct _Cnt;
#[doc = "Timer/Counter/PWM Counter Module"]
pub type Cnt = &'static _Cnt;
unsafe impl ::core::marker::Sync for _Cnt {}
impl _Cnt {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "Counter control register"]
#[inline(always)]
pub const fn ctrl(&self) -> &'static crate::common::Reg<cnt::Ctrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<cnt::Ctrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Counter status register"]
#[inline(always)]
pub const fn status(&self) -> &'static crate::common::Reg<cnt::Status_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<cnt::Status_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "Counter count register"]
#[inline(always)]
pub const fn counter(
&self,
) -> &'static crate::common::Reg<cnt::Counter_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<cnt::Counter_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(8usize),
)
}
}
#[doc = "Counter compare/capture register"]
#[inline(always)]
pub const fn cc(&self) -> &'static crate::common::Reg<cnt::Cc_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<cnt::Cc_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(12usize),
)
}
}
#[doc = "Counter buffered compare/capture register"]
#[inline(always)]
pub const fn cc_buff(
&self,
) -> &'static crate::common::Reg<cnt::CcBuff_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<cnt::CcBuff_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16usize),
)
}
}
#[doc = "Counter period register"]
#[inline(always)]
pub const fn period(&self) -> &'static crate::common::Reg<cnt::Period_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<cnt::Period_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(20usize),
)
}
}
#[doc = "Counter buffered period register"]
#[inline(always)]
pub const fn period_buff(
&self,
) -> &'static crate::common::Reg<cnt::PeriodBuff_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<cnt::PeriodBuff_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(24usize),
)
}
}
#[doc = "Counter trigger control register 0"]
#[inline(always)]
pub const fn tr_ctrl0(
&self,
) -> &'static crate::common::Reg<cnt::TrCtrl0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<cnt::TrCtrl0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "Counter trigger control register 1"]
#[inline(always)]
pub const fn tr_ctrl1(
&self,
) -> &'static crate::common::Reg<cnt::TrCtrl1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<cnt::TrCtrl1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
#[doc = "Counter trigger control register 2"]
#[inline(always)]
pub const fn tr_ctrl2(
&self,
) -> &'static crate::common::Reg<cnt::TrCtrl2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<cnt::TrCtrl2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(40usize),
)
}
}
#[doc = "Interrupt request register"]
#[inline(always)]
pub const fn intr(&self) -> &'static crate::common::Reg<cnt::Intr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<cnt::Intr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(48usize),
)
}
}
#[doc = "Interrupt set request register"]
#[inline(always)]
pub const fn intr_set(
&self,
) -> &'static crate::common::Reg<cnt::IntrSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<cnt::IntrSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(52usize),
)
}
}
#[doc = "Interrupt mask register"]
#[inline(always)]
pub const fn intr_mask(
&self,
) -> &'static crate::common::Reg<cnt::IntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<cnt::IntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(56usize),
)
}
}
#[doc = "Interrupt masked request register"]
#[inline(always)]
pub const fn intr_masked(
&self,
) -> &'static crate::common::Reg<cnt::IntrMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<cnt::IntrMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(60usize),
)
}
}
}
pub mod cnt {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctrl_SPEC;
impl crate::sealed::RegSpec for Ctrl_SPEC {
type DataType = u32;
}
#[doc = "Counter control register"]
pub type Ctrl = crate::RegValueT<Ctrl_SPEC>;
impl Ctrl {
#[doc = "Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes.\nTimer mode:\n\'0\': never switch.\n\'1\': switch on a compare match event.\nPWM, PWM_DT, PWM_PR modes: \n\'0: never switch.\n\'1\': switch on a terminal count event with an actively pending switch event."]
#[inline(always)]
pub fn auto_reload_cc(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes.\n\'0\': never switch.\n\'1\': switch on a terminal count event with and actively pending switch event."]
#[inline(always)]
pub fn auto_reload_period(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Specifies asynchronous/synchronous kill behavior:\n\'1\': synchronous kill mode: the kill event disables the \'dt_line_out\' and \'dt_line_compl_out\' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE.\n\'0\': asynchronous kill mode: the kill event only disables the \'dt_line_out\' and \'dt_line_compl_out\' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. \n\nThis field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is \'0\'."]
#[inline(always)]
pub fn pwm_sync_kill(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Specifies whether the counter stops on a kill events:\n\'0\': kill event does NOT stop counter.\n\'1\': kill event stops counter.\n\nThis field has a function in PWM, PWM_DT and PWM_PR modes only."]
#[inline(always)]
pub fn pwm_stop_on_kill(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock."]
#[inline(always)]
pub fn generic(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Ctrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Determines counter direction."]
#[inline(always)]
pub fn up_down_mode(
self,
) -> crate::common::RegisterField<
16,
0x3,
1,
0,
ctrl::UpDownMode,
ctrl::UpDownMode,
Ctrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0x3,
1,
0,
ctrl::UpDownMode,
ctrl::UpDownMode,
Ctrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "When \'0\', counter runs continuous. When \'1\', counter is turned off by hardware when a terminal count event is generated."]
#[inline(always)]
pub fn one_shot(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "In QUAD mode selects quadrature encoding mode (X1/X2/X4).\nIn PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert \'dt_line_out\' and \'dt_line_compl_out\'. Inversion is the last step in generation of \'dt_line_out\' and \'dt_line_compl_out\'; i.e. a disabled output line \'dt_line_out\' has the value QUADRATURE_MODE\\[0\\] and a disabled output line \'dt_line_compl_out\' has the value QUADRATURE_MODE\\[1\\]."]
#[inline(always)]
pub fn quadrature_mode(
self,
) -> crate::common::RegisterField<
20,
0x3,
1,
0,
ctrl::QuadratureMode,
ctrl::QuadratureMode,
Ctrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
20,
0x3,
1,
0,
ctrl::QuadratureMode,
ctrl::QuadratureMode,
Ctrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Counter mode."]
#[inline(always)]
pub fn mode(
self,
) -> crate::common::RegisterField<
24,
0x7,
1,
0,
ctrl::Mode,
ctrl::Mode,
Ctrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
24,
0x7,
1,
0,
ctrl::Mode,
ctrl::Mode,
Ctrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Ctrl {
#[inline(always)]
fn default() -> Ctrl {
<crate::RegValueT<Ctrl_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod ctrl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct UpDownMode_SPEC;
pub type UpDownMode = crate::EnumBitfieldStruct<u8, UpDownMode_SPEC>;
impl UpDownMode {
#[doc = "Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD."]
pub const COUNT_UP: Self = Self::new(0);
#[doc = "Count down (to \'0\'). An underflow event is generated when the counter changes from a state in which COUNTER equals \'0\'. A terminal count event is generated when the counter changes from a state in which COUNTER equals \'0\'."]
pub const COUNT_DOWN: Self = Self::new(1);
#[doc = "Count up (to PERIOD), then count down (to \'0\'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals \'0\'. A terminal count event is generated when the counter changes from a state in which COUNTER equals \'0\'."]
pub const COUNT_UPDN_1: Self = Self::new(2);
#[doc = "Count up (to PERIOD), then count down (to \'0\'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals \'0\'. A terminal count event is generated when the counter changes from a state in which COUNTER equals \'0\' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates)."]
pub const COUNT_UPDN_2: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct QuadratureMode_SPEC;
pub type QuadratureMode = crate::EnumBitfieldStruct<u8, QuadratureMode_SPEC>;
impl QuadratureMode {
#[doc = "X1 encoding (QUAD mode)"]
pub const X_1: Self = Self::new(0);
#[doc = "X2 encoding (QUAD mode)"]
pub const X_2: Self = Self::new(1);
#[doc = "X4 encoding (QUAD mode)"]
pub const X_4: Self = Self::new(2);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Mode_SPEC;
pub type Mode = crate::EnumBitfieldStruct<u8, Mode_SPEC>;
impl Mode {
#[doc = "Timer mode"]
pub const TIMER: Self = Self::new(0);
#[doc = "Capture mode"]
pub const CAPTURE: Self = Self::new(2);
#[doc = "Quadrature encoding mode"]
pub const QUAD: Self = Self::new(3);
#[doc = "Pulse width modulation (PWM) mode"]
pub const PWM: Self = Self::new(4);
#[doc = "PWM with deadtime insertion mode"]
pub const PWM_DT: Self = Self::new(5);
#[doc = "Pseudo random pulse width modulation"]
pub const PWM_PR: Self = Self::new(6);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Status_SPEC;
impl crate::sealed::RegSpec for Status_SPEC {
type DataType = u32;
}
#[doc = "Counter status register"]
pub type Status = crate::RegValueT<Status_SPEC>;
impl Status {
#[doc = "When \'0\', counter is counting up. When \'1\', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: \'0\' when last incremented and \'1\' when last decremented."]
#[inline(always)]
pub fn down(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,Status_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality."]
#[inline(always)]
pub fn generic(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Status_SPEC, crate::common::R>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,Status_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "When \'0\', the counter is NOT running. When \'1\', the counter is running."]
#[inline(always)]
pub fn running(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31,1,0,Status_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Status {
#[inline(always)]
fn default() -> Status {
<crate::RegValueT<Status_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Counter_SPEC;
impl crate::sealed::RegSpec for Counter_SPEC {
type DataType = u32;
}
#[doc = "Counter count register"]
pub type Counter = crate::RegValueT<Counter_SPEC>;
impl Counter {
#[doc = "16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."]
#[inline(always)]
pub fn counter(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
Counter_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
Counter_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Counter {
#[inline(always)]
fn default() -> Counter {
<crate::RegValueT<Counter_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cc_SPEC;
impl crate::sealed::RegSpec for Cc_SPEC {
type DataType = u32;
}
#[doc = "Counter compare/capture register"]
pub type Cc = crate::RegValueT<Cc_SPEC>;
impl Cc {
#[doc = "In CAPTURE mode, captures the counter value. In other modes, compared to counter value."]
#[inline(always)]
pub fn cc(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Cc_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Cc_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cc {
#[inline(always)]
fn default() -> Cc {
<crate::RegValueT<Cc_SPEC> as RegisterValue<_>>::new(4294967295)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CcBuff_SPEC;
impl crate::sealed::RegSpec for CcBuff_SPEC {
type DataType = u32;
}
#[doc = "Counter buffered compare/capture register"]
pub type CcBuff = crate::RegValueT<CcBuff_SPEC>;
impl CcBuff {
#[doc = "Additional buffer for counter CC register."]
#[inline(always)]
pub fn cc(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CcBuff_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CcBuff_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CcBuff {
#[inline(always)]
fn default() -> CcBuff {
<crate::RegValueT<CcBuff_SPEC> as RegisterValue<_>>::new(4294967295)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Period_SPEC;
impl crate::sealed::RegSpec for Period_SPEC {
type DataType = u32;
}
#[doc = "Counter period register"]
pub type Period = crate::RegValueT<Period_SPEC>;
impl Period {
#[doc = "Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1."]
#[inline(always)]
pub fn period(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
Period_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
Period_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Period {
#[inline(always)]
fn default() -> Period {
<crate::RegValueT<Period_SPEC> as RegisterValue<_>>::new(4294967295)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PeriodBuff_SPEC;
impl crate::sealed::RegSpec for PeriodBuff_SPEC {
type DataType = u32;
}
#[doc = "Counter buffered period register"]
pub type PeriodBuff = crate::RegValueT<PeriodBuff_SPEC>;
impl PeriodBuff {
#[doc = "Additional buffer for counter PERIOD register."]
#[inline(always)]
pub fn period(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
PeriodBuff_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
PeriodBuff_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PeriodBuff {
#[inline(always)]
fn default() -> PeriodBuff {
<crate::RegValueT<PeriodBuff_SPEC> as RegisterValue<_>>::new(4294967295)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrCtrl0_SPEC;
impl crate::sealed::RegSpec for TrCtrl0_SPEC {
type DataType = u32;
}
#[doc = "Counter trigger control register 0"]
pub type TrCtrl0 = crate::RegValueT<TrCtrl0_SPEC>;
impl TrCtrl0 {
#[doc = "Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always \'0\' and input trigger is always \'1\'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts."]
#[inline(always)]
pub fn capture_sel(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, TrCtrl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,TrCtrl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always \'1\'."]
#[inline(always)]
pub fn count_sel(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, TrCtrl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0xf,1,0,u8,u8,TrCtrl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint)."]
#[inline(always)]
pub fn reload_sel(
self,
) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, TrCtrl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xf,1,0,u8,u8,TrCtrl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is \'0\') or stop the functionality (PWM_STOP_ON_KILL is \'1\'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is \'1\' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event."]
#[inline(always)]
pub fn stop_sel(
self,
) -> crate::common::RegisterField<12, 0xf, 1, 0, u8, u8, TrCtrl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<12,0xf,1,0,u8,u8,TrCtrl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B)."]
#[inline(always)]
pub fn start_sel(
self,
) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, TrCtrl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xf,1,0,u8,u8,TrCtrl0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TrCtrl0 {
#[inline(always)]
fn default() -> TrCtrl0 {
<crate::RegValueT<TrCtrl0_SPEC> as RegisterValue<_>>::new(16)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrCtrl1_SPEC;
impl crate::sealed::RegSpec for TrCtrl1_SPEC {
type DataType = u32;
}
#[doc = "Counter trigger control register 1"]
pub type TrCtrl1 = crate::RegValueT<TrCtrl1_SPEC>;
impl TrCtrl1 {
#[doc = "A capture event will copy the counter value into the CC register."]
#[inline(always)]
pub fn capture_edge(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
tr_ctrl1::CaptureEdge,
tr_ctrl1::CaptureEdge,
TrCtrl1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
tr_ctrl1::CaptureEdge,
tr_ctrl1::CaptureEdge,
TrCtrl1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "A counter event will increase or decrease the counter by \'1\'."]
#[inline(always)]
pub fn count_edge(
self,
) -> crate::common::RegisterField<
2,
0x3,
1,
0,
tr_ctrl1::CountEdge,
tr_ctrl1::CountEdge,
TrCtrl1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0x3,
1,
0,
tr_ctrl1::CountEdge,
tr_ctrl1::CountEdge,
TrCtrl1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "A reload event will initialize the counter. When counting up, the counter is initialized to \'0\'. When counting down, the counter is initialized with PERIOD."]
#[inline(always)]
pub fn reload_edge(
self,
) -> crate::common::RegisterField<
4,
0x3,
1,
0,
tr_ctrl1::ReloadEdge,
tr_ctrl1::ReloadEdge,
TrCtrl1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x3,
1,
0,
tr_ctrl1::ReloadEdge,
tr_ctrl1::ReloadEdge,
TrCtrl1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter."]
#[inline(always)]
pub fn stop_edge(
self,
) -> crate::common::RegisterField<
6,
0x3,
1,
0,
tr_ctrl1::StopEdge,
tr_ctrl1::StopEdge,
TrCtrl1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
6,
0x3,
1,
0,
tr_ctrl1::StopEdge,
tr_ctrl1::StopEdge,
TrCtrl1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does."]
#[inline(always)]
pub fn start_edge(
self,
) -> crate::common::RegisterField<
8,
0x3,
1,
0,
tr_ctrl1::StartEdge,
tr_ctrl1::StartEdge,
TrCtrl1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0x3,
1,
0,
tr_ctrl1::StartEdge,
tr_ctrl1::StartEdge,
TrCtrl1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for TrCtrl1 {
#[inline(always)]
fn default() -> TrCtrl1 {
<crate::RegValueT<TrCtrl1_SPEC> as RegisterValue<_>>::new(1023)
}
}
pub mod tr_ctrl1 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CaptureEdge_SPEC;
pub type CaptureEdge = crate::EnumBitfieldStruct<u8, CaptureEdge_SPEC>;
impl CaptureEdge {
#[doc = "Rising edge. Any rising edge generates an event."]
pub const RISING_EDGE: Self = Self::new(0);
#[doc = "Falling edge. Any falling edge generates an event."]
pub const FALLING_EDGE: Self = Self::new(1);
#[doc = "Rising AND falling edge. Any odd amount of edges generates an event."]
pub const BOTH_EDGES: Self = Self::new(2);
#[doc = "No edge detection, use trigger as is."]
pub const NO_EDGE_DET: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CountEdge_SPEC;
pub type CountEdge = crate::EnumBitfieldStruct<u8, CountEdge_SPEC>;
impl CountEdge {
#[doc = "Rising edge. Any rising edge generates an event."]
pub const RISING_EDGE: Self = Self::new(0);
#[doc = "Falling edge. Any falling edge generates an event."]
pub const FALLING_EDGE: Self = Self::new(1);
#[doc = "Rising AND falling edge. Any odd amount of edges generates an event."]
pub const BOTH_EDGES: Self = Self::new(2);
#[doc = "No edge detection, use trigger as is."]
pub const NO_EDGE_DET: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ReloadEdge_SPEC;
pub type ReloadEdge = crate::EnumBitfieldStruct<u8, ReloadEdge_SPEC>;
impl ReloadEdge {
#[doc = "Rising edge. Any rising edge generates an event."]
pub const RISING_EDGE: Self = Self::new(0);
#[doc = "Falling edge. Any falling edge generates an event."]
pub const FALLING_EDGE: Self = Self::new(1);
#[doc = "Rising AND falling edge. Any odd amount of edges generates an event."]
pub const BOTH_EDGES: Self = Self::new(2);
#[doc = "No edge detection, use trigger as is."]
pub const NO_EDGE_DET: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct StopEdge_SPEC;
pub type StopEdge = crate::EnumBitfieldStruct<u8, StopEdge_SPEC>;
impl StopEdge {
#[doc = "Rising edge. Any rising edge generates an event."]
pub const RISING_EDGE: Self = Self::new(0);
#[doc = "Falling edge. Any falling edge generates an event."]
pub const FALLING_EDGE: Self = Self::new(1);
#[doc = "Rising AND falling edge. Any odd amount of edges generates an event."]
pub const BOTH_EDGES: Self = Self::new(2);
#[doc = "No edge detection, use trigger as is."]
pub const NO_EDGE_DET: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct StartEdge_SPEC;
pub type StartEdge = crate::EnumBitfieldStruct<u8, StartEdge_SPEC>;
impl StartEdge {
#[doc = "Rising edge. Any rising edge generates an event."]
pub const RISING_EDGE: Self = Self::new(0);
#[doc = "Falling edge. Any falling edge generates an event."]
pub const FALLING_EDGE: Self = Self::new(1);
#[doc = "Rising AND falling edge. Any odd amount of edges generates an event."]
pub const BOTH_EDGES: Self = Self::new(2);
#[doc = "No edge detection, use trigger as is."]
pub const NO_EDGE_DET: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrCtrl2_SPEC;
impl crate::sealed::RegSpec for TrCtrl2_SPEC {
type DataType = u32;
}
#[doc = "Counter trigger control register 2"]
pub type TrCtrl2 = crate::RegValueT<TrCtrl2_SPEC>;
impl TrCtrl2 {
#[doc = "Determines the effect of a compare match event (COUNTER equals CC register) on the \'line_out\' output signals. Note that INVERT is especially useful for center aligned pulse width modulation.\nTo generate a duty cycle of 0 percent, the counter CC register should be set to \'0\'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register."]
#[inline(always)]
pub fn cc_match_mode(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
tr_ctrl2::CcMatchMode,
tr_ctrl2::CcMatchMode,
TrCtrl2_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
tr_ctrl2::CcMatchMode,
tr_ctrl2::CcMatchMode,
TrCtrl2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the \'line_out\' output signals."]
#[inline(always)]
pub fn overflow_mode(
self,
) -> crate::common::RegisterField<
2,
0x3,
1,
0,
tr_ctrl2::OverflowMode,
tr_ctrl2::OverflowMode,
TrCtrl2_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0x3,
1,
0,
tr_ctrl2::OverflowMode,
tr_ctrl2::OverflowMode,
TrCtrl2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Determines the effect of a counter underflow event (COUNTER reaches \'0\') on the \'line_out\' output signals."]
#[inline(always)]
pub fn underflow_mode(
self,
) -> crate::common::RegisterField<
4,
0x3,
1,
0,
tr_ctrl2::UnderflowMode,
tr_ctrl2::UnderflowMode,
TrCtrl2_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x3,
1,
0,
tr_ctrl2::UnderflowMode,
tr_ctrl2::UnderflowMode,
TrCtrl2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for TrCtrl2 {
#[inline(always)]
fn default() -> TrCtrl2 {
<crate::RegValueT<TrCtrl2_SPEC> as RegisterValue<_>>::new(63)
}
}
pub mod tr_ctrl2 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CcMatchMode_SPEC;
pub type CcMatchMode = crate::EnumBitfieldStruct<u8, CcMatchMode_SPEC>;
impl CcMatchMode {
#[doc = "Set to \'1\'"]
pub const SET: Self = Self::new(0);
#[doc = "Set to \'0\'"]
pub const CLEAR: Self = Self::new(1);
#[doc = "Invert"]
pub const INVERT: Self = Self::new(2);
#[doc = "No Change"]
pub const NO_CHANGE: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct OverflowMode_SPEC;
pub type OverflowMode = crate::EnumBitfieldStruct<u8, OverflowMode_SPEC>;
impl OverflowMode {
#[doc = "Set to \'1\'"]
pub const SET: Self = Self::new(0);
#[doc = "Set to \'0\'"]
pub const CLEAR: Self = Self::new(1);
#[doc = "Invert"]
pub const INVERT: Self = Self::new(2);
#[doc = "No Change"]
pub const NO_CHANGE: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct UnderflowMode_SPEC;
pub type UnderflowMode = crate::EnumBitfieldStruct<u8, UnderflowMode_SPEC>;
impl UnderflowMode {
#[doc = "Set to \'1\'"]
pub const SET: Self = Self::new(0);
#[doc = "Set to \'0\'"]
pub const CLEAR: Self = Self::new(1);
#[doc = "Invert"]
pub const INVERT: Self = Self::new(2);
#[doc = "No Change"]
pub const NO_CHANGE: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Intr_SPEC;
impl crate::sealed::RegSpec for Intr_SPEC {
type DataType = u32;
}
#[doc = "Interrupt request register"]
pub type Intr = crate::RegValueT<Intr_SPEC>;
impl Intr {
#[doc = "Terminal count event. Set to \'1\', when event is detected. Write with \'1\' to clear bit."]
#[inline(always)]
pub fn tc(self) -> crate::common::RegisterFieldBool<0, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Counter matches CC register event. Set to \'1\', when event is detected. Write with \'1\' to clear bit."]
#[inline(always)]
pub fn cc_match(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Intr {
#[inline(always)]
fn default() -> Intr {
<crate::RegValueT<Intr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSet_SPEC;
impl crate::sealed::RegSpec for IntrSet_SPEC {
type DataType = u32;
}
#[doc = "Interrupt set request register"]
pub type IntrSet = crate::RegValueT<IntrSet_SPEC>;
impl IntrSet {
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tc(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn cc_match(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrSet {
#[inline(always)]
fn default() -> IntrSet {
<crate::RegValueT<IntrSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMask_SPEC;
impl crate::sealed::RegSpec for IntrMask_SPEC {
type DataType = u32;
}
#[doc = "Interrupt mask register"]
pub type IntrMask = crate::RegValueT<IntrMask_SPEC>;
impl IntrMask {
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tc(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn cc_match(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMask {
#[inline(always)]
fn default() -> IntrMask {
<crate::RegValueT<IntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMasked_SPEC;
impl crate::sealed::RegSpec for IntrMasked_SPEC {
type DataType = u32;
}
#[doc = "Interrupt masked request register"]
pub type IntrMasked = crate::RegValueT<IntrMasked_SPEC>;
impl IntrMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tc(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn cc_match(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMasked {
#[inline(always)]
fn default() -> IntrMasked {
<crate::RegValueT<IntrMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
}