/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"Peripheral interconnect"]
unsafe impl ::core::marker::Send for super::Peri {}
unsafe impl ::core::marker::Sync for super::Peri {}
impl super::Peri {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "Divider command register"]
#[inline(always)]
pub const fn div_cmd(
&self,
) -> &'static crate::common::Reg<self::DivCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::DivCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1024usize),
)
}
}
#[doc = "Divider control register (for 8.0 divider)"]
#[inline(always)]
pub const fn div_8_ctl(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::Div8Ctl_SPEC, crate::common::RW>,
64,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x800usize))
}
}
#[doc = "Divider control register (for 16.0 divider)"]
#[inline(always)]
pub const fn div_16_ctl(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::Div16Ctl_SPEC, crate::common::RW>,
64,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x900usize))
}
}
#[doc = "Divider control register (for 16.5 divider)"]
#[inline(always)]
pub const fn div_16_5_ctl(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::Div165Ctl_SPEC, crate::common::RW>,
64,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xa00usize))
}
}
#[doc = "Divider control register (for 24.5 divider)"]
#[inline(always)]
pub const fn div_24_5_ctl(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::Div245Ctl_SPEC, crate::common::RW>,
63,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xb00usize))
}
}
#[doc = "Clock control register"]
#[inline(always)]
pub const fn clock_ctl(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::ClockCtl_SPEC, crate::common::RW>,
128,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xc00usize))
}
}
#[doc = "Trigger command register"]
#[inline(always)]
pub const fn tr_cmd(&self) -> &'static crate::common::Reg<self::TrCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TrCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4096usize),
)
}
}
#[doc = "Peripheral group structure"]
#[inline(always)]
pub fn gr(self) -> &'static crate::common::ClusterRegisterArray<crate::peri::_Gr, 11, 0x40> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x0usize))
}
}
#[doc = "Trigger group"]
#[inline(always)]
pub fn tr_gr(
self,
) -> &'static crate::common::ClusterRegisterArray<crate::peri::_TrGr, 15, 0x200> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x2000usize))
}
}
#[doc = "PPU structure with programmable address"]
#[inline(always)]
pub fn ppu_pr(
self,
) -> &'static crate::common::ClusterRegisterArray<crate::peri::_PpuPr, 16, 0x40> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x4000usize))
}
}
#[doc = "PPU structure with fixed/constant address for a peripheral group"]
#[inline(always)]
pub fn ppu_gr(
self,
) -> &'static crate::common::ClusterRegisterArray<crate::peri::_PpuGr, 11, 0x40> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x5000usize))
}
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DivCmd_SPEC;
impl crate::sealed::RegSpec for DivCmd_SPEC {
type DataType = u32;
}
#[doc = "Divider command register"]
pub type DivCmd = crate::RegValueT<DivCmd_SPEC>;
impl DivCmd {
#[doc = "(TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed.\n \nIf DIV_SEL is \'63\' and TYPE_SEL is \'3\' (default/reset value), no divider is specified and no clock signal(s) are generated."]
#[inline(always)]
pub fn div_sel(
self,
) -> crate::common::RegisterField<0, 0x3f, 1, 0, u8, u8, DivCmd_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0x3f,1,0,u8,u8,DivCmd_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies the divider type of the divider on which the command is performed:\n0: 8.0 (integer) clock dividers.\n1: 16.0 (integer) clock dividers.\n2: 16.5 (fractional) clock dividers.\n3: 24.5 (fractional) clock dividers."]
#[inline(always)]
pub fn type_sel(
self,
) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, DivCmd_SPEC, crate::common::RW> {
crate::common::RegisterField::<6,0x3,1,0,u8,u8,DivCmd_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "(PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times.\n \nIf PA_DIV_SEL is \'63\' and PA_TYPE_SEL is \'3\', \'clk_peri\' is used as reference."]
#[inline(always)]
pub fn pa_div_sel(
self,
) -> crate::common::RegisterField<8, 0x3f, 1, 0, u8, u8, DivCmd_SPEC, crate::common::RW> {
crate::common::RegisterField::<8,0x3f,1,0,u8,u8,DivCmd_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:\n0: 8.0 (integer) clock dividers.\n1: 16.0 (integer) clock dividers.\n2: 16.5 (fractional) clock dividers.\n3: 24.5 (fractional) clock dividers."]
#[inline(always)]
pub fn pa_type_sel(
self,
) -> crate::common::RegisterField<14, 0x3, 1, 0, u8, u8, DivCmd_SPEC, crate::common::RW> {
crate::common::RegisterField::<14,0x3,1,0,u8,u8,DivCmd_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to \'1\' and HW sets this field to \'0\'.\n \nThe DIV_SEL and TYPE_SEL fields specify which divider is to be disabled.\n \nThe HW sets the DISABLE field to \'0\' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to \'0\' immediately."]
#[inline(always)]
pub fn disable(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, DivCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30, 1, 0, DivCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to \'1\' to enable a divider and HW sets this field to \'0\' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to \'0\'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps:\n0: Disable the divider using the DIV_CMD.DISABLE field.\n1: Configure the divider\'s DIV_XXX_CTL register.\n2: Enable the divider using the DIV_CMD_ENABLE field.\n \nThe DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either \'clk_peri\' (typical usage) or to ANY enabled divider.\n \nThe PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider.\n \nThe HW sets the ENABLE field to \'0\' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to \'1\' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of \'clk_peri\'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to \'clk_peri\' takes affect immediately. SW can set this field to \'0\' during phase alignment to abort the enabling process."]
#[inline(always)]
pub fn enable(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, DivCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31, 1, 0, DivCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for DivCmd {
#[inline(always)]
fn default() -> DivCmd {
<crate::RegValueT<DivCmd_SPEC> as RegisterValue<_>>::new(65535)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Div8Ctl_SPEC;
impl crate::sealed::RegSpec for Div8Ctl_SPEC {
type DataType = u32;
}
#[doc = "Divider control register (for 8.0 divider)"]
pub type Div8Ctl = crate::RegValueT<Div8Ctl_SPEC>;
impl Div8Ctl {
#[doc = "Divider enabled. HW sets this field to \'1\' as a result of an ENABLE command. HW sets this field to \'0\' as a result on a DISABLE command.\n \nNote that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode."]
#[inline(always)]
pub fn en(self) -> crate::common::RegisterFieldBool<0, 1, 0, Div8Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, Div8Ctl_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Integer division by (1+INT8_DIV). Allows for integer divisions in the range \\[1, 256\\]. Note: this type of divider does NOT allow for a fractional division.\n \nFor the generation of a divided clock, the integer division range is restricted to \\[2, 256\\].\n \nFor the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range \\[2, 256\\]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions.\n \nNote that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to \'0\' when transitioning from DeepSleep to Active power mode."]
#[inline(always)]
pub fn int8_div(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Div8Ctl_SPEC, crate::common::RW> {
crate::common::RegisterField::<8,0xff,1,0,u8,u8,Div8Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Div8Ctl {
#[inline(always)]
fn default() -> Div8Ctl {
<crate::RegValueT<Div8Ctl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Div16Ctl_SPEC;
impl crate::sealed::RegSpec for Div16Ctl_SPEC {
type DataType = u32;
}
#[doc = "Divider control register (for 16.0 divider)"]
pub type Div16Ctl = crate::RegValueT<Div16Ctl_SPEC>;
impl Div16Ctl {
#[doc = "Divider enabled. HW sets this field to \'1\' as a result of an ENABLE command. HW sets this field to \'0\' as a result on a DISABLE command.\n \nNote that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode."]
#[inline(always)]
pub fn en(self) -> crate::common::RegisterFieldBool<0, 1, 0, Div16Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, Div16Ctl_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Integer division by (1+INT16_DIV). Allows for integer divisions in the range \\[1, 65,536\\]. Note: this type of divider does NOT allow for a fractional division.\n \nFor the generation of a divided clock, the integer division range is restricted to \\[2, 65,536\\].\n \nFor the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range \\[2, 65,536\\]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions.\n \nNote that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to \'0\' when transitioning from DeepSleep to Active power mode."]
#[inline(always)]
pub fn int16_div(
self,
) -> crate::common::RegisterField<8, 0xffff, 1, 0, u16, u16, Div16Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xffff,1,0,u16,u16,Div16Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Div16Ctl {
#[inline(always)]
fn default() -> Div16Ctl {
<crate::RegValueT<Div16Ctl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Div165Ctl_SPEC;
impl crate::sealed::RegSpec for Div165Ctl_SPEC {
type DataType = u32;
}
#[doc = "Divider control register (for 16.5 divider)"]
pub type Div165Ctl = crate::RegValueT<Div165Ctl_SPEC>;
impl Div165Ctl {
#[doc = "Divider enabled. HW sets this field to \'1\' as a result of an ENABLE command. HW sets this field to \'0\' as a result on a DISABLE command.\n \nNote that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode."]
#[inline(always)]
pub fn en(self) -> crate::common::RegisterFieldBool<0, 1, 0, Div165Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, Div165Ctl_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range \\[0, 31/32\\]. Note that fractional division results in clock jitter as some clock periods may be 1 \'clk_peri\' cycle longer than other clock periods.\n \nNote that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to \'0\' when transitioning from DeepSleep to Active power mode."]
#[inline(always)]
pub fn frac5_div(
self,
) -> crate::common::RegisterField<3, 0x1f, 1, 0, u8, u8, Div165Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<3,0x1f,1,0,u8,u8,Div165Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Integer division by (1+INT16_DIV). Allows for integer divisions in the range \\[1, 65,536\\]. Note: combined with fractional division, this divider type allows for a division in the range \\[1, 65,536 31/32\\] in 1/32 increments.\n \nFor the generation of a divided clock, the division range is restricted to \\[2, 65,536 31/32\\].\n \nFor the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to \\[2, 65,536\\].\n \nNote that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to \'0\' when transitioning from DeepSleep to Active power mode."]
#[inline(always)]
pub fn int16_div(
self,
) -> crate::common::RegisterField<8, 0xffff, 1, 0, u16, u16, Div165Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xffff,1,0,u16,u16,Div165Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Div165Ctl {
#[inline(always)]
fn default() -> Div165Ctl {
<crate::RegValueT<Div165Ctl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Div245Ctl_SPEC;
impl crate::sealed::RegSpec for Div245Ctl_SPEC {
type DataType = u32;
}
#[doc = "Divider control register (for 24.5 divider)"]
pub type Div245Ctl = crate::RegValueT<Div245Ctl_SPEC>;
impl Div245Ctl {
#[doc = "Divider enabled. HW sets this field to \'1\' as a result of an ENABLE command. HW sets this field to \'0\' as a result on a DISABLE command.\n \nNote that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode."]
#[inline(always)]
pub fn en(self) -> crate::common::RegisterFieldBool<0, 1, 0, Div245Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, Div245Ctl_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range \\[0, 31/32\\]. Note that fractional division results in clock jitter as some clock periods may be 1 \'clk_peri\' cycle longer than other clock periods.\n \nNote that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to \'0\' when transitioning from DeepSleep to Active power mode."]
#[inline(always)]
pub fn frac5_div(
self,
) -> crate::common::RegisterField<3, 0x1f, 1, 0, u8, u8, Div245Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<3,0x1f,1,0,u8,u8,Div245Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Integer division by (1+INT24_DIV). Allows for integer divisions in the range \\[1, 16,777,216\\]. Note: combined with fractional division, this divider type allows for a division in the range \\[1, 16,777,216 31/32\\] in 1/32 increments.\n \nFor the generation of a divided clock, the integer division range is restricted to \\[2, 16,777,216 31/32\\].\n \nFor the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to \\[2, 16,777,216\\].\n \nNote that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to \'0\' when transitioning from DeepSleep to Active power mode."]
#[inline(always)]
pub fn int24_div(
self,
) -> crate::common::RegisterField<8, 0xffffff, 1, 0, u32, u32, Div245Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xffffff,1,0,u32,u32,Div245Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Div245Ctl {
#[inline(always)]
fn default() -> Div245Ctl {
<crate::RegValueT<Div245Ctl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClockCtl_SPEC;
impl crate::sealed::RegSpec for ClockCtl_SPEC {
type DataType = u32;
}
#[doc = "Clock control register"]
pub type ClockCtl = crate::RegValueT<ClockCtl_SPEC>;
impl ClockCtl {
#[doc = "Specifies one of the dividers of the divider type specified by TYPE_SEL.\n \nIf DIV_SEL is \'63\' and TYPE_SEL is \'3\' (default/reset value), no divider is specified and no clock control signal(s) are generated.\n \nWhen transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one \'clk_peri\' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is \'63\' and TYPE_SEL is \'3\') for a transition time that is larger than the smaller of the two divider periods."]
#[inline(always)]
pub fn div_sel(
self,
) -> crate::common::RegisterField<0, 0x3f, 1, 0, u8, u8, ClockCtl_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0x3f,1,0,u8,u8,ClockCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies divider type:\n0: 8.0 (integer) clock dividers.\n1: 16.0 (integer) clock dividers.\n2: 16.5 (fractional) clock dividers.\n3: 24.5 (fractional) clock dividers."]
#[inline(always)]
pub fn type_sel(
self,
) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, ClockCtl_SPEC, crate::common::RW> {
crate::common::RegisterField::<6,0x3,1,0,u8,u8,ClockCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClockCtl {
#[inline(always)]
fn default() -> ClockCtl {
<crate::RegValueT<ClockCtl_SPEC> as RegisterValue<_>>::new(255)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrCmd_SPEC;
impl crate::sealed::RegSpec for TrCmd_SPEC {
type DataType = u32;
}
#[doc = "Trigger command register"]
pub type TrCmd = crate::RegValueT<TrCmd_SPEC>;
impl TrCmd {
#[doc = "Specifies the activated trigger when ACTIVATE is \'1\'. OUT_SEL specifies whether the activated trigger is an input trigger or output trigger to the trigger multiplexer. During activation (ACTIVATE is \'1\'), SW should not modify this register field. If the specified trigger is not present, the trigger activation has no effect."]
#[inline(always)]
pub fn tr_sel(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, TrCmd_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0xff,1,0,u8,u8,TrCmd_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies the trigger group."]
#[inline(always)]
pub fn group_sel(
self,
) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, TrCmd_SPEC, crate::common::RW> {
crate::common::RegisterField::<8,0xf,1,0,u8,u8,TrCmd_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Amount of \'clk_peri\' cycles a specific trigger is activated. During activation (ACTIVATE is \'1\'), HW decrements this field to \'0\' using a cycle counter. During activation, SW should not modify this register field. A value of 255 is a special case: HW does NOT decrement this field to \'0\' and trigger activation is under direct control of ACTIVATE when ACTIVATE is \'1\' the trigger is activated and when ACTIVATE is \'0\' the trigger is deactivated."]
#[inline(always)]
pub fn count(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, TrCmd_SPEC, crate::common::RW> {
crate::common::RegisterField::<16,0xff,1,0,u8,u8,TrCmd_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies whether trigger activation is for a specific input or ouput trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only.\n\'0\': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer.\n\'1\': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer."]
#[inline(always)]
pub fn out_sel(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, TrCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30, 1, 0, TrCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "SW sets this field to \'1\' by to activate (set to \'1\') a trigger as identified by TR_SEL and OUT_SEL for COUNT cycles. HW sets this field to \'0\' when the cycle counter is decremented to \'0\'. Note: a COUNT value of 255 is a special case and trigger activation is under direct control of the ACTIVATE field (the counter is not decremented)."]
#[inline(always)]
pub fn activate(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, TrCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31, 1, 0, TrCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for TrCmd {
#[inline(always)]
fn default() -> TrCmd {
<crate::RegValueT<TrCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc = "Peripheral group structure"]
#[non_exhaustive]
pub struct _Gr;
#[doc = "Peripheral group structure"]
pub type Gr = &'static _Gr;
unsafe impl ::core::marker::Sync for _Gr {}
impl _Gr {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "Clock control"]
#[inline(always)]
pub const fn clock_ctl(
&self,
) -> &'static crate::common::Reg<gr::ClockCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<gr::ClockCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Slave control"]
#[inline(always)]
pub const fn sl_ctl(&self) -> &'static crate::common::Reg<gr::SlCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<gr::SlCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "Timeout control"]
#[inline(always)]
pub const fn timeout_ctl(
&self,
) -> &'static crate::common::Reg<gr::TimeoutCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<gr::TimeoutCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
}
pub mod gr {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClockCtl_SPEC;
impl crate::sealed::RegSpec for ClockCtl_SPEC {
type DataType = u32;
}
#[doc = "Clock control"]
pub type ClockCtl = crate::RegValueT<ClockCtl_SPEC>;
impl ClockCtl {
#[doc = "Specifies a group clock divider (from the peripheral clock \'clk_peri\' to the group clock \'clk_group\\[3/4/5/...15\\]\'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range \\[1, 256\\]. \n \nNote that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to \'0\' when transitioning from DeepSleep to Active power mode."]
#[inline(always)]
pub fn int8_div(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, ClockCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,ClockCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClockCtl {
#[inline(always)]
fn default() -> ClockCtl {
<crate::RegValueT<ClockCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SlCtl_SPEC;
impl crate::sealed::RegSpec for SlCtl_SPEC {
type DataType = u32;
}
#[doc = "Slave control"]
pub type SlCtl = crate::RegValueT<SlCtl_SPEC>;
impl SlCtl {
#[doc = "Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant \'1\'. This slave can NOT be disabled."]
#[inline(always)]
pub fn enabled_0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, SlCtl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, SlCtl_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant \'0\') and its resets are activated.\n\nNote: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant \'1\' (SW: R): the slave can NOT be disabled."]
#[inline(always)]
pub fn enabled_1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, SlCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,SlCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant \'0\') and its resets are activated.\n\nNote: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant \'1\' (SW: R): the slave can NOT be disabled."]
#[inline(always)]
pub fn enabled_2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, SlCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,SlCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enabled_3(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, SlCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,SlCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enabled_4(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, SlCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,SlCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enabled_5(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, SlCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,SlCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enabled_6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, SlCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,SlCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enabled_7(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SlCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SlCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enabled_8(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, SlCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,SlCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enabled_9(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, SlCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,SlCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enabled_10(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, SlCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,SlCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enabled_11(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, SlCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,SlCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enabled_12(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, SlCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,SlCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enabled_13(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, SlCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<13,1,0,SlCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enabled_14(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, SlCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<14,1,0,SlCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enabled_15(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, SlCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<15,1,0,SlCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SlCtl {
#[inline(always)]
fn default() -> SlCtl {
<crate::RegValueT<SlCtl_SPEC> as RegisterValue<_>>::new(65535)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TimeoutCtl_SPEC;
impl crate::sealed::RegSpec for TimeoutCtl_SPEC {
type DataType = u32;
}
#[doc = "Timeout control"]
pub type TimeoutCtl = crate::RegValueT<TimeoutCtl_SPEC>;
impl TimeoutCtl {
#[doc = "This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)).\n\'0x0000\'-\'0xfffe\': Number of peripheral group clock cycles.\n\'0xffff\': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated."]
#[inline(always)]
pub fn timeout(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
TimeoutCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
TimeoutCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for TimeoutCtl {
#[inline(always)]
fn default() -> TimeoutCtl {
<crate::RegValueT<TimeoutCtl_SPEC> as RegisterValue<_>>::new(65535)
}
}
}
#[doc = "Trigger group"]
#[non_exhaustive]
pub struct _TrGr;
#[doc = "Trigger group"]
pub type TrGr = &'static _TrGr;
unsafe impl ::core::marker::Sync for _TrGr {}
impl _TrGr {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "Trigger control register"]
#[inline(always)]
pub const fn tr_out_ctl(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<tr_gr::TrOutCtl_SPEC, crate::common::RW>,
128,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x0usize))
}
}
}
pub mod tr_gr {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrOutCtl_SPEC;
impl crate::sealed::RegSpec for TrOutCtl_SPEC {
type DataType = u32;
}
#[doc = "Trigger control register"]
pub type TrOutCtl = crate::RegValueT<TrOutCtl_SPEC>;
impl TrOutCtl {
#[doc = "Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of \'0\', and as a result will not cause HW activation of the output trigger."]
#[inline(always)]
pub fn tr_sel(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, TrOutCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,TrOutCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies if the output trigger is inverted."]
#[inline(always)]
pub fn tr_inv(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, TrOutCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,TrOutCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger.\n\'0\': level sensitive.\n\'1\': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock."]
#[inline(always)]
pub fn tr_edge(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, TrOutCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,TrOutCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TrOutCtl {
#[inline(always)]
fn default() -> TrOutCtl {
<crate::RegValueT<TrOutCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
}
#[doc = "PPU structure with programmable address"]
#[non_exhaustive]
pub struct _PpuPr;
#[doc = "PPU structure with programmable address"]
pub type PpuPr = &'static _PpuPr;
unsafe impl ::core::marker::Sync for _PpuPr {}
impl _PpuPr {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "PPU region address 0 (slave structure)"]
#[inline(always)]
pub const fn addr0(
&self,
) -> &'static crate::common::Reg<ppu_pr::Addr0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<ppu_pr::Addr0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "PPU region attributes 0 (slave structure)"]
#[inline(always)]
pub const fn att0(&self) -> &'static crate::common::Reg<ppu_pr::Att0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<ppu_pr::Att0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "PPU region address 1 (master structure)"]
#[inline(always)]
pub const fn addr1(&self) -> &'static crate::common::Reg<ppu_pr::Addr1_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<ppu_pr::Addr1_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "PPU region attributes 1 (master structure)"]
#[inline(always)]
pub const fn att1(&self) -> &'static crate::common::Reg<ppu_pr::Att1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<ppu_pr::Att1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
}
pub mod ppu_pr {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Addr0_SPEC;
impl crate::sealed::RegSpec for Addr0_SPEC {
type DataType = u32;
}
#[doc = "PPU region address 0 (slave structure)"]
pub type Addr0 = crate::RegValueT<Addr0_SPEC>;
impl Addr0 {
#[doc = "This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:\nBit 0: subregion 0 disable.\nBit 1: subregion 1 disable.\nBit 2: subregion 2 disable.\nBit 3: subregion 3 disable.\nBit 4: subregion 4 disable.\nBit 5: subregion 5 disable.\nBit 6: subregion 6 disable.\nBit 7: subregion 7 disable.\nE.g., a 64 KByte address region (REGION_SIZE is \'15\') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B."]
#[inline(always)]
pub fn subregion_disable(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Addr0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Addr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is \'15\') is 64 KByte aligned, and ADDR24\\[7:0\\] are ignored."]
#[inline(always)]
pub fn addr24(
self,
) -> crate::common::RegisterField<8, 0xffffff, 1, 0, u32, u32, Addr0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xffffff,1,0,u32,u32,Addr0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Addr0 {
#[inline(always)]
fn default() -> Addr0 {
<crate::RegValueT<Addr0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Att0_SPEC;
impl crate::sealed::RegSpec for Att0_SPEC {
type DataType = u32;
}
#[doc = "PPU region attributes 0 (slave structure)"]
pub type Att0 = crate::RegValueT<Att0_SPEC>;
impl Att0 {
#[doc = "User read enable:\n\'0\': Disabled (user, read accesses are NOT allowed).\n\'1\': Enabled (user, read accesses are allowed)."]
#[inline(always)]
pub fn ur(self) -> crate::common::RegisterFieldBool<0, 1, 0, Att0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Att0_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "User write enable:\n\'0\': Disabled (user, write accesses are NOT allowed).\n\'1\': Enabled (user, write accesses are allowed)."]
#[inline(always)]
pub fn uw(self) -> crate::common::RegisterFieldBool<1, 1, 0, Att0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Att0_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "User execute enable:\n\'0\': Disabled (user, execute accesses are NOT allowed).\n\'1\': Enabled (user, execute accesses are allowed)."]
#[inline(always)]
pub fn ux(self) -> crate::common::RegisterFieldBool<2, 1, 0, Att0_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2, 1, 0, Att0_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Privileged read enable:\n\'0\': Disabled (privileged, read accesses are NOT allowed).\n\'1\': Enabled (privileged, read accesses are allowed)."]
#[inline(always)]
pub fn pr(self) -> crate::common::RegisterFieldBool<3, 1, 0, Att0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, Att0_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Privileged write enable:\n\'0\': Disabled (privileged, write accesses are NOT allowed).\n\'1\': Enabled (privileged, write accesses are allowed)."]
#[inline(always)]
pub fn pw(self) -> crate::common::RegisterFieldBool<4, 1, 0, Att0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, Att0_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Privileged execute enable:\n\'0\': Disabled (privileged, execute accesses are NOT allowed).\n\'1\': Enabled (privileged, execute accesses are allowed)."]
#[inline(always)]
pub fn px(self) -> crate::common::RegisterFieldBool<5, 1, 0, Att0_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5, 1, 0, Att0_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Non-secure:\n\'0\': Secure (secure accesses allowed, non-secure access NOT allowed).\n\'1\': Non-secure (both secure and non-secure accesses allowed)."]
#[inline(always)]
pub fn ns(self) -> crate::common::RegisterFieldBool<6, 1, 0, Att0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, Att0_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "This field specifies protection context identifier based access control for protection context \'0\'."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Att0_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8, 1, 0, Att0_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "This field specifies protection context identifier based access control.\nBit i: protection context i+1 enable. If \'0\', protection context i+1 access is disabled; i.e. not allowed. If \'1\', protection context i+1 access is enabled; i.e. allowed."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<9, 0x7fff, 1, 0, u16, u16, Att0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<9,0x7fff,1,0,u16,u16,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field specifies the region size:\n\'0\'-\'6\': Undefined.\n\'7\': 256 B region\n\'8\': 512 B region\n\'9\': 1 KB region\n\'10\': 2 KB region\n\'11\': 4 KB region\n\'12\': 8 KB region\n\'13\': 16 KB region\n\'14\': 32 KB region\n\'15\': 64 KB region\n\'16\': 128 KB region\n\'17\': 256 KB region\n\'18\': 512 KB region\n\'19\': 1 MB region\n\'20\': 2 MB region\n\'21\': 4 MB region\n\'22\': 8 MB region\n\'23\': 16 MB region\n\'24\': 32 MB region\n\'25\': 64 MB region\n\'26\': 128 MB region\n\'27\': 256 MB region\n\'28\': 512 MB region\n\'29\': 1 GB region\n\'30\': 2 GB region\n\'31\': 4 GB region"]
#[inline(always)]
pub fn region_size(
self,
) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, Att0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0x1f,1,0,u8,u8,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field specifies if the PC field participates in the \'matching\' process or the \'access evaluation\' process:\n\'0\': PC field participates in \'access evaluation\'.\n\'1\': PC field participates in \'matching\'.\n\nNote that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to \'1\'."]
#[inline(always)]
pub fn pc_match(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, Att0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Region enable:\n\'0\': Disabled. A disabled region will never result in a match on the bus transfer address.\n\'1\': Enabled.\n\nNote: a disabled address region performs logic gating to reduce dynamic power consumption."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Att0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Att0 {
#[inline(always)]
fn default() -> Att0 {
<crate::RegValueT<Att0_SPEC> as RegisterValue<_>>::new(292)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Addr1_SPEC;
impl crate::sealed::RegSpec for Addr1_SPEC {
type DataType = u32;
}
#[doc = "PPU region address 1 (master structure)"]
pub type Addr1 = crate::RegValueT<Addr1_SPEC>;
impl Addr1 {
#[doc = "See corresponding field for PPU structure with programmable address.\n\nTwo out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. \n\nNote: this field is read-only."]
#[inline(always)]
pub fn subregion_disable(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Addr1_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Addr1_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See corresponding field for PPU structure with programmable address.\n\n\'ADDR_DEF1\': base address of structure.\n\nNote: this field is read-only."]
#[inline(always)]
pub fn addr24(
self,
) -> crate::common::RegisterField<8, 0xffffff, 1, 0, u32, u32, Addr1_SPEC, crate::common::R>
{
crate::common::RegisterField::<8,0xffffff,1,0,u32,u32,Addr1_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Addr1 {
#[inline(always)]
fn default() -> Addr1 {
<crate::RegValueT<Addr1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Att1_SPEC;
impl crate::sealed::RegSpec for Att1_SPEC {
type DataType = u32;
}
#[doc = "PPU region attributes 1 (master structure)"]
pub type Att1 = crate::RegValueT<Att1_SPEC>;
impl Att1 {
#[doc = "See corresponding field for PPU structure with programmable address.\n\nNote that this register is constant \'1\'; i.e. user read accesses are ALWAYS allowed."]
#[inline(always)]
pub fn ur(self) -> crate::common::RegisterFieldBool<0, 1, 0, Att1_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, Att1_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn uw(self) -> crate::common::RegisterFieldBool<1, 1, 0, Att1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Att1_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address.\n\nNote that this register is constant \'0\'; i.e. user execute accesses are NEVER allowed."]
#[inline(always)]
pub fn ux(self) -> crate::common::RegisterFieldBool<2, 1, 0, Att1_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2, 1, 0, Att1_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address.\n\nNote that this register is constant \'1\'; i.e. privileged read accesses are ALWAYS allowed."]
#[inline(always)]
pub fn pr(self) -> crate::common::RegisterFieldBool<3, 1, 0, Att1_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3, 1, 0, Att1_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn pw(self) -> crate::common::RegisterFieldBool<4, 1, 0, Att1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, Att1_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address.\n\nNote that this register is constant \'0\'; i.e. privileged execute accesses are NEVER allowed."]
#[inline(always)]
pub fn px(self) -> crate::common::RegisterFieldBool<5, 1, 0, Att1_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5, 1, 0, Att1_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn ns(self) -> crate::common::RegisterFieldBool<6, 1, 0, Att1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, Att1_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Att1_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8, 1, 0, Att1_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<9, 0x7fff, 1, 0, u16, u16, Att1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<9,0x7fff,1,0,u16,u16,Att1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See corresponding field for PPU structure with programmable address.\n\n\'7\': 256 B region"]
#[inline(always)]
pub fn region_size(
self,
) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, Att1_SPEC, crate::common::R>
{
crate::common::RegisterField::<24,0x1f,1,0,u8,u8,Att1_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn pc_match(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, Att1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,Att1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Att1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,Att1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Att1 {
#[inline(always)]
fn default() -> Att1 {
<crate::RegValueT<Att1_SPEC> as RegisterValue<_>>::new(117440777)
}
}
}
#[doc = "PPU structure with fixed/constant address for a peripheral group"]
#[non_exhaustive]
pub struct _PpuGr;
#[doc = "PPU structure with fixed/constant address for a peripheral group"]
pub type PpuGr = &'static _PpuGr;
unsafe impl ::core::marker::Sync for _PpuGr {}
impl _PpuGr {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "PPU region address 0 (slave structure)"]
#[inline(always)]
pub const fn addr0(&self) -> &'static crate::common::Reg<ppu_gr::Addr0_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<ppu_gr::Addr0_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "PPU region attributes 0 (slave structure)"]
#[inline(always)]
pub const fn att0(&self) -> &'static crate::common::Reg<ppu_gr::Att0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<ppu_gr::Att0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "PPU region address 1 (master structure)"]
#[inline(always)]
pub const fn addr1(&self) -> &'static crate::common::Reg<ppu_gr::Addr1_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<ppu_gr::Addr1_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "PPU region attributes 1 (master structure)"]
#[inline(always)]
pub const fn att1(&self) -> &'static crate::common::Reg<ppu_gr::Att1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<ppu_gr::Att1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
}
pub mod ppu_gr {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Addr0_SPEC;
impl crate::sealed::RegSpec for Addr0_SPEC {
type DataType = u32;
}
#[doc = "PPU region address 0 (slave structure)"]
pub type Addr0 = crate::RegValueT<Addr0_SPEC>;
impl Addr0 {
#[doc = "See corresponding field for PPU structure with programmable address.\n\nNote: this field is read-only. Its value is chip specific."]
#[inline(always)]
pub fn subregion_disable(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Addr0_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Addr0_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See corresponding field for PPU structure with programmable address.\n\n\'ADDR_DEF1\': address of protected region.\n\nNote: this field is read-only. Its value is chip specific."]
#[inline(always)]
pub fn addr24(
self,
) -> crate::common::RegisterField<8, 0xffffff, 1, 0, u32, u32, Addr0_SPEC, crate::common::R>
{
crate::common::RegisterField::<8,0xffffff,1,0,u32,u32,Addr0_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Addr0 {
#[inline(always)]
fn default() -> Addr0 {
<crate::RegValueT<Addr0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Att0_SPEC;
impl crate::sealed::RegSpec for Att0_SPEC {
type DataType = u32;
}
#[doc = "PPU region attributes 0 (slave structure)"]
pub type Att0 = crate::RegValueT<Att0_SPEC>;
impl Att0 {
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn ur(self) -> crate::common::RegisterFieldBool<0, 1, 0, Att0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Att0_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn uw(self) -> crate::common::RegisterFieldBool<1, 1, 0, Att0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Att0_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address.\n\nNote that this register is constant \'1\'; i.e. user execute accesses are ALWAYS allowed."]
#[inline(always)]
pub fn ux(self) -> crate::common::RegisterFieldBool<2, 1, 0, Att0_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2, 1, 0, Att0_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn pr(self) -> crate::common::RegisterFieldBool<3, 1, 0, Att0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, Att0_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn pw(self) -> crate::common::RegisterFieldBool<4, 1, 0, Att0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, Att0_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address.\n\nNote that this register is constant \'1\'; i.e. user execute accesses are ALWAYS allowed."]
#[inline(always)]
pub fn px(self) -> crate::common::RegisterFieldBool<5, 1, 0, Att0_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5, 1, 0, Att0_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn ns(self) -> crate::common::RegisterFieldBool<6, 1, 0, Att0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, Att0_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Att0_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8, 1, 0, Att0_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<9, 0x7fff, 1, 0, u16, u16, Att0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<9,0x7fff,1,0,u16,u16,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See corresponding field for PPU structure with programmable address.\n\nNote: this field is read-only. Its value is chip specific."]
#[inline(always)]
pub fn region_size(
self,
) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, Att0_SPEC, crate::common::R>
{
crate::common::RegisterField::<24,0x1f,1,0,u8,u8,Att0_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn pc_match(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, Att0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Att0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Att0 {
#[inline(always)]
fn default() -> Att0 {
<crate::RegValueT<Att0_SPEC> as RegisterValue<_>>::new(292)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Addr1_SPEC;
impl crate::sealed::RegSpec for Addr1_SPEC {
type DataType = u32;
}
#[doc = "PPU region address 1 (master structure)"]
pub type Addr1 = crate::RegValueT<Addr1_SPEC>;
impl Addr1 {
#[doc = "See corresponding field for PPU structure with programmable address.\n\nTwo out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. \n\nNote: this field is read-only."]
#[inline(always)]
pub fn subregion_disable(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Addr1_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Addr1_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See corresponding field for PPU structure with programmable address.\n\n\'ADDR_DEF1\': base address of structure.\n\nNote: this field is read-only."]
#[inline(always)]
pub fn addr24(
self,
) -> crate::common::RegisterField<8, 0xffffff, 1, 0, u32, u32, Addr1_SPEC, crate::common::R>
{
crate::common::RegisterField::<8,0xffffff,1,0,u32,u32,Addr1_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Addr1 {
#[inline(always)]
fn default() -> Addr1 {
<crate::RegValueT<Addr1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Att1_SPEC;
impl crate::sealed::RegSpec for Att1_SPEC {
type DataType = u32;
}
#[doc = "PPU region attributes 1 (master structure)"]
pub type Att1 = crate::RegValueT<Att1_SPEC>;
impl Att1 {
#[doc = "See corresponding field for PPU structure with programmable address.\n\nNote that this register is constant \'1\'; i.e. user read accesses are ALWAYS allowed."]
#[inline(always)]
pub fn ur(self) -> crate::common::RegisterFieldBool<0, 1, 0, Att1_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, Att1_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn uw(self) -> crate::common::RegisterFieldBool<1, 1, 0, Att1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Att1_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address.\n\nNote that this register is constant \'0\'; i.e. user execute accesses are NEVER allowed."]
#[inline(always)]
pub fn ux(self) -> crate::common::RegisterFieldBool<2, 1, 0, Att1_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2, 1, 0, Att1_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address.\n\nNote that this register is constant \'1\'; i.e. privileged read accesses are ALWAYS allowed."]
#[inline(always)]
pub fn pr(self) -> crate::common::RegisterFieldBool<3, 1, 0, Att1_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3, 1, 0, Att1_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn pw(self) -> crate::common::RegisterFieldBool<4, 1, 0, Att1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, Att1_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address.\n\nNote that this register is constant \'0\'; i.e. privileged execute accesses are NEVER allowed."]
#[inline(always)]
pub fn px(self) -> crate::common::RegisterFieldBool<5, 1, 0, Att1_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5, 1, 0, Att1_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn ns(self) -> crate::common::RegisterFieldBool<6, 1, 0, Att1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, Att1_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Att1_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8, 1, 0, Att1_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<9, 0x7fff, 1, 0, u16, u16, Att1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<9,0x7fff,1,0,u16,u16,Att1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See corresponding field for PPU structure with programmable address.\n\n\'7\': 256 B region"]
#[inline(always)]
pub fn region_size(
self,
) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, Att1_SPEC, crate::common::R>
{
crate::common::RegisterField::<24,0x1f,1,0,u8,u8,Att1_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn pc_match(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, Att1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,Att1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See corresponding field for PPU structure with programmable address."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Att1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,Att1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Att1 {
#[inline(always)]
fn default() -> Att1 {
<crate::RegValueT<Att1_SPEC> as RegisterValue<_>>::new(117440777)
}
}
}