/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"Serial Memory Interface"]
unsafe impl ::core::marker::Send for super::Smif {}
unsafe impl ::core::marker::Sync for super::Smif {}
impl super::Smif {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "Control"]
#[inline(always)]
pub const fn ctl(&self) -> &'static crate::common::Reg<self::Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Status"]
#[inline(always)]
pub const fn status(&self) -> &'static crate::common::Reg<self::Status_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::Status_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "Transmitter command FIFO status"]
#[inline(always)]
pub const fn tx_cmd_fifo_status(
&self,
) -> &'static crate::common::Reg<self::TxCmdFifoStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::TxCmdFifoStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(68usize),
)
}
}
#[doc = "Transmitter command FIFO write"]
#[inline(always)]
pub const fn tx_cmd_fifo_wr(
&self,
) -> &'static crate::common::Reg<self::TxCmdFifoWr_SPEC, crate::common::W> {
unsafe {
crate::common::Reg::<self::TxCmdFifoWr_SPEC, crate::common::W>::from_ptr(
self._svd2pac_as_ptr().add(80usize),
)
}
}
#[doc = "Transmitter data FIFO control"]
#[inline(always)]
pub const fn tx_data_fifo_ctl(
&self,
) -> &'static crate::common::Reg<self::TxDataFifoCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TxDataFifoCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(128usize),
)
}
}
#[doc = "Transmitter data FIFO status"]
#[inline(always)]
pub const fn tx_data_fifo_status(
&self,
) -> &'static crate::common::Reg<self::TxDataFifoStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::TxDataFifoStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(132usize),
)
}
}
#[doc = "Transmitter data FIFO write"]
#[inline(always)]
pub const fn tx_data_fifo_wr1(
&self,
) -> &'static crate::common::Reg<self::TxDataFifoWr1_SPEC, crate::common::W> {
unsafe {
crate::common::Reg::<self::TxDataFifoWr1_SPEC, crate::common::W>::from_ptr(
self._svd2pac_as_ptr().add(144usize),
)
}
}
#[doc = "Transmitter data FIFO write"]
#[inline(always)]
pub const fn tx_data_fifo_wr2(
&self,
) -> &'static crate::common::Reg<self::TxDataFifoWr2_SPEC, crate::common::W> {
unsafe {
crate::common::Reg::<self::TxDataFifoWr2_SPEC, crate::common::W>::from_ptr(
self._svd2pac_as_ptr().add(148usize),
)
}
}
#[doc = "Transmitter data FIFO write"]
#[inline(always)]
pub const fn tx_data_fifo_wr4(
&self,
) -> &'static crate::common::Reg<self::TxDataFifoWr4_SPEC, crate::common::W> {
unsafe {
crate::common::Reg::<self::TxDataFifoWr4_SPEC, crate::common::W>::from_ptr(
self._svd2pac_as_ptr().add(152usize),
)
}
}
#[doc = "Receiver data FIFO control"]
#[inline(always)]
pub const fn rx_data_fifo_ctl(
&self,
) -> &'static crate::common::Reg<self::RxDataFifoCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::RxDataFifoCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(192usize),
)
}
}
#[doc = "Receiver data FIFO status"]
#[inline(always)]
pub const fn rx_data_fifo_status(
&self,
) -> &'static crate::common::Reg<self::RxDataFifoStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::RxDataFifoStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(196usize),
)
}
}
#[doc = "Receiver data FIFO read"]
#[inline(always)]
pub const fn rx_data_fifo_rd1(
&self,
) -> &'static crate::common::Reg<self::RxDataFifoRd1_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::RxDataFifoRd1_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(208usize),
)
}
}
#[doc = "Receiver data FIFO read"]
#[inline(always)]
pub const fn rx_data_fifo_rd2(
&self,
) -> &'static crate::common::Reg<self::RxDataFifoRd2_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::RxDataFifoRd2_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(212usize),
)
}
}
#[doc = "Receiver data FIFO read"]
#[inline(always)]
pub const fn rx_data_fifo_rd4(
&self,
) -> &'static crate::common::Reg<self::RxDataFifoRd4_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::RxDataFifoRd4_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(216usize),
)
}
}
#[doc = "Receiver data FIFO silent read"]
#[inline(always)]
pub const fn rx_data_fifo_rd1_silent(
&self,
) -> &'static crate::common::Reg<self::RxDataFifoRd1Silent_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::RxDataFifoRd1Silent_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(224usize),
)
}
}
#[doc = "Slow cache control"]
#[inline(always)]
pub const fn slow_ca_ctl(
&self,
) -> &'static crate::common::Reg<self::SlowCaCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SlowCaCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(256usize),
)
}
}
#[doc = "Slow cache command"]
#[inline(always)]
pub const fn slow_ca_cmd(
&self,
) -> &'static crate::common::Reg<self::SlowCaCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SlowCaCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(264usize),
)
}
}
#[doc = "Fast cache control"]
#[inline(always)]
pub const fn fast_ca_ctl(
&self,
) -> &'static crate::common::Reg<self::FastCaCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::FastCaCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(384usize),
)
}
}
#[doc = "Fast cache command"]
#[inline(always)]
pub const fn fast_ca_cmd(
&self,
) -> &'static crate::common::Reg<self::FastCaCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::FastCaCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(392usize),
)
}
}
#[doc = "Cryptography Command"]
#[inline(always)]
pub const fn crypto_cmd(
&self,
) -> &'static crate::common::Reg<self::CryptoCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CryptoCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(512usize),
)
}
}
#[doc = "Cryptography input 0"]
#[inline(always)]
pub const fn crypto_input0(
&self,
) -> &'static crate::common::Reg<self::CryptoInput0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CryptoInput0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(544usize),
)
}
}
#[doc = "Cryptography input 1"]
#[inline(always)]
pub const fn crypto_input1(
&self,
) -> &'static crate::common::Reg<self::CryptoInput1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CryptoInput1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(548usize),
)
}
}
#[doc = "Cryptography input 2"]
#[inline(always)]
pub const fn crypto_input2(
&self,
) -> &'static crate::common::Reg<self::CryptoInput2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CryptoInput2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(552usize),
)
}
}
#[doc = "Cryptography input 3"]
#[inline(always)]
pub const fn crypto_input3(
&self,
) -> &'static crate::common::Reg<self::CryptoInput3_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CryptoInput3_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(556usize),
)
}
}
#[doc = "Cryptography key 0"]
#[inline(always)]
pub const fn crypto_key0(
&self,
) -> &'static crate::common::Reg<self::CryptoKey0_SPEC, crate::common::W> {
unsafe {
crate::common::Reg::<self::CryptoKey0_SPEC, crate::common::W>::from_ptr(
self._svd2pac_as_ptr().add(576usize),
)
}
}
#[doc = "Cryptography key 1"]
#[inline(always)]
pub const fn crypto_key1(
&self,
) -> &'static crate::common::Reg<self::CryptoKey1_SPEC, crate::common::W> {
unsafe {
crate::common::Reg::<self::CryptoKey1_SPEC, crate::common::W>::from_ptr(
self._svd2pac_as_ptr().add(580usize),
)
}
}
#[doc = "Cryptography key 2"]
#[inline(always)]
pub const fn crypto_key2(
&self,
) -> &'static crate::common::Reg<self::CryptoKey2_SPEC, crate::common::W> {
unsafe {
crate::common::Reg::<self::CryptoKey2_SPEC, crate::common::W>::from_ptr(
self._svd2pac_as_ptr().add(584usize),
)
}
}
#[doc = "Cryptography key 3"]
#[inline(always)]
pub const fn crypto_key3(
&self,
) -> &'static crate::common::Reg<self::CryptoKey3_SPEC, crate::common::W> {
unsafe {
crate::common::Reg::<self::CryptoKey3_SPEC, crate::common::W>::from_ptr(
self._svd2pac_as_ptr().add(588usize),
)
}
}
#[doc = "Cryptography output 0"]
#[inline(always)]
pub const fn crypto_output0(
&self,
) -> &'static crate::common::Reg<self::CryptoOutput0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CryptoOutput0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(608usize),
)
}
}
#[doc = "Cryptography output 1"]
#[inline(always)]
pub const fn crypto_output1(
&self,
) -> &'static crate::common::Reg<self::CryptoOutput1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CryptoOutput1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(612usize),
)
}
}
#[doc = "Cryptography output 2"]
#[inline(always)]
pub const fn crypto_output2(
&self,
) -> &'static crate::common::Reg<self::CryptoOutput2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CryptoOutput2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(616usize),
)
}
}
#[doc = "Cryptography output 3"]
#[inline(always)]
pub const fn crypto_output3(
&self,
) -> &'static crate::common::Reg<self::CryptoOutput3_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CryptoOutput3_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(620usize),
)
}
}
#[doc = "Interrupt register"]
#[inline(always)]
pub const fn intr(&self) -> &'static crate::common::Reg<self::Intr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Intr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1984usize),
)
}
}
#[doc = "Interrupt set register"]
#[inline(always)]
pub const fn intr_set(
&self,
) -> &'static crate::common::Reg<self::IntrSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1988usize),
)
}
}
#[doc = "Interrupt mask register"]
#[inline(always)]
pub const fn intr_mask(
&self,
) -> &'static crate::common::Reg<self::IntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1992usize),
)
}
}
#[doc = "Interrupt masked register"]
#[inline(always)]
pub const fn intr_masked(
&self,
) -> &'static crate::common::Reg<self::IntrMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1996usize),
)
}
}
#[doc = "Device (only used in XIP mode)"]
#[inline(always)]
pub fn device(
self,
) -> &'static crate::common::ClusterRegisterArray<crate::smif::_Device, 4, 0x80> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x800usize))
}
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctl_SPEC;
impl crate::sealed::RegSpec for Ctl_SPEC {
type DataType = u32;
}
#[doc = "Control"]
pub type Ctl = crate::RegValueT<Ctl_SPEC>;
impl Ctl {
#[doc = "Mode of operation.\n\nNote: this field should only be changed when the IP is disabled or when STATUS.BUSY is \'0\' and SW should not be executing from the XIP interface or MMIO interface."]
#[inline(always)]
pub fn xip_mode(
self,
) -> crate::common::RegisterField<
0,
0x1,
1,
0,
ctl::XipMode,
ctl::XipMode,
Ctl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1,
1,
0,
ctl::XipMode,
ctl::XipMode,
Ctl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Specifies device interface receiver clock \'clk_if_rx\' source. MISO data is captured on the rising edge of \'clk_if_rx\'.\n\'0\': \'spi_clk_out\' (internal clock)\n\'1\': !\'spi_clk_out\' (internal clock)\n\'2\': \'spi_clk_in\' (feedback clock)\n\'3\': !\'spi_clk_in\' (feedback clock)\n\nNote: the device interface transmitter clock \'clk_if_tx\' is fixed and is \'spi_clk_out\' MOSI data is driven on the falling edge of \'clk_if_tx\'."]
#[inline(always)]
pub fn clock_if_rx_sel(
self,
) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, Ctl_SPEC, crate::common::RW> {
crate::common::RegisterField::<12,0x3,1,0,u8,u8,Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies the minimum duration of SPI deselection (\'spi_select_out\\[\\]\' is high/\'1\') in between SPI transfers:\n\'0\': 1 interface clock cycle.\n\'1\': 2 interface clock cycles.\n\'2\': 3 interface clock cycles.\n\'3\': 4 interface clock cycles.\n\'4\': 5 interface clock cycles.\n\'5\': 6 interface clock cycles.\n\'6\': 7 interface clock cycles.\n\'7\': 8 interface clock cycles.\n\nDuring SPI deselection, \'spi_select_out\\[\\]\' are \'1\'/inactive, \'spi_data_out\\[\\]\' are \'1\' and \'spi_clk_out\' is \'0\'/inactive."]
#[inline(always)]
pub fn deselect_delay(
self,
) -> crate::common::RegisterField<16, 0x7, 1, 0, u8, u8, Ctl_SPEC, crate::common::RW> {
crate::common::RegisterField::<16,0x7,1,0,u8,u8,Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE.\n\nThis field is not used for test controller accesses."]
#[inline(always)]
pub fn block(
self,
) -> crate::common::RegisterField<
24,
0x1,
1,
0,
ctl::Block,
ctl::Block,
Ctl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
24,
0x1,
1,
0,
ctl::Block,
ctl::Block,
Ctl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "IP enable:\n\'0\': Disabled. All non-retention registers are reset to their default value when the IP is disabled. When the IP is disabled, the XIP accesses produce AHB-Lite bus errors.\n\'1\': Enabled.\n\nNote: Before disabling the IP, SW should ensure that the IP is NOT busy (STATUS.BUSY is \'0\'), otherwise illegal interface transfers may occur."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterField<
31,
0x1,
1,
0,
ctl::Enabled,
ctl::Enabled,
Ctl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
31,
0x1,
1,
0,
ctl::Enabled,
ctl::Enabled,
Ctl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Ctl {
#[inline(always)]
fn default() -> Ctl {
<crate::RegValueT<Ctl_SPEC> as RegisterValue<_>>::new(12288)
}
}
pub mod ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct XipMode_SPEC;
pub type XipMode = crate::EnumBitfieldStruct<u8, XipMode_SPEC>;
impl XipMode {
#[doc = "\'0\': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated."]
pub const MMIO_MODE: Self = Self::new(0);
#[doc = "1\': XIP mode. eXecute-In-Place mode: incoming read and write transfers over the AHB-Lite bus infrastructure are automatically translated in SPI transfers to read data from and write data to a device. This mode of operation allow for efficient device read and write operations. This mode is only supported in SPI_MODE."]
pub const XIP_MODE: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Block_SPEC;
pub type Block = crate::EnumBitfieldStruct<u8, Block_SPEC>;
impl Block {
#[doc = "0\': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency)."]
pub const BUS_ERROR: Self = Self::new(0);
#[doc = "1\': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency)."]
pub const WAIT_STATES: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Enabled_SPEC;
pub type Enabled = crate::EnumBitfieldStruct<u8, Enabled_SPEC>;
impl Enabled {
#[doc = "N/A"]
pub const DISABLED: Self = Self::new(0);
#[doc = "N/A"]
pub const ENABLED: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Status_SPEC;
impl crate::sealed::RegSpec for Status_SPEC {
type DataType = u32;
}
#[doc = "Status"]
pub type Status = crate::RegValueT<Status_SPEC>;
impl Status {
#[doc = "Cache, cryptography, XIP, device interface or any other logic busy in the IP:\n\'0\': not busy\n\'1\': busy\nWhen BUSY is \'0\', the IP can be safely disabled without:\n- the potential loss of transient write data.\n- the potential risk of aborting an inflight SPI device interface transfer.\nWhen BUSY is \'0\', the mode of operation (XIP_MODE or MMIO_MODE) can be safely changed."]
#[inline(always)]
pub fn busy(self) -> crate::common::RegisterFieldBool<31, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31, 1, 0, Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Status {
#[inline(always)]
fn default() -> Status {
<crate::RegValueT<Status_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxCmdFifoStatus_SPEC;
impl crate::sealed::RegSpec for TxCmdFifoStatus_SPEC {
type DataType = u32;
}
#[doc = "Transmitter command FIFO status"]
pub type TxCmdFifoStatus = crate::RegValueT<TxCmdFifoStatus_SPEC>;
impl TxCmdFifoStatus {
#[doc = "Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: \\[0, 4\\]."]
#[inline(always)]
pub fn used3(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, TxCmdFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,TxCmdFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for TxCmdFifoStatus {
#[inline(always)]
fn default() -> TxCmdFifoStatus {
<crate::RegValueT<TxCmdFifoStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxCmdFifoWr_SPEC;
impl crate::sealed::RegSpec for TxCmdFifoWr_SPEC {
type DataType = u32;
}
#[doc = "Transmitter command FIFO write"]
pub type TxCmdFifoWr = crate::RegValueT<TxCmdFifoWr_SPEC>;
impl TxCmdFifoWr {
#[doc = "Command data. The higher two bits DATA\\[19:18\\] specify the specific command\n\'0\'/TX: A SPI transfer always start with a TX command FIFO entry of the \'TX\' format.\n- DATA\\[17:16\\] specifies the width of the data transfer:\n - \'0\': 1 bit/cycle (single data transfer).\n - \'1\': 2 bits/cycle (dual data transfer).\n - \'2\': 4 bits/cycle (quad data transfer).\n - \'3\': 8 bits/cycle (octal data transfer).\n- DATA\\[15\\]: specifies whether this is the last TX Byte; i.e. whether the \'spi_select_out\\[3:0\\]\' IO output signals are de-activated after the transfer.\n- DATA\\[11:8\\] specifies which of the four devices are selected. DATA\\[11:8\\] are directly mapped to \'spi_select_out\\[3:0\\]\'. Two devices can be selected at the same time in dual-quad mode.\n - \'0\': device deselected\n - \'1\': device selected \n- DATA\\[7:0\\] specifies the transmitted Byte.\n\n\'1\'/TX_COUNT: The \'TX_COUNT\' command relies on the TX data FIFO to provide the transmitted bytes. The \'TX_COUNT\' command is ALWAYS considered to be the last command of a SPI data transfers.\n- DATA\\[17:16\\] specifies the width of the transfer.\n- DATA\\[15:0\\] specifies the number of to be transmitted Bytes (minus 1) from the TX data FIFO.\n\n\'2\'/RX_COUNT: The \'RX_COUNT\' command relies on the RX data FIFO to accept the received bytes. The \'RX_COUNT\' command is ALWAYS considered to be the last command of a SPI data transfers.\n- DATA\\[17:16\\] specifies the width of the transfer.\n- DATA\\[15:0\\] specifies the number of to be transmitted Bytes (minus 1) to the RX data FIFO.\n\n\'3\'/DUMMY_COUNT: The \'DUMMY_COUNT\' command conveys dummy cycles. Dummy cycles are used to implement a Turn-Around time in which the SPI master changes from a transmitter driving the data lines to a receiver receiving on the same data lines. The \'DUMMY_COUNT\' command is ALWAYS considered to be NOT the last command of a SPI data transfers; i.e. it needs to be followed by another command.\n- DATA\\[15:0\\] specifies the number of dummy cycles (minus 1). In dummy cycles, the data lines are not driven."]
#[inline(always)]
pub fn data20(
self,
) -> crate::common::RegisterField<0, 0xfffff, 1, 0, u32, u32, TxCmdFifoWr_SPEC, crate::common::W>
{
crate::common::RegisterField::<0,0xfffff,1,0,u32,u32,TxCmdFifoWr_SPEC,crate::common::W>::from_register(self,0)
}
}
impl ::core::default::Default for TxCmdFifoWr {
#[inline(always)]
fn default() -> TxCmdFifoWr {
<crate::RegValueT<TxCmdFifoWr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxDataFifoCtl_SPEC;
impl crate::sealed::RegSpec for TxDataFifoCtl_SPEC {
type DataType = u32;
}
#[doc = "Transmitter data FIFO control"]
pub type TxDataFifoCtl = crate::RegValueT<TxDataFifoCtl_SPEC>;
impl TxDataFifoCtl {
#[doc = "Determines when the TX data FIFO \'tr_tx_req\' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE):\n- Trigger is active when TX_DATA_FIFO_STATUS.USED <= TRIGGER_LEVEL."]
#[inline(always)]
pub fn trigger_level(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, TxDataFifoCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,TxDataFifoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TxDataFifoCtl {
#[inline(always)]
fn default() -> TxDataFifoCtl {
<crate::RegValueT<TxDataFifoCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxDataFifoStatus_SPEC;
impl crate::sealed::RegSpec for TxDataFifoStatus_SPEC {
type DataType = u32;
}
#[doc = "Transmitter data FIFO status"]
pub type TxDataFifoStatus = crate::RegValueT<TxDataFifoStatus_SPEC>;
impl TxDataFifoStatus {
#[doc = "Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: \\[0, 8\\]."]
#[inline(always)]
pub fn used4(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, TxDataFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,TxDataFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for TxDataFifoStatus {
#[inline(always)]
fn default() -> TxDataFifoStatus {
<crate::RegValueT<TxDataFifoStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxDataFifoWr1_SPEC;
impl crate::sealed::RegSpec for TxDataFifoWr1_SPEC {
type DataType = u32;
}
#[doc = "Transmitter data FIFO write"]
pub type TxDataFifoWr1 = crate::RegValueT<TxDataFifoWr1_SPEC>;
impl TxDataFifoWr1 {
#[doc = "TX data (written to TX data FIFO)."]
#[inline(always)]
pub fn data0(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, TxDataFifoWr1_SPEC, crate::common::W>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,TxDataFifoWr1_SPEC,crate::common::W>::from_register(self,0)
}
}
impl ::core::default::Default for TxDataFifoWr1 {
#[inline(always)]
fn default() -> TxDataFifoWr1 {
<crate::RegValueT<TxDataFifoWr1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxDataFifoWr2_SPEC;
impl crate::sealed::RegSpec for TxDataFifoWr2_SPEC {
type DataType = u32;
}
#[doc = "Transmitter data FIFO write"]
pub type TxDataFifoWr2 = crate::RegValueT<TxDataFifoWr2_SPEC>;
impl TxDataFifoWr2 {
#[doc = "TX data (written to TX data FIFO, first byte)."]
#[inline(always)]
pub fn data0(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, TxDataFifoWr2_SPEC, crate::common::W>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,TxDataFifoWr2_SPEC,crate::common::W>::from_register(self,0)
}
#[doc = "TX data (written to TX data FIFO, second byte)."]
#[inline(always)]
pub fn data1(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, TxDataFifoWr2_SPEC, crate::common::W>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,TxDataFifoWr2_SPEC,crate::common::W>::from_register(self,0)
}
}
impl ::core::default::Default for TxDataFifoWr2 {
#[inline(always)]
fn default() -> TxDataFifoWr2 {
<crate::RegValueT<TxDataFifoWr2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxDataFifoWr4_SPEC;
impl crate::sealed::RegSpec for TxDataFifoWr4_SPEC {
type DataType = u32;
}
#[doc = "Transmitter data FIFO write"]
pub type TxDataFifoWr4 = crate::RegValueT<TxDataFifoWr4_SPEC>;
impl TxDataFifoWr4 {
#[doc = "TX data (written to TX data FIFO, first byte)."]
#[inline(always)]
pub fn data0(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, TxDataFifoWr4_SPEC, crate::common::W>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,TxDataFifoWr4_SPEC,crate::common::W>::from_register(self,0)
}
#[doc = "TX data (written to TX data FIFO, second byte)."]
#[inline(always)]
pub fn data1(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, TxDataFifoWr4_SPEC, crate::common::W>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,TxDataFifoWr4_SPEC,crate::common::W>::from_register(self,0)
}
#[doc = "TX data (written to TX data FIFO, third byte)."]
#[inline(always)]
pub fn data2(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, TxDataFifoWr4_SPEC, crate::common::W>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,TxDataFifoWr4_SPEC,crate::common::W>::from_register(self,0)
}
#[doc = "TX data (written to TX data FIFO, fourth byte)."]
#[inline(always)]
pub fn data3(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, TxDataFifoWr4_SPEC, crate::common::W>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,TxDataFifoWr4_SPEC,crate::common::W>::from_register(self,0)
}
}
impl ::core::default::Default for TxDataFifoWr4 {
#[inline(always)]
fn default() -> TxDataFifoWr4 {
<crate::RegValueT<TxDataFifoWr4_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxDataFifoCtl_SPEC;
impl crate::sealed::RegSpec for RxDataFifoCtl_SPEC {
type DataType = u32;
}
#[doc = "Receiver data FIFO control"]
pub type RxDataFifoCtl = crate::RegValueT<RxDataFifoCtl_SPEC>;
impl RxDataFifoCtl {
#[doc = "Determines when RX data FIFO \'tr_rx_req\' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE):\n- Trigger is active when RX_DATA_FIFO_STATUS.USED > TRIGGER_LEVEL."]
#[inline(always)]
pub fn trigger_level(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, RxDataFifoCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,RxDataFifoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RxDataFifoCtl {
#[inline(always)]
fn default() -> RxDataFifoCtl {
<crate::RegValueT<RxDataFifoCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxDataFifoStatus_SPEC;
impl crate::sealed::RegSpec for RxDataFifoStatus_SPEC {
type DataType = u32;
}
#[doc = "Receiver data FIFO status"]
pub type RxDataFifoStatus = crate::RegValueT<RxDataFifoStatus_SPEC>;
impl RxDataFifoStatus {
#[doc = "Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: \\[0, 8\\]."]
#[inline(always)]
pub fn used4(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, RxDataFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,RxDataFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for RxDataFifoStatus {
#[inline(always)]
fn default() -> RxDataFifoStatus {
<crate::RegValueT<RxDataFifoStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxDataFifoRd1_SPEC;
impl crate::sealed::RegSpec for RxDataFifoRd1_SPEC {
type DataType = u32;
}
#[doc = "Receiver data FIFO read"]
pub type RxDataFifoRd1 = crate::RegValueT<RxDataFifoRd1_SPEC>;
impl RxDataFifoRd1 {
#[doc = "RX data (read from RX data FIFO)."]
#[inline(always)]
pub fn data0(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, RxDataFifoRd1_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,RxDataFifoRd1_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for RxDataFifoRd1 {
#[inline(always)]
fn default() -> RxDataFifoRd1 {
<crate::RegValueT<RxDataFifoRd1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxDataFifoRd2_SPEC;
impl crate::sealed::RegSpec for RxDataFifoRd2_SPEC {
type DataType = u32;
}
#[doc = "Receiver data FIFO read"]
pub type RxDataFifoRd2 = crate::RegValueT<RxDataFifoRd2_SPEC>;
impl RxDataFifoRd2 {
#[doc = "RX data (read from RX data FIFO, first byte)."]
#[inline(always)]
pub fn data0(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, RxDataFifoRd2_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,RxDataFifoRd2_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "RX data (read from RX data FIFO, second byte)."]
#[inline(always)]
pub fn data1(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, RxDataFifoRd2_SPEC, crate::common::R>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,RxDataFifoRd2_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for RxDataFifoRd2 {
#[inline(always)]
fn default() -> RxDataFifoRd2 {
<crate::RegValueT<RxDataFifoRd2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxDataFifoRd4_SPEC;
impl crate::sealed::RegSpec for RxDataFifoRd4_SPEC {
type DataType = u32;
}
#[doc = "Receiver data FIFO read"]
pub type RxDataFifoRd4 = crate::RegValueT<RxDataFifoRd4_SPEC>;
impl RxDataFifoRd4 {
#[doc = "RX data (read from RX data FIFO, first byte)."]
#[inline(always)]
pub fn data0(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, RxDataFifoRd4_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,RxDataFifoRd4_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "RX data (read from RX data FIFO, second byte)."]
#[inline(always)]
pub fn data1(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, RxDataFifoRd4_SPEC, crate::common::R>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,RxDataFifoRd4_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "RX data (read from RX data FIFO, third byte)."]
#[inline(always)]
pub fn data2(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, RxDataFifoRd4_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,RxDataFifoRd4_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "RX data (read from RX data FIFO, fourth byte)."]
#[inline(always)]
pub fn data3(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, RxDataFifoRd4_SPEC, crate::common::R>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,RxDataFifoRd4_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for RxDataFifoRd4 {
#[inline(always)]
fn default() -> RxDataFifoRd4 {
<crate::RegValueT<RxDataFifoRd4_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxDataFifoRd1Silent_SPEC;
impl crate::sealed::RegSpec for RxDataFifoRd1Silent_SPEC {
type DataType = u32;
}
#[doc = "Receiver data FIFO silent read"]
pub type RxDataFifoRd1Silent = crate::RegValueT<RxDataFifoRd1Silent_SPEC>;
impl RxDataFifoRd1Silent {
#[doc = "RX data (read from RX data FIFO)."]
#[inline(always)]
pub fn data0(
self,
) -> crate::common::RegisterField<
0,
0xff,
1,
0,
u8,
u8,
RxDataFifoRd1Silent_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xff,
1,
0,
u8,
u8,
RxDataFifoRd1Silent_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RxDataFifoRd1Silent {
#[inline(always)]
fn default() -> RxDataFifoRd1Silent {
<crate::RegValueT<RxDataFifoRd1Silent_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SlowCaCtl_SPEC;
impl crate::sealed::RegSpec for SlowCaCtl_SPEC {
type DataType = u32;
}
#[doc = "Slow cache control"]
pub type SlowCaCtl = crate::RegValueT<SlowCaCtl_SPEC>;
impl SlowCaCtl {
#[doc = "this is for debug purpose only, and should be hidden to customers in technical document"]
#[inline(always)]
pub fn way(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, SlowCaCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3,1,0,u8,u8,SlowCaCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "this is for debug purpose only, and should be hidden to customers in technical document"]
#[inline(always)]
pub fn set_addr(
self,
) -> crate::common::RegisterField<24, 0x3, 1, 0, u8, u8, SlowCaCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0x3,1,0,u8,u8,SlowCaCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn pref_en(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, SlowCaCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,SlowCaCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, SlowCaCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,SlowCaCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SlowCaCtl {
#[inline(always)]
fn default() -> SlowCaCtl {
<crate::RegValueT<SlowCaCtl_SPEC> as RegisterValue<_>>::new(3221225472)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SlowCaCmd_SPEC;
impl crate::sealed::RegSpec for SlowCaCmd_SPEC {
type DataType = u32;
}
#[doc = "Slow cache command"]
pub type SlowCaCmd = crate::RegValueT<SlowCaCmd_SPEC>;
impl SlowCaCmd {
#[doc = "Cache and prefetch buffer invalidation. \nSW writes a \'1\' to clear the cache and prefetch buffer. The cache\'s LRU structure is also reset to its default state.\nNote, \nA write access will invalidate the prefetch buffer automatically in hardware.\nA write access should invalidate both fast and slow caches, by firmware.\nNote, firmware should invalidate the cache and prefetch buffer only when STATUS.BUSY is \'0\'."]
#[inline(always)]
pub fn inv(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, SlowCaCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,SlowCaCmd_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SlowCaCmd {
#[inline(always)]
fn default() -> SlowCaCmd {
<crate::RegValueT<SlowCaCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct FastCaCtl_SPEC;
impl crate::sealed::RegSpec for FastCaCtl_SPEC {
type DataType = u32;
}
#[doc = "Fast cache control"]
pub type FastCaCtl = crate::RegValueT<FastCaCtl_SPEC>;
impl FastCaCtl {
#[doc = "this is for debug purpose only, and should be hidden to customers in technical document"]
#[inline(always)]
pub fn way(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, FastCaCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3,1,0,u8,u8,FastCaCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "this is for debug purpose only, and should be hidden to customers in technical document"]
#[inline(always)]
pub fn set_addr(
self,
) -> crate::common::RegisterField<24, 0x3, 1, 0, u8, u8, FastCaCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0x3,1,0,u8,u8,FastCaCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn pref_en(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, FastCaCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,FastCaCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, FastCaCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,FastCaCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for FastCaCtl {
#[inline(always)]
fn default() -> FastCaCtl {
<crate::RegValueT<FastCaCtl_SPEC> as RegisterValue<_>>::new(3221225472)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct FastCaCmd_SPEC;
impl crate::sealed::RegSpec for FastCaCmd_SPEC {
type DataType = u32;
}
#[doc = "Fast cache command"]
pub type FastCaCmd = crate::RegValueT<FastCaCmd_SPEC>;
impl FastCaCmd {
#[doc = "See SLOW_CA_CMD.INV."]
#[inline(always)]
pub fn inv(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, FastCaCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,FastCaCmd_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for FastCaCmd {
#[inline(always)]
fn default() -> FastCaCmd {
<crate::RegValueT<FastCaCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CryptoCmd_SPEC;
impl crate::sealed::RegSpec for CryptoCmd_SPEC {
type DataType = u32;
}
#[doc = "Cryptography Command"]
pub type CryptoCmd = crate::RegValueT<CryptoCmd_SPEC>;
impl CryptoCmd {
#[doc = "SW sets this field to \'1\' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to \'0\' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_RESULT0, ..., CRYPTO_RESULT3.\n\nThe operation takes roughly 13 clk_hf clock cycles.\n\nNote: An operation can only be started in MMIO_MODE."]
#[inline(always)]
pub fn start(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, CryptoCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,CryptoCmd_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CryptoCmd {
#[inline(always)]
fn default() -> CryptoCmd {
<crate::RegValueT<CryptoCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CryptoInput0_SPEC;
impl crate::sealed::RegSpec for CryptoInput0_SPEC {
type DataType = u32;
}
#[doc = "Cryptography input 0"]
pub type CryptoInput0 = crate::RegValueT<CryptoInput0_SPEC>;
impl CryptoInput0 {
#[doc = "Four Bytes of the plaintext PT\\[31:0\\] = CRYPTO_INPUT0.INPUT\\[31:0\\]."]
#[inline(always)]
pub fn input(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoInput0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoInput0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CryptoInput0 {
#[inline(always)]
fn default() -> CryptoInput0 {
<crate::RegValueT<CryptoInput0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CryptoInput1_SPEC;
impl crate::sealed::RegSpec for CryptoInput1_SPEC {
type DataType = u32;
}
#[doc = "Cryptography input 1"]
pub type CryptoInput1 = crate::RegValueT<CryptoInput1_SPEC>;
impl CryptoInput1 {
#[doc = "Four Bytes of the plaintext PT\\[63:32\\] = CRYPTO_INPUT1.INPUT\\[31:0\\]."]
#[inline(always)]
pub fn input(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoInput1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoInput1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CryptoInput1 {
#[inline(always)]
fn default() -> CryptoInput1 {
<crate::RegValueT<CryptoInput1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CryptoInput2_SPEC;
impl crate::sealed::RegSpec for CryptoInput2_SPEC {
type DataType = u32;
}
#[doc = "Cryptography input 2"]
pub type CryptoInput2 = crate::RegValueT<CryptoInput2_SPEC>;
impl CryptoInput2 {
#[doc = "Four Bytes of the plaintext PT\\[95:64\\] = CRYPTO_INPUT2.INPUT\\[31:0\\]."]
#[inline(always)]
pub fn input(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoInput2_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoInput2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CryptoInput2 {
#[inline(always)]
fn default() -> CryptoInput2 {
<crate::RegValueT<CryptoInput2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CryptoInput3_SPEC;
impl crate::sealed::RegSpec for CryptoInput3_SPEC {
type DataType = u32;
}
#[doc = "Cryptography input 3"]
pub type CryptoInput3 = crate::RegValueT<CryptoInput3_SPEC>;
impl CryptoInput3 {
#[doc = "Four Bytes of the plaintext PT\\[127:96\\] = CRYPTO_INPUT3.INPUT\\[31:0\\]."]
#[inline(always)]
pub fn input(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoInput3_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoInput3_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CryptoInput3 {
#[inline(always)]
fn default() -> CryptoInput3 {
<crate::RegValueT<CryptoInput3_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CryptoKey0_SPEC;
impl crate::sealed::RegSpec for CryptoKey0_SPEC {
type DataType = u32;
}
#[doc = "Cryptography key 0"]
pub type CryptoKey0 = crate::RegValueT<CryptoKey0_SPEC>;
impl CryptoKey0 {
#[doc = "Four Bytes of the key KEY\\[31:0\\] = CRYPTO_KEY0.KEY\\[31:0\\]."]
#[inline(always)]
pub fn key(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoKey0_SPEC,
crate::common::W,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoKey0_SPEC,
crate::common::W,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CryptoKey0 {
#[inline(always)]
fn default() -> CryptoKey0 {
<crate::RegValueT<CryptoKey0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CryptoKey1_SPEC;
impl crate::sealed::RegSpec for CryptoKey1_SPEC {
type DataType = u32;
}
#[doc = "Cryptography key 1"]
pub type CryptoKey1 = crate::RegValueT<CryptoKey1_SPEC>;
impl CryptoKey1 {
#[doc = "Four Bytes of the key KEY\\[63:32\\] = CRYPTO_KEY1.KEY\\[31:0\\]."]
#[inline(always)]
pub fn key(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoKey1_SPEC,
crate::common::W,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoKey1_SPEC,
crate::common::W,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CryptoKey1 {
#[inline(always)]
fn default() -> CryptoKey1 {
<crate::RegValueT<CryptoKey1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CryptoKey2_SPEC;
impl crate::sealed::RegSpec for CryptoKey2_SPEC {
type DataType = u32;
}
#[doc = "Cryptography key 2"]
pub type CryptoKey2 = crate::RegValueT<CryptoKey2_SPEC>;
impl CryptoKey2 {
#[doc = "Four Bytes of the key KEY\\[95:64\\] = CRYPTO_KEY2.KEY\\[31:0\\]."]
#[inline(always)]
pub fn key(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoKey2_SPEC,
crate::common::W,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoKey2_SPEC,
crate::common::W,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CryptoKey2 {
#[inline(always)]
fn default() -> CryptoKey2 {
<crate::RegValueT<CryptoKey2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CryptoKey3_SPEC;
impl crate::sealed::RegSpec for CryptoKey3_SPEC {
type DataType = u32;
}
#[doc = "Cryptography key 3"]
pub type CryptoKey3 = crate::RegValueT<CryptoKey3_SPEC>;
impl CryptoKey3 {
#[doc = "Four Bytes of the key KEY\\[127:96\\] = CRYPTO_KEY3.KEY\\[31:0\\]."]
#[inline(always)]
pub fn key(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoKey3_SPEC,
crate::common::W,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoKey3_SPEC,
crate::common::W,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CryptoKey3 {
#[inline(always)]
fn default() -> CryptoKey3 {
<crate::RegValueT<CryptoKey3_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CryptoOutput0_SPEC;
impl crate::sealed::RegSpec for CryptoOutput0_SPEC {
type DataType = u32;
}
#[doc = "Cryptography output 0"]
pub type CryptoOutput0 = crate::RegValueT<CryptoOutput0_SPEC>;
impl CryptoOutput0 {
#[doc = "Four Bytes of the ciphertext CT\\[31:0\\] = CRYPTO_OUTPUT0.OUTPUT\\[31:0\\]."]
#[inline(always)]
pub fn output(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoOutput0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoOutput0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CryptoOutput0 {
#[inline(always)]
fn default() -> CryptoOutput0 {
<crate::RegValueT<CryptoOutput0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CryptoOutput1_SPEC;
impl crate::sealed::RegSpec for CryptoOutput1_SPEC {
type DataType = u32;
}
#[doc = "Cryptography output 1"]
pub type CryptoOutput1 = crate::RegValueT<CryptoOutput1_SPEC>;
impl CryptoOutput1 {
#[doc = "Four Bytes of the ciphertext CT\\[63:32\\] = CRYPTO_OUTPUT1.OUTPUT\\[31:0\\]."]
#[inline(always)]
pub fn output(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoOutput1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoOutput1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CryptoOutput1 {
#[inline(always)]
fn default() -> CryptoOutput1 {
<crate::RegValueT<CryptoOutput1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CryptoOutput2_SPEC;
impl crate::sealed::RegSpec for CryptoOutput2_SPEC {
type DataType = u32;
}
#[doc = "Cryptography output 2"]
pub type CryptoOutput2 = crate::RegValueT<CryptoOutput2_SPEC>;
impl CryptoOutput2 {
#[doc = "Four Bytes of the ciphertext CT\\[95:64\\] = CRYPTO_OUTPUT2.OUTPUT\\[31:0\\]."]
#[inline(always)]
pub fn output(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoOutput2_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoOutput2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CryptoOutput2 {
#[inline(always)]
fn default() -> CryptoOutput2 {
<crate::RegValueT<CryptoOutput2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CryptoOutput3_SPEC;
impl crate::sealed::RegSpec for CryptoOutput3_SPEC {
type DataType = u32;
}
#[doc = "Cryptography output 3"]
pub type CryptoOutput3 = crate::RegValueT<CryptoOutput3_SPEC>;
impl CryptoOutput3 {
#[doc = "Four Bytes of the ciphertext CT\\[127:96\\] = CRYPTO_OUTPUT3.OUTPUT\\[31:0\\]."]
#[inline(always)]
pub fn output(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoOutput3_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CryptoOutput3_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CryptoOutput3 {
#[inline(always)]
fn default() -> CryptoOutput3 {
<crate::RegValueT<CryptoOutput3_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Intr_SPEC;
impl crate::sealed::RegSpec for Intr_SPEC {
type DataType = u32;
}
#[doc = "Interrupt register"]
pub type Intr = crate::RegValueT<Intr_SPEC>;
impl Intr {
#[doc = "Activated in MMIO mode, when a TX data FIFO trigger \'tr_tx_req\' is activated."]
#[inline(always)]
pub fn tr_tx_req(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Activated in MMIO mode, when a RX data FIFO trigger \'tr_rx_req\' is activated."]
#[inline(always)]
pub fn tr_rx_req(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Activated in XIP mode, if:\n- The selected device\'s ADDR_CTL.DIV2 is \'1\' and the AHB-Lite bus transfer address is not a multiple of 2.\n- The selected device\'s ADDR_CTL.DIV2 is \'1\' and the XIP transfer request is NOT for a multiple of 2 Bytes. \n\nNote: In dual-quad SPI mode (ADDR_CTL.DIV is \'1\'), each memory device contributes a 4-bit nibble for read data or write data. This is only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2."]
#[inline(always)]
pub fn xip_alignment_error(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available."]
#[inline(always)]
pub fn tx_cmd_fifo_overflow(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, TX_DATA_FIFO_WR4) with not enough free entries available."]
#[inline(always)]
pub fn tx_data_fifo_overflow(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Activated in MMIO mode, on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FIFO_RD1, RX_DATA_FIFO_RD2, RX_DATA_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers."]
#[inline(always)]
pub fn rx_data_fifo_underflow(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Intr {
#[inline(always)]
fn default() -> Intr {
<crate::RegValueT<Intr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSet_SPEC;
impl crate::sealed::RegSpec for IntrSet_SPEC {
type DataType = u32;
}
#[doc = "Interrupt set register"]
pub type IntrSet = crate::RegValueT<IntrSet_SPEC>;
impl IntrSet {
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tr_tx_req(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tr_rx_req(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn xip_alignment_error(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_cmd_fifo_overflow(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_data_fifo_overflow(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_data_fifo_underflow(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for IntrSet {
#[inline(always)]
fn default() -> IntrSet {
<crate::RegValueT<IntrSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMask_SPEC;
impl crate::sealed::RegSpec for IntrMask_SPEC {
type DataType = u32;
}
#[doc = "Interrupt mask register"]
pub type IntrMask = crate::RegValueT<IntrMask_SPEC>;
impl IntrMask {
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tr_tx_req(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tr_rx_req(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn xip_alignment_error(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_cmd_fifo_overflow(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_data_fifo_overflow(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_data_fifo_underflow(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for IntrMask {
#[inline(always)]
fn default() -> IntrMask {
<crate::RegValueT<IntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMasked_SPEC;
impl crate::sealed::RegSpec for IntrMasked_SPEC {
type DataType = u32;
}
#[doc = "Interrupt masked register"]
pub type IntrMasked = crate::RegValueT<IntrMasked_SPEC>;
impl IntrMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tr_tx_req(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tr_rx_req(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn xip_alignment_error(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tx_cmd_fifo_overflow(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tx_data_fifo_overflow(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn rx_data_fifo_underflow(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMasked {
#[inline(always)]
fn default() -> IntrMasked {
<crate::RegValueT<IntrMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc = "Device (only used in XIP mode)"]
#[non_exhaustive]
pub struct _Device;
#[doc = "Device (only used in XIP mode)"]
pub type Device = &'static _Device;
unsafe impl ::core::marker::Sync for _Device {}
impl _Device {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "Control"]
#[inline(always)]
pub const fn ctl(&self) -> &'static crate::common::Reg<device::Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<device::Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Device region base address"]
#[inline(always)]
pub const fn addr(&self) -> &'static crate::common::Reg<device::Addr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<device::Addr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(8usize),
)
}
}
#[doc = "Device region mask"]
#[inline(always)]
pub const fn mask(&self) -> &'static crate::common::Reg<device::Mask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<device::Mask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(12usize),
)
}
}
#[doc = "Address control"]
#[inline(always)]
pub const fn addr_ctl(
&self,
) -> &'static crate::common::Reg<device::AddrCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<device::AddrCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "Read command control"]
#[inline(always)]
pub const fn rd_cmd_ctl(
&self,
) -> &'static crate::common::Reg<device::RdCmdCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<device::RdCmdCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(64usize),
)
}
}
#[doc = "Read address control"]
#[inline(always)]
pub const fn rd_addr_ctl(
&self,
) -> &'static crate::common::Reg<device::RdAddrCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<device::RdAddrCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(68usize),
)
}
}
#[doc = "Read mode control"]
#[inline(always)]
pub const fn rd_mode_ctl(
&self,
) -> &'static crate::common::Reg<device::RdModeCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<device::RdModeCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(72usize),
)
}
}
#[doc = "Read dummy control"]
#[inline(always)]
pub const fn rd_dummy_ctl(
&self,
) -> &'static crate::common::Reg<device::RdDummyCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<device::RdDummyCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(76usize),
)
}
}
#[doc = "Read data control"]
#[inline(always)]
pub const fn rd_data_ctl(
&self,
) -> &'static crate::common::Reg<device::RdDataCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<device::RdDataCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(80usize),
)
}
}
#[doc = "Write command control"]
#[inline(always)]
pub const fn wr_cmd_ctl(
&self,
) -> &'static crate::common::Reg<device::WrCmdCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<device::WrCmdCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(96usize),
)
}
}
#[doc = "Write address control"]
#[inline(always)]
pub const fn wr_addr_ctl(
&self,
) -> &'static crate::common::Reg<device::WrAddrCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<device::WrAddrCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(100usize),
)
}
}
#[doc = "Write mode control"]
#[inline(always)]
pub const fn wr_mode_ctl(
&self,
) -> &'static crate::common::Reg<device::WrModeCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<device::WrModeCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(104usize),
)
}
}
#[doc = "Write dummy control"]
#[inline(always)]
pub const fn wr_dummy_ctl(
&self,
) -> &'static crate::common::Reg<device::WrDummyCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<device::WrDummyCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(108usize),
)
}
}
#[doc = "Write data control"]
#[inline(always)]
pub const fn wr_data_ctl(
&self,
) -> &'static crate::common::Reg<device::WrDataCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<device::WrDataCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(112usize),
)
}
}
}
pub mod device {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctl_SPEC;
impl crate::sealed::RegSpec for Ctl_SPEC {
type DataType = u32;
}
#[doc = "Control"]
pub type Ctl = crate::RegValueT<Ctl_SPEC>;
impl Ctl {
#[doc = "Write enable:\n\'0\': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error.\n\'1\': write transfers are allowed to this device."]
#[inline(always)]
pub fn wr_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Ctl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Cryptography on read/write accesses:\n\'0\': disabled.\n\'1\': enabled."]
#[inline(always)]
pub fn crypto_en(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, Ctl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Specifies the connection of the IP\'s data lines (spi_data\\[0\\], ..., spi_data\\[7\\]) to the device\'s data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7):\n\'0\': spi_data\\[0\\] = IO0, spi_data\\[1\\] = IO1, ..., spi_data\\[7\\] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode.\n\'1\': spi_data\\[2\\] = IO0, spi_data\\[3\\] = IO1. This value is only allowed for single and dual SPI modes.\n\'2\': spi_data\\[4\\] = IO0, spi_data\\[5\\] = IO1, ..., spi_data\\[7\\] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. \n\'3\': spi_data\\[6\\] = IO0, spi_data\\[7\\] = IO1. This value is only allowed for single and dual SPI modes."]
#[inline(always)]
pub fn data_sel(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3,1,0,u8,u8,Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Device enable:\n\'0\': Disabled.\n\'1\': Enabled."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31, 1, 0, Ctl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Ctl {
#[inline(always)]
fn default() -> Ctl {
<crate::RegValueT<Ctl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Addr_SPEC;
impl crate::sealed::RegSpec for Addr_SPEC {
type DataType = u32;
}
#[doc = "Device region base address"]
pub type Addr = crate::RegValueT<Addr_SPEC>;
impl Addr {
#[doc = "Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m.\n\nIn dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index.\n\nThe most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR\\[31:24\\] = SMIF_XIP_ADDR\\[31:24\\]."]
#[inline(always)]
pub fn addr(
self,
) -> crate::common::RegisterField<8, 0xffffff, 1, 0, u32, u32, Addr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xffffff,1,0,u32,u32,Addr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Addr {
#[inline(always)]
fn default() -> Addr {
<crate::RegValueT<Addr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Mask_SPEC;
impl crate::sealed::RegSpec for Mask_SPEC {
type DataType = u32;
}
#[doc = "Device region mask"]
pub type Mask = crate::RegValueT<Mask_SPEC>;
impl Mask {
#[doc = "Specifies the size of the device region. All \'1\' bits are used to compare the incoming transfer request address A\\[31:0\\] with the address as specified in ADDR.ADDR: Address A is in the device when (A\\[31:8\\] & MASK\\[31:8\\]) == ADDR.ADDR\\[31:8\\].\n\nThe most significant bit fields are constants and set to\'1\'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK\\[31:24\\] = 0xff.\n\nNote: a transfer request that is not in any device region results in an AHB-Lite bus error."]
#[inline(always)]
pub fn mask(
self,
) -> crate::common::RegisterField<8, 0xffffff, 1, 0, u32, u32, Mask_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xffffff,1,0,u32,u32,Mask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Mask {
#[inline(always)]
fn default() -> Mask {
<crate::RegValueT<Mask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AddrCtl_SPEC;
impl crate::sealed::RegSpec for AddrCtl_SPEC {
type DataType = u32;
}
#[doc = "Address control"]
pub type AddrCtl = crate::RegValueT<AddrCtl_SPEC>;
impl AddrCtl {
#[doc = "Specifies the size of the XIP device address in Bytes:\n\'0\': 1 Byte address.\n\'1\': 2 Byte address.\n\'2\': 3 Byte address.\n\'3\': 4 Byte address.\nThe lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated."]
#[inline(always)]
pub fn size2(
self,
) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, AddrCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x3,1,0,u8,u8,AddrCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies if the AHB-Lite bus transfer address is divided by 2 or not:\n\'0\': No divide by 2.\n\'1\': Divide by 2. \n\nThis functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to \'1\' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated."]
#[inline(always)]
pub fn div2(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, AddrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,AddrCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for AddrCtl {
#[inline(always)]
fn default() -> AddrCtl {
<crate::RegValueT<AddrCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RdCmdCtl_SPEC;
impl crate::sealed::RegSpec for RdCmdCtl_SPEC {
type DataType = u32;
}
#[doc = "Read command control"]
pub type RdCmdCtl = crate::RegValueT<RdCmdCtl_SPEC>;
impl RdCmdCtl {
#[doc = "Command byte code."]
#[inline(always)]
pub fn code(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, RdCmdCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,RdCmdCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Width of data transfer:\n\'0\': 1 bit/cycle (single data transfer).\n\'1\': 2 bits/cycle (dual data transfer).\n\'2\': 4 bits/cycle (quad data transfer).\n\'3\': 8 bits/cycle (octal data transfer)."]
#[inline(always)]
pub fn width(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, RdCmdCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3,1,0,u8,u8,RdCmdCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Presence of command field:\n\'0\': not present\n\'1\': present"]
#[inline(always)]
pub fn present(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, RdCmdCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,RdCmdCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RdCmdCtl {
#[inline(always)]
fn default() -> RdCmdCtl {
<crate::RegValueT<RdCmdCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RdAddrCtl_SPEC;
impl crate::sealed::RegSpec for RdAddrCtl_SPEC {
type DataType = u32;
}
#[doc = "Read address control"]
pub type RdAddrCtl = crate::RegValueT<RdAddrCtl_SPEC>;
impl RdAddrCtl {
#[doc = "Width of transfer."]
#[inline(always)]
pub fn width(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, RdAddrCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3,1,0,u8,u8,RdAddrCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RdAddrCtl {
#[inline(always)]
fn default() -> RdAddrCtl {
<crate::RegValueT<RdAddrCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RdModeCtl_SPEC;
impl crate::sealed::RegSpec for RdModeCtl_SPEC {
type DataType = u32;
}
#[doc = "Read mode control"]
pub type RdModeCtl = crate::RegValueT<RdModeCtl_SPEC>;
impl RdModeCtl {
#[doc = "Mode byte code."]
#[inline(always)]
pub fn code(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, RdModeCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,RdModeCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Width of transfer."]
#[inline(always)]
pub fn width(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, RdModeCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3,1,0,u8,u8,RdModeCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Presence of mode field:\n\'0\': not present\n\'1\': present"]
#[inline(always)]
pub fn present(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, RdModeCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,RdModeCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RdModeCtl {
#[inline(always)]
fn default() -> RdModeCtl {
<crate::RegValueT<RdModeCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RdDummyCtl_SPEC;
impl crate::sealed::RegSpec for RdDummyCtl_SPEC {
type DataType = u32;
}
#[doc = "Read dummy control"]
pub type RdDummyCtl = crate::RegValueT<RdDummyCtl_SPEC>;
impl RdDummyCtl {
#[doc = "Number of dummy cycles (minus 1):\n\'0\': 1 cycles\n...\n\'31\': 32 cycles.\n\nNote: this field specifies dummy cycles, not dummy Bytes!"]
#[inline(always)]
pub fn size5(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, RdDummyCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,RdDummyCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Presence of dummy cycles:\n\'0\': not present\n\'1\': present"]
#[inline(always)]
pub fn present(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, RdDummyCtl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<31,1,0,RdDummyCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RdDummyCtl {
#[inline(always)]
fn default() -> RdDummyCtl {
<crate::RegValueT<RdDummyCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RdDataCtl_SPEC;
impl crate::sealed::RegSpec for RdDataCtl_SPEC {
type DataType = u32;
}
#[doc = "Read data control"]
pub type RdDataCtl = crate::RegValueT<RdDataCtl_SPEC>;
impl RdDataCtl {
#[doc = "Width of transfer."]
#[inline(always)]
pub fn width(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, RdDataCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3,1,0,u8,u8,RdDataCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RdDataCtl {
#[inline(always)]
fn default() -> RdDataCtl {
<crate::RegValueT<RdDataCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WrCmdCtl_SPEC;
impl crate::sealed::RegSpec for WrCmdCtl_SPEC {
type DataType = u32;
}
#[doc = "Write command control"]
pub type WrCmdCtl = crate::RegValueT<WrCmdCtl_SPEC>;
impl WrCmdCtl {
#[doc = "Command byte code."]
#[inline(always)]
pub fn code(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, WrCmdCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,WrCmdCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Width of transfer."]
#[inline(always)]
pub fn width(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, WrCmdCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3,1,0,u8,u8,WrCmdCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Presence of command field:\n\'0\': not present\n\'1\': present"]
#[inline(always)]
pub fn present(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, WrCmdCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,WrCmdCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for WrCmdCtl {
#[inline(always)]
fn default() -> WrCmdCtl {
<crate::RegValueT<WrCmdCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WrAddrCtl_SPEC;
impl crate::sealed::RegSpec for WrAddrCtl_SPEC {
type DataType = u32;
}
#[doc = "Write address control"]
pub type WrAddrCtl = crate::RegValueT<WrAddrCtl_SPEC>;
impl WrAddrCtl {
#[doc = "Width of transfer."]
#[inline(always)]
pub fn width(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, WrAddrCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3,1,0,u8,u8,WrAddrCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for WrAddrCtl {
#[inline(always)]
fn default() -> WrAddrCtl {
<crate::RegValueT<WrAddrCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WrModeCtl_SPEC;
impl crate::sealed::RegSpec for WrModeCtl_SPEC {
type DataType = u32;
}
#[doc = "Write mode control"]
pub type WrModeCtl = crate::RegValueT<WrModeCtl_SPEC>;
impl WrModeCtl {
#[doc = "Mode byte code."]
#[inline(always)]
pub fn code(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, WrModeCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,WrModeCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Width of transfer."]
#[inline(always)]
pub fn width(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, WrModeCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3,1,0,u8,u8,WrModeCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Presence of mode field:\n\'0\': not present\n\'1\': present"]
#[inline(always)]
pub fn present(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, WrModeCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,WrModeCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for WrModeCtl {
#[inline(always)]
fn default() -> WrModeCtl {
<crate::RegValueT<WrModeCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WrDummyCtl_SPEC;
impl crate::sealed::RegSpec for WrDummyCtl_SPEC {
type DataType = u32;
}
#[doc = "Write dummy control"]
pub type WrDummyCtl = crate::RegValueT<WrDummyCtl_SPEC>;
impl WrDummyCtl {
#[doc = "Number of dummy cycles (minus 1):\n\'0\': 1 cycles\n...\n\'31\': 32 cycles."]
#[inline(always)]
pub fn size5(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, WrDummyCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,WrDummyCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Presence of dummy cycles:\n\'0\': not present\n\'1\': present"]
#[inline(always)]
pub fn present(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, WrDummyCtl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<31,1,0,WrDummyCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for WrDummyCtl {
#[inline(always)]
fn default() -> WrDummyCtl {
<crate::RegValueT<WrDummyCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WrDataCtl_SPEC;
impl crate::sealed::RegSpec for WrDataCtl_SPEC {
type DataType = u32;
}
#[doc = "Write data control"]
pub type WrDataCtl = crate::RegValueT<WrDataCtl_SPEC>;
impl WrDataCtl {
#[doc = "Width of transfer."]
#[inline(always)]
pub fn width(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, WrDataCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3,1,0,u8,u8,WrDataCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for WrDataCtl {
#[inline(always)]
fn default() -> WrDataCtl {
<crate::RegValueT<WrDataCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
}