/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"Cryptography component"]
unsafe impl ::core::marker::Send for super::Crypto {}
unsafe impl ::core::marker::Sync for super::Crypto {}
impl super::Crypto {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "Control"]
#[inline(always)]
pub const fn ctl(&self) -> &'static crate::common::Reg<self::Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Status"]
#[inline(always)]
pub const fn status(&self) -> &'static crate::common::Reg<self::Status_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::Status_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "Power up delay used for SRAM power domain"]
#[inline(always)]
pub const fn ram_pwrup_delay(
&self,
) -> &'static crate::common::Reg<self::RamPwrupDelay_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::RamPwrupDelay_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(8usize),
)
}
}
#[doc = "Error status 0"]
#[inline(always)]
pub const fn error_status0(
&self,
) -> &'static crate::common::Reg<self::ErrorStatus0_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::ErrorStatus0_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "Error status 1"]
#[inline(always)]
pub const fn error_status1(
&self,
) -> &'static crate::common::Reg<self::ErrorStatus1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ErrorStatus1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
#[doc = "Instruction FIFO control"]
#[inline(always)]
pub const fn instr_ff_ctl(
&self,
) -> &'static crate::common::Reg<self::InstrFfCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::InstrFfCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(64usize),
)
}
}
#[doc = "Instruction FIFO status"]
#[inline(always)]
pub const fn instr_ff_status(
&self,
) -> &'static crate::common::Reg<self::InstrFfStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::InstrFfStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(68usize),
)
}
}
#[doc = "Instruction FIFO write"]
#[inline(always)]
pub const fn instr_ff_wr(
&self,
) -> &'static crate::common::Reg<self::InstrFfWr_SPEC, crate::common::W> {
unsafe {
crate::common::Reg::<self::InstrFfWr_SPEC, crate::common::W>::from_ptr(
self._svd2pac_as_ptr().add(72usize),
)
}
}
#[doc = "Register-file"]
#[inline(always)]
pub const fn rf_data(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::RfData_SPEC, crate::common::R>,
16,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x80usize))
}
}
#[doc = "AES control"]
#[inline(always)]
pub const fn aes_ctl(
&self,
) -> &'static crate::common::Reg<self::AesCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::AesCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(256usize),
)
}
}
#[doc = "String result"]
#[inline(always)]
pub const fn str_result(
&self,
) -> &'static crate::common::Reg<self::StrResult_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::StrResult_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(384usize),
)
}
}
#[doc = "Pseudo random LFSR control 0"]
#[inline(always)]
pub const fn pr_lfsr_ctl0(
&self,
) -> &'static crate::common::Reg<self::PrLfsrCtl0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::PrLfsrCtl0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(512usize),
)
}
}
#[doc = "Pseudo random LFSR control 1"]
#[inline(always)]
pub const fn pr_lfsr_ctl1(
&self,
) -> &'static crate::common::Reg<self::PrLfsrCtl1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::PrLfsrCtl1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(516usize),
)
}
}
#[doc = "Pseudo random LFSR control 2"]
#[inline(always)]
pub const fn pr_lfsr_ctl2(
&self,
) -> &'static crate::common::Reg<self::PrLfsrCtl2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::PrLfsrCtl2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(520usize),
)
}
}
#[doc = "Pseudo random result"]
#[inline(always)]
pub const fn pr_result(
&self,
) -> &'static crate::common::Reg<self::PrResult_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::PrResult_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(528usize),
)
}
}
#[doc = "True random control 0"]
#[inline(always)]
pub const fn tr_ctl0(
&self,
) -> &'static crate::common::Reg<self::TrCtl0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TrCtl0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(640usize),
)
}
}
#[doc = "True random control 1"]
#[inline(always)]
pub const fn tr_ctl1(
&self,
) -> &'static crate::common::Reg<self::TrCtl1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TrCtl1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(644usize),
)
}
}
#[doc = "True random result"]
#[inline(always)]
pub const fn tr_result(
&self,
) -> &'static crate::common::Reg<self::TrResult_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TrResult_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(648usize),
)
}
}
#[doc = "True random GARO control"]
#[inline(always)]
pub const fn tr_garo_ctl(
&self,
) -> &'static crate::common::Reg<self::TrGaroCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TrGaroCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(672usize),
)
}
}
#[doc = "True random FIRO control"]
#[inline(always)]
pub const fn tr_firo_ctl(
&self,
) -> &'static crate::common::Reg<self::TrFiroCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TrFiroCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(676usize),
)
}
}
#[doc = "True random monitor control"]
#[inline(always)]
pub const fn tr_mon_ctl(
&self,
) -> &'static crate::common::Reg<self::TrMonCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TrMonCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(704usize),
)
}
}
#[doc = "True random monitor command"]
#[inline(always)]
pub const fn tr_mon_cmd(
&self,
) -> &'static crate::common::Reg<self::TrMonCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TrMonCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(712usize),
)
}
}
#[doc = "True random monitor RC control"]
#[inline(always)]
pub const fn tr_mon_rc_ctl(
&self,
) -> &'static crate::common::Reg<self::TrMonRcCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TrMonRcCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(720usize),
)
}
}
#[doc = "True random monitor RC status 0"]
#[inline(always)]
pub const fn tr_mon_rc_status0(
&self,
) -> &'static crate::common::Reg<self::TrMonRcStatus0_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::TrMonRcStatus0_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(728usize),
)
}
}
#[doc = "True random monitor RC status 1"]
#[inline(always)]
pub const fn tr_mon_rc_status1(
&self,
) -> &'static crate::common::Reg<self::TrMonRcStatus1_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::TrMonRcStatus1_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(732usize),
)
}
}
#[doc = "True random monitor AP control"]
#[inline(always)]
pub const fn tr_mon_ap_ctl(
&self,
) -> &'static crate::common::Reg<self::TrMonApCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TrMonApCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(736usize),
)
}
}
#[doc = "True random monitor AP status 0"]
#[inline(always)]
pub const fn tr_mon_ap_status0(
&self,
) -> &'static crate::common::Reg<self::TrMonApStatus0_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::TrMonApStatus0_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(744usize),
)
}
}
#[doc = "True random monitor AP status 1"]
#[inline(always)]
pub const fn tr_mon_ap_status1(
&self,
) -> &'static crate::common::Reg<self::TrMonApStatus1_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::TrMonApStatus1_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(748usize),
)
}
}
#[doc = "SHA control"]
#[inline(always)]
pub const fn sha_ctl(
&self,
) -> &'static crate::common::Reg<self::ShaCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ShaCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(768usize),
)
}
}
#[doc = "CRC control"]
#[inline(always)]
pub const fn crc_ctl(
&self,
) -> &'static crate::common::Reg<self::CrcCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CrcCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1024usize),
)
}
}
#[doc = "CRC data control"]
#[inline(always)]
pub const fn crc_data_ctl(
&self,
) -> &'static crate::common::Reg<self::CrcDataCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CrcDataCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1040usize),
)
}
}
#[doc = "CRC polynomial control"]
#[inline(always)]
pub const fn crc_pol_ctl(
&self,
) -> &'static crate::common::Reg<self::CrcPolCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CrcPolCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1056usize),
)
}
}
#[doc = "CRC LFSR control"]
#[inline(always)]
pub const fn crc_lfsr_ctl(
&self,
) -> &'static crate::common::Reg<self::CrcLfsrCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CrcLfsrCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1072usize),
)
}
}
#[doc = "CRC remainder control"]
#[inline(always)]
pub const fn crc_rem_ctl(
&self,
) -> &'static crate::common::Reg<self::CrcRemCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CrcRemCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1088usize),
)
}
}
#[doc = "CRC remainder result"]
#[inline(always)]
pub const fn crc_rem_result(
&self,
) -> &'static crate::common::Reg<self::CrcRemResult_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::CrcRemResult_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1096usize),
)
}
}
#[doc = "Vector unit control 0"]
#[inline(always)]
pub const fn vu_ctl0(
&self,
) -> &'static crate::common::Reg<self::VuCtl0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::VuCtl0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1152usize),
)
}
}
#[doc = "Vector unit control 1"]
#[inline(always)]
pub const fn vu_ctl1(
&self,
) -> &'static crate::common::Reg<self::VuCtl1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::VuCtl1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1156usize),
)
}
}
#[doc = "Vector unit status"]
#[inline(always)]
pub const fn vu_status(
&self,
) -> &'static crate::common::Reg<self::VuStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::VuStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1168usize),
)
}
}
#[doc = "Interrupt register"]
#[inline(always)]
pub const fn intr(&self) -> &'static crate::common::Reg<self::Intr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Intr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1984usize),
)
}
}
#[doc = "Interrupt set register"]
#[inline(always)]
pub const fn intr_set(
&self,
) -> &'static crate::common::Reg<self::IntrSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1988usize),
)
}
}
#[doc = "Interrupt mask register"]
#[inline(always)]
pub const fn intr_mask(
&self,
) -> &'static crate::common::Reg<self::IntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1992usize),
)
}
}
#[doc = "Interrupt masked register"]
#[inline(always)]
pub const fn intr_masked(
&self,
) -> &'static crate::common::Reg<self::IntrMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1996usize),
)
}
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctl_SPEC;
impl crate::sealed::RegSpec for Ctl_SPEC {
type DataType = u32;
}
#[doc = "Control"]
pub type Ctl = crate::RegValueT<Ctl_SPEC>;
impl Ctl {
#[doc = "Set power mode for memory buffer SRAM."]
#[inline(always)]
pub fn pwr_mode(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
ctl::PwrMode,
ctl::PwrMode,
Ctl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
ctl::PwrMode,
ctl::PwrMode,
Ctl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "IP enable:\n\'0\': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled.\n\'1\': Enabled."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterField<
31,
0x1,
1,
0,
ctl::Enabled,
ctl::Enabled,
Ctl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
31,
0x1,
1,
0,
ctl::Enabled,
ctl::Enabled,
Ctl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Ctl {
#[inline(always)]
fn default() -> Ctl {
<crate::RegValueT<Ctl_SPEC> as RegisterValue<_>>::new(3)
}
}
pub mod ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PwrMode_SPEC;
pub type PwrMode = crate::EnumBitfieldStruct<u8, PwrMode_SPEC>;
impl PwrMode {
#[doc = "See CM4_PWR_CTL"]
pub const OFF: Self = Self::new(0);
#[doc = "undefined"]
pub const RSVD: Self = Self::new(1);
#[doc = "See CM4_PWR_CTL"]
pub const RETAINED: Self = Self::new(2);
#[doc = "See CM4_PWR_CTL"]
pub const ENABLED: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Enabled_SPEC;
pub type Enabled = crate::EnumBitfieldStruct<u8, Enabled_SPEC>;
impl Enabled {
#[doc = "N/A"]
pub const DISABLED: Self = Self::new(0);
#[doc = "N/A"]
pub const ENABLED: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Status_SPEC;
impl crate::sealed::RegSpec for Status_SPEC {
type DataType = u32;
}
#[doc = "Status"]
pub type Status = crate::RegValueT<Status_SPEC>;
impl Status {
#[doc = "Reflects the state of the AES component:\n\'0\': Component is not busy.\n\'1\': Component is busy performing an instruction.\nWhen the component is busy, it is NOT possible to start another operation. However, it is possible to access the instruction FIFO or memory buffer (to prepare for another operation)."]
#[inline(always)]
pub fn aes_busy(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Reflects the state of the DES component."]
#[inline(always)]
pub fn des_busy(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1, 1, 0, Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Reflects the state of the SHA component."]
#[inline(always)]
pub fn sha_busy(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2, 1, 0, Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Reflects the state of the CRC component."]
#[inline(always)]
pub fn crc_busy(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3, 1, 0, Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Reflects the state of the CRC component."]
#[inline(always)]
pub fn str_busy(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4, 1, 0, Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Reflects the state of the PR component."]
#[inline(always)]
pub fn pr_busy(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5, 1, 0, Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Reflects the state of the TR component."]
#[inline(always)]
pub fn tr_busy(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<6, 1, 0, Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Reflects the state of the vector unit component."]
#[inline(always)]
pub fn vu_busy(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<7, 1, 0, Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Reflects the state of the command FIFO (copy of CMD_FF_STATUS.BUSY):\n\'0\': No instruction pending.\n\'1\': Instruction pending."]
#[inline(always)]
pub fn cmd_ff_busy(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31, 1, 0, Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Status {
#[inline(always)]
fn default() -> Status {
<crate::RegValueT<Status_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RamPwrupDelay_SPEC;
impl crate::sealed::RegSpec for RamPwrupDelay_SPEC {
type DataType = u32;
}
#[doc = "Power up delay used for SRAM power domain"]
pub type RamPwrupDelay = crate::RegValueT<RamPwrupDelay_SPEC>;
impl RamPwrupDelay {
#[doc = "Number clock cycles delay needed after power domain power up"]
#[inline(always)]
pub fn pwrup_delay(
self,
) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, RamPwrupDelay_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0x3ff,
1,
0,
u16,
u16,
RamPwrupDelay_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RamPwrupDelay {
#[inline(always)]
fn default() -> RamPwrupDelay {
<crate::RegValueT<RamPwrupDelay_SPEC> as RegisterValue<_>>::new(150)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ErrorStatus0_SPEC;
impl crate::sealed::RegSpec for ErrorStatus0_SPEC {
type DataType = u32;
}
#[doc = "Error status 0"]
pub type ErrorStatus0 = crate::RegValueT<ErrorStatus0_SPEC>;
impl ErrorStatus0 {
#[doc = "Captures error description information. For INSTR_OPC_ERROR:\n- Violating instruction.\nFor INSTR_CC_ERROR:\n- Violating instruction.\nFor BUS_ERROR:\n- Violating transfer address."]
#[inline(always)]
pub fn data32(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
ErrorStatus0_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
ErrorStatus0_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ErrorStatus0 {
#[inline(always)]
fn default() -> ErrorStatus0 {
<crate::RegValueT<ErrorStatus0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ErrorStatus1_SPEC;
impl crate::sealed::RegSpec for ErrorStatus1_SPEC {
type DataType = u32;
}
#[doc = "Error status 1"]
pub type ErrorStatus1 = crate::RegValueT<ErrorStatus1_SPEC>;
impl ErrorStatus1 {
#[doc = "Captures error description information. For BUS_ERROR:\n- Violating transfer, read attribute (DATA23\\[0\\]).\n- Violating transfer, size attribute (DATA23\\[5:4\\]). \'0\': 8-bit transfer, \'1\': 16 bits transfer, \'2\': 32-bit transfer. \nFor INSTR_CC_ERROR:"]
#[inline(always)]
pub fn data23(
self,
) -> crate::common::RegisterField<
0,
0xffffff,
1,
0,
u32,
u32,
ErrorStatus1_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffff,
1,
0,
u32,
u32,
ErrorStatus1_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "Error source:\n\'0\': INSTR_OPC_ERROR, instruction decoder error.\n\'1\': INSTR_CC_ERROR, instruction condition code error.\n\'2\': BUS_ERROR, Bus master interface AHB-Lite bus error.\n\'3\': TR_AP_DETECT_ERROR.\n\'4\': TR_RC_DETECT_ERROR.\n\'5\'-\'7\': Undefined."]
#[inline(always)]
pub fn idx(
self,
) -> crate::common::RegisterField<24, 0x7, 1, 0, u8, u8, ErrorStatus1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0x7,1,0,u8,u8,ErrorStatus1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies if ERROR_STATUS0 and ERROR_STATUS1 capture valid error information."]
#[inline(always)]
pub fn valid(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ErrorStatus1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,ErrorStatus1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ErrorStatus1 {
#[inline(always)]
fn default() -> ErrorStatus1 {
<crate::RegValueT<ErrorStatus1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InstrFfCtl_SPEC;
impl crate::sealed::RegSpec for InstrFfCtl_SPEC {
type DataType = u32;
}
#[doc = "Instruction FIFO control"]
pub type InstrFfCtl = crate::RegValueT<InstrFfCtl_SPEC>;
impl InstrFfCtl {
#[doc = "Event level. When the number of entries in the instruction FIFO is less than the amount of this field, an event is generated:\n- \'event\' = INSTR_FF_STATUS.USED < EVENT_LEVEL."]
#[inline(always)]
pub fn event_level(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, InstrFfCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,InstrFfCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When \'1\', the instruction FIFO is cleared/invalidated. Invalidation will last for as long as this field is \'1\'. If a quick clear/invalidation is required, the field should be set to \'1\' and be followed by a set to \'0\'. If a clear/invalidation is required for an extended time period, the field should be set to \'1\' during the complete time period.\n\nHW sets this field to \'1\' on when an error INTR cause is activated."]
#[inline(always)]
pub fn clear(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, InstrFfCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,InstrFfCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field specifies the behavior when an instruction is written to a full FIFO (INSTR_FIFO_WR MMIO register):\n\'0\': The write is ignored/dropped and the INTR.INSTR_FF_OVERFLOW interrupt cause is set to \'1\'.\n\'1\': The write is blocked, resulting in AHB-Lite wait states and the INTR.INSTR_FF_OVERFLOW interrupt cause is set to \'1\' (this cause may be masked out). The instruction is written to the FIFO as soon as a FIFO entry becomes available. The maximum time is roughly the time of the execution of the slowest/longest instruction. Note that this setting may \'lock up\' the CPU. When the CPU is \'locked up\' it can not respond to interrupts. As a result, the interrupt latency is increased."]
#[inline(always)]
pub fn block(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, InstrFfCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,InstrFfCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for InstrFfCtl {
#[inline(always)]
fn default() -> InstrFfCtl {
<crate::RegValueT<InstrFfCtl_SPEC> as RegisterValue<_>>::new(131072)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InstrFfStatus_SPEC;
impl crate::sealed::RegSpec for InstrFfStatus_SPEC {
type DataType = u32;
}
#[doc = "Instruction FIFO status"]
pub type InstrFfStatus = crate::RegValueT<InstrFfStatus_SPEC>;
impl InstrFfStatus {
#[doc = "Number of instructions in the instruction FIFO. The value of this field ranges from 0 to 8."]
#[inline(always)]
pub fn used(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, InstrFfStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,InstrFfStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Instruction FIFO event."]
#[inline(always)]
pub fn event(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, InstrFfStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,InstrFfStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Reflects the state of the instruction FIFO:\n\'0\': No instruction pending (USED is \'0\').\n\'1\': Instruction pending."]
#[inline(always)]
pub fn busy(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, InstrFfStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31,1,0,InstrFfStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for InstrFfStatus {
#[inline(always)]
fn default() -> InstrFfStatus {
<crate::RegValueT<InstrFfStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InstrFfWr_SPEC;
impl crate::sealed::RegSpec for InstrFfWr_SPEC {
type DataType = u32;
}
#[doc = "Instruction FIFO write"]
pub type InstrFfWr = crate::RegValueT<InstrFfWr_SPEC>;
impl InstrFfWr {
#[doc = "Instruction or instruction operand data that is written to the instruction FIFO."]
#[inline(always)]
pub fn data32(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, InstrFfWr_SPEC, crate::common::W>
{
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
InstrFfWr_SPEC,
crate::common::W,
>::from_register(self, 0)
}
}
impl ::core::default::Default for InstrFfWr {
#[inline(always)]
fn default() -> InstrFfWr {
<crate::RegValueT<InstrFfWr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RfData_SPEC;
impl crate::sealed::RegSpec for RfData_SPEC {
type DataType = u32;
}
#[doc = "Register-file"]
pub type RfData = crate::RegValueT<RfData_SPEC>;
impl RfData {
#[doc = "Register-file data. \n\nFor the vector unit component, a register-file register has the following layout:\nDATA\\[29:16\\]: data\nDATA\\[11:0\\]: bit size (minus 1)"]
#[inline(always)]
pub fn data32(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, RfData_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,RfData_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for RfData {
#[inline(always)]
fn default() -> RfData {
<crate::RegValueT<RfData_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AesCtl_SPEC;
impl crate::sealed::RegSpec for AesCtl_SPEC {
type DataType = u32;
}
#[doc = "AES control"]
pub type AesCtl = crate::RegValueT<AesCtl_SPEC>;
impl AesCtl {
#[doc = "AES key size:\n\'0\': 128-bit key, 10 rounds AES (inverse) cipher operation. SRC_CTL0 specifies the location of a 16 Byte key.\n\'1\': 192-bit key, 12 rounds AES (inverse) cipher operation. SRC_CTL0 specifies the location of a 24 Byte key.\n\'2\': 256-bit key, 14 rounds AES (inverse) cipher operation. SRC_CTL0 specifies the location of a 32 Byte key.\n\'3\': Undefined"]
#[inline(always)]
pub fn key_size(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
aes_ctl::KeySize,
aes_ctl::KeySize,
AesCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
aes_ctl::KeySize,
aes_ctl::KeySize,
AesCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for AesCtl {
#[inline(always)]
fn default() -> AesCtl {
<crate::RegValueT<AesCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod aes_ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct KeySize_SPEC;
pub type KeySize = crate::EnumBitfieldStruct<u8, KeySize_SPEC>;
impl KeySize {
#[doc = "N/A"]
pub const AES_128: Self = Self::new(0);
#[doc = "N/A"]
pub const AES_192: Self = Self::new(1);
#[doc = "N/A"]
pub const AES_256: Self = Self::new(2);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct StrResult_SPEC;
impl crate::sealed::RegSpec for StrResult_SPEC {
type DataType = u32;
}
#[doc = "String result"]
pub type StrResult = crate::RegValueT<StrResult_SPEC>;
impl StrResult {
#[doc = "Result of a STR_MEMCMP operation:\n\'0\': source 0 equals source 1.\n\'1\': source 0 does NOT equal source 1."]
#[inline(always)]
pub fn memcmp(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, StrResult_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, StrResult_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for StrResult {
#[inline(always)]
fn default() -> StrResult {
<crate::RegValueT<StrResult_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PrLfsrCtl0_SPEC;
impl crate::sealed::RegSpec for PrLfsrCtl0_SPEC {
type DataType = u32;
}
#[doc = "Pseudo random LFSR control 0"]
pub type PrLfsrCtl0 = crate::RegValueT<PrLfsrCtl0_SPEC>;
impl PrLfsrCtl0 {
#[doc = "State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. This register needs to be initialized by SW. The initialization value should be different from \'0\'.\n\nThe three PR_LFSR_CTL registers represents the state of a 32-bit, 31-bit and 29-bit LFSR. Individually, these LFSRs generate a pseudo random bit sequence that repeats itself after (2^32)-1, (2^31)-1 and (2^29)-1 bits. The numbers (2^32)-1, (2^31)-1 and (2^29)-1 are relatively prime (their greatest common denominator is \'1\'). The three bit sequence are combined (XOR\'d) into a single bitstream to create a pseudo random bit sequence that repeats itself after ((2^32)-1) * ((2^31)-1) * ((2*29)-1) bits.\n\nThe following polynomials are used:\n- 32-bit irreducible polynomial: x^32+x^30+x^26+x^25+1.\n- 31-bit irreducible polynomial: x^31+x^28+1.\n- 29-bit irreducible polynomial: x^29+x^27+1."]
#[inline(always)]
pub fn lfsr32(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
PrLfsrCtl0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
PrLfsrCtl0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PrLfsrCtl0 {
#[inline(always)]
fn default() -> PrLfsrCtl0 {
<crate::RegValueT<PrLfsrCtl0_SPEC> as RegisterValue<_>>::new(3633683401)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PrLfsrCtl1_SPEC;
impl crate::sealed::RegSpec for PrLfsrCtl1_SPEC {
type DataType = u32;
}
#[doc = "Pseudo random LFSR control 1"]
pub type PrLfsrCtl1 = crate::RegValueT<PrLfsrCtl1_SPEC>;
impl PrLfsrCtl1 {
#[doc = "State of a 31-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0."]
#[inline(always)]
pub fn lfsr31(
self,
) -> crate::common::RegisterField<
0,
0x7fffffff,
1,
0,
u32,
u32,
PrLfsrCtl1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x7fffffff,
1,
0,
u32,
u32,
PrLfsrCtl1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PrLfsrCtl1 {
#[inline(always)]
fn default() -> PrLfsrCtl1 {
<crate::RegValueT<PrLfsrCtl1_SPEC> as RegisterValue<_>>::new(733549048)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PrLfsrCtl2_SPEC;
impl crate::sealed::RegSpec for PrLfsrCtl2_SPEC {
type DataType = u32;
}
#[doc = "Pseudo random LFSR control 2"]
pub type PrLfsrCtl2 = crate::RegValueT<PrLfsrCtl2_SPEC>;
impl PrLfsrCtl2 {
#[doc = "State of a 29-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0."]
#[inline(always)]
pub fn lfsr29(
self,
) -> crate::common::RegisterField<
0,
0x1fffffff,
1,
0,
u32,
u32,
PrLfsrCtl2_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1fffffff,
1,
0,
u32,
u32,
PrLfsrCtl2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PrLfsrCtl2 {
#[inline(always)]
fn default() -> PrLfsrCtl2 {
<crate::RegValueT<PrLfsrCtl2_SPEC> as RegisterValue<_>>::new(101462455)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PrResult_SPEC;
impl crate::sealed::RegSpec for PrResult_SPEC {
type DataType = u32;
}
#[doc = "Pseudo random result"]
pub type PrResult = crate::RegValueT<PrResult_SPEC>;
impl PrResult {
#[doc = "Result of a pseudo random number generation operation. The resulting value DATA is in the range \\[0, MAX\\], with MAX specified by rsrc0. HW generates the number in this field.\n\nNote that SW can write this field. This functionality can be used prevent information leakage."]
#[inline(always)]
pub fn data32(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, PrResult_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
PrResult_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PrResult {
#[inline(always)]
fn default() -> PrResult {
<crate::RegValueT<PrResult_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrCtl0_SPEC;
impl crate::sealed::RegSpec for TrCtl0_SPEC {
type DataType = u32;
}
#[doc = "True random control 0"]
pub type TrCtl0 = crate::RegValueT<TrCtl0_SPEC>;
impl TrCtl0 {
#[doc = "Specifies the clock divider that is used to sample oscillator data. This clock divider is wrt. \'clk_sys\'.\n\'0\': sample clock is \'clk_sys\'.\n\'1\': sample clock is \'clk_sys\'/2.\n...\n\'255\': sample clock is \'clk_sys\'/256."]
#[inline(always)]
pub fn sample_clock_div(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, TrCtl0_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0xff,1,0,u8,u8,TrCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies the clock divider that is used to produce reduced bits. \n\'0\': 1 reduced bit is produced for each sample.\n\'1\': 1 reduced bit is produced for each 2 samples.\n...\n\'255\': 1 reduced bit is produced for each 256 samples.\n\nThe reduced bits are considered random bits and shifted into TR_RESULT0.DATA32."]
#[inline(always)]
pub fn red_clock_div(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, TrCtl0_SPEC, crate::common::RW> {
crate::common::RegisterField::<8,0xff,1,0,u8,u8,TrCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies an initialization delay: number of removed/dropped samples before reduced bits are generated. This field should be programmed in the range \\[1, 255\\]. After starting the oscillators, at least the first 2 samples should be removed/dropped to clear the state of internal synchronizers. In addition, it is advised to drop at least the second 2 samples from the oscillators (to circumvent the semi-predictable oscillator startup behavior). This result in the default field value of \'3\'. Field encoding is as follows:\n\'0\': 1 sample is dropped.\n\'1\': 2 samples are dropped.\n...\n\'255\': 256 samples are dropped.\n\nThe TR_INITIALIZED interrupt cause is set to \'1\', when the initialization delay is passed."]
#[inline(always)]
pub fn init_delay(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, TrCtl0_SPEC, crate::common::RW> {
crate::common::RegisterField::<16,0xff,1,0,u8,u8,TrCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies if the \'von Neumann corrector\' is disabled or enabled:\n\'0\': disabled.\n\'1\': enabled.\nThe \'von Neumann corrector\' post-processes the reduced bits to remove a \'0\' or \'1\' bias. The corrector operates on reduced bit pairs (\'oldest bit, newest bit\'):\n\'00\': no bit is produced.\n\'01\': \'0\' bit is produced (oldest bit).\n\'10\': \'1\' bit is produced (oldest bit).\n\'11\': no bit is produced.\nNote that the corrector produces bits at a random pace and at a frequency that is 1/4 of the reduced bit frequency (reduced bits are processed in pairs, and half of the pairs do NOT produce a bit)."]
#[inline(always)]
pub fn von_neumann_corr(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, TrCtl0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24, 1, 0, TrCtl0_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Specifies if TRNG functionality is stopped on an adaptive proportion test detection (when HW sets INTR.TR_AP_DETECT to \'1\'):\n\'0\': Functionality is NOT stopped.\n\'1\': Functionality is stopped (TR_CTL1 fields are set to \'0\' by HW)."]
#[inline(always)]
pub fn stop_on_ap_detect(
self,
) -> crate::common::RegisterFieldBool<28, 1, 0, TrCtl0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<28, 1, 0, TrCtl0_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Specifies if TRNG functionality is stopped on a repetition count test detection (when HW sets INTR.TR_RC_DETECT to \'1\'):\n\'0\': Functionality is NOT stopped.\n\'1\': Functionality is stopped (TR_CTL1 fields are set to \'0\' by HW)."]
#[inline(always)]
pub fn stop_on_rc_detect(
self,
) -> crate::common::RegisterFieldBool<29, 1, 0, TrCtl0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<29, 1, 0, TrCtl0_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for TrCtl0 {
#[inline(always)]
fn default() -> TrCtl0 {
<crate::RegValueT<TrCtl0_SPEC> as RegisterValue<_>>::new(196608)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrCtl1_SPEC;
impl crate::sealed::RegSpec for TrCtl1_SPEC {
type DataType = u32;
}
#[doc = "True random control 1"]
pub type TrCtl1 = crate::RegValueT<TrCtl1_SPEC>;
impl TrCtl1 {
#[doc = "FW sets this field to \'1\' to enable the ring oscillator with 11 inverters."]
#[inline(always)]
pub fn ro11_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, TrCtl1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, TrCtl1_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "FW sets this field to \'1\' to enable the ring oscillator with 15 inverters."]
#[inline(always)]
pub fn ro15_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, TrCtl1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, TrCtl1_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "FW sets this field to \'1\' to enable the fixed Galois ring oscillator with 15 inverters."]
#[inline(always)]
pub fn garo15_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, TrCtl1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, TrCtl1_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "FW sets this field to \'1\' to enable the programmable Galois ring oscillator with up to 31 inverters. The TR_GARO_CTL register specifies the programmable polynomial."]
#[inline(always)]
pub fn garo31_en(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, TrCtl1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, TrCtl1_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "FW sets this field to \'1\' to enable the fixed Fibonacci ring oscillator with 15 inverters."]
#[inline(always)]
pub fn firo15_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, TrCtl1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, TrCtl1_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "FW sets this field to \'1\' to enable the programmable Fibonacci ring oscillator with up to 31 inverters. The TR_FIRO_CTL register specifies the programmable polynomial."]
#[inline(always)]
pub fn firo31_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, TrCtl1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, TrCtl1_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for TrCtl1 {
#[inline(always)]
fn default() -> TrCtl1 {
<crate::RegValueT<TrCtl1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrResult_SPEC;
impl crate::sealed::RegSpec for TrResult_SPEC {
type DataType = u32;
}
#[doc = "True random result"]
pub type TrResult = crate::RegValueT<TrResult_SPEC>;
impl TrResult {
#[doc = "Generated true random number. HW generates the number in the least significant bit positions of this field. The TR_DATA_AVAILABLE interrupt cause is activated when the number is generated.\n\nNote that SW can write this field. This functionality can be used prevent information leakage."]
#[inline(always)]
pub fn data32(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, TrResult_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
TrResult_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for TrResult {
#[inline(always)]
fn default() -> TrResult {
<crate::RegValueT<TrResult_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrGaroCtl_SPEC;
impl crate::sealed::RegSpec for TrGaroCtl_SPEC {
type DataType = u32;
}
#[doc = "True random GARO control"]
pub type TrGaroCtl = crate::RegValueT<TrGaroCtl_SPEC>;
impl TrGaroCtl {
#[doc = "Polynomial for programmable Galois ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed \'1\'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding \'0\'s."]
#[inline(always)]
pub fn polynomial31(
self,
) -> crate::common::RegisterField<
0,
0x7fffffff,
1,
0,
u32,
u32,
TrGaroCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x7fffffff,
1,
0,
u32,
u32,
TrGaroCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for TrGaroCtl {
#[inline(always)]
fn default() -> TrGaroCtl {
<crate::RegValueT<TrGaroCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrFiroCtl_SPEC;
impl crate::sealed::RegSpec for TrFiroCtl_SPEC {
type DataType = u32;
}
#[doc = "True random FIRO control"]
pub type TrFiroCtl = crate::RegValueT<TrFiroCtl_SPEC>;
impl TrFiroCtl {
#[doc = "Polynomial for programmable Fibonacci ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed \'1\'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding \'0\'s."]
#[inline(always)]
pub fn polynomial31(
self,
) -> crate::common::RegisterField<
0,
0x7fffffff,
1,
0,
u32,
u32,
TrFiroCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x7fffffff,
1,
0,
u32,
u32,
TrFiroCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for TrFiroCtl {
#[inline(always)]
fn default() -> TrFiroCtl {
<crate::RegValueT<TrFiroCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrMonCtl_SPEC;
impl crate::sealed::RegSpec for TrMonCtl_SPEC {
type DataType = u32;
}
#[doc = "True random monitor control"]
pub type TrMonCtl = crate::RegValueT<TrMonCtl_SPEC>;
impl TrMonCtl {
#[doc = "Selection of the bitstream:\n\'0\': DAS bitstream.\n\'1\': RED bitstream.\n\'2\': TR bitstream.\n\'3\': Undefined."]
#[inline(always)]
pub fn bitstream_sel(
self,
) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, TrMonCtl_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0x3,1,0,u8,u8,TrMonCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TrMonCtl {
#[inline(always)]
fn default() -> TrMonCtl {
<crate::RegValueT<TrMonCtl_SPEC> as RegisterValue<_>>::new(2)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrMonCmd_SPEC;
impl crate::sealed::RegSpec for TrMonCmd_SPEC {
type DataType = u32;
}
#[doc = "True random monitor command"]
pub type TrMonCmd = crate::RegValueT<TrMonCmd_SPEC>;
impl TrMonCmd {
#[doc = "Adaptive proportion (AP) test enable:\n\'0\': Stopped.\n\'1\': Started.\n\nOn a AP detection, HW sets this field to \'0\' and sets INTR.TR_AP_DETECT to \'1."]
#[inline(always)]
pub fn start_ap(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, TrMonCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, TrMonCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Repetition count (RC) test enable:\n\'0\': Disabled.\n\'1\': Enabled.\n\nOn a RC detection, HW sets this field to \'0\' and sets INTR.TR_RC_DETECT to \'1."]
#[inline(always)]
pub fn start_rc(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, TrMonCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, TrMonCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for TrMonCmd {
#[inline(always)]
fn default() -> TrMonCmd {
<crate::RegValueT<TrMonCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrMonRcCtl_SPEC;
impl crate::sealed::RegSpec for TrMonRcCtl_SPEC {
type DataType = u32;
}
#[doc = "True random monitor RC control"]
pub type TrMonRcCtl = crate::RegValueT<TrMonRcCtl_SPEC>;
impl TrMonRcCtl {
#[doc = "Cutoff count (legal range is \\[1, 255\\]):\n\'0\': Illegal.\n\'1\': 1 repetition.\n...\n\'255\': 255 repetitions."]
#[inline(always)]
pub fn cutoff_count8(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, TrMonRcCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,TrMonRcCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TrMonRcCtl {
#[inline(always)]
fn default() -> TrMonRcCtl {
<crate::RegValueT<TrMonRcCtl_SPEC> as RegisterValue<_>>::new(255)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrMonRcStatus0_SPEC;
impl crate::sealed::RegSpec for TrMonRcStatus0_SPEC {
type DataType = u32;
}
#[doc = "True random monitor RC status 0"]
pub type TrMonRcStatus0 = crate::RegValueT<TrMonRcStatus0_SPEC>;
impl TrMonRcStatus0 {
#[doc = "Current active bit value:\n\'0\': \'0\'.\n\'1\': \'1\'.\n\nThis field is only valid when TR_MON_RC_STATUS1.REP_COUNT is NOT equal to \'0\'."]
#[inline(always)]
pub fn bit(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, TrMonRcStatus0_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,TrMonRcStatus0_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for TrMonRcStatus0 {
#[inline(always)]
fn default() -> TrMonRcStatus0 {
<crate::RegValueT<TrMonRcStatus0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrMonRcStatus1_SPEC;
impl crate::sealed::RegSpec for TrMonRcStatus1_SPEC {
type DataType = u32;
}
#[doc = "True random monitor RC status 1"]
pub type TrMonRcStatus1 = crate::RegValueT<TrMonRcStatus1_SPEC>;
impl TrMonRcStatus1 {
#[doc = "Number of repetitions of the current active bit counter:\n\'0\': 0 repetitions.\n...\n\'255\': 255 repetitions."]
#[inline(always)]
pub fn rep_count(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, TrMonRcStatus1_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,TrMonRcStatus1_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for TrMonRcStatus1 {
#[inline(always)]
fn default() -> TrMonRcStatus1 {
<crate::RegValueT<TrMonRcStatus1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrMonApCtl_SPEC;
impl crate::sealed::RegSpec for TrMonApCtl_SPEC {
type DataType = u32;
}
#[doc = "True random monitor AP control"]
pub type TrMonApCtl = crate::RegValueT<TrMonApCtl_SPEC>;
impl TrMonApCtl {
#[doc = "Cutoff count (legal range is \\[1, 65535\\]).\n\'0\': Illegal.\n\'1\': 1 occurrence.\n...\n\'65535\': 65535 occurrences."]
#[inline(always)]
pub fn cutoff_count16(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, TrMonApCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,TrMonApCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Window size (minus 1) :\n\'0\': 1 bit.\n...\n\'65535\': 65536 bits."]
#[inline(always)]
pub fn window_size(
self,
) -> crate::common::RegisterField<16, 0xffff, 1, 0, u16, u16, TrMonApCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xffff,1,0,u16,u16,TrMonApCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TrMonApCtl {
#[inline(always)]
fn default() -> TrMonApCtl {
<crate::RegValueT<TrMonApCtl_SPEC> as RegisterValue<_>>::new(4294967295)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrMonApStatus0_SPEC;
impl crate::sealed::RegSpec for TrMonApStatus0_SPEC {
type DataType = u32;
}
#[doc = "True random monitor AP status 0"]
pub type TrMonApStatus0 = crate::RegValueT<TrMonApStatus0_SPEC>;
impl TrMonApStatus0 {
#[doc = "Current active bit value:\n\'0\': \'0\'.\n\'1\': \'1\'.\n\nThis field is only valid when TR_MON_AP_STATUS1.OCC_COUNT is NOT equal to \'0\'."]
#[inline(always)]
pub fn bit(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, TrMonApStatus0_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,TrMonApStatus0_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for TrMonApStatus0 {
#[inline(always)]
fn default() -> TrMonApStatus0 {
<crate::RegValueT<TrMonApStatus0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrMonApStatus1_SPEC;
impl crate::sealed::RegSpec for TrMonApStatus1_SPEC {
type DataType = u32;
}
#[doc = "True random monitor AP status 1"]
pub type TrMonApStatus1 = crate::RegValueT<TrMonApStatus1_SPEC>;
impl TrMonApStatus1 {
#[doc = "Number of occurrences of the current active bit counter:\n\'0\': 0 occurrences\n...\n\'65535\': 65535 occurrences"]
#[inline(always)]
pub fn occ_count(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
TrMonApStatus1_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
TrMonApStatus1_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "Counter to keep track of the current index in the window (counts from \'0\' to TR_MON_AP_CTL.WINDOW_SIZE)."]
#[inline(always)]
pub fn window_index(
self,
) -> crate::common::RegisterField<
16,
0xffff,
1,
0,
u16,
u16,
TrMonApStatus1_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
16,
0xffff,
1,
0,
u16,
u16,
TrMonApStatus1_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for TrMonApStatus1 {
#[inline(always)]
fn default() -> TrMonApStatus1 {
<crate::RegValueT<TrMonApStatus1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ShaCtl_SPEC;
impl crate::sealed::RegSpec for ShaCtl_SPEC {
type DataType = u32;
}
#[doc = "SHA control"]
pub type ShaCtl = crate::RegValueT<ShaCtl_SPEC>;
impl ShaCtl {
#[doc = "SHA mode:\n\'0\': SHA1. The message is 16 32 bits words: 64 Bytes. The hash is 5 32-bit words: 20 Bytes. There are 80 32-bit message schedule round constants: 320 Bytes.\n\'1\': SHA224, SHA256. The message is 16 32-bit words: 64 Bytes. The hash is 8 32-bit words: 32 Bytes. There are 64 32-bit message schedule round constants: 256 Bytes. The difference between SHA224 and SHA256 is entirely in software (differences in initialization hash and message digest size).\n\'2\': SHA512/224, SHA512/256, SHA384, SHA512. The message is 8 64-bit words: 64 Bytes. The hash is 8 64-bit words: 64 Bytes. There are 80 64-bit message schedule round constants: 640 Bytes. The difference between SHA512/224, SHA512/256, SHA384 and SHA512 is entirely in software (differences in initialization hash and message digest size).\n\'3\'-\'7\': Undefined."]
#[inline(always)]
pub fn mode(
self,
) -> crate::common::RegisterField<
0,
0x7,
1,
0,
sha_ctl::Mode,
sha_ctl::Mode,
ShaCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x7,
1,
0,
sha_ctl::Mode,
sha_ctl::Mode,
ShaCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ShaCtl {
#[inline(always)]
fn default() -> ShaCtl {
<crate::RegValueT<ShaCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sha_ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Mode_SPEC;
pub type Mode = crate::EnumBitfieldStruct<u8, Mode_SPEC>;
impl Mode {
#[doc = "N/A"]
pub const SHA_1: Self = Self::new(0);
#[doc = "N/A"]
pub const SHA_256: Self = Self::new(1);
#[doc = "N/A"]
pub const SHA_512: Self = Self::new(2);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CrcCtl_SPEC;
impl crate::sealed::RegSpec for CrcCtl_SPEC {
type DataType = u32;
}
#[doc = "CRC control"]
pub type CrcCtl = crate::RegValueT<CrcCtl_SPEC>;
impl CrcCtl {
#[doc = "Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):\n\'0\': Most significant bit (bit 1) first.\n\'1\': Least significant bit (bit 0) first."]
#[inline(always)]
pub fn data_reverse(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, CrcCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, CrcCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Specifies whether the remainder is bit reversed (reversal is performed after XORing):\n\'0\': No.\n\'1\': Yes."]
#[inline(always)]
pub fn rem_reverse(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, CrcCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, CrcCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for CrcCtl {
#[inline(always)]
fn default() -> CrcCtl {
<crate::RegValueT<CrcCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CrcDataCtl_SPEC;
impl crate::sealed::RegSpec for CrcDataCtl_SPEC {
type DataType = u32;
}
#[doc = "CRC data control"]
pub type CrcDataCtl = crate::RegValueT<CrcDataCtl_SPEC>;
impl CrcDataCtl {
#[doc = "Specifies a byte mask with which each data byte is XOR\'d. The XOR is performed before data reversal."]
#[inline(always)]
pub fn data_xor(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, CrcDataCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,CrcDataCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CrcDataCtl {
#[inline(always)]
fn default() -> CrcDataCtl {
<crate::RegValueT<CrcDataCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CrcPolCtl_SPEC;
impl crate::sealed::RegSpec for CrcPolCtl_SPEC {
type DataType = u32;
}
#[doc = "CRC polynomial control"]
pub type CrcPolCtl = crate::RegValueT<CrcPolCtl_SPEC>;
impl CrcPolCtl {
#[doc = "CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed \'1\'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding \'0\'s. Some frequently used polynomials:\n- CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1).\n- CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions).\n- CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions)."]
#[inline(always)]
pub fn polynomial(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CrcPolCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CrcPolCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CrcPolCtl {
#[inline(always)]
fn default() -> CrcPolCtl {
<crate::RegValueT<CrcPolCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CrcLfsrCtl_SPEC;
impl crate::sealed::RegSpec for CrcLfsrCtl_SPEC {
type DataType = u32;
}
#[doc = "CRC LFSR control"]
pub type CrcLfsrCtl = crate::RegValueT<CrcLfsrCtl_SPEC>;
impl CrcLfsrCtl {
#[doc = "State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value.\n\nThe seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding \'0\'s. \n\nNote that SW can write this field. This functionality can be used prevent information leakage (through either CRC_LFSR_CTL or CRC_REM_RESULT) from the privileged domain to the user domain."]
#[inline(always)]
pub fn lfsr32(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CrcLfsrCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CrcLfsrCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CrcLfsrCtl {
#[inline(always)]
fn default() -> CrcLfsrCtl {
<crate::RegValueT<CrcLfsrCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CrcRemCtl_SPEC;
impl crate::sealed::RegSpec for CrcRemCtl_SPEC {
type DataType = u32;
}
#[doc = "CRC remainder control"]
pub type CrcRemCtl = crate::RegValueT<CrcRemCtl_SPEC>;
impl CrcRemCtl {
#[doc = "Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR\'d to produce a remainder. The XOR is performed before remainder reversal."]
#[inline(always)]
pub fn rem_xor(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CrcRemCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CrcRemCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CrcRemCtl {
#[inline(always)]
fn default() -> CrcRemCtl {
<crate::RegValueT<CrcRemCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CrcRemResult_SPEC;
impl crate::sealed::RegSpec for CrcRemResult_SPEC {
type DataType = u32;
}
#[doc = "CRC remainder result"]
pub type CrcRemResult = crate::RegValueT<CrcRemResult_SPEC>;
impl CrcRemResult {
#[doc = "Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE: \n\'0\': the more significant bits (bit 31 and down) contain the remainder.\n\'1\': the less significant bits (bit 0 and up) contain the remainder. \n\nNote: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_REM_CTL0.REM_REVERSE and CRC_REM_CTL1.REM_XOR."]
#[inline(always)]
pub fn rem(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
CrcRemResult_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
CrcRemResult_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CrcRemResult {
#[inline(always)]
fn default() -> CrcRemResult {
<crate::RegValueT<CrcRemResult_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct VuCtl0_SPEC;
impl crate::sealed::RegSpec for VuCtl0_SPEC {
type DataType = u32;
}
#[doc = "Vector unit control 0"]
pub type VuCtl0 = crate::RegValueT<VuCtl0_SPEC>;
impl VuCtl0 {
#[doc = "Specifies if a conditional instruction is executed or not, when its condition code evaluates to false/\'0\'.\n\'0\': The instruction is NOT executed. As a result, the instruction may be handled faster than when it is executed.\n\'1\': The instruction is executed, but the execution result (including status field information) is not reflected in the IP. The instruction is handled just as fast as when it is executed.\n\nNote: a conditional instruction with a condition code that evaluates to false/\'0\' does not affect the architectural state: VU_STATUS fields, memory or register-file data.\n\nNote: Always execution is useful to prevent/complicate differential timing and differential power attacks."]
#[inline(always)]
pub fn always_execute(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, VuCtl0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, VuCtl0_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for VuCtl0 {
#[inline(always)]
fn default() -> VuCtl0 {
<crate::RegValueT<VuCtl0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct VuCtl1_SPEC;
impl crate::sealed::RegSpec for VuCtl1_SPEC {
type DataType = u32;
}
#[doc = "Vector unit control 1"]
pub type VuCtl1 = crate::RegValueT<VuCtl1_SPEC>;
impl VuCtl1 {
#[doc = "Specifies base address of vector unit operands in memory. The register-file registers provide offsets wrt. this base address.\n\nThe base address is a multiple of 16 KB. The register-file registers provide 12-bit word address offsets in this 16 KB. Together, they provide access to a 16 KB memory region for vector unit instructions:\nADDR\\[31:14\\] = VU_CTL1.ADDR\\[31:14\\]\nADDR\\[13:2\\] = register-file register offset\n\nThe base address is either the IP\'s internal memory buffer (memory capacity is the internal memory buffer capacity) or a location in system memory (memory capacity is 16 KB).\n\nFor best performance, the IP\'s memory buffer should be used and VU_CTL1.ADDR should be programmed to MEM_BUFF. If VU_CTL1.ADDR is set to MEM_BUFF and the memory buffer capacity is less than 16 KB, memory accesses beyond the memory buffer capacity access a memory hole (reads return \'0\' and writes are ignored). E.g., if the memory buffer is 8 KB, accesses with ADDR\\[13\\] set to \'1\', access a memory hole.\n\nIf the IP\'s memory buffer capacity is not large enough to support the vector unit operands, VU_CTL1.ADDR can be set to a 16 KB aligned location in system memory."]
#[inline(always)]
pub fn addr(
self,
) -> crate::common::RegisterField<14, 0x3ffff, 1, 0, u32, u32, VuCtl1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<14,0x3ffff,1,0,u32,u32,VuCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for VuCtl1 {
#[inline(always)]
fn default() -> VuCtl1 {
<crate::RegValueT<VuCtl1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct VuStatus_SPEC;
impl crate::sealed::RegSpec for VuStatus_SPEC {
type DataType = u32;
}
#[doc = "Vector unit status"]
pub type VuStatus = crate::RegValueT<VuStatus_SPEC>;
impl VuStatus {
#[doc = "STATUS CARRY field."]
#[inline(always)]
pub fn carry(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, VuStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, VuStatus_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "STATUS EVEN field."]
#[inline(always)]
pub fn even(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, VuStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1, 1, 0, VuStatus_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "STATUS ZERO field."]
#[inline(always)]
pub fn zero(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, VuStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2, 1, 0, VuStatus_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "STATUS ONE field."]
#[inline(always)]
pub fn one(self) -> crate::common::RegisterFieldBool<3, 1, 0, VuStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3, 1, 0, VuStatus_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for VuStatus {
#[inline(always)]
fn default() -> VuStatus {
<crate::RegValueT<VuStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Intr_SPEC;
impl crate::sealed::RegSpec for Intr_SPEC {
type DataType = u32;
}
#[doc = "Interrupt register"]
pub type Intr = crate::RegValueT<Intr_SPEC>;
impl Intr {
#[doc = "This interrupt cause is activated (HW sets the field to \'1\') when the instruction FIFO event is activated."]
#[inline(always)]
pub fn instr_ff_level(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "This interrupt cause is activated (HW sets the field to \'1\') when the instruction FIFO overflows (an attempt is made to write to a full FIFO)."]
#[inline(always)]
pub fn instr_ff_overflow(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "This interrupt cause is activated (HW sets the field to \'1\') when the true random number generator is initialized."]
#[inline(always)]
pub fn tr_initialized(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "This interrupt cause is activated (HW sets the field to \'1\') when the true random number generator has generated a data value of the specified bit size."]
#[inline(always)]
pub fn tr_data_available(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "This interrupt cause is activated (HW sets the field to \'1\') when the pseudo random number generator has generated a data value."]
#[inline(always)]
pub fn pr_data_available(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "This interrupt cause is activated (HW sets the field to \'1\') when the instruction decoder encounters an instruction with a non-defined operation code (opcode)."]
#[inline(always)]
pub fn instr_opc_error(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "This interrupt cause is activated (HW sets the field to \'1\') when the instruction decoder encounters an instruction with a non-defined condition code. This error is only generated for VU instructions."]
#[inline(always)]
pub fn instr_cc_error(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "This interrupt cause is activated (HW sets the field to \'1\') when a AHB-Lite bus error is observed on the AHB-Lite master interface."]
#[inline(always)]
pub fn bus_error(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "This interrupt cause is activated (HW sets the field to \'1\') when the true random number generator monitor adaptive proportion test detects a repetition of a specific bit value."]
#[inline(always)]
pub fn tr_ap_detect_error(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "This interrupt cause is activated (HW sets the field to \'1\') when the true random number generator monitor adaptive proportion test detects a disproportionate occurrence of a specific bit value."]
#[inline(always)]
pub fn tr_rc_detect_error(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Intr {
#[inline(always)]
fn default() -> Intr {
<crate::RegValueT<Intr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSet_SPEC;
impl crate::sealed::RegSpec for IntrSet_SPEC {
type DataType = u32;
}
#[doc = "Interrupt set register"]
pub type IntrSet = crate::RegValueT<IntrSet_SPEC>;
impl IntrSet {
#[doc = "SW writes a \'1\' to this field to set the corresponding field in interrupt request register."]
#[inline(always)]
pub fn instr_ff_level(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "SW writes a \'1\' to this field to set the corresponding field in interrupt request register."]
#[inline(always)]
pub fn instr_ff_overflow(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "SW writes a \'1\' to this field to set the corresponding field in interrupt request register."]
#[inline(always)]
pub fn tr_initialized(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "SW writes a \'1\' to this field to set the corresponding field in interrupt request register."]
#[inline(always)]
pub fn tr_data_available(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "SW writes a \'1\' to this field to set the corresponding field in interrupt request register."]
#[inline(always)]
pub fn pr_data_available(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "SW writes a \'1\' to this field to set the corresponding field in interrupt request register."]
#[inline(always)]
pub fn instr_opc_error(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "SW writes a \'1\' to this field to set the corresponding field in interrupt request register."]
#[inline(always)]
pub fn instr_cc_error(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "SW writes a \'1\' to this field to set the corresponding field in interrupt request register."]
#[inline(always)]
pub fn bus_error(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "SW writes a \'1\' to this field to set the corresponding field in interrupt request register."]
#[inline(always)]
pub fn tr_ap_detect_error(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "SW writes a \'1\' to this field to set the corresponding field in interrupt request register."]
#[inline(always)]
pub fn tr_rc_detect_error(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for IntrSet {
#[inline(always)]
fn default() -> IntrSet {
<crate::RegValueT<IntrSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMask_SPEC;
impl crate::sealed::RegSpec for IntrMask_SPEC {
type DataType = u32;
}
#[doc = "Interrupt mask register"]
pub type IntrMask = crate::RegValueT<IntrMask_SPEC>;
impl IntrMask {
#[doc = "Mask bit for corresponding field in interrupt request register."]
#[inline(always)]
pub fn instr_ff_level(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding field in interrupt request register."]
#[inline(always)]
pub fn instr_ff_overflow(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding field in interrupt request register."]
#[inline(always)]
pub fn tr_initialized(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding field in interrupt request register."]
#[inline(always)]
pub fn tr_data_available(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding field in interrupt request register."]
#[inline(always)]
pub fn pr_data_available(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding field in interrupt request register."]
#[inline(always)]
pub fn instr_opc_error(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding field in interrupt request register."]
#[inline(always)]
pub fn instr_cc_error(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding field in interrupt request register."]
#[inline(always)]
pub fn bus_error(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding field in interrupt request register."]
#[inline(always)]
pub fn tr_ap_detect_error(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding field in interrupt request register."]
#[inline(always)]
pub fn tr_rc_detect_error(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMask {
#[inline(always)]
fn default() -> IntrMask {
<crate::RegValueT<IntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMasked_SPEC;
impl crate::sealed::RegSpec for IntrMasked_SPEC {
type DataType = u32;
}
#[doc = "Interrupt masked register"]
pub type IntrMasked = crate::RegValueT<IntrMasked_SPEC>;
impl IntrMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn instr_ff_level(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn instr_ff_overflow(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tr_initialized(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tr_data_available(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn pr_data_available(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn instr_opc_error(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn instr_cc_error(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<17,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn bus_error(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<18,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tr_ap_detect_error(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<19,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tr_rc_detect_error(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<20,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMasked {
#[inline(always)]
fn default() -> IntrMasked {
<crate::RegValueT<IntrMasked_SPEC> as RegisterValue<_>>::new(0)
}
}