/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"SAR ADC with Sequencer"]
unsafe impl ::core::marker::Send for super::Sar {}
unsafe impl ::core::marker::Sync for super::Sar {}
impl super::Sar {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "Analog control register."]
#[inline(always)]
pub const fn ctrl(&self) -> &'static crate::common::Reg<self::Ctrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Ctrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Sample control register."]
#[inline(always)]
pub const fn sample_ctrl(
&self,
) -> &'static crate::common::Reg<self::SampleCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SampleCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "Sample time specification ST0 and ST1"]
#[inline(always)]
pub const fn sample_time01(
&self,
) -> &'static crate::common::Reg<self::SampleTime01_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SampleTime01_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16usize),
)
}
}
#[doc = "Sample time specification ST2 and ST3"]
#[inline(always)]
pub const fn sample_time23(
&self,
) -> &'static crate::common::Reg<self::SampleTime23_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SampleTime23_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(20usize),
)
}
}
#[doc = "Global range detect threshold register."]
#[inline(always)]
pub const fn range_thres(
&self,
) -> &'static crate::common::Reg<self::RangeThres_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::RangeThres_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(24usize),
)
}
}
#[doc = "Global range detect mode register."]
#[inline(always)]
pub const fn range_cond(
&self,
) -> &'static crate::common::Reg<self::RangeCond_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::RangeCond_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(28usize),
)
}
}
#[doc = "Enable bits for the channels"]
#[inline(always)]
pub const fn chan_en(
&self,
) -> &'static crate::common::Reg<self::ChanEn_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ChanEn_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "Start control register (firmware trigger)."]
#[inline(always)]
pub const fn start_ctrl(
&self,
) -> &'static crate::common::Reg<self::StartCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::StartCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
#[doc = "Channel configuration register."]
#[inline(always)]
pub const fn chan_config(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::ChanConfig_SPEC, crate::common::RW>,
16,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x80usize))
}
}
#[doc = "Channel working data register"]
#[inline(always)]
pub const fn chan_work(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::ChanWork_SPEC, crate::common::R>,
16,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x100usize))
}
}
#[doc = "Channel result data register"]
#[inline(always)]
pub const fn chan_result(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::ChanResult_SPEC, crate::common::R>,
16,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x180usize))
}
}
#[doc = "Channel working data register \'updated\' bits"]
#[inline(always)]
pub const fn chan_work_updated(
&self,
) -> &'static crate::common::Reg<self::ChanWorkUpdated_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::ChanWorkUpdated_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(512usize),
)
}
}
#[doc = "Channel result data register \'updated\' bits"]
#[inline(always)]
pub const fn chan_result_updated(
&self,
) -> &'static crate::common::Reg<self::ChanResultUpdated_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::ChanResultUpdated_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(516usize),
)
}
}
#[doc = "Channel working data register \'new value\' bits"]
#[inline(always)]
pub const fn chan_work_newvalue(
&self,
) -> &'static crate::common::Reg<self::ChanWorkNewvalue_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::ChanWorkNewvalue_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(520usize),
)
}
}
#[doc = "Channel result data register \'new value\' bits"]
#[inline(always)]
pub const fn chan_result_newvalue(
&self,
) -> &'static crate::common::Reg<self::ChanResultNewvalue_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::ChanResultNewvalue_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(524usize),
)
}
}
#[doc = "Interrupt request register."]
#[inline(always)]
pub const fn intr(&self) -> &'static crate::common::Reg<self::Intr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Intr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(528usize),
)
}
}
#[doc = "Interrupt set request register"]
#[inline(always)]
pub const fn intr_set(
&self,
) -> &'static crate::common::Reg<self::IntrSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(532usize),
)
}
}
#[doc = "Interrupt mask register."]
#[inline(always)]
pub const fn intr_mask(
&self,
) -> &'static crate::common::Reg<self::IntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(536usize),
)
}
}
#[doc = "Interrupt masked request register"]
#[inline(always)]
pub const fn intr_masked(
&self,
) -> &'static crate::common::Reg<self::IntrMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(540usize),
)
}
}
#[doc = "Saturate interrupt request register."]
#[inline(always)]
pub const fn saturate_intr(
&self,
) -> &'static crate::common::Reg<self::SaturateIntr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SaturateIntr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(544usize),
)
}
}
#[doc = "Saturate interrupt set request register"]
#[inline(always)]
pub const fn saturate_intr_set(
&self,
) -> &'static crate::common::Reg<self::SaturateIntrSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SaturateIntrSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(548usize),
)
}
}
#[doc = "Saturate interrupt mask register."]
#[inline(always)]
pub const fn saturate_intr_mask(
&self,
) -> &'static crate::common::Reg<self::SaturateIntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SaturateIntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(552usize),
)
}
}
#[doc = "Saturate interrupt masked request register"]
#[inline(always)]
pub const fn saturate_intr_masked(
&self,
) -> &'static crate::common::Reg<self::SaturateIntrMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::SaturateIntrMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(556usize),
)
}
}
#[doc = "Range detect interrupt request register."]
#[inline(always)]
pub const fn range_intr(
&self,
) -> &'static crate::common::Reg<self::RangeIntr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::RangeIntr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(560usize),
)
}
}
#[doc = "Range detect interrupt set request register"]
#[inline(always)]
pub const fn range_intr_set(
&self,
) -> &'static crate::common::Reg<self::RangeIntrSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::RangeIntrSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(564usize),
)
}
}
#[doc = "Range detect interrupt mask register."]
#[inline(always)]
pub const fn range_intr_mask(
&self,
) -> &'static crate::common::Reg<self::RangeIntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::RangeIntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(568usize),
)
}
}
#[doc = "Range interrupt masked request register"]
#[inline(always)]
pub const fn range_intr_masked(
&self,
) -> &'static crate::common::Reg<self::RangeIntrMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::RangeIntrMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(572usize),
)
}
}
#[doc = "Interrupt cause register"]
#[inline(always)]
pub const fn intr_cause(
&self,
) -> &'static crate::common::Reg<self::IntrCause_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrCause_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(576usize),
)
}
}
#[doc = "Injection channel configuration register."]
#[inline(always)]
pub const fn inj_chan_config(
&self,
) -> &'static crate::common::Reg<self::InjChanConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::InjChanConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(640usize),
)
}
}
#[doc = "Injection channel result register"]
#[inline(always)]
pub const fn inj_result(
&self,
) -> &'static crate::common::Reg<self::InjResult_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::InjResult_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(656usize),
)
}
}
#[doc = "Current status of internal SAR registers (mostly for debug)"]
#[inline(always)]
pub const fn status(&self) -> &'static crate::common::Reg<self::Status_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::Status_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(672usize),
)
}
}
#[doc = "Current averaging status (for debug)"]
#[inline(always)]
pub const fn avg_stat(
&self,
) -> &'static crate::common::Reg<self::AvgStat_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::AvgStat_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(676usize),
)
}
}
#[doc = "SARMUX Firmware switch controls"]
#[inline(always)]
pub const fn mux_switch0(
&self,
) -> &'static crate::common::Reg<self::MuxSwitch0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::MuxSwitch0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(768usize),
)
}
}
#[doc = "SARMUX Firmware switch control clear"]
#[inline(always)]
pub const fn mux_switch_clear0(
&self,
) -> &'static crate::common::Reg<self::MuxSwitchClear0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::MuxSwitchClear0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(772usize),
)
}
}
#[doc = "SARMUX switch DSI control"]
#[inline(always)]
pub const fn mux_switch_ds_ctrl(
&self,
) -> &'static crate::common::Reg<self::MuxSwitchDsCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::MuxSwitchDsCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(832usize),
)
}
}
#[doc = "SARMUX switch Sar Sequencer control"]
#[inline(always)]
pub const fn mux_switch_sq_ctrl(
&self,
) -> &'static crate::common::Reg<self::MuxSwitchSqCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::MuxSwitchSqCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(836usize),
)
}
}
#[doc = "SARMUX switch status"]
#[inline(always)]
pub const fn mux_switch_status(
&self,
) -> &'static crate::common::Reg<self::MuxSwitchStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::MuxSwitchStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(840usize),
)
}
}
#[doc = "Analog trim register."]
#[inline(always)]
pub const fn ana_trim0(
&self,
) -> &'static crate::common::Reg<self::AnaTrim0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::AnaTrim0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3840usize),
)
}
}
#[doc = "Analog trim register."]
#[inline(always)]
pub const fn ana_trim1(
&self,
) -> &'static crate::common::Reg<self::AnaTrim1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::AnaTrim1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3844usize),
)
}
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctrl_SPEC;
impl crate::sealed::RegSpec for Ctrl_SPEC {
type DataType = u32;
}
#[doc = "Analog control register."]
pub type Ctrl = crate::RegValueT<Ctrl_SPEC>;
impl Ctrl {
#[doc = "VREF buffer low power mode."]
#[inline(always)]
pub fn pwr_ctrl_vref(
self,
) -> crate::common::RegisterField<
0,
0x7,
1,
0,
ctrl::PwrCtrlVref,
ctrl::PwrCtrlVref,
Ctrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x7,
1,
0,
ctrl::PwrCtrlVref,
ctrl::PwrCtrlVref,
Ctrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vref_sel(
self,
) -> crate::common::RegisterField<
4,
0x7,
1,
0,
ctrl::VrefSel,
ctrl::VrefSel,
Ctrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x7,
1,
0,
ctrl::VrefSel,
ctrl::VrefSel,
Ctrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vref_byp_cap_en(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn neg_sel(
self,
) -> crate::common::RegisterField<
9,
0x7,
1,
0,
ctrl::NegSel,
ctrl::NegSel,
Ctrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
9,
0x7,
1,
0,
ctrl::NegSel,
ctrl::NegSel,
Ctrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn sar_hw_ctrl_negvref(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<13, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn comp_dly(
self,
) -> crate::common::RegisterField<
14,
0x3,
1,
0,
ctrl::CompDly,
ctrl::CompDly,
Ctrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
14,
0x3,
1,
0,
ctrl::CompDly,
ctrl::CompDly,
Ctrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn spare(
self,
) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterField::<16,0xf,1,0,u8,u8,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn boostpump_en(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn refbuf_en(
self,
) -> crate::common::RegisterFieldBool<21, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<21, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Comparator power mode."]
#[inline(always)]
pub fn comp_pwr(
self,
) -> crate::common::RegisterField<
24,
0x7,
1,
0,
ctrl::CompPwr,
ctrl::CompPwr,
Ctrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
24,
0x7,
1,
0,
ctrl::CompPwr,
ctrl::CompPwr,
Ctrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn deepsleep_on(
self,
) -> crate::common::RegisterFieldBool<27, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<27, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn dsi_sync_config(
self,
) -> crate::common::RegisterFieldBool<28, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<28, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1)\n- 0: Normal mode, SAR sequencer operates according to CHAN_EN enables and CHAN_CONFIG channel configurations\n- 1: CHAN_EN and channel configurations in CHAN_CONFIG are ignored"]
#[inline(always)]
pub fn dsi_mode(
self,
) -> crate::common::RegisterFieldBool<29, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<29, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Disable SAR sequencer from enabling routing switches \n- 0: Normal mode, SAR sequencer changes switches according to pin address in channel configurations\n- 1: Switches disabled, SAR sequencer does not enable any switches. Other methods such as firmware control can be used to set the switches to route the signal to be converted through the SARMUX"]
#[inline(always)]
pub fn switch_disable(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "- 0: SAR disabled (put analog in power down and stop clocks), also can clear FW_TRIGGER on write.\n- 1: SAR IP enabled."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Ctrl {
#[inline(always)]
fn default() -> Ctrl {
<crate::RegValueT<Ctrl_SPEC> as RegisterValue<_>>::new(268435456)
}
}
pub mod ctrl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PwrCtrlVref_SPEC;
pub type PwrCtrlVref = crate::EnumBitfieldStruct<u8, PwrCtrlVref_SPEC>;
impl PwrCtrlVref {
#[doc = "full power (100 percent) (default), bypass cap, max clk_sar is 18MHz."]
pub const PWR_100: Self = Self::new(0);
#[doc = "80 percent power"]
pub const PWR_80: Self = Self::new(1);
#[doc = "60 percent power"]
pub const PWR_60: Self = Self::new(2);
#[doc = "50 percent power"]
pub const PWR_50: Self = Self::new(3);
#[doc = "40 percent power"]
pub const PWR_40: Self = Self::new(4);
#[doc = "30 percent power"]
pub const PWR_30: Self = Self::new(5);
#[doc = "20 percent power"]
pub const PWR_20: Self = Self::new(6);
#[doc = "10 percent power"]
pub const PWR_10: Self = Self::new(7);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct VrefSel_SPEC;
pub type VrefSel = crate::EnumBitfieldStruct<u8, VrefSel_SPEC>;
impl VrefSel {
#[doc = "VREF0 from PRB (VREF buffer on)"]
pub const VREF_0: Self = Self::new(0);
#[doc = "VREF1 from PRB (VREF buffer on)"]
pub const VREF_1: Self = Self::new(1);
#[doc = "VREF2 from PRB (VREF buffer on)"]
pub const VREF_2: Self = Self::new(2);
#[doc = "VREF from AROUTE (VREF buffer on)"]
pub const VREF_AROUTE: Self = Self::new(3);
#[doc = "1.024V from BandGap (VREF buffer on)"]
pub const VBGR: Self = Self::new(4);
#[doc = "External precision Vref direct from a pin (low impedance path)."]
pub const VREF_EXT: Self = Self::new(5);
#[doc = "Vdda/2 (VREF buffer on)"]
pub const VDDA_DIV_2: Self = Self::new(6);
#[doc = "Vdda."]
pub const VDDA: Self = Self::new(7);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct NegSel_SPEC;
pub type NegSel = crate::EnumBitfieldStruct<u8, NegSel_SPEC>;
impl NegSel {
#[doc = "NEG input of SARADC is connected to \'vssa_kelvin\', gives more precision around zero. Note this opens both SARADC internal switches, therefore use this value to insert a break-before-make cycle on those switches when SWITCH_DISABLE is high."]
pub const VSSA_KELVIN: Self = Self::new(0);
#[doc = "NEG input of SARADC is connected to VSSA in AROUTE close to the SARADC"]
pub const ART_VSSA: Self = Self::new(1);
#[doc = "NEG input of SARADC is connected to P1 pin of SARMUX"]
pub const P_1: Self = Self::new(2);
#[doc = "NEG input of SARADC is connected to P3 pin of SARMUX"]
pub const P_3: Self = Self::new(3);
#[doc = "NEG input of SARADC is connected to P5 pin of SARMUX"]
pub const P_5: Self = Self::new(4);
#[doc = "NEG input of SARADC is connected to P7 pin of SARMUX"]
pub const P_7: Self = Self::new(5);
#[doc = "NEG input of SARADC is connected to an ACORE in AROUTE"]
pub const ACORE: Self = Self::new(6);
#[doc = "NEG input of SARADC is shorted with VREF input of SARADC."]
pub const VREF: Self = Self::new(7);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CompDly_SPEC;
pub type CompDly = crate::EnumBitfieldStruct<u8, CompDly_SPEC>;
impl CompDly {
#[doc = "2.5ns delay, use this for 2.5Msps"]
pub const D_2_P_5: Self = Self::new(0);
#[doc = "4.0ns delay, use this for 2.0Msps"]
pub const D_4: Self = Self::new(1);
#[doc = "10ns delay, use this for 1.5Msps"]
pub const D_10: Self = Self::new(2);
#[doc = "12ns delay, use this for 1.0Msps or less"]
pub const D_12: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CompPwr_SPEC;
pub type CompPwr = crate::EnumBitfieldStruct<u8, CompPwr_SPEC>;
impl CompPwr {
#[doc = "Power = 100 percent, Use this for SAR Clock Frequency greater than 18MHz"]
pub const P_100: Self = Self::new(0);
#[doc = "N/A"]
pub const P_80: Self = Self::new(1);
#[doc = "Power = 60 percent, Use this for SAR Clock Frequency greater than 1.8MHz up to 18MHz."]
pub const P_60: Self = Self::new(2);
#[doc = "N/A"]
pub const P_50: Self = Self::new(3);
#[doc = "N/A"]
pub const P_40: Self = Self::new(4);
#[doc = "N/A"]
pub const P_30: Self = Self::new(5);
#[doc = "Power = 20 percent, Use this for SAR Clock Frequency less than or equal to 1.8MHz"]
pub const P_20: Self = Self::new(6);
#[doc = "N/A"]
pub const P_10: Self = Self::new(7);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SampleCtrl_SPEC;
impl crate::sealed::RegSpec for SampleCtrl_SPEC {
type DataType = u32;
}
#[doc = "Sample control register."]
pub type SampleCtrl = crate::RegValueT<SampleCtrl_SPEC>;
impl SampleCtrl {
#[doc = "N/A"]
#[inline(always)]
pub fn left_align(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, SampleCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,SampleCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn single_ended_signed(
self,
) -> crate::common::RegisterField<
2,
0x1,
1,
0,
sample_ctrl::SingleEndedSigned,
sample_ctrl::SingleEndedSigned,
SampleCtrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0x1,
1,
0,
sample_ctrl::SingleEndedSigned,
sample_ctrl::SingleEndedSigned,
SampleCtrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn differential_signed(
self,
) -> crate::common::RegisterField<
3,
0x1,
1,
0,
sample_ctrl::DifferentialSigned,
sample_ctrl::DifferentialSigned,
SampleCtrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
3,
0x1,
1,
0,
sample_ctrl::DifferentialSigned,
sample_ctrl::DifferentialSigned,
SampleCtrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn avg_cnt(
self,
) -> crate::common::RegisterField<4, 0x7, 1, 0, u8, u8, SampleCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0x7,1,0,u8,u8,SampleCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn avg_shift(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, SampleCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,SampleCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Averaging mode"]
#[inline(always)]
pub fn avg_mode(
self,
) -> crate::common::RegisterField<
8,
0x1,
1,
0,
sample_ctrl::AvgMode,
sample_ctrl::AvgMode,
SampleCtrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0x1,
1,
0,
sample_ctrl::AvgMode,
sample_ctrl::AvgMode,
SampleCtrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn continuous(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, SampleCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,SampleCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "- 0: firmware trigger only: disable hardware trigger tr_sar_in.\n- 1: enable hardware trigger tr_sar_in (e.g. from TCPWM, GPIO etc)"]
#[inline(always)]
pub fn dsi_trigger_en(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, SampleCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,SampleCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn dsi_trigger_level(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, SampleCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,SampleCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn dsi_sync_trigger(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, SampleCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,SampleCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn uab_scan_mode(
self,
) -> crate::common::RegisterField<
22,
0x1,
1,
0,
sample_ctrl::UabScanMode,
sample_ctrl::UabScanMode,
SampleCtrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
22,
0x1,
1,
0,
sample_ctrl::UabScanMode,
sample_ctrl::UabScanMode,
SampleCtrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn repeat_invalid(
self,
) -> crate::common::RegisterFieldBool<23, 1, 0, SampleCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<23,1,0,SampleCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn valid_sel(
self,
) -> crate::common::RegisterField<24, 0x7, 1, 0, u8, u8, SampleCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0x7,1,0,u8,u8,SampleCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn valid_sel_en(
self,
) -> crate::common::RegisterFieldBool<27, 1, 0, SampleCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<27,1,0,SampleCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn valid_ignore(
self,
) -> crate::common::RegisterFieldBool<28, 1, 0, SampleCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<28,1,0,SampleCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn trigger_out_en(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, SampleCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,SampleCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable to output EOS_INTR. When enabled each time EOS_INTR is set by the hardware also a trigger pulse is send on the tr_sar_out signal."]
#[inline(always)]
pub fn eos_dsi_out_en(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, SampleCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,SampleCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SampleCtrl {
#[inline(always)]
fn default() -> SampleCtrl {
<crate::RegValueT<SampleCtrl_SPEC> as RegisterValue<_>>::new(524296)
}
}
pub mod sample_ctrl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct SingleEndedSigned_SPEC;
pub type SingleEndedSigned = crate::EnumBitfieldStruct<u8, SingleEndedSigned_SPEC>;
impl SingleEndedSigned {
#[doc = "Default: result data is unsigned (zero extended if needed)"]
pub const UNSIGNED: Self = Self::new(0);
#[doc = "result data is signed (sign extended if needed)"]
pub const SIGNED: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DifferentialSigned_SPEC;
pub type DifferentialSigned = crate::EnumBitfieldStruct<u8, DifferentialSigned_SPEC>;
impl DifferentialSigned {
#[doc = "result data is unsigned (zero extended if needed)"]
pub const UNSIGNED: Self = Self::new(0);
#[doc = "Default: result data is signed (sign extended if needed)"]
pub const SIGNED: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct AvgMode_SPEC;
pub type AvgMode = crate::EnumBitfieldStruct<u8, AvgMode_SPEC>;
impl AvgMode {
#[doc = "Accumulate and Dump (1st order accumulate and dump filter): a channel will be sampled back to back and averaged"]
pub const ACCUNDUMP: Self = Self::new(0);
#[doc = "Interleaved: Each scan (trigger) one sample is taken per channel and averaged over several scans."]
pub const INTERLEAVED: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct UabScanMode_SPEC;
pub type UabScanMode = crate::EnumBitfieldStruct<u8, UabScanMode_SPEC>;
impl UabScanMode {
#[doc = "Unscheduled UABs: one or more of the UABs scanned by the SAR is not scheduled, for each channel that scans a UAB the SAR will wait for a positive edge on the trigger output of that UAB. Caveat: in this mode the length of SAR scan can be variable."]
pub const UNSCHEDULED: Self = Self::new(0);
#[doc = "Scheduled UABs: All UABs scanned by the SAR are assumed to be properly scheduled, i.e. their output is assumed to be valid when sampled by the SAR and the SAR does not wait. In this mode the length of the SAR scan is constant. \nThis mode requires that the SAR scans strictly periodically, i.e. the SAR has to either run continuously or has to be triggered by a periodic hardware trigger (TCPWM or UDB timer). It also requires that the end of the UAB valid phase is precisely aligned with the end of the SAR sample period (using UAB.STARTUP_DELAY). Normally this scheduling is done by Creator."]
pub const SCHEDULED: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SampleTime01_SPEC;
impl crate::sealed::RegSpec for SampleTime01_SPEC {
type DataType = u32;
}
#[doc = "Sample time specification ST0 and ST1"]
pub type SampleTime01 = crate::RegValueT<SampleTime01_SPEC>;
impl SampleTime01 {
#[doc = "Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is one clock less than specified here. The minimum sample time is 167ns, which is 3.0 cycles (4 in this field) with an 18MHz clock. Minimum legal value in this register is 2."]
#[inline(always)]
pub fn sample_time0(
self,
) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, SampleTime01_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x3ff,1,0,u16,u16,SampleTime01_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sample time1"]
#[inline(always)]
pub fn sample_time1(
self,
) -> crate::common::RegisterField<16, 0x3ff, 1, 0, u16, u16, SampleTime01_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
16,
0x3ff,
1,
0,
u16,
u16,
SampleTime01_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for SampleTime01 {
#[inline(always)]
fn default() -> SampleTime01 {
<crate::RegValueT<SampleTime01_SPEC> as RegisterValue<_>>::new(196611)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SampleTime23_SPEC;
impl crate::sealed::RegSpec for SampleTime23_SPEC {
type DataType = u32;
}
#[doc = "Sample time specification ST2 and ST3"]
pub type SampleTime23 = crate::RegValueT<SampleTime23_SPEC>;
impl SampleTime23 {
#[doc = "Sample time2"]
#[inline(always)]
pub fn sample_time2(
self,
) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, SampleTime23_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x3ff,1,0,u16,u16,SampleTime23_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sample time3"]
#[inline(always)]
pub fn sample_time3(
self,
) -> crate::common::RegisterField<16, 0x3ff, 1, 0, u16, u16, SampleTime23_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
16,
0x3ff,
1,
0,
u16,
u16,
SampleTime23_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for SampleTime23 {
#[inline(always)]
fn default() -> SampleTime23 {
<crate::RegValueT<SampleTime23_SPEC> as RegisterValue<_>>::new(196611)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RangeThres_SPEC;
impl crate::sealed::RegSpec for RangeThres_SPEC {
type DataType = u32;
}
#[doc = "Global range detect threshold register."]
pub type RangeThres = crate::RegValueT<RangeThres_SPEC>;
impl RangeThres {
#[doc = "Low threshold for range detect."]
#[inline(always)]
pub fn range_low(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, RangeThres_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,RangeThres_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "High threshold for range detect."]
#[inline(always)]
pub fn range_high(
self,
) -> crate::common::RegisterField<16, 0xffff, 1, 0, u16, u16, RangeThres_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xffff,1,0,u16,u16,RangeThres_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RangeThres {
#[inline(always)]
fn default() -> RangeThres {
<crate::RegValueT<RangeThres_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RangeCond_SPEC;
impl crate::sealed::RegSpec for RangeCond_SPEC {
type DataType = u32;
}
#[doc = "Global range detect mode register."]
pub type RangeCond = crate::RegValueT<RangeCond_SPEC>;
impl RangeCond {
#[doc = "Range condition select."]
#[inline(always)]
pub fn range_cond(
self,
) -> crate::common::RegisterField<
30,
0x3,
1,
0,
range_cond::RangeCond,
range_cond::RangeCond,
RangeCond_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
30,
0x3,
1,
0,
range_cond::RangeCond,
range_cond::RangeCond,
RangeCond_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RangeCond {
#[inline(always)]
fn default() -> RangeCond {
<crate::RegValueT<RangeCond_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod range_cond {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct RangeCond_SPEC;
pub type RangeCond = crate::EnumBitfieldStruct<u8, RangeCond_SPEC>;
impl RangeCond {
#[doc = "result < RANGE_LOW"]
pub const BELOW: Self = Self::new(0);
#[doc = "RANGE_LOW <= result < RANGE_HIGH"]
pub const INSIDE: Self = Self::new(1);
#[doc = "RANGE_HIGH <= result"]
pub const ABOVE: Self = Self::new(2);
#[doc = "result < RANGE_LOW || RANGE_HIGH <= result"]
pub const OUTSIDE: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ChanEn_SPEC;
impl crate::sealed::RegSpec for ChanEn_SPEC {
type DataType = u32;
}
#[doc = "Enable bits for the channels"]
pub type ChanEn = crate::RegValueT<ChanEn_SPEC>;
impl ChanEn {
#[doc = "Channel enable. \n- 0: the corresponding channel is disabled.\n- 1: the corresponding channel is enabled, it will be included in the next scan."]
#[inline(always)]
pub fn chan_en(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, ChanEn_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,ChanEn_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ChanEn {
#[inline(always)]
fn default() -> ChanEn {
<crate::RegValueT<ChanEn_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct StartCtrl_SPEC;
impl crate::sealed::RegSpec for StartCtrl_SPEC {
type DataType = u32;
}
#[doc = "Start control register (firmware trigger)."]
pub type StartCtrl = crate::RegValueT<StartCtrl_SPEC>;
impl StartCtrl {
#[doc = "When firmware writes a 1 here it will trigger the next scan of enabled channels, hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after the next scan is done. This bit is also cleared when the SAR is disabled."]
#[inline(always)]
pub fn fw_trigger(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, StartCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,StartCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for StartCtrl {
#[inline(always)]
fn default() -> StartCtrl {
<crate::RegValueT<StartCtrl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ChanConfig_SPEC;
impl crate::sealed::RegSpec for ChanConfig_SPEC {
type DataType = u32;
}
#[doc = "Channel configuration register."]
pub type ChanConfig = crate::RegValueT<ChanConfig_SPEC>;
impl ChanConfig {
#[doc = "N/A"]
#[inline(always)]
pub fn pos_pin_addr(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, ChanConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,ChanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn pos_port_addr(
self,
) -> crate::common::RegisterField<
4,
0x7,
1,
0,
chan_config::PosPortAddr,
chan_config::PosPortAddr,
ChanConfig_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x7,
1,
0,
chan_config::PosPortAddr,
chan_config::PosPortAddr,
ChanConfig_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn differential_en(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, ChanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,ChanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn avg_en(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, ChanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,ChanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn sample_time_sel(
self,
) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, ChanConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<12,0x3,1,0,u8,u8,ChanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn neg_pin_addr(
self,
) -> crate::common::RegisterField<16, 0x7, 1, 0, u8, u8, ChanConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x7,1,0,u8,u8,ChanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn neg_port_addr(
self,
) -> crate::common::RegisterField<
20,
0x7,
1,
0,
chan_config::NegPortAddr,
chan_config::NegPortAddr,
ChanConfig_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
20,
0x7,
1,
0,
chan_config::NegPortAddr,
chan_config::NegPortAddr,
ChanConfig_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn neg_addr_en(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, ChanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,ChanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn dsi_out_en(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ChanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,ChanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ChanConfig {
#[inline(always)]
fn default() -> ChanConfig {
<crate::RegValueT<ChanConfig_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod chan_config {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PosPortAddr_SPEC;
pub type PosPortAddr = crate::EnumBitfieldStruct<u8, PosPortAddr_SPEC>;
impl PosPortAddr {
#[doc = "SARMUX pins."]
pub const SARMUX: Self = Self::new(0);
#[doc = "CTB0"]
pub const CTB_0: Self = Self::new(1);
#[doc = "CTB1"]
pub const CTB_1: Self = Self::new(2);
#[doc = "CTB2"]
pub const CTB_2: Self = Self::new(3);
#[doc = "CTB3"]
pub const CTB_3: Self = Self::new(4);
#[doc = "AROUTE virtual port2 (VPORT2)"]
pub const AROUTE_VIRT_2: Self = Self::new(5);
#[doc = "AROUTE virtual port1 (VPORT1)"]
pub const AROUTE_VIRT_1: Self = Self::new(6);
#[doc = "SARMUX virtual port (VPORT0)"]
pub const SARMUX_VIRT: Self = Self::new(7);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct NegPortAddr_SPEC;
pub type NegPortAddr = crate::EnumBitfieldStruct<u8, NegPortAddr_SPEC>;
impl NegPortAddr {
#[doc = "SARMUX pins."]
pub const SARMUX: Self = Self::new(0);
#[doc = "AROUTE virtual port2 (VPORT2)"]
pub const AROUTE_VIRT_2: Self = Self::new(5);
#[doc = "AROUTE virtual port1 (VPORT1)"]
pub const AROUTE_VIRT_1: Self = Self::new(6);
#[doc = "SARMUX virtual port (VPORT0)"]
pub const SARMUX_VIRT: Self = Self::new(7);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ChanWork_SPEC;
impl crate::sealed::RegSpec for ChanWork_SPEC {
type DataType = u32;
}
#[doc = "Channel working data register"]
pub type ChanWork = crate::RegValueT<ChanWork_SPEC>;
impl ChanWork {
#[doc = "SAR conversion working data of the channel. The data is written here right after sampling this channel."]
#[inline(always)]
pub fn work(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, ChanWork_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,ChanWork_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register"]
#[inline(always)]
pub fn chan_work_newvalue_mir(
self,
) -> crate::common::RegisterFieldBool<27, 1, 0, ChanWork_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<27, 1, 0, ChanWork_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register"]
#[inline(always)]
pub fn chan_work_updated_mir(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ChanWork_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31, 1, 0, ChanWork_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for ChanWork {
#[inline(always)]
fn default() -> ChanWork {
<crate::RegValueT<ChanWork_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ChanResult_SPEC;
impl crate::sealed::RegSpec for ChanResult_SPEC {
type DataType = u32;
}
#[doc = "Channel result data register"]
pub type ChanResult = crate::RegValueT<ChanResult_SPEC>;
impl ChanResult {
#[doc = "SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled."]
#[inline(always)]
pub fn result(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, ChanResult_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,ChanResult_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register"]
#[inline(always)]
pub fn chan_result_newvalue_mir(
self,
) -> crate::common::RegisterFieldBool<27, 1, 0, ChanResult_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<27,1,0,ChanResult_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "mirror bit of corresponding bit in SAR_SATURATE_INTR register"]
#[inline(always)]
pub fn saturate_intr_mir(
self,
) -> crate::common::RegisterFieldBool<29, 1, 0, ChanResult_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<29,1,0,ChanResult_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "mirror bit of corresponding bit in SAR_RANGE_INTR register"]
#[inline(always)]
pub fn range_intr_mir(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, ChanResult_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<30,1,0,ChanResult_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register"]
#[inline(always)]
pub fn chan_result_updated_mir(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ChanResult_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31,1,0,ChanResult_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for ChanResult {
#[inline(always)]
fn default() -> ChanResult {
<crate::RegValueT<ChanResult_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ChanWorkUpdated_SPEC;
impl crate::sealed::RegSpec for ChanWorkUpdated_SPEC {
type DataType = u32;
}
#[doc = "Channel working data register \'updated\' bits"]
pub type ChanWorkUpdated = crate::RegValueT<ChanWorkUpdated_SPEC>;
impl ChanWorkUpdated {
#[doc = "If set the corresponding WORK register was updated, i.e. was already sampled during the current scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging."]
#[inline(always)]
pub fn chan_work_updated(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ChanWorkUpdated_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ChanWorkUpdated_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ChanWorkUpdated {
#[inline(always)]
fn default() -> ChanWorkUpdated {
<crate::RegValueT<ChanWorkUpdated_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ChanResultUpdated_SPEC;
impl crate::sealed::RegSpec for ChanResultUpdated_SPEC {
type DataType = u32;
}
#[doc = "Channel result data register \'updated\' bits"]
pub type ChanResultUpdated = crate::RegValueT<ChanResultUpdated_SPEC>;
impl ChanResultUpdated {
#[doc = "If set the corresponding RESULT register was updated, i.e. was sampled during the previous scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging."]
#[inline(always)]
pub fn chan_result_updated(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ChanResultUpdated_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ChanResultUpdated_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ChanResultUpdated {
#[inline(always)]
fn default() -> ChanResultUpdated {
<crate::RegValueT<ChanResultUpdated_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ChanWorkNewvalue_SPEC;
impl crate::sealed::RegSpec for ChanWorkNewvalue_SPEC {
type DataType = u32;
}
#[doc = "Channel working data register \'new value\' bits"]
pub type ChanWorkNewvalue = crate::RegValueT<ChanWorkNewvalue_SPEC>;
impl ChanWorkNewvalue {
#[doc = "If set the corresponding WORK data received a new value, i.e. was already sampled during the current scan and data was valid.\nIn case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid.\nIn case of averaging this New Value bit is an OR of all the valid bits received by each conversion."]
#[inline(always)]
pub fn chan_work_newvalue(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ChanWorkNewvalue_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ChanWorkNewvalue_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ChanWorkNewvalue {
#[inline(always)]
fn default() -> ChanWorkNewvalue {
<crate::RegValueT<ChanWorkNewvalue_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ChanResultNewvalue_SPEC;
impl crate::sealed::RegSpec for ChanResultNewvalue_SPEC {
type DataType = u32;
}
#[doc = "Channel result data register \'new value\' bits"]
pub type ChanResultNewvalue = crate::RegValueT<ChanResultNewvalue_SPEC>;
impl ChanResultNewvalue {
#[doc = "If set the corresponding RESULT data received a new value, i.e. was sampled during the last scan and data was valid.\nIn case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid.\nIn case of averaging this New Value bit is an OR of all the valid bits received by each conversion."]
#[inline(always)]
pub fn chan_result_newvalue(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ChanResultNewvalue_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ChanResultNewvalue_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ChanResultNewvalue {
#[inline(always)]
fn default() -> ChanResultNewvalue {
<crate::RegValueT<ChanResultNewvalue_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Intr_SPEC;
impl crate::sealed::RegSpec for Intr_SPEC {
type DataType = u32;
}
#[doc = "Interrupt request register."]
pub type Intr = crate::RegValueT<Intr_SPEC>;
impl Intr {
#[doc = "N/A"]
#[inline(always)]
pub fn eos_intr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn overflow_intr(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn fw_collision_intr(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "This interrupt is set when a hardware trigger signal is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the hardware trigger has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with \'1\' to clear bit."]
#[inline(always)]
pub fn dsi_collision_intr(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_eoc_intr(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_saturate_intr(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_range_intr(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_collision_intr(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Intr {
#[inline(always)]
fn default() -> Intr {
<crate::RegValueT<Intr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSet_SPEC;
impl crate::sealed::RegSpec for IntrSet_SPEC {
type DataType = u32;
}
#[doc = "Interrupt set request register"]
pub type IntrSet = crate::RegValueT<IntrSet_SPEC>;
impl IntrSet {
#[doc = "N/A"]
#[inline(always)]
pub fn eos_set(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn overflow_set(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn fw_collision_set(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn dsi_collision_set(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_eoc_set(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_saturate_set(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_range_set(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_collision_set(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for IntrSet {
#[inline(always)]
fn default() -> IntrSet {
<crate::RegValueT<IntrSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMask_SPEC;
impl crate::sealed::RegSpec for IntrMask_SPEC {
type DataType = u32;
}
#[doc = "Interrupt mask register."]
pub type IntrMask = crate::RegValueT<IntrMask_SPEC>;
impl IntrMask {
#[doc = "N/A"]
#[inline(always)]
pub fn eos_mask(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn overflow_mask(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn fw_collision_mask(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn dsi_collision_mask(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_eoc_mask(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_saturate_mask(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_range_mask(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_collision_mask(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for IntrMask {
#[inline(always)]
fn default() -> IntrMask {
<crate::RegValueT<IntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMasked_SPEC;
impl crate::sealed::RegSpec for IntrMasked_SPEC {
type DataType = u32;
}
#[doc = "Interrupt masked request register"]
pub type IntrMasked = crate::RegValueT<IntrMasked_SPEC>;
impl IntrMasked {
#[doc = "N/A"]
#[inline(always)]
pub fn eos_masked(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn overflow_masked(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn fw_collision_masked(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn dsi_collision_masked(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_eoc_masked(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_saturate_masked(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_range_masked(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<6,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_collision_masked(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<7,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMasked {
#[inline(always)]
fn default() -> IntrMasked {
<crate::RegValueT<IntrMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SaturateIntr_SPEC;
impl crate::sealed::RegSpec for SaturateIntr_SPEC {
type DataType = u32;
}
#[doc = "Saturate interrupt request register."]
pub type SaturateIntr = crate::RegValueT<SaturateIntr_SPEC>;
impl SaturateIntr {
#[doc = "Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with \'1\' to clear bit."]
#[inline(always)]
pub fn saturate_intr(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, SaturateIntr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
SaturateIntr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for SaturateIntr {
#[inline(always)]
fn default() -> SaturateIntr {
<crate::RegValueT<SaturateIntr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SaturateIntrSet_SPEC;
impl crate::sealed::RegSpec for SaturateIntrSet_SPEC {
type DataType = u32;
}
#[doc = "Saturate interrupt set request register"]
pub type SaturateIntrSet = crate::RegValueT<SaturateIntrSet_SPEC>;
impl SaturateIntrSet {
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn saturate_set(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
SaturateIntrSet_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
SaturateIntrSet_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for SaturateIntrSet {
#[inline(always)]
fn default() -> SaturateIntrSet {
<crate::RegValueT<SaturateIntrSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SaturateIntrMask_SPEC;
impl crate::sealed::RegSpec for SaturateIntrMask_SPEC {
type DataType = u32;
}
#[doc = "Saturate interrupt mask register."]
pub type SaturateIntrMask = crate::RegValueT<SaturateIntrMask_SPEC>;
impl SaturateIntrMask {
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn saturate_mask(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
SaturateIntrMask_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
SaturateIntrMask_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for SaturateIntrMask {
#[inline(always)]
fn default() -> SaturateIntrMask {
<crate::RegValueT<SaturateIntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SaturateIntrMasked_SPEC;
impl crate::sealed::RegSpec for SaturateIntrMasked_SPEC {
type DataType = u32;
}
#[doc = "Saturate interrupt masked request register"]
pub type SaturateIntrMasked = crate::RegValueT<SaturateIntrMasked_SPEC>;
impl SaturateIntrMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn saturate_masked(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
SaturateIntrMasked_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
SaturateIntrMasked_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for SaturateIntrMasked {
#[inline(always)]
fn default() -> SaturateIntrMasked {
<crate::RegValueT<SaturateIntrMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RangeIntr_SPEC;
impl crate::sealed::RegSpec for RangeIntr_SPEC {
type DataType = u32;
}
#[doc = "Range detect interrupt request register."]
pub type RangeIntr = crate::RegValueT<RangeIntr_SPEC>;
impl RangeIntr {
#[doc = "Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. Write with \'1\' to clear bit."]
#[inline(always)]
pub fn range_intr(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, RangeIntr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,RangeIntr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RangeIntr {
#[inline(always)]
fn default() -> RangeIntr {
<crate::RegValueT<RangeIntr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RangeIntrSet_SPEC;
impl crate::sealed::RegSpec for RangeIntrSet_SPEC {
type DataType = u32;
}
#[doc = "Range detect interrupt set request register"]
pub type RangeIntrSet = crate::RegValueT<RangeIntrSet_SPEC>;
impl RangeIntrSet {
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn range_set(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, RangeIntrSet_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
RangeIntrSet_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RangeIntrSet {
#[inline(always)]
fn default() -> RangeIntrSet {
<crate::RegValueT<RangeIntrSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RangeIntrMask_SPEC;
impl crate::sealed::RegSpec for RangeIntrMask_SPEC {
type DataType = u32;
}
#[doc = "Range detect interrupt mask register."]
pub type RangeIntrMask = crate::RegValueT<RangeIntrMask_SPEC>;
impl RangeIntrMask {
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn range_mask(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
RangeIntrMask_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
RangeIntrMask_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RangeIntrMask {
#[inline(always)]
fn default() -> RangeIntrMask {
<crate::RegValueT<RangeIntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RangeIntrMasked_SPEC;
impl crate::sealed::RegSpec for RangeIntrMasked_SPEC {
type DataType = u32;
}
#[doc = "Range interrupt masked request register"]
pub type RangeIntrMasked = crate::RegValueT<RangeIntrMasked_SPEC>;
impl RangeIntrMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn range_masked(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
RangeIntrMasked_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
RangeIntrMasked_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RangeIntrMasked {
#[inline(always)]
fn default() -> RangeIntrMasked {
<crate::RegValueT<RangeIntrMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrCause_SPEC;
impl crate::sealed::RegSpec for IntrCause_SPEC {
type DataType = u32;
}
#[doc = "Interrupt cause register"]
pub type IntrCause = crate::RegValueT<IntrCause_SPEC>;
impl IntrCause {
#[doc = "N/A"]
#[inline(always)]
pub fn eos_masked_mir(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn overflow_masked_mir(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn fw_collision_masked_mir(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn dsi_collision_masked_mir(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_eoc_masked_mir(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_saturate_masked_mir(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_range_masked_mir(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<6, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_collision_masked_mir(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<7, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn saturate_masked_red(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<30,1,0,IntrCause_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn range_masked_red(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31,1,0,IntrCause_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrCause {
#[inline(always)]
fn default() -> IntrCause {
<crate::RegValueT<IntrCause_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InjChanConfig_SPEC;
impl crate::sealed::RegSpec for InjChanConfig_SPEC {
type DataType = u32;
}
#[doc = "Injection channel configuration register."]
pub type InjChanConfig = crate::RegValueT<InjChanConfig_SPEC>;
impl InjChanConfig {
#[doc = "N/A"]
#[inline(always)]
pub fn inj_pin_addr(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, InjChanConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,InjChanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_port_addr(
self,
) -> crate::common::RegisterField<
4,
0x7,
1,
0,
inj_chan_config::InjPortAddr,
inj_chan_config::InjPortAddr,
InjChanConfig_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x7,
1,
0,
inj_chan_config::InjPortAddr,
inj_chan_config::InjPortAddr,
InjChanConfig_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_differential_en(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, InjChanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,InjChanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_avg_en(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, InjChanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,InjChanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_sample_time_sel(
self,
) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, InjChanConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<12,0x3,1,0,u8,u8,InjChanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_tailgating(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, InjChanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,InjChanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn inj_start_en(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, InjChanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,InjChanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for InjChanConfig {
#[inline(always)]
fn default() -> InjChanConfig {
<crate::RegValueT<InjChanConfig_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod inj_chan_config {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct InjPortAddr_SPEC;
pub type InjPortAddr = crate::EnumBitfieldStruct<u8, InjPortAddr_SPEC>;
impl InjPortAddr {
#[doc = "SARMUX pins."]
pub const SARMUX: Self = Self::new(0);
#[doc = "CTB0"]
pub const CTB_0: Self = Self::new(1);
#[doc = "CTB1"]
pub const CTB_1: Self = Self::new(2);
#[doc = "CTB2"]
pub const CTB_2: Self = Self::new(3);
#[doc = "CTB3"]
pub const CTB_3: Self = Self::new(4);
#[doc = "AROUTE virtual port"]
pub const AROUTE_VIRT: Self = Self::new(6);
#[doc = "SARMUX virtual port"]
pub const SARMUX_VIRT: Self = Self::new(7);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InjResult_SPEC;
impl crate::sealed::RegSpec for InjResult_SPEC {
type DataType = u32;
}
#[doc = "Injection channel result register"]
pub type InjResult = crate::RegValueT<InjResult_SPEC>;
impl InjResult {
#[doc = "SAR conversion result of the channel."]
#[inline(always)]
pub fn inj_result(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, InjResult_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,InjResult_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "The data in this register received a new value (only relevant for UAB, this bit shows the value of the UAB valid bit)"]
#[inline(always)]
pub fn inj_newvalue(
self,
) -> crate::common::RegisterFieldBool<27, 1, 0, InjResult_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<27,1,0,InjResult_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "mirror bit of corresponding bit in SAR_INTR register"]
#[inline(always)]
pub fn inj_collision_intr_mir(
self,
) -> crate::common::RegisterFieldBool<28, 1, 0, InjResult_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<28,1,0,InjResult_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "mirror bit of corresponding bit in SAR_INTR register"]
#[inline(always)]
pub fn inj_saturate_intr_mir(
self,
) -> crate::common::RegisterFieldBool<29, 1, 0, InjResult_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<29,1,0,InjResult_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "mirror bit of corresponding bit in SAR_INTR register"]
#[inline(always)]
pub fn inj_range_intr_mir(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, InjResult_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<30,1,0,InjResult_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "mirror bit of corresponding bit in SAR_INTR register"]
#[inline(always)]
pub fn inj_eoc_intr_mir(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, InjResult_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31,1,0,InjResult_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for InjResult {
#[inline(always)]
fn default() -> InjResult {
<crate::RegValueT<InjResult_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Status_SPEC;
impl crate::sealed::RegSpec for Status_SPEC {
type DataType = u32;
}
#[doc = "Current status of internal SAR registers (mostly for debug)"]
pub type Status = crate::RegValueT<Status_SPEC>;
impl Status {
#[doc = "current channel being sampled (channel 16 indicates the injection channel), only valid if BUSY."]
#[inline(always)]
pub fn cur_chan(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, Status_SPEC, crate::common::R> {
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,Status_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "the current switch status, including DSI and sequencer controls, of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL)."]
#[inline(always)]
pub fn sw_vref_neg(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<30, 1, 0, Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down."]
#[inline(always)]
pub fn busy(self) -> crate::common::RegisterFieldBool<31, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31, 1, 0, Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Status {
#[inline(always)]
fn default() -> Status {
<crate::RegValueT<Status_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AvgStat_SPEC;
impl crate::sealed::RegSpec for AvgStat_SPEC {
type DataType = u32;
}
#[doc = "Current averaging status (for debug)"]
pub type AvgStat = crate::RegValueT<AvgStat_SPEC>;
impl AvgStat {
#[doc = "the current value of the averaging accumulator"]
#[inline(always)]
pub fn cur_avg_accu(
self,
) -> crate::common::RegisterField<0, 0xfffff, 1, 0, u32, u32, AvgStat_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xfffff,1,0,u32,u32,AvgStat_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "If high then the SAR is in the middle of Interleaved averaging spanning several scans. While this bit is high the Firmware should not make any changes to the configuration registers otherwise some results may be incorrect. Note that the CUR_AVG_CNT status register below gives an indication how many more scans need to be done to complete the Interleaved averaging.\nThis bit can be cleared by changing the averaging mode to ACCUNDUMP or by disabling the SAR."]
#[inline(always)]
pub fn intrlv_busy(
self,
) -> crate::common::RegisterFieldBool<23, 1, 0, AvgStat_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<23, 1, 0, AvgStat_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "the current value of the averaging counter. Note that the value shown is updated after the sampling time and therefore runs ahead of the accumulator update."]
#[inline(always)]
pub fn cur_avg_cnt(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, AvgStat_SPEC, crate::common::R> {
crate::common::RegisterField::<24,0xff,1,0,u8,u8,AvgStat_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for AvgStat {
#[inline(always)]
fn default() -> AvgStat {
<crate::RegValueT<AvgStat_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MuxSwitch0_SPEC;
impl crate::sealed::RegSpec for MuxSwitch0_SPEC {
type DataType = u32;
}
#[doc = "SARMUX Firmware switch controls"]
pub type MuxSwitch0 = crate::RegValueT<MuxSwitch0_SPEC>;
impl MuxSwitch0 {
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p0_vplus(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p1_vplus(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p2_vplus(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p3_vplus(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p4_vplus(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p5_vplus(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p6_vplus(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p7_vplus(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p0_vminus(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p1_vminus(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p2_vminus(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p3_vminus(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p4_vminus(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p5_vminus(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<13,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p6_vminus(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<14,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p7_vminus(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<15,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_vssa_vminus(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_temp_vplus(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_amuxbusa_vplus(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_amuxbusb_vplus(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_amuxbusa_vminus(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_amuxbusb_vminus(
self,
) -> crate::common::RegisterFieldBool<21, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<21,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_sarbus0_vplus(
self,
) -> crate::common::RegisterFieldBool<22, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<22,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_sarbus1_vplus(
self,
) -> crate::common::RegisterFieldBool<23, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<23,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_sarbus0_vminus(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_sarbus1_vminus(
self,
) -> crate::common::RegisterFieldBool<25, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<25,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p4_coreio0(
self,
) -> crate::common::RegisterFieldBool<26, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<26,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p5_coreio1(
self,
) -> crate::common::RegisterFieldBool<27, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<27,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p6_coreio2(
self,
) -> crate::common::RegisterFieldBool<28, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<28,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p7_coreio3(
self,
) -> crate::common::RegisterFieldBool<29, 1, 0, MuxSwitch0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<29,1,0,MuxSwitch0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for MuxSwitch0 {
#[inline(always)]
fn default() -> MuxSwitch0 {
<crate::RegValueT<MuxSwitch0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MuxSwitchClear0_SPEC;
impl crate::sealed::RegSpec for MuxSwitchClear0_SPEC {
type DataType = u32;
}
#[doc = "SARMUX Firmware switch control clear"]
pub type MuxSwitchClear0 = crate::RegValueT<MuxSwitchClear0_SPEC>;
impl MuxSwitchClear0 {
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p0_vplus(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p1_vplus(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p2_vplus(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p3_vplus(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p4_vplus(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p5_vplus(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p6_vplus(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p7_vplus(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p0_vminus(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p1_vminus(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p2_vminus(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p3_vminus(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p4_vminus(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p5_vminus(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<13,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p6_vminus(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<14,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p7_vminus(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<15,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_vssa_vminus(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_temp_vplus(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_amuxbusa_vplus(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_amuxbusb_vplus(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_amuxbusa_vminus(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_amuxbusb_vminus(
self,
) -> crate::common::RegisterFieldBool<21, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<21,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_sarbus0_vplus(
self,
) -> crate::common::RegisterFieldBool<22, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<22,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_sarbus1_vplus(
self,
) -> crate::common::RegisterFieldBool<23, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<23,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_sarbus0_vminus(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_sarbus1_vminus(
self,
) -> crate::common::RegisterFieldBool<25, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<25,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p4_coreio0(
self,
) -> crate::common::RegisterFieldBool<26, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<26,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p5_coreio1(
self,
) -> crate::common::RegisterFieldBool<27, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<27,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p6_coreio2(
self,
) -> crate::common::RegisterFieldBool<28, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<28,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mux_fw_p7_coreio3(
self,
) -> crate::common::RegisterFieldBool<29, 1, 0, MuxSwitchClear0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<29,1,0,MuxSwitchClear0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for MuxSwitchClear0 {
#[inline(always)]
fn default() -> MuxSwitchClear0 {
<crate::RegValueT<MuxSwitchClear0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MuxSwitchDsCtrl_SPEC;
impl crate::sealed::RegSpec for MuxSwitchDsCtrl_SPEC {
type DataType = u32;
}
#[doc = "SARMUX switch DSI control"]
pub type MuxSwitchDsCtrl = crate::RegValueT<MuxSwitchDsCtrl_SPEC>;
impl MuxSwitchDsCtrl {
#[doc = "for P0 switches"]
#[inline(always)]
pub fn mux_ds_ctrl_p0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, MuxSwitchDsCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,MuxSwitchDsCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for P1 switches"]
#[inline(always)]
pub fn mux_ds_ctrl_p1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, MuxSwitchDsCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,MuxSwitchDsCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for P2 switches"]
#[inline(always)]
pub fn mux_ds_ctrl_p2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, MuxSwitchDsCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,MuxSwitchDsCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for P3 switches"]
#[inline(always)]
pub fn mux_ds_ctrl_p3(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, MuxSwitchDsCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,MuxSwitchDsCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for P4 switches"]
#[inline(always)]
pub fn mux_ds_ctrl_p4(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, MuxSwitchDsCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,MuxSwitchDsCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for P5 switches"]
#[inline(always)]
pub fn mux_ds_ctrl_p5(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, MuxSwitchDsCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,MuxSwitchDsCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for P6 switches"]
#[inline(always)]
pub fn mux_ds_ctrl_p6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, MuxSwitchDsCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,MuxSwitchDsCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for P7 switches"]
#[inline(always)]
pub fn mux_ds_ctrl_p7(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, MuxSwitchDsCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,MuxSwitchDsCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for vssa switch"]
#[inline(always)]
pub fn mux_ds_ctrl_vssa(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, MuxSwitchDsCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,MuxSwitchDsCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for temp switch"]
#[inline(always)]
pub fn mux_ds_ctrl_temp(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, MuxSwitchDsCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,MuxSwitchDsCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for amuxbusa switch"]
#[inline(always)]
pub fn mux_ds_ctrl_amuxbusa(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, MuxSwitchDsCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,MuxSwitchDsCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for amuxbusb switches"]
#[inline(always)]
pub fn mux_ds_ctrl_amuxbusb(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, MuxSwitchDsCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,MuxSwitchDsCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for sarbus0 switch"]
#[inline(always)]
pub fn mux_ds_ctrl_sarbus0(
self,
) -> crate::common::RegisterFieldBool<22, 1, 0, MuxSwitchDsCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<22,1,0,MuxSwitchDsCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for sarbus1 switch"]
#[inline(always)]
pub fn mux_ds_ctrl_sarbus1(
self,
) -> crate::common::RegisterFieldBool<23, 1, 0, MuxSwitchDsCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<23,1,0,MuxSwitchDsCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for MuxSwitchDsCtrl {
#[inline(always)]
fn default() -> MuxSwitchDsCtrl {
<crate::RegValueT<MuxSwitchDsCtrl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MuxSwitchSqCtrl_SPEC;
impl crate::sealed::RegSpec for MuxSwitchSqCtrl_SPEC {
type DataType = u32;
}
#[doc = "SARMUX switch Sar Sequencer control"]
pub type MuxSwitchSqCtrl = crate::RegValueT<MuxSwitchSqCtrl_SPEC>;
impl MuxSwitchSqCtrl {
#[doc = "for P0 switches"]
#[inline(always)]
pub fn mux_sq_ctrl_p0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, MuxSwitchSqCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,MuxSwitchSqCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for P1 switches"]
#[inline(always)]
pub fn mux_sq_ctrl_p1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, MuxSwitchSqCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,MuxSwitchSqCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for P2 switches"]
#[inline(always)]
pub fn mux_sq_ctrl_p2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, MuxSwitchSqCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,MuxSwitchSqCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for P3 switches"]
#[inline(always)]
pub fn mux_sq_ctrl_p3(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, MuxSwitchSqCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,MuxSwitchSqCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for P4 switches"]
#[inline(always)]
pub fn mux_sq_ctrl_p4(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, MuxSwitchSqCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,MuxSwitchSqCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for P5 switches"]
#[inline(always)]
pub fn mux_sq_ctrl_p5(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, MuxSwitchSqCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,MuxSwitchSqCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for P6 switches"]
#[inline(always)]
pub fn mux_sq_ctrl_p6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, MuxSwitchSqCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,MuxSwitchSqCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for P7 switches"]
#[inline(always)]
pub fn mux_sq_ctrl_p7(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, MuxSwitchSqCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,MuxSwitchSqCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for vssa switch"]
#[inline(always)]
pub fn mux_sq_ctrl_vssa(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, MuxSwitchSqCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,MuxSwitchSqCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for temp switch"]
#[inline(always)]
pub fn mux_sq_ctrl_temp(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, MuxSwitchSqCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,MuxSwitchSqCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for amuxbusa switch"]
#[inline(always)]
pub fn mux_sq_ctrl_amuxbusa(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, MuxSwitchSqCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,MuxSwitchSqCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for amuxbusb switches"]
#[inline(always)]
pub fn mux_sq_ctrl_amuxbusb(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, MuxSwitchSqCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,MuxSwitchSqCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for sarbus0 switch"]
#[inline(always)]
pub fn mux_sq_ctrl_sarbus0(
self,
) -> crate::common::RegisterFieldBool<22, 1, 0, MuxSwitchSqCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<22,1,0,MuxSwitchSqCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "for sarbus1 switch"]
#[inline(always)]
pub fn mux_sq_ctrl_sarbus1(
self,
) -> crate::common::RegisterFieldBool<23, 1, 0, MuxSwitchSqCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<23,1,0,MuxSwitchSqCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for MuxSwitchSqCtrl {
#[inline(always)]
fn default() -> MuxSwitchSqCtrl {
<crate::RegValueT<MuxSwitchSqCtrl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MuxSwitchStatus_SPEC;
impl crate::sealed::RegSpec for MuxSwitchStatus_SPEC {
type DataType = u32;
}
#[doc = "SARMUX switch status"]
pub type MuxSwitchStatus = crate::RegValueT<MuxSwitchStatus_SPEC>;
impl MuxSwitchStatus {
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_p0_vplus(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_p1_vplus(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_p2_vplus(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_p3_vplus(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_p4_vplus(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_p5_vplus(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_p6_vplus(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<6,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_p7_vplus(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<7,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_p0_vminus(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_p1_vminus(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<9,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_p2_vminus(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<10,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_p3_vminus(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<11,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_p4_vminus(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<12,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_p5_vminus(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<13,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_p6_vminus(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<14,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_p7_vminus(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<15,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_vssa_vminus(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_temp_vplus(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<17,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_amuxbusa_vplus(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<18,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_amuxbusb_vplus(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<19,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_amuxbusa_vminus(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<20,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_amuxbusb_vminus(
self,
) -> crate::common::RegisterFieldBool<21, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<21,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_sarbus0_vplus(
self,
) -> crate::common::RegisterFieldBool<22, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<22,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_sarbus1_vplus(
self,
) -> crate::common::RegisterFieldBool<23, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<23,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_sarbus0_vminus(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<24,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "switch status of corresponding bit in MUX_SWITCH0"]
#[inline(always)]
pub fn mux_fw_sarbus1_vminus(
self,
) -> crate::common::RegisterFieldBool<25, 1, 0, MuxSwitchStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<25,1,0,MuxSwitchStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for MuxSwitchStatus {
#[inline(always)]
fn default() -> MuxSwitchStatus {
<crate::RegValueT<MuxSwitchStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AnaTrim0_SPEC;
impl crate::sealed::RegSpec for AnaTrim0_SPEC {
type DataType = u32;
}
#[doc = "Analog trim register."]
pub type AnaTrim0 = crate::RegValueT<AnaTrim0_SPEC>;
impl AnaTrim0 {
#[doc = "Attenuation cap trimming"]
#[inline(always)]
pub fn cap_trim(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, AnaTrim0_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,AnaTrim0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Attenuation cap trimming"]
#[inline(always)]
pub fn trimunit(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, AnaTrim0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, AnaTrim0_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for AnaTrim0 {
#[inline(always)]
fn default() -> AnaTrim0 {
<crate::RegValueT<AnaTrim0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AnaTrim1_SPEC;
impl crate::sealed::RegSpec for AnaTrim1_SPEC {
type DataType = u32;
}
#[doc = "Analog trim register."]
pub type AnaTrim1 = crate::RegValueT<AnaTrim1_SPEC>;
impl AnaTrim1 {
#[doc = "SAR Reference buffer trim"]
#[inline(always)]
pub fn sar_ref_buf_trim(
self,
) -> crate::common::RegisterField<0, 0x3f, 1, 0, u8, u8, AnaTrim1_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0x3f,1,0,u8,u8,AnaTrim1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for AnaTrim1 {
#[inline(always)]
fn default() -> AnaTrim1 {
<crate::RegValueT<AnaTrim1_SPEC> as RegisterValue<_>>::new(0)
}
}