/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"Capsense Controller"]
unsafe impl ::core::marker::Send for super::Csd {}
unsafe impl ::core::marker::Sync for super::Csd {}
impl super::Csd {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "Configuration and Control"]
#[inline(always)]
pub const fn config(
&self,
) -> &'static crate::common::Reg<self::Config_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Config_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Spare MMIO"]
#[inline(always)]
pub const fn spare(&self) -> &'static crate::common::Reg<self::Spare_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Spare_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "Status Register"]
#[inline(always)]
pub const fn status(&self) -> &'static crate::common::Reg<self::Status_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::Status_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(128usize),
)
}
}
#[doc = "Current Sequencer status"]
#[inline(always)]
pub const fn stat_seq(
&self,
) -> &'static crate::common::Reg<self::StatSeq_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::StatSeq_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(132usize),
)
}
}
#[doc = "Current status counts"]
#[inline(always)]
pub const fn stat_cnts(
&self,
) -> &'static crate::common::Reg<self::StatCnts_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::StatCnts_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(136usize),
)
}
}
#[doc = "Current count of the HSCMP counter"]
#[inline(always)]
pub const fn stat_hcnt(
&self,
) -> &'static crate::common::Reg<self::StatHcnt_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::StatHcnt_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(140usize),
)
}
}
#[doc = "Result CSD/CSX accumulation counter value 1"]
#[inline(always)]
pub const fn result_val1(
&self,
) -> &'static crate::common::Reg<self::ResultVal1_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::ResultVal1_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(208usize),
)
}
}
#[doc = "Result CSX accumulation counter value 2"]
#[inline(always)]
pub const fn result_val2(
&self,
) -> &'static crate::common::Reg<self::ResultVal2_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::ResultVal2_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(212usize),
)
}
}
#[doc = "ADC measurement"]
#[inline(always)]
pub const fn adc_res(
&self,
) -> &'static crate::common::Reg<self::AdcRes_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::AdcRes_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(224usize),
)
}
}
#[doc = "CSD Interrupt Request Register"]
#[inline(always)]
pub const fn intr(&self) -> &'static crate::common::Reg<self::Intr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Intr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(240usize),
)
}
}
#[doc = "CSD Interrupt set register"]
#[inline(always)]
pub const fn intr_set(
&self,
) -> &'static crate::common::Reg<self::IntrSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(244usize),
)
}
}
#[doc = "CSD Interrupt mask register"]
#[inline(always)]
pub const fn intr_mask(
&self,
) -> &'static crate::common::Reg<self::IntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(248usize),
)
}
}
#[doc = "CSD Interrupt masked register"]
#[inline(always)]
pub const fn intr_masked(
&self,
) -> &'static crate::common::Reg<self::IntrMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(252usize),
)
}
}
#[doc = "High Speed Comparator configuration"]
#[inline(always)]
pub const fn hscmp(&self) -> &'static crate::common::Reg<self::Hscmp_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Hscmp_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(384usize),
)
}
}
#[doc = "Reference Generator configuration"]
#[inline(always)]
pub const fn ambuf(&self) -> &'static crate::common::Reg<self::Ambuf_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Ambuf_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(388usize),
)
}
}
#[doc = "Reference Generator configuration"]
#[inline(always)]
pub const fn refgen(
&self,
) -> &'static crate::common::Reg<self::Refgen_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Refgen_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(392usize),
)
}
}
#[doc = "CSD Comparator configuration"]
#[inline(always)]
pub const fn csdcmp(
&self,
) -> &'static crate::common::Reg<self::Csdcmp_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Csdcmp_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(396usize),
)
}
}
#[doc = "Switch Resistance configuration"]
#[inline(always)]
pub const fn sw_res(&self) -> &'static crate::common::Reg<self::SwRes_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SwRes_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(496usize),
)
}
}
#[doc = "Sense clock period"]
#[inline(always)]
pub const fn sense_period(
&self,
) -> &'static crate::common::Reg<self::SensePeriod_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SensePeriod_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(512usize),
)
}
}
#[doc = "Sense clock duty cycle"]
#[inline(always)]
pub const fn sense_duty(
&self,
) -> &'static crate::common::Reg<self::SenseDuty_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SenseDuty_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(516usize),
)
}
}
#[doc = "HSCMP Pos input switch Waveform selection"]
#[inline(always)]
pub const fn sw_hs_p_sel(
&self,
) -> &'static crate::common::Reg<self::SwHsPSel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SwHsPSel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(640usize),
)
}
}
#[doc = "HSCMP Neg input switch Waveform selection"]
#[inline(always)]
pub const fn sw_hs_n_sel(
&self,
) -> &'static crate::common::Reg<self::SwHsNSel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SwHsNSel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(644usize),
)
}
}
#[doc = "Shielding switches Waveform selection"]
#[inline(always)]
pub const fn sw_shield_sel(
&self,
) -> &'static crate::common::Reg<self::SwShieldSel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SwShieldSel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(648usize),
)
}
}
#[doc = "Amuxbuffer switches Waveform selection"]
#[inline(always)]
pub const fn sw_amuxbuf_sel(
&self,
) -> &'static crate::common::Reg<self::SwAmuxbufSel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SwAmuxbufSel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(656usize),
)
}
}
#[doc = "AMUXBUS bypass switches Waveform selection"]
#[inline(always)]
pub const fn sw_byp_sel(
&self,
) -> &'static crate::common::Reg<self::SwBypSel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SwBypSel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(660usize),
)
}
}
#[doc = "CSDCMP Pos Switch Waveform selection"]
#[inline(always)]
pub const fn sw_cmp_p_sel(
&self,
) -> &'static crate::common::Reg<self::SwCmpPSel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SwCmpPSel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(672usize),
)
}
}
#[doc = "CSDCMP Neg Switch Waveform selection"]
#[inline(always)]
pub const fn sw_cmp_n_sel(
&self,
) -> &'static crate::common::Reg<self::SwCmpNSel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SwCmpNSel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(676usize),
)
}
}
#[doc = "Reference Generator Switch Waveform selection"]
#[inline(always)]
pub const fn sw_refgen_sel(
&self,
) -> &'static crate::common::Reg<self::SwRefgenSel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SwRefgenSel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(680usize),
)
}
}
#[doc = "Full Wave Cmod Switch Waveform selection"]
#[inline(always)]
pub const fn sw_fw_mod_sel(
&self,
) -> &'static crate::common::Reg<self::SwFwModSel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SwFwModSel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(688usize),
)
}
}
#[doc = "Full Wave Csh_tank Switch Waveform selection"]
#[inline(always)]
pub const fn sw_fw_tank_sel(
&self,
) -> &'static crate::common::Reg<self::SwFwTankSel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SwFwTankSel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(692usize),
)
}
}
#[doc = "DSI output switch control Waveform selection"]
#[inline(always)]
pub const fn sw_dsi_sel(
&self,
) -> &'static crate::common::Reg<self::SwDsiSel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SwDsiSel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(704usize),
)
}
}
#[doc = "IO output control Waveform selection"]
#[inline(always)]
pub const fn io_sel(&self) -> &'static crate::common::Reg<self::IoSel_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IoSel_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(720usize),
)
}
}
#[doc = "Sequencer Timing"]
#[inline(always)]
pub const fn seq_time(
&self,
) -> &'static crate::common::Reg<self::SeqTime_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SeqTime_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(768usize),
)
}
}
#[doc = "Sequencer Initial conversion and sample counts"]
#[inline(always)]
pub const fn seq_init_cnt(
&self,
) -> &'static crate::common::Reg<self::SeqInitCnt_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SeqInitCnt_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(784usize),
)
}
}
#[doc = "Sequencer Normal conversion and sample counts"]
#[inline(always)]
pub const fn seq_norm_cnt(
&self,
) -> &'static crate::common::Reg<self::SeqNormCnt_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SeqNormCnt_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(788usize),
)
}
}
#[doc = "ADC Control"]
#[inline(always)]
pub const fn adc_ctl(
&self,
) -> &'static crate::common::Reg<self::AdcCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::AdcCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(800usize),
)
}
}
#[doc = "Sequencer start"]
#[inline(always)]
pub const fn seq_start(
&self,
) -> &'static crate::common::Reg<self::SeqStart_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SeqStart_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(832usize),
)
}
}
#[doc = "IDACA Configuration"]
#[inline(always)]
pub const fn idaca(&self) -> &'static crate::common::Reg<self::Idaca_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Idaca_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1024usize),
)
}
}
#[doc = "IDACB Configuration"]
#[inline(always)]
pub const fn idacb(&self) -> &'static crate::common::Reg<self::Idacb_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Idacb_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1280usize),
)
}
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Config_SPEC;
impl crate::sealed::RegSpec for Config_SPEC {
type DataType = u32;
}
#[doc = "Configuration and Control"]
pub type Config = crate::RegValueT<Config_SPEC>;
impl Config {
#[doc = "N/A"]
#[inline(always)]
pub fn iref_sel(
self,
) -> crate::common::RegisterField<
0,
0x1,
1,
0,
config::IrefSel,
config::IrefSel,
Config_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1,
1,
0,
config::IrefSel,
config::IrefSel,
Config_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Enables the digital filtering on the CSD comparator"]
#[inline(always)]
pub fn filter_delay(
self,
) -> crate::common::RegisterField<4, 0x1f, 1, 0, u8, u8, Config_SPEC, crate::common::RW> {
crate::common::RegisterField::<4,0x1f,1,0,u8,u8,Config_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Configures the delay between shield clock and sensor clock"]
#[inline(always)]
pub fn shield_delay(
self,
) -> crate::common::RegisterField<
10,
0x3,
1,
0,
config::ShieldDelay,
config::ShieldDelay,
Config_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
10,
0x3,
1,
0,
config::ShieldDelay,
config::ShieldDelay,
Config_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Enables the sensor and shield clocks, CSD modulator output and turns on the IDAC compensation current as selected by CSD_IDAC."]
#[inline(always)]
pub fn sense_en(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, Config_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12, 1, 0, Config_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn full_wave(
self,
) -> crate::common::RegisterField<
17,
0x1,
1,
0,
config::FullWave,
config::FullWave,
Config_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
17,
0x1,
1,
0,
config::FullWave,
config::FullWave,
Config_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mutual_cap(
self,
) -> crate::common::RegisterField<
18,
0x1,
1,
0,
config::MutualCap,
config::MutualCap,
Config_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
18,
0x1,
1,
0,
config::MutualCap,
config::MutualCap,
Config_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn csx_dual_cnt(
self,
) -> crate::common::RegisterField<
19,
0x1,
1,
0,
config::CsxDualCnt,
config::CsxDualCnt,
Config_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
19,
0x1,
1,
0,
config::CsxDualCnt,
config::CsxDualCnt,
Config_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn dsi_count_sel(
self,
) -> crate::common::RegisterField<
24,
0x1,
1,
0,
config::DsiCountSel,
config::DsiCountSel,
Config_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
24,
0x1,
1,
0,
config::DsiCountSel,
config::DsiCountSel,
Config_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "DSI_SAMPLE_EN = 1 -> COUNTER will count the samples generated by DSI\nDSI_SAMPLE_EN = 0 -> COUNTER will count the samples generated by CSD modulator"]
#[inline(always)]
pub fn dsi_sample_en(
self,
) -> crate::common::RegisterFieldBool<25, 1, 0, Config_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<25, 1, 0, Config_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn sample_sync(
self,
) -> crate::common::RegisterFieldBool<26, 1, 0, Config_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<26, 1, 0, Config_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "DSI_SENSE_EN = 1-> sensor clock is driven directly by DSI\nDSI_SENSE_EN = 0-> sensor clock is driven by PRS/divide-by-2/DIRECT_CLOCK"]
#[inline(always)]
pub fn dsi_sense_en(
self,
) -> crate::common::RegisterFieldBool<27, 1, 0, Config_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<27, 1, 0, Config_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn lp_mode(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, Config_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30, 1, 0, Config_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enable(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Config_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31, 1, 0, Config_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Config {
#[inline(always)]
fn default() -> Config {
<crate::RegValueT<Config_SPEC> as RegisterValue<_>>::new(67108864)
}
}
pub mod config {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct IrefSel_SPEC;
pub type IrefSel = crate::EnumBitfieldStruct<u8, IrefSel_SPEC>;
impl IrefSel {
#[doc = "select SRSS Iref (default)"]
pub const IREF_SRSS: Self = Self::new(0);
#[doc = "select PASS.AREF Iref, only available if PASS IP is on the chip."]
pub const IREF_PASS: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ShieldDelay_SPEC;
pub type ShieldDelay = crate::EnumBitfieldStruct<u8, ShieldDelay_SPEC>;
impl ShieldDelay {
#[doc = "Delay line is off, csd_shield=csd_sense"]
pub const OFF: Self = Self::new(0);
#[doc = "Introduces a 5ns delay (typ)"]
pub const D_5_NS: Self = Self::new(1);
#[doc = "Introduces a 10ns delay (typ)"]
pub const D_10_NS: Self = Self::new(2);
#[doc = "Introduces a 20ns delay (typ)"]
pub const D_20_NS: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct FullWave_SPEC;
pub type FullWave = crate::EnumBitfieldStruct<u8, FullWave_SPEC>;
impl FullWave {
#[doc = "Half Wave mode (normal).\nIn this mode the comparator always trips in the same direction (positive or negative edge) and the same Vref, i.e. no polarity change."]
pub const HALFWAVE: Self = Self::new(0);
#[doc = "Full Wave mode.\nIn this mode the comparator trips in opposite direction and with different Vref in each phase, i.e. the polarity flips."]
pub const FULLWAVE: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct MutualCap_SPEC;
pub type MutualCap = crate::EnumBitfieldStruct<u8, MutualCap_SPEC>;
impl MutualCap {
#[doc = "Self-cap mode (configure sense line as CSD_SENSE)"]
pub const SELFCAP: Self = Self::new(0);
#[doc = "Mutual-cap mode (configure Tx line as CSD_SENSE, inverted Tx line as CSD_SHIELD and Rx Line as AMUXA). In this mode the polarity bit of the IDAC is controlled by csd_sense."]
pub const MUTUALCAP: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CsxDualCnt_SPEC;
pub type CsxDualCnt = crate::EnumBitfieldStruct<u8, CsxDualCnt_SPEC>;
impl CsxDualCnt {
#[doc = "Use one counter for both phases (source and sink)."]
pub const ONE: Self = Self::new(0);
#[doc = "Use two counters, separate count for when csd_sense is high and when csd_sense is low."]
pub const TWO: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DsiCountSel_SPEC;
pub type DsiCountSel = crate::EnumBitfieldStruct<u8, DsiCountSel_SPEC>;
impl DsiCountSel {
#[doc = "depending on the dsi_count_val_sel input either output RESULT_VAL1.VALUE (0) or RESULT_VAL2.VALUE (1) on the dsi_count bus. Note that dsi_count_val_sel is not synchronized, i.e. it controls the mux combinatorially."]
pub const CSD_RESULT: Self = Self::new(0);
#[doc = "output ADC_RES.VIN_CNT on the dsi_count bus"]
pub const ADC_RESULT: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Spare_SPEC;
impl crate::sealed::RegSpec for Spare_SPEC {
type DataType = u32;
}
#[doc = "Spare MMIO"]
pub type Spare = crate::RegValueT<Spare_SPEC>;
impl Spare {
#[doc = "Spare MMIO"]
#[inline(always)]
pub fn spare(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, Spare_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0xf,1,0,u8,u8,Spare_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Spare {
#[inline(always)]
fn default() -> Spare {
<crate::RegValueT<Spare_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Status_SPEC;
impl crate::sealed::RegSpec for Status_SPEC {
type DataType = u32;
}
#[doc = "Status Register"]
pub type Status = crate::RegValueT<Status_SPEC>;
impl Status {
#[doc = "Only for Debug/test purpose this internal signal (sensor clock) status can be read by CPU"]
#[inline(always)]
pub fn csd_sense(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1, 1, 0, Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Only for Debug/test purpose the output status of CSD comparator can be read by CPU"]
#[inline(always)]
pub fn hscmp_out(
self,
) -> crate::common::RegisterField<
2,
0x1,
1,
0,
status::HscmpOut,
status::HscmpOut,
Status_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
2,
0x1,
1,
0,
status::HscmpOut,
status::HscmpOut,
Status_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "Only for Debug/test purpose the output status of CSD modulator can be read by CPU"]
#[inline(always)]
pub fn csdcmp_out(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3, 1, 0, Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Status {
#[inline(always)]
fn default() -> Status {
<crate::RegValueT<Status_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod status {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct HscmpOut_SPEC;
pub type HscmpOut = crate::EnumBitfieldStruct<u8, HscmpOut_SPEC>;
impl HscmpOut {
#[doc = "Vin < Vref"]
pub const C_LT_VREF: Self = Self::new(0);
#[doc = "Vin > Vref"]
pub const C_GT_VREF: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct StatSeq_SPEC;
impl crate::sealed::RegSpec for StatSeq_SPEC {
type DataType = u32;
}
#[doc = "Current Sequencer status"]
pub type StatSeq = crate::RegValueT<StatSeq_SPEC>;
impl StatSeq {
#[doc = "CSD sequencer state"]
#[inline(always)]
pub fn seq_state(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, StatSeq_SPEC, crate::common::R> {
crate::common::RegisterField::<0,0x7,1,0,u8,u8,StatSeq_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "ADC sequencer state (only relevant after SEQ_STATE has reached SAMPLE_NORM and ADC sequencer has started)"]
#[inline(always)]
pub fn adc_state(
self,
) -> crate::common::RegisterField<16, 0x7, 1, 0, u8, u8, StatSeq_SPEC, crate::common::R> {
crate::common::RegisterField::<16,0x7,1,0,u8,u8,StatSeq_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for StatSeq {
#[inline(always)]
fn default() -> StatSeq {
<crate::RegValueT<StatSeq_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct StatCnts_SPEC;
impl crate::sealed::RegSpec for StatCnts_SPEC {
type DataType = u32;
}
#[doc = "Current status counts"]
pub type StatCnts = crate::RegValueT<StatCnts_SPEC>;
impl StatCnts {
#[doc = "Current number of conversions remaining when in Sample_* states (note that in AutoZero* states the same down counter is reused to count the cycles)"]
#[inline(always)]
pub fn num_conv(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, StatCnts_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,StatCnts_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for StatCnts {
#[inline(always)]
fn default() -> StatCnts {
<crate::RegValueT<StatCnts_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct StatHcnt_SPEC;
impl crate::sealed::RegSpec for StatHcnt_SPEC {
type DataType = u32;
}
#[doc = "Current count of the HSCMP counter"]
pub type StatHcnt = crate::RegValueT<StatHcnt_SPEC>;
impl StatHcnt {
#[doc = "Current value of HSCMP counter"]
#[inline(always)]
pub fn cnt(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, StatHcnt_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,StatHcnt_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for StatHcnt {
#[inline(always)]
fn default() -> StatHcnt {
<crate::RegValueT<StatHcnt_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ResultVal1_SPEC;
impl crate::sealed::RegSpec for ResultVal1_SPEC {
type DataType = u32;
}
#[doc = "Result CSD/CSX accumulation counter value 1"]
pub type ResultVal1 = crate::RegValueT<ResultVal1_SPEC>;
impl ResultVal1 {
#[doc = "Accumulated counter value for this result. In case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt) this counter counts when csd_sense is high."]
#[inline(always)]
pub fn value(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, ResultVal1_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,ResultVal1_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Number of \'bad\' conversion for which the CSD comparator did not trigger within the normal time window, either because Vref was not crossed at all, or if the Vref was already crossed before the window started. This counter is reset when the sequencer is started and will saturate at 255 when more than 255 conversions are bad."]
#[inline(always)]
pub fn bad_convs(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, ResultVal1_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,ResultVal1_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for ResultVal1 {
#[inline(always)]
fn default() -> ResultVal1 {
<crate::RegValueT<ResultVal1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ResultVal2_SPEC;
impl crate::sealed::RegSpec for ResultVal2_SPEC {
type DataType = u32;
}
#[doc = "Result CSX accumulation counter value 2"]
pub type ResultVal2 = crate::RegValueT<ResultVal2_SPEC>;
impl ResultVal2 {
#[doc = "Only used in case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt), this counter counts when csd_sense is low."]
#[inline(always)]
pub fn value(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, ResultVal2_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,ResultVal2_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for ResultVal2 {
#[inline(always)]
fn default() -> ResultVal2 {
<crate::RegValueT<ResultVal2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AdcRes_SPEC;
impl crate::sealed::RegSpec for AdcRes_SPEC {
type DataType = u32;
}
#[doc = "ADC measurement"]
pub type AdcRes = crate::RegValueT<AdcRes_SPEC>;
impl AdcRes {
#[doc = "Count to source/sink Cref1 + Cref2 from Vin to Vrefhi."]
#[inline(always)]
pub fn vin_cnt(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, AdcRes_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,AdcRes_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Polarity used for IDACB for this last ADC result, 0= source, 1= sink"]
#[inline(always)]
pub fn hscmp_pol(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, AdcRes_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16, 1, 0, AdcRes_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "This flag is set when the ADC counter overflows. This is an indication to the firmware that the IDACB current level is too low."]
#[inline(always)]
pub fn adc_overflow(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, AdcRes_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<30, 1, 0, AdcRes_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "This flag is set when the ADC sequencer was aborted before tripping HSCMP."]
#[inline(always)]
pub fn adc_abort(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, AdcRes_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31, 1, 0, AdcRes_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for AdcRes {
#[inline(always)]
fn default() -> AdcRes {
<crate::RegValueT<AdcRes_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Intr_SPEC;
impl crate::sealed::RegSpec for Intr_SPEC {
type DataType = u32;
}
#[doc = "CSD Interrupt Request Register"]
pub type Intr = crate::RegValueT<Intr_SPEC>;
impl Intr {
#[doc = "A normal sample is complete"]
#[inline(always)]
pub fn sample(self) -> crate::common::RegisterFieldBool<1, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Coarse initialization complete or Sample initialization complete (the latter is typically ignored)"]
#[inline(always)]
pub fn init(self) -> crate::common::RegisterFieldBool<2, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "ADC Result ready"]
#[inline(always)]
pub fn adc_res(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Intr {
#[inline(always)]
fn default() -> Intr {
<crate::RegValueT<Intr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSet_SPEC;
impl crate::sealed::RegSpec for IntrSet_SPEC {
type DataType = u32;
}
#[doc = "CSD Interrupt set register"]
pub type IntrSet = crate::RegValueT<IntrSet_SPEC>;
impl IntrSet {
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn sample(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn init(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn adc_res(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for IntrSet {
#[inline(always)]
fn default() -> IntrSet {
<crate::RegValueT<IntrSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMask_SPEC;
impl crate::sealed::RegSpec for IntrMask_SPEC {
type DataType = u32;
}
#[doc = "CSD Interrupt mask register"]
pub type IntrMask = crate::RegValueT<IntrMask_SPEC>;
impl IntrMask {
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn sample(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn init(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn adc_res(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for IntrMask {
#[inline(always)]
fn default() -> IntrMask {
<crate::RegValueT<IntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMasked_SPEC;
impl crate::sealed::RegSpec for IntrMasked_SPEC {
type DataType = u32;
}
#[doc = "CSD Interrupt masked register"]
pub type IntrMasked = crate::RegValueT<IntrMasked_SPEC>;
impl IntrMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn sample(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn init(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn adc_res(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMasked {
#[inline(always)]
fn default() -> IntrMasked {
<crate::RegValueT<IntrMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Hscmp_SPEC;
impl crate::sealed::RegSpec for Hscmp_SPEC {
type DataType = u32;
}
#[doc = "High Speed Comparator configuration"]
pub type Hscmp = crate::RegValueT<Hscmp_SPEC>;
impl Hscmp {
#[doc = "High Speed Comparator enable"]
#[inline(always)]
pub fn hscmp_en(
self,
) -> crate::common::RegisterField<
0,
0x1,
1,
0,
hscmp::HscmpEn,
hscmp::HscmpEn,
Hscmp_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1,
1,
0,
hscmp::HscmpEn,
hscmp::HscmpEn,
Hscmp_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Invert the HSCMP output before it is used to control switches and the CSD sequencer. This bit does not affect the ADC sequencer or the STATUS.HSCMP_OUT"]
#[inline(always)]
pub fn hscmp_invert(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Hscmp_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, Hscmp_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Auto-Zero enable, allow the Sequencer to Auto-Zero this component"]
#[inline(always)]
pub fn az_en(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Hscmp_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31, 1, 0, Hscmp_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Hscmp {
#[inline(always)]
fn default() -> Hscmp {
<crate::RegValueT<Hscmp_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod hscmp {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct HscmpEn_SPEC;
pub type HscmpEn = crate::EnumBitfieldStruct<u8, HscmpEn_SPEC>;
impl HscmpEn {
#[doc = "Disable comparator, output is zero"]
pub const OFF: Self = Self::new(0);
#[doc = "On, regular operation. Note that CONFIG.LP_MODE determines the power mode level"]
pub const ON: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ambuf_SPEC;
impl crate::sealed::RegSpec for Ambuf_SPEC {
type DataType = u32;
}
#[doc = "Reference Generator configuration"]
pub type Ambuf = crate::RegValueT<Ambuf_SPEC>;
impl Ambuf {
#[doc = "Amux buffer power level"]
#[inline(always)]
pub fn pwr_mode(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
ambuf::PwrMode,
ambuf::PwrMode,
Ambuf_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
ambuf::PwrMode,
ambuf::PwrMode,
Ambuf_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Ambuf {
#[inline(always)]
fn default() -> Ambuf {
<crate::RegValueT<Ambuf_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod ambuf {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PwrMode_SPEC;
pub type PwrMode = crate::EnumBitfieldStruct<u8, PwrMode_SPEC>;
impl PwrMode {
#[doc = "Disable buffer"]
pub const OFF: Self = Self::new(0);
#[doc = "On, normal or low power level depending on CONFIG.LP_MODE."]
pub const NORM: Self = Self::new(1);
#[doc = "On, high or low power level depending on CONFIG.LP_MODE."]
pub const HI: Self = Self::new(2);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Refgen_SPEC;
impl crate::sealed::RegSpec for Refgen_SPEC {
type DataType = u32;
}
#[doc = "Reference Generator configuration"]
pub type Refgen = crate::RegValueT<Refgen_SPEC>;
impl Refgen {
#[doc = "Reference Generator Enable"]
#[inline(always)]
pub fn refgen_en(
self,
) -> crate::common::RegisterField<
0,
0x1,
1,
0,
refgen::RefgenEn,
refgen::RefgenEn,
Refgen_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1,
1,
0,
refgen::RefgenEn,
refgen::RefgenEn,
Refgen_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Bypass selected input reference unbuffered to Vrefhi"]
#[inline(always)]
pub fn bypass(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Refgen_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, Refgen_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Close Vdda switch to top of resistor string (or Vrefhi?)"]
#[inline(always)]
pub fn vdda_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Refgen_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, Refgen_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Resistor string enable; 0= open switch on top of the resistor string (Vreflo=Vssa)"]
#[inline(always)]
pub fn res_en(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, Refgen_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, Refgen_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Select resistor string tap for feedback, 0= minimum vout, 31= maximum vout = vrefhi -> gain=1 (only works if the resistor string is enabled; RES_EN=1)"]
#[inline(always)]
pub fn gain(
self,
) -> crate::common::RegisterField<8, 0x1f, 1, 0, u8, u8, Refgen_SPEC, crate::common::RW> {
crate::common::RegisterField::<8,0x1f,1,0,u8,u8,Refgen_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select resistor string tap for Vreflo/Vreflo_int, 0= minimum vout, 31= maximum vout = vrefhi (only works if the resistor string is enabled; RES_EN=1)"]
#[inline(always)]
pub fn vreflo_sel(
self,
) -> crate::common::RegisterField<16, 0x1f, 1, 0, u8, u8, Refgen_SPEC, crate::common::RW> {
crate::common::RegisterField::<16,0x1f,1,0,u8,u8,Refgen_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Ouput the resistor string tap either to Vreflo (0) or Vreflo_int (1)."]
#[inline(always)]
pub fn vreflo_int(
self,
) -> crate::common::RegisterFieldBool<23, 1, 0, Refgen_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<23, 1, 0, Refgen_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Refgen {
#[inline(always)]
fn default() -> Refgen {
<crate::RegValueT<Refgen_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod refgen {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct RefgenEn_SPEC;
pub type RefgenEn = crate::EnumBitfieldStruct<u8, RefgenEn_SPEC>;
impl RefgenEn {
#[doc = "Disable Reference Generator"]
pub const OFF: Self = Self::new(0);
#[doc = "On, regular operation. Note that CONFIG.LP_MODE determines the power mode level"]
pub const ON: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Csdcmp_SPEC;
impl crate::sealed::RegSpec for Csdcmp_SPEC {
type DataType = u32;
}
#[doc = "CSD Comparator configuration"]
pub type Csdcmp = crate::RegValueT<Csdcmp_SPEC>;
impl Csdcmp {
#[doc = "CSD Comparator Enable"]
#[inline(always)]
pub fn csdcmp_en(
self,
) -> crate::common::RegisterField<
0,
0x1,
1,
0,
csdcmp::CsdcmpEn,
csdcmp::CsdcmpEn,
Csdcmp_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1,
1,
0,
csdcmp::CsdcmpEn,
csdcmp::CsdcmpEn,
Csdcmp_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Select which IDAC polarity to use to detect CSDCMP triggering"]
#[inline(always)]
pub fn polarity_sel(
self,
) -> crate::common::RegisterField<
4,
0x3,
1,
0,
csdcmp::PolaritySel,
csdcmp::PolaritySel,
Csdcmp_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x3,
1,
0,
csdcmp::PolaritySel,
csdcmp::PolaritySel,
Csdcmp_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Select in what phase(s) the comparator is active, typically set to match the BAL_MODE of the used IDAC. Note, this also determines when a bad conversion is detected, namely at the beginning and end of the comparator active phase (also taking into account FILTER_DELAY and non-overlap)."]
#[inline(always)]
pub fn cmp_phase(
self,
) -> crate::common::RegisterField<
8,
0x3,
1,
0,
csdcmp::CmpPhase,
csdcmp::CmpPhase,
Csdcmp_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0x3,
1,
0,
csdcmp::CmpPhase,
csdcmp::CmpPhase,
Csdcmp_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Select which signal to output on dsi_sample_out."]
#[inline(always)]
pub fn cmp_mode(
self,
) -> crate::common::RegisterField<
28,
0x1,
1,
0,
csdcmp::CmpMode,
csdcmp::CmpMode,
Csdcmp_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
28,
0x1,
1,
0,
csdcmp::CmpMode,
csdcmp::CmpMode,
Csdcmp_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This bit controls whether the output directly from the comparator (csdcmp_out) or the flopped version (csdcmp_out_ff) is used. For CSD operation, the selected signal controls the IDAC(s), in GP mode the signal goes out on dsi_sample_out."]
#[inline(always)]
pub fn feedback_mode(
self,
) -> crate::common::RegisterField<
29,
0x1,
1,
0,
csdcmp::FeedbackMode,
csdcmp::FeedbackMode,
Csdcmp_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
29,
0x1,
1,
0,
csdcmp::FeedbackMode,
csdcmp::FeedbackMode,
Csdcmp_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Auto-Zero enable, allow the Sequencer to Auto-Zero this component"]
#[inline(always)]
pub fn az_en(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Csdcmp_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31, 1, 0, Csdcmp_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Csdcmp {
#[inline(always)]
fn default() -> Csdcmp {
<crate::RegValueT<Csdcmp_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod csdcmp {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CsdcmpEn_SPEC;
pub type CsdcmpEn = crate::EnumBitfieldStruct<u8, CsdcmpEn_SPEC>;
impl CsdcmpEn {
#[doc = "Disable comparator, output is zero"]
pub const OFF: Self = Self::new(0);
#[doc = "On, regular operation. Note that CONFIG.LP_MODE determines the power mode level"]
pub const ON: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PolaritySel_SPEC;
pub type PolaritySel = crate::EnumBitfieldStruct<u8, PolaritySel_SPEC>;
impl PolaritySel {
#[doc = "Use idaca_pol (firmware setting with CSX and optionally DSI mixed in) to determine the direction, this is the most common use-case, used for normal CSD and normal CSX"]
pub const IDACA_POL: Self = Self::new(0);
#[doc = "Use idacb_pol (firmware setting with optional DSI mixed in) to determine the direction, this is only used for normal CSD if IDACB is used i.s.o. IDACA (not common)"]
pub const IDACB_POL: Self = Self::new(1);
#[doc = "Use the expression (csd_sense ? idaca_pol : idacb_pol) to determine the direction, this is only useful for the CSX with DUAL_IDAC use-case"]
pub const DUAL_POL: Self = Self::new(2);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CmpPhase_SPEC;
pub type CmpPhase = crate::EnumBitfieldStruct<u8, CmpPhase_SPEC>;
impl CmpPhase {
#[doc = "Comparator is active from start of Phi2 and kept active into Phi1. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off)"]
pub const FULL: Self = Self::new(0);
#[doc = "Comparator is active during Phi1 only. Currently no known use-case."]
pub const PHI_1: Self = Self::new(1);
#[doc = "Comparator is active during Phi2 only. Intended usage: CSD Low EMI."]
pub const PHI_2: Self = Self::new(2);
#[doc = "Comparator is activated at the start of both Phi1 and Phi2 (non-overlap should be enabled). Intended usage: CSX, or Full-Wave."]
pub const PHI_1_2: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct CmpMode_SPEC;
pub type CmpMode = crate::EnumBitfieldStruct<u8, CmpMode_SPEC>;
impl CmpMode {
#[doc = "CSD mode: output the filtered sample signal on dsi_sample_out"]
pub const CSD: Self = Self::new(0);
#[doc = "General Purpose mode: output the unfiltered sample unfiltered comparator output, either asynchronous or flopped."]
pub const GP: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct FeedbackMode_SPEC;
pub type FeedbackMode = crate::EnumBitfieldStruct<u8, FeedbackMode_SPEC>;
impl FeedbackMode {
#[doc = "Use feedback from sampling flip-flop (used in most modes)."]
pub const FLOP: Self = Self::new(0);
#[doc = "Use feedback from comparator directly (used in single Cmod mutual cap sensing only)"]
pub const COMP: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SwRes_SPEC;
impl crate::sealed::RegSpec for SwRes_SPEC {
type DataType = u32;
}
#[doc = "Switch Resistance configuration"]
pub type SwRes = crate::RegValueT<SwRes_SPEC>;
impl SwRes {
#[doc = "Select resistance or low EMI (slow ramp) for the HCAV switch"]
#[inline(always)]
pub fn res_hcav(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
sw_res::ResHcav,
sw_res::ResHcav,
SwRes_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
sw_res::ResHcav,
sw_res::ResHcav,
SwRes_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Select resistance or low EMI for the corresponding switch"]
#[inline(always)]
pub fn res_hcag(
self,
) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, SwRes_SPEC, crate::common::RW> {
crate::common::RegisterField::<2,0x3,1,0,u8,u8,SwRes_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select resistance or low EMI for the corresponding switch"]
#[inline(always)]
pub fn res_hcbv(
self,
) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, SwRes_SPEC, crate::common::RW> {
crate::common::RegisterField::<4,0x3,1,0,u8,u8,SwRes_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select resistance or low EMI for the corresponding switch"]
#[inline(always)]
pub fn res_hcbg(
self,
) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, SwRes_SPEC, crate::common::RW> {
crate::common::RegisterField::<6,0x3,1,0,u8,u8,SwRes_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select resistance for the corresponding switch"]
#[inline(always)]
pub fn res_f1pm(
self,
) -> crate::common::RegisterField<
16,
0x3,
1,
0,
sw_res::ResF1Pm,
sw_res::ResF1Pm,
SwRes_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0x3,
1,
0,
sw_res::ResF1Pm,
sw_res::ResF1Pm,
SwRes_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Select resistance for the corresponding switch"]
#[inline(always)]
pub fn res_f2pt(
self,
) -> crate::common::RegisterField<18, 0x3, 1, 0, u8, u8, SwRes_SPEC, crate::common::RW> {
crate::common::RegisterField::<18,0x3,1,0,u8,u8,SwRes_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SwRes {
#[inline(always)]
fn default() -> SwRes {
<crate::RegValueT<SwRes_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod sw_res {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ResHcav_SPEC;
pub type ResHcav = crate::EnumBitfieldStruct<u8, ResHcav_SPEC>;
impl ResHcav {
#[doc = "Low"]
pub const LOW: Self = Self::new(0);
#[doc = "Medium"]
pub const MED: Self = Self::new(1);
#[doc = "High"]
pub const HIGH: Self = Self::new(2);
#[doc = "Low EMI (slow ramp: 3 switches closed by fixed delay line)"]
pub const LOWEMI: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ResF1Pm_SPEC;
pub type ResF1Pm = crate::EnumBitfieldStruct<u8, ResF1Pm_SPEC>;
impl ResF1Pm {
#[doc = "Low"]
pub const LOW: Self = Self::new(0);
#[doc = "Medium"]
pub const MED: Self = Self::new(1);
#[doc = "High"]
pub const HIGH: Self = Self::new(2);
#[doc = "N/A"]
pub const RSVD: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SensePeriod_SPEC;
impl crate::sealed::RegSpec for SensePeriod_SPEC {
type DataType = u32;
}
#[doc = "Sense clock period"]
pub type SensePeriod = crate::RegValueT<SensePeriod_SPEC>;
impl SensePeriod {
#[doc = "The length-1 of the Sense modulation \'clock\' period in clk_csd cycles. For regular CSD one sense clock cycle = one conversion (=phi1+phi2) .\nNote this is the base divider, clock dithering may change the actual period length.\nNote that SENSE_DIV must be at least 1 and additionally also allow for one clk_hf of non overlap (if OVERLAP_HI1/2 is set) on both phases, i.e. if clk_csd=clk_hf then SENSE_DIV must be >=3.\nIn addition the FILTER_DELAY needs to be added to the minimum allowed SENSE_DIV value."]
#[inline(always)]
pub fn sense_div(
self,
) -> crate::common::RegisterField<0, 0xfff, 1, 0, u16, u16, SensePeriod_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xfff,1,0,u16,u16,SensePeriod_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Selects the length of the LFSR which determines the LFSR repeat period. LFSR_BITS LSB of the LFSR are used for the clock dithering variation on the base period (was PRS in CSDv1). Whenever the LFSR is used (non zero value in this field) the LFSR_CLEAR bit should also be set."]
#[inline(always)]
pub fn lfsr_size(
self,
) -> crate::common::RegisterField<
16,
0x7,
1,
0,
sense_period::LfsrSize,
sense_period::LfsrSize,
SensePeriod_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0x7,
1,
0,
sense_period::LfsrSize,
sense_period::LfsrSize,
SensePeriod_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This dithering is disabled when SEL_LSFR_MSB is set.\nThe clock divider to be used = (SENSE_DIV+1) + (SEL_LSFR_MSB ? 0 : (LFSR_OUT<<LFSR_SCALE)).\nNote that the clock divider including the dithering term must fit in 12 bits, otherwise the result is undefined."]
#[inline(always)]
pub fn lfsr_scale(
self,
) -> crate::common::RegisterField<20, 0xf, 1, 0, u8, u8, SensePeriod_SPEC, crate::common::RW>
{
crate::common::RegisterField::<20,0xf,1,0,u8,u8,SensePeriod_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When set, forces the LFSR to it\'s initial state (all ones). This bit is automatically cleared by hardware after the LFSR is cleared, which is at the next clk_csd positive edge. This bit should be set whenever this register is written and the LFSR is used.\nNote that the LFSR will also get reset to all ones during the AutoZero_1/2 states."]
#[inline(always)]
pub fn lfsr_clear(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, SensePeriod_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,SensePeriod_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Use the MSB of configured LSFR size as csd_sense signal. Intended to be used only with bit 8 or 12-bit LFSR size for CSDv1 backward compatibility (PRS). When this bit is set then clock divider dithering is disabled and SENSE_WIDTH is disabled."]
#[inline(always)]
pub fn sel_lfsr_msb(
self,
) -> crate::common::RegisterFieldBool<25, 1, 0, SensePeriod_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<25,1,0,SensePeriod_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period.\nCaveat make sure that SENSE_DIV > the maximum absolute range (e.g. for 4B SENSE_DIV > 8), otherwise results are undefined."]
#[inline(always)]
pub fn lfsr_bits(
self,
) -> crate::common::RegisterField<
26,
0x3,
1,
0,
sense_period::LfsrBits,
sense_period::LfsrBits,
SensePeriod_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
26,
0x3,
1,
0,
sense_period::LfsrBits,
sense_period::LfsrBits,
SensePeriod_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for SensePeriod {
#[inline(always)]
fn default() -> SensePeriod {
<crate::RegValueT<SensePeriod_SPEC> as RegisterValue<_>>::new(201326592)
}
}
pub mod sense_period {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct LfsrSize_SPEC;
pub type LfsrSize = crate::EnumBitfieldStruct<u8, LfsrSize_SPEC>;
impl LfsrSize {
#[doc = "Don\'t use clock dithering (=spreadspectrum) (LFSR output value is zero)"]
pub const OFF: Self = Self::new(0);
#[doc = "6-bit LFSR (G(x)=X^6 +X^4+X^3+ X+1, period= 63)"]
pub const _6_B: Self = Self::new(1);
#[doc = "7-bit LFSR (G(x)=X^7 +X^4+X^3+X^2+1, period= 127)"]
pub const _7_B: Self = Self::new(2);
#[doc = "9-bit LFSR (G(x)=X^9 +X^4+X^3+ X+1, period= 511)"]
pub const _9_B: Self = Self::new(3);
#[doc = "10-bit LFSR (G(x)=X^10+X^4+X^3+ X+1, period= 1023)"]
pub const _10_B: Self = Self::new(4);
#[doc = "8-bit LFSR (G(x)=X^8+X^4+X^3+X^2+1, period= 255)"]
pub const _8_B: Self = Self::new(5);
#[doc = "12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1, period= 4095)"]
pub const _12_B: Self = Self::new(6);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct LfsrBits_SPEC;
pub type LfsrBits = crate::EnumBitfieldStruct<u8, LfsrBits_SPEC>;
impl LfsrBits {
#[doc = "use 2 bits: range = \\[-2,1\\]"]
pub const _2_B: Self = Self::new(0);
#[doc = "use 3 bits: range = \\[-4,3\\]"]
pub const _3_B: Self = Self::new(1);
#[doc = "use 4 bits: range = \\[-8,7\\]"]
pub const _4_B: Self = Self::new(2);
#[doc = "use 5 bits: range = \\[-16,15\\] (default)"]
pub const _5_B: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SenseDuty_SPEC;
impl crate::sealed::RegSpec for SenseDuty_SPEC {
type DataType = u32;
}
#[doc = "Sense clock duty cycle"]
pub type SenseDuty = crate::RegValueT<SenseDuty_SPEC>;
impl SenseDuty {
#[doc = "Defines the length of the first phase of the sense clock in clk_csd cycles. \nA value of 0 disables this feature and the duty cycle of csd_sense will be 50 percent, which is equal to SENSE_WIDTH = (SENSE_DIV+1)/2, or when clock dithering is used that becomes \\[(SENSE_DIV+1) + (LFSR_OUT << LSFR_SCALE)\\]/2. At all times it must be assured that the phases are at least 2 clk_csd cycles (1 for non overlap, if used), if this rule is violated the result is undefined.\nNote that this feature is not available when SEL_LFSR_MSB (PRS) is selected."]
#[inline(always)]
pub fn sense_width(
self,
) -> crate::common::RegisterField<0, 0xfff, 1, 0, u16, u16, SenseDuty_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xfff,1,0,u16,u16,SenseDuty_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Polarity of the sense clock\n0 = start with low phase (typical for regular negative transfer CSD)\n1 = start with high phase"]
#[inline(always)]
pub fn sense_pol(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, SenseDuty_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,SenseDuty_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "NonOverlap or not for Phi1 (csd_sense=0).\n0 = Non-overlap for Phi1, the Phi1 signal is csd_sense inverted except that the signal goes low 1 clk_sample before csd_sense goes high. Intended usage: new low EMI CSD/CSX with static GPIO.\n1 = \'Overlap\' (= not non-overlap) for Phi1, the Phi1 signal is csd_sense inverted. Intended usage: legacy CSD with GPIO switching, the GPIO internal circuit ensures that the switches are non-overlapping."]
#[inline(always)]
pub fn overlap_phi1(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, SenseDuty_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,SenseDuty_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Same as OVERLAP_PHI1 but for Phi2 (csd_sense=1)."]
#[inline(always)]
pub fn overlap_phi2(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, SenseDuty_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,SenseDuty_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SenseDuty {
#[inline(always)]
fn default() -> SenseDuty {
<crate::RegValueT<SenseDuty_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SwHsPSel_SPEC;
impl crate::sealed::RegSpec for SwHsPSel_SPEC {
type DataType = u32;
}
#[doc = "HSCMP Pos input switch Waveform selection"]
pub type SwHsPSel = crate::RegValueT<SwHsPSel_SPEC>;
impl SwHsPSel {
#[doc = "Set HMPM switch\n0: static open\n1: static closed"]
#[inline(always)]
pub fn sw_hmpm(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, SwHsPSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, SwHsPSel_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_hmpt(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, SwHsPSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, SwHsPSel_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_hmps(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, SwHsPSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, SwHsPSel_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_hmma(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, SwHsPSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,SwHsPSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_hmmb(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, SwHsPSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,SwHsPSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_hmca(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, SwHsPSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,SwHsPSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_hmcb(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, SwHsPSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,SwHsPSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_hmrh(
self,
) -> crate::common::RegisterFieldBool<28, 1, 0, SwHsPSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<28,1,0,SwHsPSel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SwHsPSel {
#[inline(always)]
fn default() -> SwHsPSel {
<crate::RegValueT<SwHsPSel_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SwHsNSel_SPEC;
impl crate::sealed::RegSpec for SwHsNSel_SPEC {
type DataType = u32;
}
#[doc = "HSCMP Neg input switch Waveform selection"]
pub type SwHsNSel = crate::RegValueT<SwHsNSel_SPEC>;
impl SwHsNSel {
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_hccc(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, SwHsNSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,SwHsNSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_hccd(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, SwHsNSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,SwHsNSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for corresponding switch"]
#[inline(always)]
pub fn sw_hcrh(
self,
) -> crate::common::RegisterField<24, 0x7, 1, 0, u8, u8, SwHsNSel_SPEC, crate::common::RW> {
crate::common::RegisterField::<24,0x7,1,0,u8,u8,SwHsNSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for corresponding switch"]
#[inline(always)]
pub fn sw_hcrl(
self,
) -> crate::common::RegisterField<28, 0x7, 1, 0, u8, u8, SwHsNSel_SPEC, crate::common::RW> {
crate::common::RegisterField::<28,0x7,1,0,u8,u8,SwHsNSel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SwHsNSel {
#[inline(always)]
fn default() -> SwHsNSel {
<crate::RegValueT<SwHsNSel_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SwShieldSel_SPEC;
impl crate::sealed::RegSpec for SwShieldSel_SPEC {
type DataType = u32;
}
#[doc = "Shielding switches Waveform selection"]
pub type SwShieldSel = crate::RegValueT<SwShieldSel_SPEC>;
impl SwShieldSel {
#[doc = "N/A"]
#[inline(always)]
pub fn sw_hcav(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, SwShieldSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,SwShieldSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for corresponding switch"]
#[inline(always)]
pub fn sw_hcag(
self,
) -> crate::common::RegisterField<4, 0x7, 1, 0, u8, u8, SwShieldSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0x7,1,0,u8,u8,SwShieldSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn sw_hcbv(
self,
) -> crate::common::RegisterField<8, 0x7, 1, 0, u8, u8, SwShieldSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x7,1,0,u8,u8,SwShieldSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for corresponding switch, using csd_shield as base"]
#[inline(always)]
pub fn sw_hcbg(
self,
) -> crate::common::RegisterField<12, 0x7, 1, 0, u8, u8, SwShieldSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<12,0x7,1,0,u8,u8,SwShieldSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_hccv(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, SwShieldSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,SwShieldSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch\nIf the ADC is enabled then this switch is directly controlled by the ADC sequencer."]
#[inline(always)]
pub fn sw_hccg(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, SwShieldSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,SwShieldSel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SwShieldSel {
#[inline(always)]
fn default() -> SwShieldSel {
<crate::RegValueT<SwShieldSel_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SwAmuxbufSel_SPEC;
impl crate::sealed::RegSpec for SwAmuxbufSel_SPEC {
type DataType = u32;
}
#[doc = "Amuxbuffer switches Waveform selection"]
pub type SwAmuxbufSel = crate::RegValueT<SwAmuxbufSel_SPEC>;
impl SwAmuxbufSel {
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_irby(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, SwAmuxbufSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,SwAmuxbufSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_irlb(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, SwAmuxbufSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,SwAmuxbufSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_ica(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, SwAmuxbufSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,SwAmuxbufSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for corresponding switch"]
#[inline(always)]
pub fn sw_icb(
self,
) -> crate::common::RegisterField<16, 0x7, 1, 0, u8, u8, SwAmuxbufSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x7,1,0,u8,u8,SwAmuxbufSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_irli(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, SwAmuxbufSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,SwAmuxbufSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_irh(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, SwAmuxbufSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,SwAmuxbufSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_irl(
self,
) -> crate::common::RegisterFieldBool<28, 1, 0, SwAmuxbufSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<28,1,0,SwAmuxbufSel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SwAmuxbufSel {
#[inline(always)]
fn default() -> SwAmuxbufSel {
<crate::RegValueT<SwAmuxbufSel_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SwBypSel_SPEC;
impl crate::sealed::RegSpec for SwBypSel_SPEC {
type DataType = u32;
}
#[doc = "AMUXBUS bypass switches Waveform selection"]
pub type SwBypSel = crate::RegValueT<SwBypSel_SPEC>;
impl SwBypSel {
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_bya(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, SwBypSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,SwBypSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_byb(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, SwBypSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,SwBypSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch\nIf the ADC is enabled then this switch is directly controlled by the ADC sequencer."]
#[inline(always)]
pub fn sw_cbcc(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, SwBypSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,SwBypSel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SwBypSel {
#[inline(always)]
fn default() -> SwBypSel {
<crate::RegValueT<SwBypSel_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SwCmpPSel_SPEC;
impl crate::sealed::RegSpec for SwCmpPSel_SPEC {
type DataType = u32;
}
#[doc = "CSDCMP Pos Switch Waveform selection"]
pub type SwCmpPSel = crate::RegValueT<SwCmpPSel_SPEC>;
impl SwCmpPSel {
#[doc = "Select waveform for corresponding switch"]
#[inline(always)]
pub fn sw_sfpm(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, SwCmpPSel_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0x7,1,0,u8,u8,SwCmpPSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for corresponding switch"]
#[inline(always)]
pub fn sw_sfpt(
self,
) -> crate::common::RegisterField<4, 0x7, 1, 0, u8, u8, SwCmpPSel_SPEC, crate::common::RW> {
crate::common::RegisterField::<4,0x7,1,0,u8,u8,SwCmpPSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for corresponding switch"]
#[inline(always)]
pub fn sw_sfps(
self,
) -> crate::common::RegisterField<8, 0x7, 1, 0, u8, u8, SwCmpPSel_SPEC, crate::common::RW> {
crate::common::RegisterField::<8,0x7,1,0,u8,u8,SwCmpPSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_sfma(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, SwCmpPSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,SwCmpPSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_sfmb(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, SwCmpPSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,SwCmpPSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_sfca(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, SwCmpPSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,SwCmpPSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_sfcb(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, SwCmpPSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,SwCmpPSel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SwCmpPSel {
#[inline(always)]
fn default() -> SwCmpPSel {
<crate::RegValueT<SwCmpPSel_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SwCmpNSel_SPEC;
impl crate::sealed::RegSpec for SwCmpNSel_SPEC {
type DataType = u32;
}
#[doc = "CSDCMP Neg Switch Waveform selection"]
pub type SwCmpNSel = crate::RegValueT<SwCmpNSel_SPEC>;
impl SwCmpNSel {
#[doc = "Select waveform for corresponding switch"]
#[inline(always)]
pub fn sw_scrh(
self,
) -> crate::common::RegisterField<24, 0x7, 1, 0, u8, u8, SwCmpNSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0x7,1,0,u8,u8,SwCmpNSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for corresponding switch"]
#[inline(always)]
pub fn sw_scrl(
self,
) -> crate::common::RegisterField<28, 0x7, 1, 0, u8, u8, SwCmpNSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<28,0x7,1,0,u8,u8,SwCmpNSel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SwCmpNSel {
#[inline(always)]
fn default() -> SwCmpNSel {
<crate::RegValueT<SwCmpNSel_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SwRefgenSel_SPEC;
impl crate::sealed::RegSpec for SwRefgenSel_SPEC {
type DataType = u32;
}
#[doc = "Reference Generator Switch Waveform selection"]
pub type SwRefgenSel = crate::RegValueT<SwRefgenSel_SPEC>;
impl SwRefgenSel {
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_iaib(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, SwRefgenSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,SwRefgenSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_ibcb(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, SwRefgenSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,SwRefgenSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_sgmb(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, SwRefgenSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,SwRefgenSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_sgrp(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, SwRefgenSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,SwRefgenSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_sgre(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, SwRefgenSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,SwRefgenSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_sgr(
self,
) -> crate::common::RegisterFieldBool<28, 1, 0, SwRefgenSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<28,1,0,SwRefgenSel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SwRefgenSel {
#[inline(always)]
fn default() -> SwRefgenSel {
<crate::RegValueT<SwRefgenSel_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SwFwModSel_SPEC;
impl crate::sealed::RegSpec for SwFwModSel_SPEC {
type DataType = u32;
}
#[doc = "Full Wave Cmod Switch Waveform selection"]
pub type SwFwModSel = crate::RegValueT<SwFwModSel_SPEC>;
impl SwFwModSel {
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_f1pm(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, SwFwModSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,SwFwModSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for corresponding switch"]
#[inline(always)]
pub fn sw_f1ma(
self,
) -> crate::common::RegisterField<8, 0x7, 1, 0, u8, u8, SwFwModSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x7,1,0,u8,u8,SwFwModSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for corresponding switch"]
#[inline(always)]
pub fn sw_f1ca(
self,
) -> crate::common::RegisterField<16, 0x7, 1, 0, u8, u8, SwFwModSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x7,1,0,u8,u8,SwFwModSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_c1cc(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, SwFwModSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,SwFwModSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_c1cd(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, SwFwModSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,SwFwModSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_c1f1(
self,
) -> crate::common::RegisterFieldBool<28, 1, 0, SwFwModSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<28,1,0,SwFwModSel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SwFwModSel {
#[inline(always)]
fn default() -> SwFwModSel {
<crate::RegValueT<SwFwModSel_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SwFwTankSel_SPEC;
impl crate::sealed::RegSpec for SwFwTankSel_SPEC {
type DataType = u32;
}
#[doc = "Full Wave Csh_tank Switch Waveform selection"]
pub type SwFwTankSel = crate::RegValueT<SwFwTankSel_SPEC>;
impl SwFwTankSel {
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_f2pt(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, SwFwTankSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,SwFwTankSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for corresponding switch"]
#[inline(always)]
pub fn sw_f2ma(
self,
) -> crate::common::RegisterField<8, 0x7, 1, 0, u8, u8, SwFwTankSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x7,1,0,u8,u8,SwFwTankSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for corresponding switch"]
#[inline(always)]
pub fn sw_f2ca(
self,
) -> crate::common::RegisterField<12, 0x7, 1, 0, u8, u8, SwFwTankSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<12,0x7,1,0,u8,u8,SwFwTankSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for corresponding switch"]
#[inline(always)]
pub fn sw_f2cb(
self,
) -> crate::common::RegisterField<16, 0x7, 1, 0, u8, u8, SwFwTankSel_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x7,1,0,u8,u8,SwFwTankSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_c2cc(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, SwFwTankSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,SwFwTankSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_c2cd(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, SwFwTankSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,SwFwTankSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Set corresponding switch"]
#[inline(always)]
pub fn sw_c2f2(
self,
) -> crate::common::RegisterFieldBool<28, 1, 0, SwFwTankSel_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<28,1,0,SwFwTankSel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SwFwTankSel {
#[inline(always)]
fn default() -> SwFwTankSel {
<crate::RegValueT<SwFwTankSel_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SwDsiSel_SPEC;
impl crate::sealed::RegSpec for SwDsiSel_SPEC {
type DataType = u32;
}
#[doc = "DSI output switch control Waveform selection"]
pub type SwDsiSel = crate::RegValueT<SwDsiSel_SPEC>;
impl SwDsiSel {
#[doc = "Select waveform for dsi_csh_tank output signal\n0: static open\n1: static closed\n2: phi1\n3: phi2\n4: phi1 & HSCMP\n5: phi2 & HSCMP\n6: HSCMP // ignores phi1/2\n7: !sense // = phi1 but ignores OVERLAP_PHI1\n\n8: phi1_delay // phi1 delayed with shield delay\n9: phi2_delay // phi2 delayed with shield delay\n\n10: !phi1\n11: !phi2\n12: !(phi1 & HSCMP)\n13: !(phi2 & HSCMP)\n14: !HSCMP // ignores phi1/2\n15: sense // = phi2 but ignores OVERLAP_PHI2"]
#[inline(always)]
pub fn dsi_csh_tank(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, SwDsiSel_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0xf,1,0,u8,u8,SwDsiSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for dsi_cmod output signal"]
#[inline(always)]
pub fn dsi_cmod(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, SwDsiSel_SPEC, crate::common::RW> {
crate::common::RegisterField::<4,0xf,1,0,u8,u8,SwDsiSel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SwDsiSel {
#[inline(always)]
fn default() -> SwDsiSel {
<crate::RegValueT<SwDsiSel_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IoSel_SPEC;
impl crate::sealed::RegSpec for IoSel_SPEC {
type DataType = u32;
}
#[doc = "IO output control Waveform selection"]
pub type IoSel = crate::RegValueT<IoSel_SPEC>;
impl IoSel {
#[doc = "Select waveform for csd_tx_out output signal"]
#[inline(always)]
pub fn csd_tx_out(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, IoSel_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0xf,1,0,u8,u8,IoSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for csd_tx_out_en output signal"]
#[inline(always)]
pub fn csd_tx_out_en(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, IoSel_SPEC, crate::common::RW> {
crate::common::RegisterField::<4,0xf,1,0,u8,u8,IoSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for csd_tx_amuxb_en output signal"]
#[inline(always)]
pub fn csd_tx_amuxb_en(
self,
) -> crate::common::RegisterField<12, 0xf, 1, 0, u8, u8, IoSel_SPEC, crate::common::RW> {
crate::common::RegisterField::<12,0xf,1,0,u8,u8,IoSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for csd_tx_n_out output signal"]
#[inline(always)]
pub fn csd_tx_n_out(
self,
) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, IoSel_SPEC, crate::common::RW> {
crate::common::RegisterField::<16,0xf,1,0,u8,u8,IoSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for csd_tx_n_out_en output signal"]
#[inline(always)]
pub fn csd_tx_n_out_en(
self,
) -> crate::common::RegisterField<20, 0xf, 1, 0, u8, u8, IoSel_SPEC, crate::common::RW> {
crate::common::RegisterField::<20,0xf,1,0,u8,u8,IoSel_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select waveform for csd_tx_n_amuxa_en output signal"]
#[inline(always)]
pub fn csd_tx_n_amuxa_en(
self,
) -> crate::common::RegisterField<24, 0xf, 1, 0, u8, u8, IoSel_SPEC, crate::common::RW> {
crate::common::RegisterField::<24,0xf,1,0,u8,u8,IoSel_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IoSel {
#[inline(always)]
fn default() -> IoSel {
<crate::RegValueT<IoSel_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SeqTime_SPEC;
impl crate::sealed::RegSpec for SeqTime_SPEC {
type DataType = u32;
}
#[doc = "Sequencer Timing"]
pub type SeqTime = crate::RegValueT<SeqTime_SPEC>;
impl SeqTime {
#[doc = "Define Auto-Zero time in csd_sense cycles -1."]
#[inline(always)]
pub fn az_time(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, SeqTime_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0xff,1,0,u8,u8,SeqTime_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SeqTime {
#[inline(always)]
fn default() -> SeqTime {
<crate::RegValueT<SeqTime_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SeqInitCnt_SPEC;
impl crate::sealed::RegSpec for SeqInitCnt_SPEC {
type DataType = u32;
}
#[doc = "Sequencer Initial conversion and sample counts"]
pub type SeqInitCnt = crate::RegValueT<SeqInitCnt_SPEC>;
impl SeqInitCnt {
#[doc = "Number of conversion per Initialization sample, if set to 0 the Sample_init state will be skipped."]
#[inline(always)]
pub fn conv_cnt(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, SeqInitCnt_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,SeqInitCnt_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SeqInitCnt {
#[inline(always)]
fn default() -> SeqInitCnt {
<crate::RegValueT<SeqInitCnt_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SeqNormCnt_SPEC;
impl crate::sealed::RegSpec for SeqNormCnt_SPEC {
type DataType = u32;
}
#[doc = "Sequencer Normal conversion and sample counts"]
pub type SeqNormCnt = crate::RegValueT<SeqNormCnt_SPEC>;
impl SeqNormCnt {
#[doc = "Number of conversion per sample, if set to 0 the Sample_norm state will be skipped.\nSample window size = SEQ_NORM_CNT.CONV_CNT * (SENSE_PERIOD.SENSE_DIV+1).\nNote for CSDv1 Sample window size = PERIOD"]
#[inline(always)]
pub fn conv_cnt(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, SeqNormCnt_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,SeqNormCnt_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SeqNormCnt {
#[inline(always)]
fn default() -> SeqNormCnt {
<crate::RegValueT<SeqNormCnt_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AdcCtl_SPEC;
impl crate::sealed::RegSpec for AdcCtl_SPEC {
type DataType = u32;
}
#[doc = "ADC Control"]
pub type AdcCtl = crate::RegValueT<AdcCtl_SPEC>;
impl AdcCtl {
#[doc = "ADC timing -1 in csd_sense clock cycles (actual time is ADC_TIME+1 cycles), either used to discharge Cref1&2, or as the aperture to capture the input voltage on Cref1&2"]
#[inline(always)]
pub fn adc_time(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, AdcCtl_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0xff,1,0,u8,u8,AdcCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable ADC measurement. When enabled the ADC sequencer will be started when the main sequencer goes to the SAMPLE_NORM state"]
#[inline(always)]
pub fn adc_mode(
self,
) -> crate::common::RegisterField<
16,
0x3,
1,
0,
adc_ctl::AdcMode,
adc_ctl::AdcMode,
AdcCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0x3,
1,
0,
adc_ctl::AdcMode,
adc_ctl::AdcMode,
AdcCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for AdcCtl {
#[inline(always)]
fn default() -> AdcCtl {
<crate::RegValueT<AdcCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod adc_ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct AdcMode_SPEC;
pub type AdcMode = crate::EnumBitfieldStruct<u8, AdcMode_SPEC>;
impl AdcMode {
#[doc = "No ADC measurement"]
pub const OFF: Self = Self::new(0);
#[doc = "Count time A to bring Cref1 + Cref2 up from Vssa to Vrefhi with IDACB"]
pub const VREF_CNT: Self = Self::new(1);
#[doc = "Count time B to bring Cref1 + Cref2 back up to Vrefhi with IDACB (after bringing them down for time A/2 cycles with IDACB sinking)"]
pub const VREF_BY_2_CNT: Self = Self::new(2);
#[doc = "Determine HSCMP polarity and count time C to source/sink Cref1 + Cref2 from Vin to Vrefhi."]
pub const VIN_CNT: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SeqStart_SPEC;
impl crate::sealed::RegSpec for SeqStart_SPEC {
type DataType = u32;
}
#[doc = "Sequencer start"]
pub type SeqStart = crate::RegValueT<SeqStart_SPEC>;
impl SeqStart {
#[doc = "Start the CSD sequencer. The sequencer will clear this bit when it is done. Depending on the mode the sequencer is done when a sample has been accumulated, when the high speed comparator trips or if the sequencer is aborted. When the ADC is enabled the ADC sequencer will start when the CSD sequencer reaches the Sample_norm state (only with the regular CSD scan mode)."]
#[inline(always)]
pub fn start(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, SeqStart_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, SeqStart_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "0 = regular CSD scan + optional ADC \n1 = coarse initialization, the Sequencer will go to the INIT_COARSE state."]
#[inline(always)]
pub fn seq_mode(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, SeqStart_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, SeqStart_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "When a 1 is written the CSD and ADC sequencers will be aborted (if they are running) and the START bit will be cleared. This bit always read as 0."]
#[inline(always)]
pub fn abort(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, SeqStart_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, SeqStart_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "When this bit is set a positive edge on dsi_start will start the CSD sequencer and if enabled also the ADC sequencer."]
#[inline(always)]
pub fn dsi_start_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, SeqStart_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, SeqStart_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "When set the AutoZero_0 state will be skipped"]
#[inline(always)]
pub fn az0_skip(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, SeqStart_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, SeqStart_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "When set the AutoZero_1 state will be skipped"]
#[inline(always)]
pub fn az1_skip(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, SeqStart_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9, 1, 0, SeqStart_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for SeqStart {
#[inline(always)]
fn default() -> SeqStart {
<crate::RegValueT<SeqStart_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Idaca_SPEC;
impl crate::sealed::RegSpec for Idaca_SPEC {
type DataType = u32;
}
#[doc = "IDACA Configuration"]
pub type Idaca = crate::RegValueT<Idaca_SPEC>;
impl Idaca {
#[doc = "N/A"]
#[inline(always)]
pub fn val(
self,
) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, Idaca_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0x7f,1,0,u8,u8,Idaca_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn pol_dyn(
self,
) -> crate::common::RegisterField<
7,
0x1,
1,
0,
idaca::PolDyn,
idaca::PolDyn,
Idaca_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
7,
0x1,
1,
0,
idaca::PolDyn,
idaca::PolDyn,
Idaca_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn polarity(
self,
) -> crate::common::RegisterField<
8,
0x3,
1,
0,
idaca::Polarity,
idaca::Polarity,
Idaca_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0x3,
1,
0,
idaca::Polarity,
idaca::Polarity,
Idaca_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn bal_mode(
self,
) -> crate::common::RegisterField<
10,
0x3,
1,
0,
idaca::BalMode,
idaca::BalMode,
Idaca_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
10,
0x3,
1,
0,
idaca::BalMode,
idaca::BalMode,
Idaca_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn leg1_mode(
self,
) -> crate::common::RegisterField<
16,
0x3,
1,
0,
idaca::Leg1Mode,
idaca::Leg1Mode,
Idaca_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0x3,
1,
0,
idaca::Leg1Mode,
idaca::Leg1Mode,
Idaca_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn leg2_mode(
self,
) -> crate::common::RegisterField<
18,
0x3,
1,
0,
idaca::Leg2Mode,
idaca::Leg2Mode,
Idaca_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
18,
0x3,
1,
0,
idaca::Leg2Mode,
idaca::Leg2Mode,
Idaca_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn dsi_ctrl_en(
self,
) -> crate::common::RegisterFieldBool<21, 1, 0, Idaca_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<21, 1, 0, Idaca_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn range(
self,
) -> crate::common::RegisterField<
22,
0x3,
1,
0,
idaca::Range,
idaca::Range,
Idaca_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
22,
0x3,
1,
0,
idaca::Range,
idaca::Range,
Idaca_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn leg1_en(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, Idaca_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24, 1, 0, Idaca_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn leg2_en(
self,
) -> crate::common::RegisterFieldBool<25, 1, 0, Idaca_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<25, 1, 0, Idaca_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Idaca {
#[inline(always)]
fn default() -> Idaca {
<crate::RegValueT<Idaca_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod idaca {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PolDyn_SPEC;
pub type PolDyn = crate::EnumBitfieldStruct<u8, PolDyn_SPEC>;
impl PolDyn {
#[doc = "Static polarity. Polarity is expected to be stable, so to save power this avoids the shunting of the unused polarity, at the expense of response time."]
pub const STATIC: Self = Self::new(0);
#[doc = "Dynamic polarity. Polarity is expected to change frequently (e.g. invert after every csd_sense phase), so to improve response time this keeps the shunt of the unused polarity on at the expense of power."]
pub const DYNAMIC: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Polarity_SPEC;
pub type Polarity = crate::EnumBitfieldStruct<u8, Polarity_SPEC>;
impl Polarity {
#[doc = "Normal: switch between Vssa and Cmod. For non-CSD application, IDAC will source current."]
pub const VSSA_SRC: Self = Self::new(0);
#[doc = "Inverted: switch between Vdda and Cmod. For non-CSD application, IDAC will sink current."]
pub const VDDA_SNK: Self = Self::new(1);
#[doc = "The polarity of the IDAC will follow the csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC."]
pub const SENSE: Self = Self::new(2);
#[doc = "The polarity of the IDAC will follow the inverted csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC."]
pub const SENSE_INV: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct BalMode_SPEC;
pub type BalMode = crate::EnumBitfieldStruct<u8, BalMode_SPEC>;
impl BalMode {
#[doc = "enabled from start of Phi2 until disabled by CSDCMP. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off)"]
pub const FULL: Self = Self::new(0);
#[doc = "enabled from start of Phi1 and disabled by CSDCMP or at end of Phi1. Enables dual IDAC CSX or Full-Wave, one for sourcing and the other for sinking."]
pub const PHI_1: Self = Self::new(1);
#[doc = "enabled from start of Phi2 and disabled by CSDCMP or at end of Phi2. Intended usage: CSD Low EMI or dual IDAC CSX or Full-Wave."]
pub const PHI_2: Self = Self::new(2);
#[doc = "enabled from start of both Phi1 and Phi2 and disabled by CSDCMP or at end of Phi1 or Phi2 (if non-overlap enabled). Intended usage: single IDAC CSX, or Full-Wave."]
pub const PHI_1_2: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Leg1Mode_SPEC;
pub type Leg1Mode = crate::EnumBitfieldStruct<u8, Leg1Mode_SPEC>;
impl Leg1Mode {
#[doc = "General Purpose static mode: LEG1 and POLARITY are controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer."]
pub const GP_STATIC: Self = Self::new(0);
#[doc = "General Purpose dynamic mode: LEG1 and POLARITY are controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled."]
pub const GP: Self = Self::new(1);
#[doc = "CSD static mode: LEG1 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG1 is controlled by LEG1_EN, csd_sense and the CSD configuration. Polarity is controlled by the CSD configuration and operation. In addition leg1 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer."]
pub const CSD_STATIC: Self = Self::new(2);
#[doc = "CSD dynamic mode: LEG1 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In thoses states LEG1 is controlled by LEG1_EN, the CSD configuration, csd_sense and the flopped CSDCMP output (CSDCMP_OUT_FF). Polarity is controlled by the CSD configuration and operation. In addition leg1 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled."]
pub const CSD: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Leg2Mode_SPEC;
pub type Leg2Mode = crate::EnumBitfieldStruct<u8, Leg2Mode_SPEC>;
impl Leg2Mode {
#[doc = "General Purpose static mode: LEG2 is controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer."]
pub const GP_STATIC: Self = Self::new(0);
#[doc = "General Purpose dynamic mode: LEG2 is controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled."]
pub const GP: Self = Self::new(1);
#[doc = "CSD static mode: LEG2 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG2 is controlled by LEG2_EN, csd_sense and the CSD configuration. Polarity is controlled by the CSD configuration and operation. In addition leg2 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer."]
pub const CSD_STATIC: Self = Self::new(2);
#[doc = "CSD dynamic mode: LEG2 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG2 is controlled by LEG2_EN, the CSD configuration, csd_sense and the flopped CSDCMP output (CSDCMP_OUT_FF). In addition leg2 enable can optionally be mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled."]
pub const CSD: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Range_SPEC;
pub type Range = crate::EnumBitfieldStruct<u8, Range_SPEC>;
impl Range {
#[doc = "1 LSB = 37.5 nA"]
pub const IDAC_LO: Self = Self::new(0);
#[doc = "1 LSB = 300 nA"]
pub const IDAC_MED: Self = Self::new(1);
#[doc = "1 LSB = 2400 nA"]
pub const IDAC_HI: Self = Self::new(2);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Idacb_SPEC;
impl crate::sealed::RegSpec for Idacb_SPEC {
type DataType = u32;
}
#[doc = "IDACB Configuration"]
pub type Idacb = crate::RegValueT<Idacb_SPEC>;
impl Idacb {
#[doc = "N/A"]
#[inline(always)]
pub fn val(
self,
) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, Idacb_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0x7f,1,0,u8,u8,Idacb_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn pol_dyn(
self,
) -> crate::common::RegisterField<
7,
0x1,
1,
0,
idacb::PolDyn,
idacb::PolDyn,
Idacb_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
7,
0x1,
1,
0,
idacb::PolDyn,
idacb::PolDyn,
Idacb_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn polarity(
self,
) -> crate::common::RegisterField<
8,
0x3,
1,
0,
idacb::Polarity,
idacb::Polarity,
Idacb_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0x3,
1,
0,
idacb::Polarity,
idacb::Polarity,
Idacb_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn bal_mode(
self,
) -> crate::common::RegisterField<
10,
0x3,
1,
0,
idacb::BalMode,
idacb::BalMode,
Idacb_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
10,
0x3,
1,
0,
idacb::BalMode,
idacb::BalMode,
Idacb_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn leg1_mode(
self,
) -> crate::common::RegisterField<
16,
0x3,
1,
0,
idacb::Leg1Mode,
idacb::Leg1Mode,
Idacb_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0x3,
1,
0,
idacb::Leg1Mode,
idacb::Leg1Mode,
Idacb_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn leg2_mode(
self,
) -> crate::common::RegisterField<
18,
0x3,
1,
0,
idacb::Leg2Mode,
idacb::Leg2Mode,
Idacb_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
18,
0x3,
1,
0,
idacb::Leg2Mode,
idacb::Leg2Mode,
Idacb_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn dsi_ctrl_en(
self,
) -> crate::common::RegisterFieldBool<21, 1, 0, Idacb_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<21, 1, 0, Idacb_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn range(
self,
) -> crate::common::RegisterField<
22,
0x3,
1,
0,
idacb::Range,
idacb::Range,
Idacb_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
22,
0x3,
1,
0,
idacb::Range,
idacb::Range,
Idacb_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn leg1_en(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, Idacb_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24, 1, 0, Idacb_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn leg2_en(
self,
) -> crate::common::RegisterFieldBool<25, 1, 0, Idacb_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<25, 1, 0, Idacb_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn leg3_en(
self,
) -> crate::common::RegisterFieldBool<26, 1, 0, Idacb_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<26, 1, 0, Idacb_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Idacb {
#[inline(always)]
fn default() -> Idacb {
<crate::RegValueT<Idacb_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod idacb {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PolDyn_SPEC;
pub type PolDyn = crate::EnumBitfieldStruct<u8, PolDyn_SPEC>;
impl PolDyn {
#[doc = "Static polarity. Polarity is expected to be stable, so to save power this avoids the shunting of the unused polarity, at the expense of response time."]
pub const STATIC: Self = Self::new(0);
#[doc = "Dynamic polarity. Polarity is expected to change frequently (e.g. invert after every csd_sense phase), so to improve response time this keeps the shunt of the unused polarity on at the expense of power."]
pub const DYNAMIC: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Polarity_SPEC;
pub type Polarity = crate::EnumBitfieldStruct<u8, Polarity_SPEC>;
impl Polarity {
#[doc = "Normal: switch between Vssa and Cmod. For non-CSD application, IDAC will source current."]
pub const VSSA_SRC: Self = Self::new(0);
#[doc = "Inverted: switch between Vdda and Cmod. For non-CSD application, IDAC will sink current."]
pub const VDDA_SNK: Self = Self::new(1);
#[doc = "The polarity of the IDAC will follow the csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC."]
pub const SENSE: Self = Self::new(2);
#[doc = "The polarity of the IDAC will follow the inverted csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC."]
pub const SENSE_INV: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct BalMode_SPEC;
pub type BalMode = crate::EnumBitfieldStruct<u8, BalMode_SPEC>;
impl BalMode {
#[doc = "same as corresponding IDACA Balancing mode"]
pub const FULL: Self = Self::new(0);
#[doc = "same as corresponding IDACA Balancing mode"]
pub const PHI_1: Self = Self::new(1);
#[doc = "same as corresponding IDACA Balancing mode"]
pub const PHI_2: Self = Self::new(2);
#[doc = "same as corresponding IDACA Balancing mode"]
pub const PHI_1_2: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Leg1Mode_SPEC;
pub type Leg1Mode = crate::EnumBitfieldStruct<u8, Leg1Mode_SPEC>;
impl Leg1Mode {
#[doc = "same as corresponding IDACA.LEG1_MODE"]
pub const GP_STATIC: Self = Self::new(0);
#[doc = "same as corresponding IDACA.LEG1_MODE"]
pub const GP: Self = Self::new(1);
#[doc = "same as corresponding IDACA.LEG1_MODE"]
pub const CSD_STATIC: Self = Self::new(2);
#[doc = "same as corresponding IDACA.LEG1_MODE"]
pub const CSD: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Leg2Mode_SPEC;
pub type Leg2Mode = crate::EnumBitfieldStruct<u8, Leg2Mode_SPEC>;
impl Leg2Mode {
#[doc = "same as corresponding IDACA.LEG2_MODE"]
pub const GP_STATIC: Self = Self::new(0);
#[doc = "same as corresponding IDACA.LEG2_MODE"]
pub const GP: Self = Self::new(1);
#[doc = "same as corresponding IDACA.LEG2_MODE"]
pub const CSD_STATIC: Self = Self::new(2);
#[doc = "same as corresponding IDACA.LEG2_MODE"]
pub const CSD: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Range_SPEC;
pub type Range = crate::EnumBitfieldStruct<u8, Range_SPEC>;
impl Range {
#[doc = "1 LSB = 37.5 nA"]
pub const IDAC_LO: Self = Self::new(0);
#[doc = "1 LSB = 300 nA"]
pub const IDAC_MED: Self = Self::new(1);
#[doc = "1 LSB = 2400 nA"]
pub const IDAC_HI: Self = Self::new(2);
}
}