/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"Bluetooth Low Energy Subsystem"]
unsafe impl ::core::marker::Send for super::Ble {}
unsafe impl ::core::marker::Sync for super::Ble {}
impl super::Ble {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "Radio Control Bus (RCB) controller"]
#[inline(always)]
pub const fn rcb(self) -> crate::ble::Rcb {
unsafe { crate::ble::_Rcb::_svd2pac_from_ptr(self._svd2pac_as_ptr().add(0usize)) }
}
#[doc = "Bluetooth Low Energy Link Layer"]
#[inline(always)]
pub const fn blell(self) -> crate::ble::Blell {
unsafe { crate::ble::_Blell::_svd2pac_from_ptr(self._svd2pac_as_ptr().add(4096usize)) }
}
#[doc = "Bluetooth Low Energy Subsystem Miscellaneous"]
#[inline(always)]
pub const fn bless(self) -> crate::ble::Bless {
unsafe { crate::ble::_Bless::_svd2pac_from_ptr(self._svd2pac_as_ptr().add(126976usize)) }
}
}
#[doc = "Radio Control Bus (RCB) controller"]
#[non_exhaustive]
pub struct _Rcb;
#[doc = "Radio Control Bus (RCB) controller"]
pub type Rcb = &'static _Rcb;
unsafe impl ::core::marker::Sync for _Rcb {}
impl _Rcb {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "RCB control register."]
#[inline(always)]
pub const fn ctrl(&self) -> &'static crate::common::Reg<rcb::Ctrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcb::Ctrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "RCB status register."]
#[inline(always)]
pub const fn status(&self) -> &'static crate::common::Reg<rcb::Status_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<rcb::Status_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "Transmitter control register."]
#[inline(always)]
pub const fn tx_ctrl(
&self,
) -> &'static crate::common::Reg<rcb::TxCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcb::TxCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16usize),
)
}
}
#[doc = "Transmitter FIFO control register."]
#[inline(always)]
pub const fn tx_fifo_ctrl(
&self,
) -> &'static crate::common::Reg<rcb::TxFifoCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcb::TxFifoCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(20usize),
)
}
}
#[doc = "Transmitter FIFO status register."]
#[inline(always)]
pub const fn tx_fifo_status(
&self,
) -> &'static crate::common::Reg<rcb::TxFifoStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<rcb::TxFifoStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(24usize),
)
}
}
#[doc = "Transmitter FIFO write register."]
#[inline(always)]
pub const fn tx_fifo_wr(
&self,
) -> &'static crate::common::Reg<rcb::TxFifoWr_SPEC, crate::common::W> {
unsafe {
crate::common::Reg::<rcb::TxFifoWr_SPEC, crate::common::W>::from_ptr(
self._svd2pac_as_ptr().add(28usize),
)
}
}
#[doc = "Receiver control register."]
#[inline(always)]
pub const fn rx_ctrl(
&self,
) -> &'static crate::common::Reg<rcb::RxCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcb::RxCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "Receiver FIFO control register."]
#[inline(always)]
pub const fn rx_fifo_ctrl(
&self,
) -> &'static crate::common::Reg<rcb::RxFifoCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcb::RxFifoCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
#[doc = "Receiver FIFO status register."]
#[inline(always)]
pub const fn rx_fifo_status(
&self,
) -> &'static crate::common::Reg<rcb::RxFifoStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<rcb::RxFifoStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(40usize),
)
}
}
#[doc = "Receiver FIFO read register."]
#[inline(always)]
pub const fn rx_fifo_rd(
&self,
) -> &'static crate::common::Reg<rcb::RxFifoRd_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<rcb::RxFifoRd_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(44usize),
)
}
}
#[doc = "Receiver FIFO read register."]
#[inline(always)]
pub const fn rx_fifo_rd_silent(
&self,
) -> &'static crate::common::Reg<rcb::RxFifoRdSilent_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<rcb::RxFifoRdSilent_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(48usize),
)
}
}
#[doc = "Master interrupt request register."]
#[inline(always)]
pub const fn intr(&self) -> &'static crate::common::Reg<rcb::Intr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcb::Intr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(64usize),
)
}
}
#[doc = "Master interrupt set request register"]
#[inline(always)]
pub const fn intr_set(
&self,
) -> &'static crate::common::Reg<rcb::IntrSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcb::IntrSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(68usize),
)
}
}
#[doc = "Master interrupt mask register."]
#[inline(always)]
pub const fn intr_mask(
&self,
) -> &'static crate::common::Reg<rcb::IntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcb::IntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(72usize),
)
}
}
#[doc = "Master interrupt masked request register"]
#[inline(always)]
pub const fn intr_masked(
&self,
) -> &'static crate::common::Reg<rcb::IntrMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<rcb::IntrMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(76usize),
)
}
}
#[doc = "Radio Control Bus (RCB) & Link Layer controller"]
#[inline(always)]
pub const fn rcbll(self) -> crate::ble::rcb::Rcbll {
unsafe { crate::ble::rcb::_Rcbll::_svd2pac_from_ptr(self._svd2pac_as_ptr().add(256usize)) }
}
}
pub mod rcb {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctrl_SPEC;
impl crate::sealed::RegSpec for Ctrl_SPEC {
type DataType = u32;
}
#[doc = "RCB control register."]
pub type Ctrl = crate::RegValueT<Ctrl_SPEC>;
impl Ctrl {
#[doc = "N/A"]
#[inline(always)]
pub fn tx_clk_edge(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rx_clk_edge(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rx_clk_src(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn sclk_continuous(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn ssel_polarity(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn lead(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ctrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn lag(
self,
) -> crate::common::RegisterField<10, 0x3, 1, 0, u8, u8, Ctrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<10,0x3,1,0,u8,u8,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn div_enabled(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn div(
self,
) -> crate::common::RegisterField<13, 0x3f, 1, 0, u8, u8, Ctrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<13,0x3f,1,0,u8,u8,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn addr_width(
self,
) -> crate::common::RegisterField<19, 0xf, 1, 0, u8, u8, Ctrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<19,0xf,1,0,u8,u8,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn data_width(
self,
) -> crate::common::RegisterFieldBool<23, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<23,1,0,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ctrl {
#[inline(always)]
fn default() -> Ctrl {
<crate::RegValueT<Ctrl_SPEC> as RegisterValue<_>>::new(16252928)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Status_SPEC;
impl crate::sealed::RegSpec for Status_SPEC {
type DataType = u32;
}
#[doc = "RCB status register."]
pub type Status = crate::RegValueT<Status_SPEC>;
impl Status {
#[doc = "RCB bus is busy. The bus is considered busy (\'1\') during an ongoing transaction."]
#[inline(always)]
pub fn bus_busy(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,Status_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Status {
#[inline(always)]
fn default() -> Status {
<crate::RegValueT<Status_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxCtrl_SPEC;
impl crate::sealed::RegSpec for TxCtrl_SPEC {
type DataType = u32;
}
#[doc = "Transmitter control register."]
pub type TxCtrl = crate::RegValueT<TxCtrl_SPEC>;
impl TxCtrl {
#[doc = "Least significant bit first (\'0\') or most significant bit first (\'1\').\nThis field also affects the Address field\nWhen MSB_FIRST = 1, then \\[15:0\\] is data and \\[(ADDR_WIDTH+15):16\\] is used for address \nWhen MSB_FIRST = 0, then \\[15:0\\] is for data. No address field"]
#[inline(always)]
pub fn msb_first(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, TxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,TxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Setting this bit, clears the FIFO and resets the pointer"]
#[inline(always)]
pub fn fifo_reconfig(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, TxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,TxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field determines the depth of the TX_FIFO. Allowed legal values are 8 and 16 only"]
#[inline(always)]
pub fn tx_entries(
self,
) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, TxCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<2,0x1f,1,0,u8,u8,TxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TxCtrl {
#[inline(always)]
fn default() -> TxCtrl {
<crate::RegValueT<TxCtrl_SPEC> as RegisterValue<_>>::new(33)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxFifoCtrl_SPEC;
impl crate::sealed::RegSpec for TxFifoCtrl_SPEC {
type DataType = u32;
}
#[doc = "Transmitter FIFO control register."]
pub type TxFifoCtrl = crate::RegValueT<TxFifoCtrl_SPEC>;
impl TxFifoCtrl {
#[doc = "Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event is generated."]
#[inline(always)]
pub fn tx_trigger_level(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, TxFifoCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,TxFifoCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When \'1\', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is \'1\'. If a quick clear/invalidation is required, the field should be set to \'1\' and be followed by a set to \'0\'. If a clear/invalidation is required for an extended time period, the field should be set to \'1\' during the complete time period."]
#[inline(always)]
pub fn clear(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, TxFifoCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<16,1,0,TxFifoCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TxFifoCtrl {
#[inline(always)]
fn default() -> TxFifoCtrl {
<crate::RegValueT<TxFifoCtrl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxFifoStatus_SPEC;
impl crate::sealed::RegSpec for TxFifoStatus_SPEC {
type DataType = u32;
}
#[doc = "Transmitter FIFO status register."]
pub type TxFifoStatus = crate::RegValueT<TxFifoStatus_SPEC>;
impl TxFifoStatus {
#[doc = "Amount of enties in the transmitter FIFO. The value of this field ranges from 0 to 16"]
#[inline(always)]
pub fn used(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, TxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,TxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Indicates whether the TX shift registers holds a valid data frame (\'1\') or not (\'0\'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is tranmitted next (when the protocol state machine is not transmitting a data frame)."]
#[inline(always)]
pub fn sr_valid(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, TxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<15,1,0,TxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "FIFO read pointer: FIFO location from which a data frame is read by the hardware."]
#[inline(always)]
pub fn rd_ptr(
self,
) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, TxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xf,1,0,u8,u8,TxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "FIFO write pointer: FIFO location at which a new data frame is written."]
#[inline(always)]
pub fn wr_ptr(
self,
) -> crate::common::RegisterField<24, 0xf, 1, 0, u8, u8, TxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<24,0xf,1,0,u8,u8,TxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for TxFifoStatus {
#[inline(always)]
fn default() -> TxFifoStatus {
<crate::RegValueT<TxFifoStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxFifoWr_SPEC;
impl crate::sealed::RegSpec for TxFifoWr_SPEC {
type DataType = u32;
}
#[doc = "Transmitter FIFO write register."]
pub type TxFifoWr = crate::RegValueT<TxFifoWr_SPEC>;
impl TxFifoWr {
#[doc = "Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. \nA write to a full TX FIFO sets INTR_TX.OVERFLOW to \'1\'."]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
TxFifoWr_SPEC,
crate::common::W,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
TxFifoWr_SPEC,
crate::common::W,
>::from_register(self, 0)
}
}
impl ::core::default::Default for TxFifoWr {
#[inline(always)]
fn default() -> TxFifoWr {
<crate::RegValueT<TxFifoWr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxCtrl_SPEC;
impl crate::sealed::RegSpec for RxCtrl_SPEC {
type DataType = u32;
}
#[doc = "Receiver control register."]
pub type RxCtrl = crate::RegValueT<RxCtrl_SPEC>;
impl RxCtrl {
#[doc = "Least significant bit first (\'0\') or most significant bit first (\'1\').\nThis field also affects the Address field\nWhen MSB_FIRST = 1, then \\[15:0\\] is data and \\[(ADDR_WIDTH+15):16\\] is used for address \nWhen MSB_FIRST = 0, then \\[15:0\\] is for data. No address field"]
#[inline(always)]
pub fn msb_first(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, RxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,RxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RxCtrl {
#[inline(always)]
fn default() -> RxCtrl {
<crate::RegValueT<RxCtrl_SPEC> as RegisterValue<_>>::new(1)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxFifoCtrl_SPEC;
impl crate::sealed::RegSpec for RxFifoCtrl_SPEC {
type DataType = u32;
}
#[doc = "Receiver FIFO control register."]
pub type RxFifoCtrl = crate::RegValueT<RxFifoCtrl_SPEC>;
impl RxFifoCtrl {
#[doc = "Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event is generated."]
#[inline(always)]
pub fn trigger_level(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, RxFifoCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,RxFifoCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When \'1\', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is \'1\'. If a quick clear/invalidation is required, the field should be set to \'1\' and be followed by a set to \'0\'. If a clear/invalidation is required for an extended time period, the field should be set to \'1\' during the complete time period."]
#[inline(always)]
pub fn clear(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, RxFifoCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<16,1,0,RxFifoCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RxFifoCtrl {
#[inline(always)]
fn default() -> RxFifoCtrl {
<crate::RegValueT<RxFifoCtrl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxFifoStatus_SPEC;
impl crate::sealed::RegSpec for RxFifoStatus_SPEC {
type DataType = u32;
}
#[doc = "Receiver FIFO status register."]
pub type RxFifoStatus = crate::RegValueT<RxFifoStatus_SPEC>;
impl RxFifoStatus {
#[doc = "Amount of enties in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR."]
#[inline(always)]
pub fn used(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, RxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,RxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Indicates whether the RX shift registers holds a (partial) valid data frame (\'1\') or not (\'0\'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame)."]
#[inline(always)]
pub fn sr_valid(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, RxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<15,1,0,RxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "FIFO read pointer: FIFO location from which a data frame is read."]
#[inline(always)]
pub fn rd_ptr(
self,
) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, RxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xf,1,0,u8,u8,RxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "FIFO write pointer: FIFO location at which a new data frame is written by the hardware."]
#[inline(always)]
pub fn wr_ptr(
self,
) -> crate::common::RegisterField<24, 0xf, 1, 0, u8, u8, RxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<24,0xf,1,0,u8,u8,RxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for RxFifoStatus {
#[inline(always)]
fn default() -> RxFifoStatus {
<crate::RegValueT<RxFifoStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxFifoRd_SPEC;
impl crate::sealed::RegSpec for RxFifoRd_SPEC {
type DataType = u32;
}
#[doc = "Receiver FIFO read register."]
pub type RxFifoRd = crate::RegValueT<RxFifoRd_SPEC>;
impl RxFifoRd {
#[doc = "N/A"]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
RxFifoRd_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
RxFifoRd_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RxFifoRd {
#[inline(always)]
fn default() -> RxFifoRd {
<crate::RegValueT<RxFifoRd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxFifoRdSilent_SPEC;
impl crate::sealed::RegSpec for RxFifoRdSilent_SPEC {
type DataType = u32;
}
#[doc = "Receiver FIFO read register."]
pub type RxFifoRdSilent = crate::RegValueT<RxFifoRdSilent_SPEC>;
impl RxFifoRdSilent {
#[doc = "Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation.\nA read from an empty RX FIFO sets INTR_RX.UNDERFLOW to \'1\'."]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
RxFifoRdSilent_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
RxFifoRdSilent_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RxFifoRdSilent {
#[inline(always)]
fn default() -> RxFifoRdSilent {
<crate::RegValueT<RxFifoRdSilent_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Intr_SPEC;
impl crate::sealed::RegSpec for Intr_SPEC {
type DataType = u32;
}
#[doc = "Master interrupt request register."]
pub type Intr = crate::RegValueT<Intr_SPEC>;
impl Intr {
#[doc = "N/A"]
#[inline(always)]
pub fn rcb_done(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn tx_fifo_trigger(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn tx_fifo_not_full(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn tx_fifo_empty(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,Intr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn tx_fifo_overflow(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,Intr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is \'1\'.\n\nOnly used in FIFO mode."]
#[inline(always)]
pub fn tx_fifo_underflow(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,Intr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rx_fifo_trigger(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,Intr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rx_fifo_not_empty(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,Intr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rx_fifo_full(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,Intr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rx_fifo_overflow(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,Intr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rx_fifo_underflow(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,Intr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Intr {
#[inline(always)]
fn default() -> Intr {
<crate::RegValueT<Intr_SPEC> as RegisterValue<_>>::new(1536)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSet_SPEC;
impl crate::sealed::RegSpec for IntrSet_SPEC {
type DataType = u32;
}
#[doc = "Master interrupt set request register"]
pub type IntrSet = crate::RegValueT<IntrSet_SPEC>;
impl IntrSet {
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rcb_done(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_fifo_trigger(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_fifo_not_full(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_fifo_empty(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_fifo_overflow(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_fifo_underflow(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_fifo_trigger(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_fifo_not_empty(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_fifo_full(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_fifo_overflow(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_fifo_underflow(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrSet {
#[inline(always)]
fn default() -> IntrSet {
<crate::RegValueT<IntrSet_SPEC> as RegisterValue<_>>::new(1536)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMask_SPEC;
impl crate::sealed::RegSpec for IntrMask_SPEC {
type DataType = u32;
}
#[doc = "Master interrupt mask register."]
pub type IntrMask = crate::RegValueT<IntrMask_SPEC>;
impl IntrMask {
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rcb_done(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_fifo_trigger(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_fifo_not_full(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_fifo_empty(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_fifo_overflow(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_fifo_underflow(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_fifo_trigger(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_fifo_not_empty(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_fifo_full(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_fifo_overflow(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_fifo_underflow(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMask {
#[inline(always)]
fn default() -> IntrMask {
<crate::RegValueT<IntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMasked_SPEC;
impl crate::sealed::RegSpec for IntrMasked_SPEC {
type DataType = u32;
}
#[doc = "Master interrupt masked request register"]
pub type IntrMasked = crate::RegValueT<IntrMasked_SPEC>;
impl IntrMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn rcb_done(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tx_fifo_trigger(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tx_fifo_not_full(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<9,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tx_fifo_empty(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<10,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tx_fifo_overflow(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<11,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tx_fifo_underflow(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<12,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn rx_fifo_trigger(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn rx_fifo_not_empty(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<17,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn rx_fifo_full(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<18,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn rx_fifo_overflow(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<19,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn rx_fifo_underflow(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<20,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMasked {
#[inline(always)]
fn default() -> IntrMasked {
<crate::RegValueT<IntrMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc = "Radio Control Bus (RCB) & Link Layer controller"]
#[non_exhaustive]
pub struct _Rcbll;
#[doc = "Radio Control Bus (RCB) & Link Layer controller"]
pub type Rcbll = &'static _Rcbll;
unsafe impl ::core::marker::Sync for _Rcbll {}
impl _Rcbll {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "RCB LL control register."]
#[inline(always)]
pub const fn ctrl(
&self,
) -> &'static crate::common::Reg<rcbll::Ctrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcbll::Ctrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Master interrupt request register."]
#[inline(always)]
pub const fn intr(
&self,
) -> &'static crate::common::Reg<rcbll::Intr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcbll::Intr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16usize),
)
}
}
#[doc = "Master interrupt set request register"]
#[inline(always)]
pub const fn intr_set(
&self,
) -> &'static crate::common::Reg<rcbll::IntrSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcbll::IntrSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(20usize),
)
}
}
#[doc = "Master interrupt mask register."]
#[inline(always)]
pub const fn intr_mask(
&self,
) -> &'static crate::common::Reg<rcbll::IntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcbll::IntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(24usize),
)
}
}
#[doc = "Master interrupt masked request register"]
#[inline(always)]
pub const fn intr_masked(
&self,
) -> &'static crate::common::Reg<rcbll::IntrMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<rcbll::IntrMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(28usize),
)
}
}
#[doc = "Address of Register#1 in Radio (MDON)"]
#[inline(always)]
pub const fn radio_reg1_addr(
&self,
) -> &'static crate::common::Reg<rcbll::RadioReg1Addr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcbll::RadioReg1Addr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "Address of Register#2 in Radio (RSSI)"]
#[inline(always)]
pub const fn radio_reg2_addr(
&self,
) -> &'static crate::common::Reg<rcbll::RadioReg2Addr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcbll::RadioReg2Addr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
#[doc = "Address of Register#3 in Radio (ACCL)"]
#[inline(always)]
pub const fn radio_reg3_addr(
&self,
) -> &'static crate::common::Reg<rcbll::RadioReg3Addr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcbll::RadioReg3Addr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(40usize),
)
}
}
#[doc = "Address of Register#4 in Radio (ACCH)"]
#[inline(always)]
pub const fn radio_reg4_addr(
&self,
) -> &'static crate::common::Reg<rcbll::RadioReg4Addr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcbll::RadioReg4Addr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(44usize),
)
}
}
#[doc = "Address of Register#5 in Radio (RSSI ENERGY)"]
#[inline(always)]
pub const fn radio_reg5_addr(
&self,
) -> &'static crate::common::Reg<rcbll::RadioReg5Addr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcbll::RadioReg5Addr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(48usize),
)
}
}
#[doc = "N/A"]
#[inline(always)]
pub const fn cpu_write_reg(
&self,
) -> &'static crate::common::Reg<rcbll::CpuWriteReg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcbll::CpuWriteReg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(64usize),
)
}
}
#[doc = "N/A"]
#[inline(always)]
pub const fn cpu_read_reg(
&self,
) -> &'static crate::common::Reg<rcbll::CpuReadReg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<rcbll::CpuReadReg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(68usize),
)
}
}
}
pub mod rcbll {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctrl_SPEC;
impl crate::sealed::RegSpec for Ctrl_SPEC {
type DataType = u32;
}
#[doc = "RCB LL control register."]
pub type Ctrl = crate::RegValueT<Ctrl_SPEC>;
impl Ctrl {
#[doc = "N/A"]
#[inline(always)]
pub fn rcbll_ctrl(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ctrl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rcbll_cpu_req(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ctrl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn cpu_single_write(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, Ctrl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn cpu_single_read(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Ctrl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn allow_cpu_access_tx_rx(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Ctrl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn enable_radio_bod(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Ctrl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ctrl {
#[inline(always)]
fn default() -> Ctrl {
<crate::RegValueT<Ctrl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Intr_SPEC;
impl crate::sealed::RegSpec for Intr_SPEC {
type DataType = u32;
}
#[doc = "Master interrupt request register."]
pub type Intr = crate::RegValueT<Intr_SPEC>;
impl Intr {
#[doc = "RCB_LL is done and the access is given back to CPU"]
#[inline(always)]
pub fn rcb_ll_done(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Intr_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,Intr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn single_write_done(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, Intr_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,Intr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn single_read_done(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Intr_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,Intr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Intr {
#[inline(always)]
fn default() -> Intr {
<crate::RegValueT<Intr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSet_SPEC;
impl crate::sealed::RegSpec for IntrSet_SPEC {
type DataType = u32;
}
#[doc = "Master interrupt set request register"]
pub type IntrSet = crate::RegValueT<IntrSet_SPEC>;
impl IntrSet {
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rcb_ll_done(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn single_write_done(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn single_read_done(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrSet_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrSet {
#[inline(always)]
fn default() -> IntrSet {
<crate::RegValueT<IntrSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMask_SPEC;
impl crate::sealed::RegSpec for IntrMask_SPEC {
type DataType = u32;
}
#[doc = "Master interrupt mask register."]
pub type IntrMask = crate::RegValueT<IntrMask_SPEC>;
impl IntrMask {
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rcb_ll_done(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn single_write_done(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn single_read_done(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMask {
#[inline(always)]
fn default() -> IntrMask {
<crate::RegValueT<IntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMasked_SPEC;
impl crate::sealed::RegSpec for IntrMasked_SPEC {
type DataType = u32;
}
#[doc = "Master interrupt masked request register"]
pub type IntrMasked = crate::RegValueT<IntrMasked_SPEC>;
impl IntrMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn rcb_ll_done(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<0,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn single_write_done(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<2,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn single_read_done(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrMasked_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<3,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMasked {
#[inline(always)]
fn default() -> IntrMasked {
<crate::RegValueT<IntrMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RadioReg1Addr_SPEC;
impl crate::sealed::RegSpec for RadioReg1Addr_SPEC {
type DataType = u32;
}
#[doc = "Address of Register#1 in Radio (MDON)"]
pub type RadioReg1Addr = crate::RegValueT<RadioReg1Addr_SPEC>;
impl RadioReg1Addr {
#[doc = "N/A"]
#[inline(always)]
pub fn reg_addr(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
RadioReg1Addr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
RadioReg1Addr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RadioReg1Addr {
#[inline(always)]
fn default() -> RadioReg1Addr {
<crate::RegValueT<RadioReg1Addr_SPEC> as RegisterValue<_>>::new(7682)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RadioReg2Addr_SPEC;
impl crate::sealed::RegSpec for RadioReg2Addr_SPEC {
type DataType = u32;
}
#[doc = "Address of Register#2 in Radio (RSSI)"]
pub type RadioReg2Addr = crate::RegValueT<RadioReg2Addr_SPEC>;
impl RadioReg2Addr {
#[doc = "N/A"]
#[inline(always)]
pub fn reg_addr(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
RadioReg2Addr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
RadioReg2Addr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RadioReg2Addr {
#[inline(always)]
fn default() -> RadioReg2Addr {
<crate::RegValueT<RadioReg2Addr_SPEC> as RegisterValue<_>>::new(2563)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RadioReg3Addr_SPEC;
impl crate::sealed::RegSpec for RadioReg3Addr_SPEC {
type DataType = u32;
}
#[doc = "Address of Register#3 in Radio (ACCL)"]
pub type RadioReg3Addr = crate::RegValueT<RadioReg3Addr_SPEC>;
impl RadioReg3Addr {
#[doc = "N/A"]
#[inline(always)]
pub fn reg_addr(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
RadioReg3Addr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
RadioReg3Addr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RadioReg3Addr {
#[inline(always)]
fn default() -> RadioReg3Addr {
<crate::RegValueT<RadioReg3Addr_SPEC> as RegisterValue<_>>::new(2084)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RadioReg4Addr_SPEC;
impl crate::sealed::RegSpec for RadioReg4Addr_SPEC {
type DataType = u32;
}
#[doc = "Address of Register#4 in Radio (ACCH)"]
pub type RadioReg4Addr = crate::RegValueT<RadioReg4Addr_SPEC>;
impl RadioReg4Addr {
#[doc = "N/A"]
#[inline(always)]
pub fn reg_addr(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
RadioReg4Addr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
RadioReg4Addr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RadioReg4Addr {
#[inline(always)]
fn default() -> RadioReg4Addr {
<crate::RegValueT<RadioReg4Addr_SPEC> as RegisterValue<_>>::new(2083)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RadioReg5Addr_SPEC;
impl crate::sealed::RegSpec for RadioReg5Addr_SPEC {
type DataType = u32;
}
#[doc = "Address of Register#5 in Radio (RSSI ENERGY)"]
pub type RadioReg5Addr = crate::RegValueT<RadioReg5Addr_SPEC>;
impl RadioReg5Addr {
#[doc = "N/A"]
#[inline(always)]
pub fn reg_addr(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
RadioReg5Addr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
RadioReg5Addr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RadioReg5Addr {
#[inline(always)]
fn default() -> RadioReg5Addr {
<crate::RegValueT<RadioReg5Addr_SPEC> as RegisterValue<_>>::new(2563)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CpuWriteReg_SPEC;
impl crate::sealed::RegSpec for CpuWriteReg_SPEC {
type DataType = u32;
}
#[doc = "N/A"]
pub type CpuWriteReg = crate::RegValueT<CpuWriteReg_SPEC>;
impl CpuWriteReg {
#[doc = "N/A"]
#[inline(always)]
pub fn addr(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
CpuWriteReg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
CpuWriteReg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn write_data(
self,
) -> crate::common::RegisterField<
16,
0xffff,
1,
0,
u16,
u16,
CpuWriteReg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0xffff,
1,
0,
u16,
u16,
CpuWriteReg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CpuWriteReg {
#[inline(always)]
fn default() -> CpuWriteReg {
<crate::RegValueT<CpuWriteReg_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CpuReadReg_SPEC;
impl crate::sealed::RegSpec for CpuReadReg_SPEC {
type DataType = u32;
}
#[doc = "N/A"]
pub type CpuReadReg = crate::RegValueT<CpuReadReg_SPEC>;
impl CpuReadReg {
#[doc = "N/A"]
#[inline(always)]
pub fn addr(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
CpuReadReg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
CpuReadReg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn read_data(
self,
) -> crate::common::RegisterField<
16,
0xffff,
1,
0,
u16,
u16,
CpuReadReg_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
16,
0xffff,
1,
0,
u16,
u16,
CpuReadReg_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CpuReadReg {
#[inline(always)]
fn default() -> CpuReadReg {
<crate::RegValueT<CpuReadReg_SPEC> as RegisterValue<_>>::new(0)
}
}
}
}
#[doc = "Bluetooth Low Energy Link Layer"]
#[non_exhaustive]
pub struct _Blell;
#[doc = "Bluetooth Low Energy Link Layer"]
pub type Blell = &'static _Blell;
unsafe impl ::core::marker::Sync for _Blell {}
impl _Blell {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "Instruction Register"]
#[inline(always)]
pub const fn command_register(
&self,
) -> &'static crate::common::Reg<blell::CommandRegister_SPEC, crate::common::W> {
unsafe {
crate::common::Reg::<blell::CommandRegister_SPEC, crate::common::W>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Event(Interrupt) status and Clear register"]
#[inline(always)]
pub const fn event_intr(
&self,
) -> &'static crate::common::Reg<blell::EventIntr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::EventIntr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(8usize),
)
}
}
#[doc = "Event indications enable."]
#[inline(always)]
pub const fn event_enable(
&self,
) -> &'static crate::common::Reg<blell::EventEnable_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::EventEnable_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16usize),
)
}
}
#[doc = "Advertising parameters register."]
#[inline(always)]
pub const fn adv_params(
&self,
) -> &'static crate::common::Reg<blell::AdvParams_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::AdvParams_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(24usize),
)
}
}
#[doc = "Advertising interval register."]
#[inline(always)]
pub const fn adv_interval_timeout(
&self,
) -> &'static crate::common::Reg<blell::AdvIntervalTimeout_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::AdvIntervalTimeout_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(28usize),
)
}
}
#[doc = "Advertising interrupt status and Clear register"]
#[inline(always)]
pub const fn adv_intr(
&self,
) -> &'static crate::common::Reg<blell::AdvIntr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::AdvIntr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "Advertising next instant."]
#[inline(always)]
pub const fn adv_next_instant(
&self,
) -> &'static crate::common::Reg<blell::AdvNextInstant_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::AdvNextInstant_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
#[doc = "Scan Interval Register"]
#[inline(always)]
pub const fn scan_interval(
&self,
) -> &'static crate::common::Reg<blell::ScanInterval_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ScanInterval_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(40usize),
)
}
}
#[doc = "Scan window Register"]
#[inline(always)]
pub const fn scan_window(
&self,
) -> &'static crate::common::Reg<blell::ScanWindow_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ScanWindow_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(44usize),
)
}
}
#[doc = "Scanning parameters register"]
#[inline(always)]
pub const fn scan_param(
&self,
) -> &'static crate::common::Reg<blell::ScanParam_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ScanParam_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(48usize),
)
}
}
#[doc = "Scan interrupt status and Clear register"]
#[inline(always)]
pub const fn scan_intr(
&self,
) -> &'static crate::common::Reg<blell::ScanIntr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ScanIntr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(56usize),
)
}
}
#[doc = "Advertising next instant."]
#[inline(always)]
pub const fn scan_next_instant(
&self,
) -> &'static crate::common::Reg<blell::ScanNextInstant_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::ScanNextInstant_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(60usize),
)
}
}
#[doc = "Initiator Interval Register"]
#[inline(always)]
pub const fn init_interval(
&self,
) -> &'static crate::common::Reg<blell::InitInterval_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::InitInterval_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(64usize),
)
}
}
#[doc = "Initiator window Register"]
#[inline(always)]
pub const fn init_window(
&self,
) -> &'static crate::common::Reg<blell::InitWindow_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::InitWindow_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(68usize),
)
}
}
#[doc = "Initiator parameters register"]
#[inline(always)]
pub const fn init_param(
&self,
) -> &'static crate::common::Reg<blell::InitParam_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::InitParam_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(72usize),
)
}
}
#[doc = "Scan interrupt status and Clear register"]
#[inline(always)]
pub const fn init_intr(
&self,
) -> &'static crate::common::Reg<blell::InitIntr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::InitIntr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(80usize),
)
}
}
#[doc = "Initiator next instant."]
#[inline(always)]
pub const fn init_next_instant(
&self,
) -> &'static crate::common::Reg<blell::InitNextInstant_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::InitNextInstant_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(84usize),
)
}
}
#[doc = "Lower 16 bit random address of the device."]
#[inline(always)]
pub const fn device_rand_addr_l(
&self,
) -> &'static crate::common::Reg<blell::DeviceRandAddrL_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DeviceRandAddrL_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(88usize),
)
}
}
#[doc = "Middle 16 bit random address of the device."]
#[inline(always)]
pub const fn device_rand_addr_m(
&self,
) -> &'static crate::common::Reg<blell::DeviceRandAddrM_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DeviceRandAddrM_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(92usize),
)
}
}
#[doc = "Higher 16 bit random address of the device."]
#[inline(always)]
pub const fn device_rand_addr_h(
&self,
) -> &'static crate::common::Reg<blell::DeviceRandAddrH_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DeviceRandAddrH_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(96usize),
)
}
}
#[doc = "Lower 16 bit address of the peer device."]
#[inline(always)]
pub const fn peer_addr_l(
&self,
) -> &'static crate::common::Reg<blell::PeerAddrL_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::PeerAddrL_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(104usize),
)
}
}
#[doc = "Middle 16 bit address of the peer device."]
#[inline(always)]
pub const fn peer_addr_m(
&self,
) -> &'static crate::common::Reg<blell::PeerAddrM_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::PeerAddrM_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(108usize),
)
}
}
#[doc = "Higher 16 bit address of the peer device."]
#[inline(always)]
pub const fn peer_addr_h(
&self,
) -> &'static crate::common::Reg<blell::PeerAddrH_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::PeerAddrH_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(112usize),
)
}
}
#[doc = "whitelist address type"]
#[inline(always)]
pub const fn wl_addr_type(
&self,
) -> &'static crate::common::Reg<blell::WlAddrType_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::WlAddrType_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(120usize),
)
}
}
#[doc = "whitelist valid entry bit"]
#[inline(always)]
pub const fn wl_enable(
&self,
) -> &'static crate::common::Reg<blell::WlEnable_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::WlEnable_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(124usize),
)
}
}
#[doc = "Transmit window offset"]
#[inline(always)]
pub const fn transmit_window_offset(
&self,
) -> &'static crate::common::Reg<blell::TransmitWindowOffset_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::TransmitWindowOffset_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(128usize),
)
}
}
#[doc = "Transmit window size"]
#[inline(always)]
pub const fn transmit_window_size(
&self,
) -> &'static crate::common::Reg<blell::TransmitWindowSize_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::TransmitWindowSize_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(132usize),
)
}
}
#[doc = "Data channel map 0 (lower word)"]
#[inline(always)]
pub const fn data_channels_l0(
&self,
) -> &'static crate::common::Reg<blell::DataChannelsL0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DataChannelsL0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(136usize),
)
}
}
#[doc = "Data channel map 0 (middle word)"]
#[inline(always)]
pub const fn data_channels_m0(
&self,
) -> &'static crate::common::Reg<blell::DataChannelsM0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DataChannelsM0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(140usize),
)
}
}
#[doc = "Data channel map 0 (upper word)"]
#[inline(always)]
pub const fn data_channels_h0(
&self,
) -> &'static crate::common::Reg<blell::DataChannelsH0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DataChannelsH0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(144usize),
)
}
}
#[doc = "Data channel map 1 (lower word)"]
#[inline(always)]
pub const fn data_channels_l1(
&self,
) -> &'static crate::common::Reg<blell::DataChannelsL1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DataChannelsL1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(152usize),
)
}
}
#[doc = "Data channel map 1 (middle word)"]
#[inline(always)]
pub const fn data_channels_m1(
&self,
) -> &'static crate::common::Reg<blell::DataChannelsM1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DataChannelsM1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(156usize),
)
}
}
#[doc = "Data channel map 1 (upper word)"]
#[inline(always)]
pub const fn data_channels_h1(
&self,
) -> &'static crate::common::Reg<blell::DataChannelsH1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DataChannelsH1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(160usize),
)
}
}
#[doc = "Connection interrupt status and Clear register"]
#[inline(always)]
pub const fn conn_intr(
&self,
) -> &'static crate::common::Reg<blell::ConnIntr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnIntr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(168usize),
)
}
}
#[doc = "Connection channel status"]
#[inline(always)]
pub const fn conn_status(
&self,
) -> &'static crate::common::Reg<blell::ConnStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::ConnStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(172usize),
)
}
}
#[doc = "Connection Index register"]
#[inline(always)]
pub const fn conn_index(
&self,
) -> &'static crate::common::Reg<blell::ConnIndex_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnIndex_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(176usize),
)
}
}
#[doc = "Wakeup configuration"]
#[inline(always)]
pub const fn wakeup_config(
&self,
) -> &'static crate::common::Reg<blell::WakeupConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::WakeupConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(184usize),
)
}
}
#[doc = "Wakeup control"]
#[inline(always)]
pub const fn wakeup_control(
&self,
) -> &'static crate::common::Reg<blell::WakeupControl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::WakeupControl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(192usize),
)
}
}
#[doc = "Clock control"]
#[inline(always)]
pub const fn clock_config(
&self,
) -> &'static crate::common::Reg<blell::ClockConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ClockConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(196usize),
)
}
}
#[doc = "Reference Clock"]
#[inline(always)]
pub const fn tim_counter_l(
&self,
) -> &'static crate::common::Reg<blell::TimCounterL_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::TimCounterL_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(200usize),
)
}
}
#[doc = "Wakeup configuration extended"]
#[inline(always)]
pub const fn wakeup_config_extd(
&self,
) -> &'static crate::common::Reg<blell::WakeupConfigExtd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::WakeupConfigExtd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(204usize),
)
}
}
#[doc = "BLE Time Control"]
#[inline(always)]
pub const fn poc_reg__tim_control(
&self,
) -> &'static crate::common::Reg<blell::PocRegTimControl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::PocRegTimControl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(216usize),
)
}
}
#[doc = "Advertising data transmit FIFO. Access ADVCH_TX_FIFO."]
#[inline(always)]
pub const fn adv_tx_data_fifo(
&self,
) -> &'static crate::common::Reg<blell::AdvTxDataFifo_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::AdvTxDataFifo_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(224usize),
)
}
}
#[doc = "Advertising scan response data transmit FIFO. Access ADVCH_TX_FIFO."]
#[inline(always)]
pub const fn adv_scn_rsp_tx_fifo(
&self,
) -> &'static crate::common::Reg<blell::AdvScnRspTxFifo_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::AdvScnRspTxFifo_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(232usize),
)
}
}
#[doc = "advertising scan response data receive data FIFO. Access ADVRX_FIFO."]
#[inline(always)]
pub const fn init_scn_adv_rx_fifo(
&self,
) -> &'static crate::common::Reg<blell::InitScnAdvRxFifo_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::InitScnAdvRxFifo_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(248usize),
)
}
}
#[doc = "Connection Interval"]
#[inline(always)]
pub const fn conn_interval(
&self,
) -> &'static crate::common::Reg<blell::ConnInterval_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnInterval_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(256usize),
)
}
}
#[doc = "Supervision timeout"]
#[inline(always)]
pub const fn sup_timeout(
&self,
) -> &'static crate::common::Reg<blell::SupTimeout_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::SupTimeout_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(260usize),
)
}
}
#[doc = "Slave Latency"]
#[inline(always)]
pub const fn slave_latency(
&self,
) -> &'static crate::common::Reg<blell::SlaveLatency_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::SlaveLatency_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(264usize),
)
}
}
#[doc = "Connection event length"]
#[inline(always)]
pub const fn ce_length(
&self,
) -> &'static crate::common::Reg<blell::CeLength_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::CeLength_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(268usize),
)
}
}
#[doc = "Access address (lower)"]
#[inline(always)]
pub const fn pdu_access_addr_l_register(
&self,
) -> &'static crate::common::Reg<blell::PduAccessAddrLRegister_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::PduAccessAddrLRegister_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(272usize),
)
}
}
#[doc = "Access address (upper)"]
#[inline(always)]
pub const fn pdu_access_addr_h_register(
&self,
) -> &'static crate::common::Reg<blell::PduAccessAddrHRegister_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::PduAccessAddrHRegister_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(276usize),
)
}
}
#[doc = "Connection event instant"]
#[inline(always)]
pub const fn conn_ce_instant(
&self,
) -> &'static crate::common::Reg<blell::ConnCeInstant_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnCeInstant_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(280usize),
)
}
}
#[doc = "connection configuration & status register"]
#[inline(always)]
pub const fn ce_cnfg_sts_register(
&self,
) -> &'static crate::common::Reg<blell::CeCnfgStsRegister_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::CeCnfgStsRegister_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(284usize),
)
}
}
#[doc = "Next connection event instant"]
#[inline(always)]
pub const fn next_ce_instant(
&self,
) -> &'static crate::common::Reg<blell::NextCeInstant_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::NextCeInstant_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(288usize),
)
}
}
#[doc = "connection event counter"]
#[inline(always)]
pub const fn conn_ce_counter(
&self,
) -> &'static crate::common::Reg<blell::ConnCeCounter_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::ConnCeCounter_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(292usize),
)
}
}
#[doc = "data list sent update and status"]
#[inline(always)]
pub const fn data_list_sent_update__status(
&self,
) -> &'static crate::common::Reg<blell::DataListSentUpdateStatus_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DataListSentUpdateStatus_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(296usize),
)
}
}
#[doc = "data list ack update and status"]
#[inline(always)]
pub const fn data_list_ack_update__status(
&self,
) -> &'static crate::common::Reg<blell::DataListAckUpdateStatus_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DataListAckUpdateStatus_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(300usize),
)
}
}
#[doc = "connection configuration & status register"]
#[inline(always)]
pub const fn ce_cnfg_sts_register_ext(
&self,
) -> &'static crate::common::Reg<blell::CeCnfgStsRegisterExt_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::CeCnfgStsRegisterExt_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(304usize),
)
}
}
#[doc = "Connection extended interrupt status and Clear register"]
#[inline(always)]
pub const fn conn_ext_intr(
&self,
) -> &'static crate::common::Reg<blell::ConnExtIntr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnExtIntr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(308usize),
)
}
}
#[doc = "Connection Extended Interrupt mask"]
#[inline(always)]
pub const fn conn_ext_intr_mask(
&self,
) -> &'static crate::common::Reg<blell::ConnExtIntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnExtIntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(312usize),
)
}
}
#[doc = "Data buffer descriptor 0 to 4"]
#[inline(always)]
pub const fn data_mem_descriptor(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<blell::DataMemDescriptor_SPEC, crate::common::RW>,
5,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x140usize))
}
}
#[doc = "Window widen for interval"]
#[inline(always)]
pub const fn window_widen_intvl(
&self,
) -> &'static crate::common::Reg<blell::WindowWidenIntvl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::WindowWidenIntvl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(352usize),
)
}
}
#[doc = "Window widen for offset"]
#[inline(always)]
pub const fn window_widen_winoff(
&self,
) -> &'static crate::common::Reg<blell::WindowWidenWinoff_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::WindowWidenWinoff_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(356usize),
)
}
}
#[doc = "Direct Test Mode control"]
#[inline(always)]
pub const fn le_rf_test_mode(
&self,
) -> &'static crate::common::Reg<blell::LeRfTestMode_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::LeRfTestMode_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(368usize),
)
}
}
#[doc = "Direct Test Mode receive packet count"]
#[inline(always)]
pub const fn dtm_rx_pkt_count(
&self,
) -> &'static crate::common::Reg<blell::DtmRxPktCount_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::DtmRxPktCount_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(372usize),
)
}
}
#[doc = "Direct Test Mode control"]
#[inline(always)]
pub const fn le_rf_test_mode_ext(
&self,
) -> &'static crate::common::Reg<blell::LeRfTestModeExt_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::LeRfTestModeExt_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(376usize),
)
}
}
#[doc = "Channel Address register"]
#[inline(always)]
pub const fn txrx_hop(
&self,
) -> &'static crate::common::Reg<blell::TxrxHop_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::TxrxHop_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(392usize),
)
}
}
#[doc = "Transmit/Receive data delay"]
#[inline(always)]
pub const fn tx_rx_on_delay(
&self,
) -> &'static crate::common::Reg<blell::TxRxOnDelay_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::TxRxOnDelay_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(400usize),
)
}
}
#[doc = "ADV packet access code low word"]
#[inline(always)]
pub const fn adv_accaddr_l(
&self,
) -> &'static crate::common::Reg<blell::AdvAccaddrL_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::AdvAccaddrL_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(424usize),
)
}
}
#[doc = "ADV packet access code high word"]
#[inline(always)]
pub const fn adv_accaddr_h(
&self,
) -> &'static crate::common::Reg<blell::AdvAccaddrH_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::AdvAccaddrH_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(428usize),
)
}
}
#[doc = "Advertising channel transmit power setting"]
#[inline(always)]
pub const fn adv_ch_tx_power_lvl_ls(
&self,
) -> &'static crate::common::Reg<blell::AdvChTxPowerLvlLs_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::AdvChTxPowerLvlLs_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(432usize),
)
}
}
#[doc = "Advertising channel transmit power setting extension"]
#[inline(always)]
pub const fn adv_ch_tx_power_lvl_ms(
&self,
) -> &'static crate::common::Reg<blell::AdvChTxPowerLvlMs_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::AdvChTxPowerLvlMs_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(436usize),
)
}
}
#[doc = "Connection channel transmit power setting"]
#[inline(always)]
pub const fn conn_ch_tx_power_lvl_ls(
&self,
) -> &'static crate::common::Reg<blell::ConnChTxPowerLvlLs_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnChTxPowerLvlLs_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(440usize),
)
}
}
#[doc = "Connection channel transmit power setting extension"]
#[inline(always)]
pub const fn conn_ch_tx_power_lvl_ms(
&self,
) -> &'static crate::common::Reg<blell::ConnChTxPowerLvlMs_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnChTxPowerLvlMs_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(444usize),
)
}
}
#[doc = "Device public address lower register"]
#[inline(always)]
pub const fn dev_pub_addr_l(
&self,
) -> &'static crate::common::Reg<blell::DevPubAddrL_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DevPubAddrL_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(448usize),
)
}
}
#[doc = "Device public address middle register"]
#[inline(always)]
pub const fn dev_pub_addr_m(
&self,
) -> &'static crate::common::Reg<blell::DevPubAddrM_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DevPubAddrM_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(452usize),
)
}
}
#[doc = "Device public address higher register"]
#[inline(always)]
pub const fn dev_pub_addr_h(
&self,
) -> &'static crate::common::Reg<blell::DevPubAddrH_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DevPubAddrH_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(456usize),
)
}
}
#[doc = "Offset to first instant"]
#[inline(always)]
pub const fn offset_to_first_instant(
&self,
) -> &'static crate::common::Reg<blell::OffsetToFirstInstant_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::OffsetToFirstInstant_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(464usize),
)
}
}
#[doc = "Advertiser configuration register"]
#[inline(always)]
pub const fn adv_config(
&self,
) -> &'static crate::common::Reg<blell::AdvConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::AdvConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(468usize),
)
}
}
#[doc = "Scan configuration register"]
#[inline(always)]
pub const fn scan_config(
&self,
) -> &'static crate::common::Reg<blell::ScanConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ScanConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(472usize),
)
}
}
#[doc = "Initiator configuration register"]
#[inline(always)]
pub const fn init_config(
&self,
) -> &'static crate::common::Reg<blell::InitConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::InitConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(476usize),
)
}
}
#[doc = "Connection configuration register"]
#[inline(always)]
pub const fn conn_config(
&self,
) -> &'static crate::common::Reg<blell::ConnConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(480usize),
)
}
}
#[doc = "Connection parameter 1"]
#[inline(always)]
pub const fn conn_param1(
&self,
) -> &'static crate::common::Reg<blell::ConnParam1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnParam1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(488usize),
)
}
}
#[doc = "Connection parameter 2"]
#[inline(always)]
pub const fn conn_param2(
&self,
) -> &'static crate::common::Reg<blell::ConnParam2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnParam2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(492usize),
)
}
}
#[doc = "Connection Interrupt mask"]
#[inline(always)]
pub const fn conn_intr_mask(
&self,
) -> &'static crate::common::Reg<blell::ConnIntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnIntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(496usize),
)
}
}
#[doc = "slave timing control"]
#[inline(always)]
pub const fn slave_timing_control(
&self,
) -> &'static crate::common::Reg<blell::SlaveTimingControl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::SlaveTimingControl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(500usize),
)
}
}
#[doc = "Receive trigger control"]
#[inline(always)]
pub const fn receive_trig_ctrl(
&self,
) -> &'static crate::common::Reg<blell::ReceiveTrigCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ReceiveTrigCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(504usize),
)
}
}
#[doc = "LL debug register 1"]
#[inline(always)]
pub const fn ll_dbg_1(
&self,
) -> &'static crate::common::Reg<blell::LlDbg1_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::LlDbg1_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(512usize),
)
}
}
#[doc = "LL debug register 2"]
#[inline(always)]
pub const fn ll_dbg_2(
&self,
) -> &'static crate::common::Reg<blell::LlDbg2_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::LlDbg2_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(516usize),
)
}
}
#[doc = "LL debug register 3"]
#[inline(always)]
pub const fn ll_dbg_3(
&self,
) -> &'static crate::common::Reg<blell::LlDbg3_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::LlDbg3_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(520usize),
)
}
}
#[doc = "LL debug register 4"]
#[inline(always)]
pub const fn ll_dbg_4(
&self,
) -> &'static crate::common::Reg<blell::LlDbg4_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::LlDbg4_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(524usize),
)
}
}
#[doc = "LL debug register 5"]
#[inline(always)]
pub const fn ll_dbg_5(
&self,
) -> &'static crate::common::Reg<blell::LlDbg5_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::LlDbg5_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(528usize),
)
}
}
#[doc = "LL debug register 6"]
#[inline(always)]
pub const fn ll_dbg_6(
&self,
) -> &'static crate::common::Reg<blell::LlDbg6_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::LlDbg6_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(532usize),
)
}
}
#[doc = "LL debug register 7"]
#[inline(always)]
pub const fn ll_dbg_7(
&self,
) -> &'static crate::common::Reg<blell::LlDbg7_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::LlDbg7_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(536usize),
)
}
}
#[doc = "LL debug register 8"]
#[inline(always)]
pub const fn ll_dbg_8(
&self,
) -> &'static crate::common::Reg<blell::LlDbg8_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::LlDbg8_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(540usize),
)
}
}
#[doc = "LL debug register 9"]
#[inline(always)]
pub const fn ll_dbg_9(
&self,
) -> &'static crate::common::Reg<blell::LlDbg9_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::LlDbg9_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(544usize),
)
}
}
#[doc = "LL debug register 10"]
#[inline(always)]
pub const fn ll_dbg_10(
&self,
) -> &'static crate::common::Reg<blell::LlDbg10_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::LlDbg10_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(548usize),
)
}
}
#[doc = "Lower 16 bit address of the peer device for INIT."]
#[inline(always)]
pub const fn peer_addr_init_l(
&self,
) -> &'static crate::common::Reg<blell::PeerAddrInitL_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::PeerAddrInitL_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(560usize),
)
}
}
#[doc = "Middle 16 bit address of the peer device for INIT."]
#[inline(always)]
pub const fn peer_addr_init_m(
&self,
) -> &'static crate::common::Reg<blell::PeerAddrInitM_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::PeerAddrInitM_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(564usize),
)
}
}
#[doc = "Higher 16 bit address of the peer device for INIT."]
#[inline(always)]
pub const fn peer_addr_init_h(
&self,
) -> &'static crate::common::Reg<blell::PeerAddrInitH_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::PeerAddrInitH_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(568usize),
)
}
}
#[doc = "Lower 16 bits of the secondary address of the peer device for ADV_DIR."]
#[inline(always)]
pub const fn peer_sec_addr_adv_l(
&self,
) -> &'static crate::common::Reg<blell::PeerSecAddrAdvL_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::PeerSecAddrAdvL_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(572usize),
)
}
}
#[doc = "Middle 16 bits of the secondary address of the peer device for ADV_DIR."]
#[inline(always)]
pub const fn peer_sec_addr_adv_m(
&self,
) -> &'static crate::common::Reg<blell::PeerSecAddrAdvM_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::PeerSecAddrAdvM_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(576usize),
)
}
}
#[doc = "Higher 16 bits of the secondary address of the peer device for ADV_DIR."]
#[inline(always)]
pub const fn peer_sec_addr_adv_h(
&self,
) -> &'static crate::common::Reg<blell::PeerSecAddrAdvH_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::PeerSecAddrAdvH_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(580usize),
)
}
}
#[doc = "Initiator Window NI timer control"]
#[inline(always)]
pub const fn init_window_timer_ctrl(
&self,
) -> &'static crate::common::Reg<blell::InitWindowTimerCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::InitWindowTimerCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(584usize),
)
}
}
#[doc = "Connection extended configuration register"]
#[inline(always)]
pub const fn conn_config_ext(
&self,
) -> &'static crate::common::Reg<blell::ConnConfigExt_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnConfigExt_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(588usize),
)
}
}
#[doc = "DPLL & CY Correlator configuration register"]
#[inline(always)]
pub const fn dpll_config(
&self,
) -> &'static crate::common::Reg<blell::DpllConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DpllConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(600usize),
)
}
}
#[doc = "Initiator Window NI instant"]
#[inline(always)]
pub const fn init_ni_val(
&self,
) -> &'static crate::common::Reg<blell::InitNiVal_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::InitNiVal_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(608usize),
)
}
}
#[doc = "Initiator Window offset captured at conn request"]
#[inline(always)]
pub const fn init_window_offset(
&self,
) -> &'static crate::common::Reg<blell::InitWindowOffset_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::InitWindowOffset_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(612usize),
)
}
}
#[doc = "Initiator Window NI anchor point captured at conn request"]
#[inline(always)]
pub const fn init_window_ni_anchor_pt(
&self,
) -> &'static crate::common::Reg<blell::InitWindowNiAnchorPt_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::InitWindowNiAnchorPt_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(616usize),
)
}
}
#[doc = "Connection update new interval"]
#[inline(always)]
pub const fn conn_update_new_interval(
&self,
) -> &'static crate::common::Reg<blell::ConnUpdateNewInterval_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnUpdateNewInterval_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(932usize),
)
}
}
#[doc = "Connection update new latency"]
#[inline(always)]
pub const fn conn_update_new_latency(
&self,
) -> &'static crate::common::Reg<blell::ConnUpdateNewLatency_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnUpdateNewLatency_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(936usize),
)
}
}
#[doc = "Connection update new supervision timeout"]
#[inline(always)]
pub const fn conn_update_new_sup_to(
&self,
) -> &'static crate::common::Reg<blell::ConnUpdateNewSupTo_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnUpdateNewSupTo_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(940usize),
)
}
}
#[doc = "Connection update new Slave Latency X Conn interval Value"]
#[inline(always)]
pub const fn conn_update_new_sl_interval(
&self,
) -> &'static crate::common::Reg<blell::ConnUpdateNewSlInterval_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnUpdateNewSlInterval_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(944usize),
)
}
}
#[doc = "Connection request address word 0"]
#[inline(always)]
pub const fn conn_req_word0(
&self,
) -> &'static crate::common::Reg<blell::ConnReqWord0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnReqWord0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(960usize),
)
}
}
#[doc = "Connection request address word 1"]
#[inline(always)]
pub const fn conn_req_word1(
&self,
) -> &'static crate::common::Reg<blell::ConnReqWord1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnReqWord1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(964usize),
)
}
}
#[doc = "Connection request address word 2"]
#[inline(always)]
pub const fn conn_req_word2(
&self,
) -> &'static crate::common::Reg<blell::ConnReqWord2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnReqWord2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(968usize),
)
}
}
#[doc = "Connection request address word 3"]
#[inline(always)]
pub const fn conn_req_word3(
&self,
) -> &'static crate::common::Reg<blell::ConnReqWord3_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnReqWord3_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(972usize),
)
}
}
#[doc = "Connection request address word 4"]
#[inline(always)]
pub const fn conn_req_word4(
&self,
) -> &'static crate::common::Reg<blell::ConnReqWord4_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnReqWord4_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(976usize),
)
}
}
#[doc = "Connection request address word 5"]
#[inline(always)]
pub const fn conn_req_word5(
&self,
) -> &'static crate::common::Reg<blell::ConnReqWord5_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnReqWord5_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(980usize),
)
}
}
#[doc = "Connection request address word 6"]
#[inline(always)]
pub const fn conn_req_word6(
&self,
) -> &'static crate::common::Reg<blell::ConnReqWord6_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnReqWord6_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(984usize),
)
}
}
#[doc = "Connection request address word 7"]
#[inline(always)]
pub const fn conn_req_word7(
&self,
) -> &'static crate::common::Reg<blell::ConnReqWord7_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnReqWord7_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(988usize),
)
}
}
#[doc = "Connection request address word 8"]
#[inline(always)]
pub const fn conn_req_word8(
&self,
) -> &'static crate::common::Reg<blell::ConnReqWord8_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnReqWord8_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(992usize),
)
}
}
#[doc = "Connection request address word 9"]
#[inline(always)]
pub const fn conn_req_word9(
&self,
) -> &'static crate::common::Reg<blell::ConnReqWord9_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnReqWord9_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(996usize),
)
}
}
#[doc = "Connection request address word 10"]
#[inline(always)]
pub const fn conn_req_word10(
&self,
) -> &'static crate::common::Reg<blell::ConnReqWord10_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnReqWord10_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1000usize),
)
}
}
#[doc = "Connection request address word 11"]
#[inline(always)]
pub const fn conn_req_word11(
&self,
) -> &'static crate::common::Reg<blell::ConnReqWord11_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnReqWord11_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1004usize),
)
}
}
#[doc = "PDU response timer/Generic Timer (MMMS mode)"]
#[inline(always)]
pub const fn pdu_resp_timer(
&self,
) -> &'static crate::common::Reg<blell::PduRespTimer_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::PduRespTimer_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2564usize),
)
}
}
#[doc = "Next response timeout instant"]
#[inline(always)]
pub const fn next_resp_timer_exp(
&self,
) -> &'static crate::common::Reg<blell::NextRespTimerExp_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::NextRespTimerExp_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(2568usize),
)
}
}
#[doc = "Next supervision timeout instant"]
#[inline(always)]
pub const fn next_sup_to(
&self,
) -> &'static crate::common::Reg<blell::NextSupTo_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::NextSupTo_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(2572usize),
)
}
}
#[doc = "Feature enable"]
#[inline(always)]
pub const fn llh_feature_config(
&self,
) -> &'static crate::common::Reg<blell::LlhFeatureConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::LlhFeatureConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2576usize),
)
}
}
#[doc = "Window minimum step size"]
#[inline(always)]
pub const fn win_min_step_size(
&self,
) -> &'static crate::common::Reg<blell::WinMinStepSize_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::WinMinStepSize_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2580usize),
)
}
}
#[doc = "Slave window adjustment"]
#[inline(always)]
pub const fn slv_win_adj(
&self,
) -> &'static crate::common::Reg<blell::SlvWinAdj_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::SlvWinAdj_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2584usize),
)
}
}
#[doc = "Slave Latency X Conn Interval Value"]
#[inline(always)]
pub const fn sl_conn_interval(
&self,
) -> &'static crate::common::Reg<blell::SlConnInterval_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::SlConnInterval_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2588usize),
)
}
}
#[doc = "LE Ping connection timer address"]
#[inline(always)]
pub const fn le_ping_timer_addr(
&self,
) -> &'static crate::common::Reg<blell::LePingTimerAddr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::LePingTimerAddr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2592usize),
)
}
}
#[doc = "LE Ping connection timer offset"]
#[inline(always)]
pub const fn le_ping_timer_offset(
&self,
) -> &'static crate::common::Reg<blell::LePingTimerOffset_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::LePingTimerOffset_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(2596usize),
)
}
}
#[doc = "LE Ping timer next expiry instant"]
#[inline(always)]
pub const fn le_ping_timer_next_exp(
&self,
) -> &'static crate::common::Reg<blell::LePingTimerNextExp_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::LePingTimerNextExp_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(2600usize),
)
}
}
#[doc = "LE Ping Timer wrap count"]
#[inline(always)]
pub const fn le_ping_timer_wrap_count(
&self,
) -> &'static crate::common::Reg<blell::LePingTimerWrapCount_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::LePingTimerWrapCount_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(2604usize),
)
}
}
#[doc = "Transmit enable extension delay"]
#[inline(always)]
pub const fn tx_en_ext_delay(
&self,
) -> &'static crate::common::Reg<blell::TxEnExtDelay_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::TxEnExtDelay_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3584usize),
)
}
}
#[doc = "Transmit/Receive enable delay"]
#[inline(always)]
pub const fn tx_rx_synth_delay(
&self,
) -> &'static crate::common::Reg<blell::TxRxSynthDelay_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::TxRxSynthDelay_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3588usize),
)
}
}
#[doc = "External TX PA and RX LNA delay configuration"]
#[inline(always)]
pub const fn ext_pa_lna_dly_cnfg(
&self,
) -> &'static crate::common::Reg<blell::ExtPaLnaDlyCnfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ExtPaLnaDlyCnfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3592usize),
)
}
}
#[doc = "Link Layer additional configuration"]
#[inline(always)]
pub const fn ll_config(
&self,
) -> &'static crate::common::Reg<blell::LlConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::LlConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3600usize),
)
}
}
#[doc = "LL Backward compatibility"]
#[inline(always)]
pub const fn ll_control(
&self,
) -> &'static crate::common::Reg<blell::LlControl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::LlControl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3840usize),
)
}
}
#[doc = "Device Resolvable/Non-Resolvable Private address lower register"]
#[inline(always)]
pub const fn dev_pa_addr_l(
&self,
) -> &'static crate::common::Reg<blell::DevPaAddrL_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DevPaAddrL_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3844usize),
)
}
}
#[doc = "Device Resolvable/Non-Resolvable Private address middle register"]
#[inline(always)]
pub const fn dev_pa_addr_m(
&self,
) -> &'static crate::common::Reg<blell::DevPaAddrM_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DevPaAddrM_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3848usize),
)
}
}
#[doc = "Device Resolvable/Non-Resolvable Private address higher register"]
#[inline(always)]
pub const fn dev_pa_addr_h(
&self,
) -> &'static crate::common::Reg<blell::DevPaAddrH_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::DevPaAddrH_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3852usize),
)
}
}
#[doc = "Resolving list entry control bit"]
#[inline(always)]
pub const fn rslv_list_enable(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<blell::RslvListEnable_SPEC, crate::common::RW>,
16,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xf10usize))
}
}
#[doc = "whitelist valid entry bit"]
#[inline(always)]
pub const fn wl_connection_status(
&self,
) -> &'static crate::common::Reg<blell::WlConnectionStatus_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::WlConnectionStatus_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4000usize),
)
}
}
#[doc = "DLE Connection RX memory base address"]
#[inline(always)]
pub const fn conn_rxmem_base_addr_dle(
&self,
) -> &'static crate::common::Reg<blell::ConnRxmemBaseAddrDle_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnRxmemBaseAddrDle_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(6144usize),
)
}
}
#[doc = "DLE Connection TX memory base address"]
#[inline(always)]
pub const fn conn_txmem_base_addr_dle(
&self,
) -> &'static crate::common::Reg<blell::ConnTxmemBaseAddrDle_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnTxmemBaseAddrDle_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(10240usize),
)
}
}
#[doc = "Connection Parameter memory base address for connection 1"]
#[inline(always)]
pub const fn conn_1_param_mem_base_addr(
&self,
) -> &'static crate::common::Reg<blell::Conn1ParamMemBaseAddr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::Conn1ParamMemBaseAddr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(75776usize),
)
}
}
#[doc = "Connection Parameter memory base address for connection 2"]
#[inline(always)]
pub const fn conn_2_param_mem_base_addr(
&self,
) -> &'static crate::common::Reg<blell::Conn2ParamMemBaseAddr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::Conn2ParamMemBaseAddr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(75904usize),
)
}
}
#[doc = "Connection Parameter memory base address for connection 3"]
#[inline(always)]
pub const fn conn_3_param_mem_base_addr(
&self,
) -> &'static crate::common::Reg<blell::Conn3ParamMemBaseAddr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::Conn3ParamMemBaseAddr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(76032usize),
)
}
}
#[doc = "Connection Parameter memory base address for connection 4"]
#[inline(always)]
pub const fn conn_4_param_mem_base_addr(
&self,
) -> &'static crate::common::Reg<blell::Conn4ParamMemBaseAddr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::Conn4ParamMemBaseAddr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(76160usize),
)
}
}
#[doc = "Next Instant Timer"]
#[inline(always)]
pub const fn ni_timer(
&self,
) -> &'static crate::common::Reg<blell::NiTimer_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::NiTimer_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(81920usize),
)
}
}
#[doc = "Micro-second Offset"]
#[inline(always)]
pub const fn us_offset(
&self,
) -> &'static crate::common::Reg<blell::UsOffset_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::UsOffset_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(81924usize),
)
}
}
#[doc = "Next Connection"]
#[inline(always)]
pub const fn next_conn(
&self,
) -> &'static crate::common::Reg<blell::NextConn_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::NextConn_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(81928usize),
)
}
}
#[doc = "Abort next scheduled connection"]
#[inline(always)]
pub const fn ni_abort(
&self,
) -> &'static crate::common::Reg<blell::NiAbort_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::NiAbort_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(81932usize),
)
}
}
#[doc = "Connection NI Status"]
#[inline(always)]
pub const fn conn_ni_status(
&self,
) -> &'static crate::common::Reg<blell::ConnNiStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::ConnNiStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(81952usize),
)
}
}
#[doc = "Next Supervision timeout Status"]
#[inline(always)]
pub const fn next_sup_to_status(
&self,
) -> &'static crate::common::Reg<blell::NextSupToStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::NextSupToStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(81956usize),
)
}
}
#[doc = "Connection Status"]
#[inline(always)]
pub const fn mmms_conn_status(
&self,
) -> &'static crate::common::Reg<blell::MmmsConnStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::MmmsConnStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(81960usize),
)
}
}
#[doc = "BT Slot Captured Status"]
#[inline(always)]
pub const fn bt_slot_capt_status(
&self,
) -> &'static crate::common::Reg<blell::BtSlotCaptStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::BtSlotCaptStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(81964usize),
)
}
}
#[doc = "Micro-second Capture Status"]
#[inline(always)]
pub const fn us_capt_status(
&self,
) -> &'static crate::common::Reg<blell::UsCaptStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::UsCaptStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(81968usize),
)
}
}
#[doc = "Micro-second Offset Status"]
#[inline(always)]
pub const fn us_offset_status(
&self,
) -> &'static crate::common::Reg<blell::UsOffsetStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::UsOffsetStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(81972usize),
)
}
}
#[doc = "Accumulated Window Widen Status"]
#[inline(always)]
pub const fn accu_window_widen_status(
&self,
) -> &'static crate::common::Reg<blell::AccuWindowWidenStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::AccuWindowWidenStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(81976usize),
)
}
}
#[doc = "Status when early interrupt is raised"]
#[inline(always)]
pub const fn early_intr_status(
&self,
) -> &'static crate::common::Reg<blell::EarlyIntrStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::EarlyIntrStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(81980usize),
)
}
}
#[doc = "Multi-Master Multi-Slave Config"]
#[inline(always)]
pub const fn mmms_config(
&self,
) -> &'static crate::common::Reg<blell::MmmsConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::MmmsConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(81984usize),
)
}
}
#[doc = "Running US of the current BT Slot"]
#[inline(always)]
pub const fn us_counter(
&self,
) -> &'static crate::common::Reg<blell::UsCounter_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::UsCounter_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(81988usize),
)
}
}
#[doc = "Previous captured US of the BT Slot"]
#[inline(always)]
pub const fn us_capt_prev(
&self,
) -> &'static crate::common::Reg<blell::UsCaptPrev_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::UsCaptPrev_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(81992usize),
)
}
}
#[doc = "NI at early interrupt"]
#[inline(always)]
pub const fn early_intr_ni(
&self,
) -> &'static crate::common::Reg<blell::EarlyIntrNi_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::EarlyIntrNi_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(81996usize),
)
}
}
#[doc = "BT slot capture for master connection creation"]
#[inline(always)]
pub const fn mmms_master_create_bt_capt(
&self,
) -> &'static crate::common::Reg<blell::MmmsMasterCreateBtCapt_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::MmmsMasterCreateBtCapt_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(82048usize),
)
}
}
#[doc = "BT slot capture for slave connection creation"]
#[inline(always)]
pub const fn mmms_slave_create_bt_capt(
&self,
) -> &'static crate::common::Reg<blell::MmmsSlaveCreateBtCapt_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::MmmsSlaveCreateBtCapt_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(82052usize),
)
}
}
#[doc = "Micro second capture for slave connection creation"]
#[inline(always)]
pub const fn mmms_slave_create_us_capt(
&self,
) -> &'static crate::common::Reg<blell::MmmsSlaveCreateUsCapt_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::MmmsSlaveCreateUsCapt_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(82056usize),
)
}
}
#[doc = "Data buffer descriptor 0 to 15"]
#[inline(always)]
pub const fn mmms_data_mem_descriptor(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<blell::MmmsDataMemDescriptor_SPEC, crate::common::RW>,
16,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x14100usize))
}
}
#[doc = "data list sent update and status for connection 1"]
#[inline(always)]
pub const fn conn_1_data_list_sent(
&self,
) -> &'static crate::common::Reg<blell::Conn1DataListSent_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::Conn1DataListSent_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82432usize),
)
}
}
#[doc = "data list ack update and status for connection 1"]
#[inline(always)]
pub const fn conn_1_data_list_ack(
&self,
) -> &'static crate::common::Reg<blell::Conn1DataListAck_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::Conn1DataListAck_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82436usize),
)
}
}
#[doc = "Connection specific pause resume for connection 1"]
#[inline(always)]
pub const fn conn_1_ce_data_list_cfg(
&self,
) -> &'static crate::common::Reg<blell::Conn1CeDataListCfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::Conn1CeDataListCfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82440usize),
)
}
}
#[doc = "data list sent update and status for connection 2"]
#[inline(always)]
pub const fn conn_2_data_list_sent(
&self,
) -> &'static crate::common::Reg<blell::Conn2DataListSent_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::Conn2DataListSent_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82448usize),
)
}
}
#[doc = "data list ack update and status for connection 2"]
#[inline(always)]
pub const fn conn_2_data_list_ack(
&self,
) -> &'static crate::common::Reg<blell::Conn2DataListAck_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::Conn2DataListAck_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82452usize),
)
}
}
#[doc = "Connection specific pause resume for connection 2"]
#[inline(always)]
pub const fn conn_2_ce_data_list_cfg(
&self,
) -> &'static crate::common::Reg<blell::Conn2CeDataListCfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::Conn2CeDataListCfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82456usize),
)
}
}
#[doc = "data list sent update and status for connection 3"]
#[inline(always)]
pub const fn conn_3_data_list_sent(
&self,
) -> &'static crate::common::Reg<blell::Conn3DataListSent_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::Conn3DataListSent_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82464usize),
)
}
}
#[doc = "data list ack update and status for connection 3"]
#[inline(always)]
pub const fn conn_3_data_list_ack(
&self,
) -> &'static crate::common::Reg<blell::Conn3DataListAck_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::Conn3DataListAck_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82468usize),
)
}
}
#[doc = "Connection specific pause resume for connection 3"]
#[inline(always)]
pub const fn conn_3_ce_data_list_cfg(
&self,
) -> &'static crate::common::Reg<blell::Conn3CeDataListCfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::Conn3CeDataListCfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82472usize),
)
}
}
#[doc = "data list sent update and status for connection 4"]
#[inline(always)]
pub const fn conn_4_data_list_sent(
&self,
) -> &'static crate::common::Reg<blell::Conn4DataListSent_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::Conn4DataListSent_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82480usize),
)
}
}
#[doc = "data list ack update and status for connection 4"]
#[inline(always)]
pub const fn conn_4_data_list_ack(
&self,
) -> &'static crate::common::Reg<blell::Conn4DataListAck_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::Conn4DataListAck_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82484usize),
)
}
}
#[doc = "Connection specific pause resume for connection 4"]
#[inline(always)]
pub const fn conn_4_ce_data_list_cfg(
&self,
) -> &'static crate::common::Reg<blell::Conn4CeDataListCfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::Conn4CeDataListCfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82488usize),
)
}
}
#[doc = "Enable bits for ADV_NI, SCAN_NI and INIT_NI"]
#[inline(always)]
pub const fn mmms_advch_ni_enable(
&self,
) -> &'static crate::common::Reg<blell::MmmsAdvchNiEnable_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::MmmsAdvchNiEnable_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82944usize),
)
}
}
#[doc = "Next instant valid for ADV, SCAN, INIT"]
#[inline(always)]
pub const fn mmms_advch_ni_valid(
&self,
) -> &'static crate::common::Reg<blell::MmmsAdvchNiValid_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::MmmsAdvchNiValid_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82948usize),
)
}
}
#[doc = "Abort the next instant of ADV, SCAN, INIT"]
#[inline(always)]
pub const fn mmms_advch_ni_abort(
&self,
) -> &'static crate::common::Reg<blell::MmmsAdvchNiAbort_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::MmmsAdvchNiAbort_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82952usize),
)
}
}
#[doc = "Register to configure the supervision timeout for next scheduled connection"]
#[inline(always)]
pub const fn conn_param_next_sup_to(
&self,
) -> &'static crate::common::Reg<blell::ConnParamNextSupTo_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnParamNextSupTo_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82960usize),
)
}
}
#[doc = "Register to configure Accumulated window widening for next scheduled connection"]
#[inline(always)]
pub const fn conn_param_acc_win_widen(
&self,
) -> &'static crate::common::Reg<blell::ConnParamAccWinWiden_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::ConnParamAccWinWiden_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82964usize),
)
}
}
#[doc = "Register to configure offset from connection anchor point at which connection parameter memory should be read"]
#[inline(always)]
pub const fn hw_load_offset(
&self,
) -> &'static crate::common::Reg<blell::HwLoadOffset_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::HwLoadOffset_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(82976usize),
)
}
}
#[doc = "Random number generated by Hardware for ADV NI calculation"]
#[inline(always)]
pub const fn adv_rand(
&self,
) -> &'static crate::common::Reg<blell::AdvRand_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::AdvRand_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(82980usize),
)
}
}
#[doc = "Packet Counter of packets in RX FIFO in MMMS mode"]
#[inline(always)]
pub const fn mmms_rx_pkt_cntr(
&self,
) -> &'static crate::common::Reg<blell::MmmsRxPktCntr_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<blell::MmmsRxPktCntr_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(82984usize),
)
}
}
#[doc = "Packet Counter for Individual connection index"]
#[inline(always)]
pub const fn conn_rx_pkt_cntr(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<blell::ConnRxPktCntr_SPEC, crate::common::R>,
8,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x14430usize))
}
}
#[doc = "Whitelist base address"]
#[inline(always)]
pub const fn whitelist_base_addr(
&self,
) -> &'static crate::common::Reg<blell::WhitelistBaseAddr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::WhitelistBaseAddr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(83968usize),
)
}
}
#[doc = "Resolving list base address for storing Peer Identity address"]
#[inline(always)]
pub const fn rslv_list_peer_idntt_base_addr(
&self,
) -> &'static crate::common::Reg<blell::RslvListPeerIdnttBaseAddr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::RslvListPeerIdnttBaseAddr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(84160usize),
)
}
}
#[doc = "Resolving list base address for storing resolved Peer RPA address"]
#[inline(always)]
pub const fn rslv_list_peer_rpa_base_addr(
&self,
) -> &'static crate::common::Reg<blell::RslvListPeerRpaBaseAddr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::RslvListPeerRpaBaseAddr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(84352usize),
)
}
}
#[doc = "Resolving list base address for storing Resolved received INITA RPA"]
#[inline(always)]
pub const fn rslv_list_rcvd_init_rpa_base_addr(
&self,
) -> &'static crate::common::Reg<blell::RslvListRcvdInitRpaBaseAddr_SPEC, crate::common::RW>
{
unsafe {
crate::common::Reg::<blell::RslvListRcvdInitRpaBaseAddr_SPEC, crate::common::RW>::from_ptr(self._svd2pac_as_ptr().add(84544usize))
}
}
#[doc = "Resolving list base address for storing generated TX INITA RPA"]
#[inline(always)]
pub const fn rslv_list_tx_init_rpa_base_addr(
&self,
) -> &'static crate::common::Reg<blell::RslvListTxInitRpaBaseAddr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<blell::RslvListTxInitRpaBaseAddr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(84736usize),
)
}
}
}
pub mod blell {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CommandRegister_SPEC;
impl crate::sealed::RegSpec for CommandRegister_SPEC {
type DataType = u32;
}
#[doc = "Instruction Register"]
pub type CommandRegister = crate::RegValueT<CommandRegister_SPEC>;
impl CommandRegister {
#[doc = "N/A"]
#[inline(always)]
pub fn command(
self,
) -> crate::common::RegisterField<
0,
0xff,
1,
0,
u8,
u8,
CommandRegister_SPEC,
crate::common::W,
> {
crate::common::RegisterField::<
0,
0xff,
1,
0,
u8,
u8,
CommandRegister_SPEC,
crate::common::W,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CommandRegister {
#[inline(always)]
fn default() -> CommandRegister {
<crate::RegValueT<CommandRegister_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EventIntr_SPEC;
impl crate::sealed::RegSpec for EventIntr_SPEC {
type DataType = u32;
}
#[doc = "Event(Interrupt) status and Clear register"]
pub type EventIntr = crate::RegValueT<EventIntr_SPEC>;
impl EventIntr {
#[doc = "Advertiser interrupt. If bit is set to 1, it indicates an event occurred in the advertising procedure. The source of the event needs to be read from the ADV_INTR register. \nThis bit is cleared, when firmware clears ALL interrupts by writing to the ADV_INTR register."]
#[inline(always)]
pub fn adv_intr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, EventIntr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,EventIntr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Scanner interrupt. If bit is set to 1, it indicates an event occurred in the scanning procedure. The source of the event needs to be read from the SCAN_INTR register. \nThis bit is cleared, when firmware clears ALL interrupts by writing to the SCAN_INTR register."]
#[inline(always)]
pub fn scan_intr(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, EventIntr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,EventIntr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Initiator interrupt. If bit is set to 1, it indicates an event occurred in the initiating procedure. The source of the event needs to be read from the INIT_INTR register. \nThis bit is cleared, when firmware clears ALL interrupts by writing to the INIT_INTR register."]
#[inline(always)]
pub fn init_intr(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, EventIntr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,EventIntr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Connection interrupt. If bit is set to 1, it indicates an event occurred in the connection operation. This interrupt is aggregation of interrupts for all the connections. The source of the event for the specific connection, needs to be read from the CONN_INTR register specific to the connection. This bit is cleared, when firmware clears ALL interrupts by writing to the CONN_INTR register."]
#[inline(always)]
pub fn conn_intr(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, EventIntr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3,1,0,EventIntr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Read: Sleep-mode-exit interrupt. This bit is set, when link layer hardware exits from sleep mode. \nWrite: Clear sleep-mode-exit interrupt. Write to the register with this bit set to 1, clears the interrupt source. \nThis interrupt is deprecated and should not be used."]
#[inline(always)]
pub fn sm_intr(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, EventIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,EventIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Read: Deep sleep mode exit interrupt. This bit is set, when link layer hardware exits from deep sleep mode. \nWrite: Clear deep sleep mode exit interrupt. Write to the register with this bit set to 1, clears the interrupt source."]
#[inline(always)]
pub fn dsm_intr(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, EventIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,EventIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Encryption module interrupt. \nThis interrupt id deprecated and should not be used"]
#[inline(always)]
pub fn enc_intr(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, EventIntr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<6,1,0,EventIntr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "RSSI RX done interrupt."]
#[inline(always)]
pub fn rssi_rx_done_intr(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, EventIntr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<7,1,0,EventIntr_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for EventIntr {
#[inline(always)]
fn default() -> EventIntr {
<crate::RegValueT<EventIntr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EventEnable_SPEC;
impl crate::sealed::RegSpec for EventEnable_SPEC {
type DataType = u32;
}
#[doc = "Event indications enable."]
pub type EventEnable = crate::RegValueT<EventEnable_SPEC>;
impl EventEnable {
#[doc = "Advertiser interrupt enable.\n1 - enable advertiser procedure to interrupt the firmware.\n0 - disable advertiser procedure interrupt to firmware."]
#[inline(always)]
pub fn adv_int_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, EventEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,EventEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Scanner interrupt enable.\n1 - enable scan procedure to interrupt the firmware.\n0 - disable scan procedure interrupt to firmware."]
#[inline(always)]
pub fn scn_int_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, EventEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,EventEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Initiator interrupt enable.\n1 - enable initiator procedure to interrupt the firmware.\n0 - disable initiator procedure interrupt to firmware."]
#[inline(always)]
pub fn init_int_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, EventEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,EventEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Connection interrupt enable. \n1 - enable connection procedure to interrupt the firmware.\n0 - disable connection procedure interrupt to firmware."]
#[inline(always)]
pub fn conn_int_en(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, EventEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,EventEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sleep-mode-exit interrupt enable. \n1 - enable sleep mode exit event to interrupt the firmware.\n0 - disable sleep mode exit interrupt to firmware. \nThis interrupt is deprecated and should not be used."]
#[inline(always)]
pub fn sm_int_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, EventEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,EventEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Deep Sleep-mode-exit interrupt enable. \n1 - enable deep sleep mode exit event to interrupt the firmware.\n0 - disable deep sleep mode exit interrupt to firmware."]
#[inline(always)]
pub fn dsm_int_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, EventEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,EventEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Encryption module interrupt enable. \n1 - Enable encryption module interrupt to firmware.\n0 - disable encryption module interrupt to firmware. \nThis interrupt is deprecated and should not be used"]
#[inline(always)]
pub fn enc_int_en(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, EventEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,EventEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "RSSI Rx interrupt enable. \n1 - Enable RSSI Rx done interrupt to firmware.\n0 - Disable RSSI Rx done interrupt to firmware."]
#[inline(always)]
pub fn rssi_rx_done_int_en(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, EventEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<7,1,0,EventEnable_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for EventEnable {
#[inline(always)]
fn default() -> EventEnable {
<crate::RegValueT<EventEnable_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AdvParams_SPEC;
impl crate::sealed::RegSpec for AdvParams_SPEC {
type DataType = u32;
}
#[doc = "Advertising parameters register."]
pub type AdvParams = crate::RegValueT<AdvParams_SPEC>;
impl AdvParams {
#[doc = "Device own address type. \n1 - Address type is random. \n0 - Address type is public."]
#[inline(always)]
pub fn tx_addr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, AdvParams_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,AdvParams_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The Advertising type is used to determine the packet type that is used for advertising when advertising is enabled. \n0x0 - Connectable undirected advertising. (adv_ind) \n0x1 - Connectable directed advertising (adv_direct_ind). \n0x2 - Discoverable undirected advertising (adv_discover_ind) \n0x3 - Non connectable undirected advertising (adv_nonconn_ind)."]
#[inline(always)]
pub fn adv_type(
self,
) -> crate::common::RegisterField<1, 0x3, 1, 0, u8, u8, AdvParams_SPEC, crate::common::RW>
{
crate::common::RegisterField::<1,0x3,1,0,u8,u8,AdvParams_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Advertising filter policy. The set of devices that the advertising procedure uses for device filtering is called the White List. \n0x0 - Allow scan request from any device, allow connect request from any device. \n0x1 - Allow scan request from devices in white list only, allow connect request from any device. \n0x2 - Allow scan request from any device, allow connect request from devices in white list only. \n0x3 - Allow scan request from devices in white list only, allow connect request from devices in white list only."]
#[inline(always)]
pub fn adv_filt_policy(
self,
) -> crate::common::RegisterField<3, 0x3, 1, 0, u8, u8, AdvParams_SPEC, crate::common::RW>
{
crate::common::RegisterField::<3,0x3,1,0,u8,u8,AdvParams_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Advertising channel map indicates the advertising channels used for advertising. By setting the bit, corresponding channel is enabled for use. Atleast one channel bit should be set. \n7 - enable channel 39. \n6 - enable channel 38. \n5 - enable channel 37."]
#[inline(always)]
pub fn adv_channel_map(
self,
) -> crate::common::RegisterField<5, 0x7, 1, 0, u8, u8, AdvParams_SPEC, crate::common::RW>
{
crate::common::RegisterField::<5,0x7,1,0,u8,u8,AdvParams_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Peer addresses type. This is the Direct_Address_type field programmed, only if ADV_DIRECT_IND type is sent.\n1 - Rx addr type is random.\n0 - Rx addr type is public"]
#[inline(always)]
pub fn rx_addr(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, AdvParams_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,AdvParams_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Peer secondary addresses type. This is the Direct_Address_type field programmed, only if ADV_DIRECT_IND type is sent. This address type corresponds to the PEER_SERC_ADDR register. Valid only if PRIV_1_2_ADV is set.\n1 - Rx secondary addr type is random.\n0 - Rx secondary addr type is public"]
#[inline(always)]
pub fn rx_sec_addr(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, AdvParams_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,AdvParams_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit field is used to specify to the Controller the Low Duty Cycle connectable directed advertising variant being used.\n1 - Low Duty Cycle Connectable Directed Advertising.\n0 - High Duty Cycle Connectable Directed Advertising."]
#[inline(always)]
pub fn adv_low_duty_cycle(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, AdvParams_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,AdvParams_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit field is used to specify the Advertiser behavior on receiving the same INITA in the connect_req as in the ADV_DIRECT_IND packet it sent. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set.\n0 - Accept the connect_req packet\n1 - Reject the connect_req packet"]
#[inline(always)]
pub fn inita_rpa_check(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, AdvParams_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,AdvParams_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Device own address type subtype when Address type is random. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set.\n1 - Random Address type is private. \n0 - Random Address type is static."]
#[inline(always)]
pub fn tx_addr_priv(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, AdvParams_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,AdvParams_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Advertiser behavior when a peer Identity address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set.\n1 - Accept packets with peer identity address not in the Resolving list in privacy mode\n0 - Reject packets with peer identity address not in the Resolving list in privacy mode"]
#[inline(always)]
pub fn adv_rcv_ia_in_priv(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, AdvParams_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<13,1,0,AdvParams_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Advertiser behavior when a peer Non Resolvable Private Address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. This is applicable when whitelist is disabled.\n1 - Only report the packets with peer NRPA address in privacy mode\n0 - Respond to packets with peer NRPA address in privacy mode"]
#[inline(always)]
pub fn adv_rpt_peer_nrpa_addr_in_priv(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, AdvParams_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<14,1,0,AdvParams_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Transmit address field of the received packet extracted from the receive packet. This field is used by firmware to report peer_addr_type parameter in the connection complete event."]
#[inline(always)]
pub fn rcv_tx_addr(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, AdvParams_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<15,1,0,AdvParams_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for AdvParams {
#[inline(always)]
fn default() -> AdvParams {
<crate::RegValueT<AdvParams_SPEC> as RegisterValue<_>>::new(224)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AdvIntervalTimeout_SPEC;
impl crate::sealed::RegSpec for AdvIntervalTimeout_SPEC {
type DataType = u32;
}
#[doc = "Advertising interval register."]
pub type AdvIntervalTimeout = crate::RegValueT<AdvIntervalTimeout_SPEC>;
impl AdvIntervalTimeout {
#[doc = "Range: 0x0020 to 0x4000 (For ADV_IND) \n0x00A0 to 0x4000 (For ADV_SCAN_IND and NONCONN_IND) \nInvalid for ADV_DIRECT_IND \nTime = N * 0.625 msec \nTime Range: 20 ms to 10.24 sec. \nFor directed advertising, firmware programs the default value of 1.28 seconds.\n\nIn MMMS mode, this register is used as ADV_NI_TIMER when the ADV_NI_VALID is set by firmware"]
#[inline(always)]
pub fn adv_interval(
self,
) -> crate::common::RegisterField<
0,
0x7fff,
1,
0,
u16,
u16,
AdvIntervalTimeout_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x7fff,
1,
0,
u16,
u16,
AdvIntervalTimeout_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for AdvIntervalTimeout {
#[inline(always)]
fn default() -> AdvIntervalTimeout {
<crate::RegValueT<AdvIntervalTimeout_SPEC> as RegisterValue<_>>::new(32)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AdvIntr_SPEC;
impl crate::sealed::RegSpec for AdvIntr_SPEC {
type DataType = u32;
}
#[doc = "Advertising interrupt status and Clear register"]
pub type AdvIntr = crate::RegValueT<AdvIntr_SPEC>;
impl AdvIntr {
#[doc = "If this bit is set it indicates a new advertising event started after interval expiry.\nWrite to the register with this bit set to 1, clears the interrupt source."]
#[inline(always)]
pub fn adv_strt_intr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, AdvIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,AdvIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates current advertising event is closed.\nWrite to the register with this bit set to 1, clears the interrupt source."]
#[inline(always)]
pub fn adv_close_intr(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, AdvIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,AdvIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates ADV packet is transmitted. \nWrite to the register with this bit set to 1, clears the interrupt source."]
#[inline(always)]
pub fn adv_tx_intr(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, AdvIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,AdvIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates scan response packet transmitted in response to previous scan request packet received.\nWrite to the register with this bit set to 1, clears the interrupt source."]
#[inline(always)]
pub fn scan_rsp_tx_intr(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, AdvIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,AdvIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates scan request packet received.\nWrite to the register with this bit set to 1, clears the interrupt source."]
#[inline(always)]
pub fn scan_req_rx_intr(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, AdvIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,AdvIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates connect request packet is received.\nWrite to the register with this bit set to 1, clears the interrupt source."]
#[inline(always)]
pub fn conn_req_rx_intr(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, AdvIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,AdvIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that connection is created as slave. \nWrite to the register with this bit set to 1, clears the interrupt source.\nNote: On a slave connection creation, the link layer cannot enter deepsleep mode in the same slot . It can enter deepsleep mode only in the subsequent slots."]
#[inline(always)]
pub fn slv_connected(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, AdvIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,AdvIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that the directed advertising event has timed out after 1.28 seconds. Applicable in adv_direct_ind advertising. \nWrite to the register with this bit set to 1, clears the interrupt source."]
#[inline(always)]
pub fn adv_timeout(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, AdvIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,AdvIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Advertiser procedure is ON in hardware. Indicates that advertiser procedure is ON in hardware.\n1 - ON\n0 - OFF"]
#[inline(always)]
pub fn adv_on(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, AdvIntr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8,1,0,AdvIntr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that connection is created as slave, but the peer device Resolvable Private Address is not resolved/ ID or NRPA are not matched yet. If the address is not resolved prior to connection establishment, the connection will be terminated.\nWrite to the register with this bit set to 1, clears the interrupt source. \nThis bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set."]
#[inline(always)]
pub fn slv_conn_peer_rpa_unmch_intr(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, AdvIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,AdvIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates scan request packet received, but the peer device Resolvable Private Address is not resolved/ ID or NRPA are not matched yet. \nWrite to the register with this bit set to 1, clears the interrupt source. \nThis bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set."]
#[inline(always)]
pub fn scan_req_rx_peer_rpa_unmch_intr(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, AdvIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,AdvIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that an Identity address is received from a Scanner and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the Scanner\nWrite to the register with this bit set to 1, clears the interrupt source.\nThis bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set."]
#[inline(always)]
pub fn init_addr_match_priv_mismatch_intr(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, AdvIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,AdvIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator\nWrite to the register with this bit set to 1, clears the interrupt source.\nThis bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set."]
#[inline(always)]
pub fn scan_addr_match_priv_mismatch_intr(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, AdvIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,AdvIntr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for AdvIntr {
#[inline(always)]
fn default() -> AdvIntr {
<crate::RegValueT<AdvIntr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AdvNextInstant_SPEC;
impl crate::sealed::RegSpec for AdvNextInstant_SPEC {
type DataType = u32;
}
#[doc = "Advertising next instant."]
pub type AdvNextInstant = crate::RegValueT<AdvNextInstant_SPEC>;
impl AdvNextInstant {
#[doc = "Shows the next start of advertising event with reference to the internal reference clock."]
#[inline(always)]
pub fn adv_next_instant(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
AdvNextInstant_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
AdvNextInstant_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for AdvNextInstant {
#[inline(always)]
fn default() -> AdvNextInstant {
<crate::RegValueT<AdvNextInstant_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ScanInterval_SPEC;
impl crate::sealed::RegSpec for ScanInterval_SPEC {
type DataType = u32;
}
#[doc = "Scan Interval Register"]
pub type ScanInterval = crate::RegValueT<ScanInterval_SPEC>;
impl ScanInterval {
#[doc = "Scan interval register. Interval between two consecutive scanning events. Firmware sets the scanning interval value to this register before issuing start scan command.\nRange: 0x0004 to 0x4000 \nDefault: 0x0010 (10 ms) \nTime = N * 0.625 msec \nTime Range: 2.5 msec to 10.24 sec.\n\nIn MMMS mode, this register is used as SCAN_NI_TIMER when the SCAN_NI_VALID is set by firmware"]
#[inline(always)]
pub fn scan_interval(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ScanInterval_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ScanInterval_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ScanInterval {
#[inline(always)]
fn default() -> ScanInterval {
<crate::RegValueT<ScanInterval_SPEC> as RegisterValue<_>>::new(16)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ScanWindow_SPEC;
impl crate::sealed::RegSpec for ScanWindow_SPEC {
type DataType = u32;
}
#[doc = "Scan window Register"]
pub type ScanWindow = crate::RegValueT<ScanWindow_SPEC>;
impl ScanWindow {
#[doc = "Duration of scan in a scanning event, which should be less than or equal to scan interval value. Firmware sets the scan window value to this register before issuing start scan command.\nRange: 0x0004 to 0x4000 \nDefault: 0x0010 (10 ms) \nTime = N * 0.625 msec \nTime Range: 2.5 msec to 10.24 sec.\n(To prevent ADV RX - SCAN REQ TX - SCAN RSP RX spilling over across the scan window, when not in continuous scan, the scan window must be 2 slots less that the scan interval."]
#[inline(always)]
pub fn scan_window(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ScanWindow_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ScanWindow_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ScanWindow {
#[inline(always)]
fn default() -> ScanWindow {
<crate::RegValueT<ScanWindow_SPEC> as RegisterValue<_>>::new(16)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ScanParam_SPEC;
impl crate::sealed::RegSpec for ScanParam_SPEC {
type DataType = u32;
}
#[doc = "Scanning parameters register"]
pub type ScanParam = crate::RegValueT<ScanParam_SPEC>;
impl ScanParam {
#[doc = "Device\'s own address type. \n1 - addr type is random. \n0 - addr type is public."]
#[inline(always)]
pub fn tx_addr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ScanParam_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ScanParam_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "0x00 - passive scanning.(default) \n0x01 - active scanning. \n0x10 - RFU \n0x11 - RFU"]
#[inline(always)]
pub fn scan_type(
self,
) -> crate::common::RegisterField<1, 0x3, 1, 0, u8, u8, ScanParam_SPEC, crate::common::RW>
{
crate::common::RegisterField::<1,0x3,1,0,u8,u8,ScanParam_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The scanner filter policy determines how the scanner processes advertising packets. \n0x00 - Accept advertising packets from any device. \n0x01 - Accept advertising packets from only devices in the whitelist. \nIn the above 2 policies, the directed advertising packets which are not addressed to this device are ignored.\n0x10 - Accept all undirected advertising packets and directed advertising packet addressed to this device. \n0x11 - Accept undirected advertising packets from devices in the whitelist and directed advertising packet addressed to this device\nIn the above 2 policies, the directed advertising packets where the initiator address is a resolvable private address are accepted. The above 2 policies are extended scanner filter policies."]
#[inline(always)]
pub fn scan_filt_policy(
self,
) -> crate::common::RegisterField<3, 0x3, 1, 0, u8, u8, ScanParam_SPEC, crate::common::RW>
{
crate::common::RegisterField::<3,0x3,1,0,u8,u8,ScanParam_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Filter duplicate packets.\n1- Duplicate filtering enabled. \n0- Duplicate filtering not enabled.\nThis field is derived from the LE_set_scan_enable command."]
#[inline(always)]
pub fn dup_filt_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ScanParam_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,ScanParam_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit field is used to specify the Scanner duplicate filter behavior for ADV_DIRECT_IND packet when duplicate DUP_FILT_EN is set. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.\n0 - Do not filter ADV_DIRECT_IND duplicate packets.\n1 - Filter ADV_DIRECT_IND duplicate packets"]
#[inline(always)]
pub fn dup_filt_chk_adv_dir(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, ScanParam_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,ScanParam_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit field is used to specify the Scanner behavior with respect to ADVA while receiving a SCAN_RSP packet. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.\n0 - The ADVA in SCAN_RSP packets are not verified\n1 - The ADVA in SCAN_RSP packets are verified against ADVA received in ADV packet . If it fails, then abort the packet."]
#[inline(always)]
pub fn scan_rsp_adva_check(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, ScanParam_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,ScanParam_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Scanner behavior when a peer Identity address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.\n1 - Accept packets with peer identity address not in the Resolving list in privacy mode\n0 - Reject packets with peer identity address not in the Resolving list in privacy mode"]
#[inline(always)]
pub fn scan_rcv_ia_in_priv(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, ScanParam_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,ScanParam_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Scanner behavior when a peer Non Resolvable Private Address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. This is applicable when whitelist is disabled.\n1 - Only report packets with peer NRPA address in privacy mode\n0 - Respond packets with peer NRPA address in privacy mode"]
#[inline(always)]
pub fn scan_rpt_peer_nrpa_addr_in_priv(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, ScanParam_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,ScanParam_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ScanParam {
#[inline(always)]
fn default() -> ScanParam {
<crate::RegValueT<ScanParam_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ScanIntr_SPEC;
impl crate::sealed::RegSpec for ScanIntr_SPEC {
type DataType = u32;
}
#[doc = "Scan interrupt status and Clear register"]
pub type ScanIntr = crate::RegValueT<ScanIntr_SPEC>;
impl ScanIntr {
#[doc = "If this bit is set it indicates scan window is opened.\nWrite to the register with this bit set to 1, clears the interrupt source."]
#[inline(always)]
pub fn scan_strt_intr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ScanIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ScanIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates scan window is closed.\nWrite to the register with this bit set to 1, clears the interrupt source."]
#[inline(always)]
pub fn scan_close_intr(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ScanIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ScanIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates scan request packet is transmitted. \nWrite to the register with this bit set to 1, clears the interrupt source."]
#[inline(always)]
pub fn scan_tx_intr(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ScanIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,ScanIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates ADV packet received. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO.\nWrite to the register with this bit set to 1, clears the interrupt source.\nThis interrupt is generated while active/passive scanning upon receiving adv packets.\nNote: Any ADV RX interrupt received after issuing SCAN_STOP command must be ignored and the ADVCH FIFO flushed."]
#[inline(always)]
pub fn adv_rx_intr(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ScanIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,ScanIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates SCAN_RSP packet is received. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO.\nWrite to the register with this bit set to 1, clears the interrupt source. \nNOTE: This interrupt is generated while active scanning upon receiving scan response packet."]
#[inline(always)]
pub fn scan_rsp_rx_intr(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ScanIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,ScanIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates ADV packet received but the peer device Address is not match yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.\nWrite to the register with this bit set to 1, clears the interrupt source.\nThis interrupt is generated while active/passive scanning upon receiving adv packets."]
#[inline(always)]
pub fn adv_rx_peer_rpa_unmch_intr(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ScanIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,ScanIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates ADV_DIRECT packet received but the self device Resolvable Private Address is not resolved yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.\nWrite to the register with this bit set to 1, clears the interrupt source.\nThis interrupt is generated while active/passive scanning upon receiving adv_direct packets."]
#[inline(always)]
pub fn adv_rx_self_rpa_unmch_intr(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, ScanIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,ScanIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that a valid ScanA RPA to be transmitted in SCAN_REQ packet in response to an ADV packet is not present in the resolving list\nWrite to the register with this bit set to 1, clears the interrupt source.\nThis bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set."]
#[inline(always)]
pub fn scana_tx_addr_not_set_intr(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, ScanIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,ScanIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Scan procedure status. \n1 - scan procedure is active. \n0 - scan procedure is not active."]
#[inline(always)]
pub fn scan_on(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, ScanIntr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8,1,0,ScanIntr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator\nWrite to the register with this bit set to 1, clears the interrupt source.\nThis bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set."]
#[inline(always)]
pub fn peer_addr_match_priv_mismatch_intr(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, ScanIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,ScanIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that the self Identity address is received from an initiator and matches, but self IRK is set and hence a corresponding RPA is expected from the initiator\nWrite to the register with this bit set to 1, clears the interrupt source.\nThis bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set."]
#[inline(always)]
pub fn self_addr_match_priv_mismatch_intr(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, ScanIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,ScanIntr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ScanIntr {
#[inline(always)]
fn default() -> ScanIntr {
<crate::RegValueT<ScanIntr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ScanNextInstant_SPEC;
impl crate::sealed::RegSpec for ScanNextInstant_SPEC {
type DataType = u32;
}
#[doc = "Advertising next instant."]
pub type ScanNextInstant = crate::RegValueT<ScanNextInstant_SPEC>;
impl ScanNextInstant {
#[doc = "Shows the instant with respect to internal reference clock of resolution 625 us at which next scanning event begins."]
#[inline(always)]
pub fn next_scan_instant(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ScanNextInstant_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ScanNextInstant_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ScanNextInstant {
#[inline(always)]
fn default() -> ScanNextInstant {
<crate::RegValueT<ScanNextInstant_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InitInterval_SPEC;
impl crate::sealed::RegSpec for InitInterval_SPEC {
type DataType = u32;
}
#[doc = "Initiator Interval Register"]
pub type InitInterval = crate::RegValueT<InitInterval_SPEC>;
impl InitInterval {
#[doc = "Initiator interval register. Firmware sets the initiator\'s scanning interval value to this regis-ter before issuing create connection command. Interval between two consecutive scanning events.\nRange: 0x0004 to 0x4000 \nTime = N * 0.625 msec \nTime Range: 2.5 msec to 10.24 sec.\n\nIn MMMS mode, this register is used as INIT_NI_TIMER when the INIT_NI_VALID is set by firmware"]
#[inline(always)]
pub fn init_scan_interval(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
InitInterval_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
InitInterval_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for InitInterval {
#[inline(always)]
fn default() -> InitInterval {
<crate::RegValueT<InitInterval_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InitWindow_SPEC;
impl crate::sealed::RegSpec for InitWindow_SPEC {
type DataType = u32;
}
#[doc = "Initiator window Register"]
pub type InitWindow = crate::RegValueT<InitWindow_SPEC>;
impl InitWindow {
#[doc = "Duration of scan in a scanning event, which should be less than or equal to scan interval value. Firmware sets the scan window value to this register before issuing create connection command.\nRange: 0x0004 to 0x4000 \nTime = N * 0.625 msec \nTime Range: 2.5 msec to 10.24 sec.\n\nIn MMMS mode, this register is used as INIT_NI_TIMER when the INIT_NI_VALID is set by firmware"]
#[inline(always)]
pub fn init_scan_window(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
InitWindow_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
InitWindow_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for InitWindow {
#[inline(always)]
fn default() -> InitWindow {
<crate::RegValueT<InitWindow_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InitParam_SPEC;
impl crate::sealed::RegSpec for InitParam_SPEC {
type DataType = u32;
}
#[doc = "Initiator parameters register"]
pub type InitParam = crate::RegValueT<InitParam_SPEC>;
impl InitParam {
#[doc = "Device\' own address type. \n1 - addr type is random. \n0 - addr type is public."]
#[inline(always)]
pub fn tx_addr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, InitParam_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,InitParam_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Peer address type.\nThe rx_addr field is updated by the receiver with the address type of the received connectable advertising packet.\n1 - addr type is random. \n0 - addr type is public."]
#[inline(always)]
pub fn rx_addr__rx_tx_addr(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, InitParam_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,InitParam_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The Initiator_Filter_Policy is used to determine whether the White List is used or not.\n0 - White list is not used to determine which advertiser to connect to. Instead the Peer_Address_Type and Peer Address fields are used to specify the address type and address of the advertising device to connect to.\n1 - White list is used to determine the advertising device to connect to.\nPeer_Address_Type and Peer_Address fields are ignored when whitelist is used."]
#[inline(always)]
pub fn init_filt_policy(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, InitParam_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,InitParam_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Init behavior when a peer Identity address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set.\n1 - Accept packets with peer identity address not in the Resolving list in privacy mode\n0 - Reject packets with peer identity address not in the Resolving list in privacy mode & HW_RSLV_LIST_FULL is not set"]
#[inline(always)]
pub fn init_rcv_ia_in_priv(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, InitParam_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,InitParam_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for InitParam {
#[inline(always)]
fn default() -> InitParam {
<crate::RegValueT<InitParam_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InitIntr_SPEC;
impl crate::sealed::RegSpec for InitIntr_SPEC {
type DataType = u32;
}
#[doc = "Scan interrupt status and Clear register"]
pub type InitIntr = crate::RegValueT<InitIntr_SPEC>;
impl InitIntr {
#[doc = "If this bit is set it indicates initiator scan window has started.\nWrite to the register with this bit set to 1, clears the interrupt source."]
#[inline(always)]
pub fn init_interval_expire_intr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, InitIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,InitIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates initiator scan window has finished.\nWrite to the register with this bit set to 1, clears the interrupt source."]
#[inline(always)]
pub fn init_close_window_inr(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, InitIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,InitIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates initiator packet (CONREQ) transmission has started.\nWrite to the register with this bit set to 1, clears the interrupt source."]
#[inline(always)]
pub fn init_tx_start_intr(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, InitIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,InitIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates connection is created as master. \nWrite to the register with this bit set to 1, clears the interrupt source."]
#[inline(always)]
pub fn master_conn_created(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, InitIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,InitIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates ADV_DIRECT packet received but the self device Resolvable Private Address is not resolved yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set.\nWrite to the register with this bit set to 1, clears the interrupt source.\nThis interrupt is generated while active/passive scanning upon receiving adv packets."]
#[inline(always)]
pub fn adv_rx_self_addr_unmch_intr(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, InitIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,InitIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates ADV packet received but the peer device Address is not matched yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set.\nWrite to the register with this bit set to 1, clears the interrupt source.\nThis interrupt is generated while active/passive scanning upon receiving adv packets."]
#[inline(always)]
pub fn adv_rx_peer_addr_unmch_intr(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, InitIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,InitIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that a valid INITA RPA to be transmitted in CONN_REQ packet in response to an ADV packet is not present in the resolving list\nWrite to the register with this bit set to 1, clears the interrupt source.\nThis bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set."]
#[inline(always)]
pub fn inita_tx_addr_not_set_intr(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, InitIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,InitIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator\nWrite to the register with this bit set to 1, clears the interrupt source.\nThis bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set."]
#[inline(always)]
pub fn ini_peer_addr_match_priv_mismatch_intr(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, InitIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,InitIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that \n- an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator\n- or an RPA is received from an initiator and matches an entry in the resolving list, but peer IRK is not set and hence a corresponding Identity address is expected from the initiator\nWrite to the register with this bit set to 1, clears the interrupt source.\nThis bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set."]
#[inline(always)]
pub fn ini_self_addr_match_priv_mismatch_intr(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, InitIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,InitIntr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for InitIntr {
#[inline(always)]
fn default() -> InitIntr {
<crate::RegValueT<InitIntr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InitNextInstant_SPEC;
impl crate::sealed::RegSpec for InitNextInstant_SPEC {
type DataType = u32;
}
#[doc = "Initiator next instant."]
pub type InitNextInstant = crate::RegValueT<InitNextInstant_SPEC>;
impl InitNextInstant {
#[doc = "Shows the instant with respect to internal reference clock of resolution 625 us at which next initiator scanning event begins."]
#[inline(always)]
pub fn init_next_instant(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
InitNextInstant_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
InitNextInstant_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for InitNextInstant {
#[inline(always)]
fn default() -> InitNextInstant {
<crate::RegValueT<InitNextInstant_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DeviceRandAddrL_SPEC;
impl crate::sealed::RegSpec for DeviceRandAddrL_SPEC {
type DataType = u32;
}
#[doc = "Lower 16 bit random address of the device."]
pub type DeviceRandAddrL = crate::RegValueT<DeviceRandAddrL_SPEC>;
impl DeviceRandAddrL {
#[doc = "Lower 16 bit of 48-bit random address of the device."]
#[inline(always)]
pub fn device_rand_addr_l(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
DeviceRandAddrL_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
DeviceRandAddrL_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DeviceRandAddrL {
#[inline(always)]
fn default() -> DeviceRandAddrL {
<crate::RegValueT<DeviceRandAddrL_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DeviceRandAddrM_SPEC;
impl crate::sealed::RegSpec for DeviceRandAddrM_SPEC {
type DataType = u32;
}
#[doc = "Middle 16 bit random address of the device."]
pub type DeviceRandAddrM = crate::RegValueT<DeviceRandAddrM_SPEC>;
impl DeviceRandAddrM {
#[doc = "Middle 16 bit of 48-bit random address of the device."]
#[inline(always)]
pub fn device_rand_addr_m(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
DeviceRandAddrM_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
DeviceRandAddrM_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DeviceRandAddrM {
#[inline(always)]
fn default() -> DeviceRandAddrM {
<crate::RegValueT<DeviceRandAddrM_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DeviceRandAddrH_SPEC;
impl crate::sealed::RegSpec for DeviceRandAddrH_SPEC {
type DataType = u32;
}
#[doc = "Higher 16 bit random address of the device."]
pub type DeviceRandAddrH = crate::RegValueT<DeviceRandAddrH_SPEC>;
impl DeviceRandAddrH {
#[doc = "Higher 16 bit of 48-bit random address of the device."]
#[inline(always)]
pub fn device_rand_addr_h(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
DeviceRandAddrH_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
DeviceRandAddrH_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DeviceRandAddrH {
#[inline(always)]
fn default() -> DeviceRandAddrH {
<crate::RegValueT<DeviceRandAddrH_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PeerAddrL_SPEC;
impl crate::sealed::RegSpec for PeerAddrL_SPEC {
type DataType = u32;
}
#[doc = "Lower 16 bit address of the peer device."]
pub type PeerAddrL = crate::RegValueT<PeerAddrL_SPEC>;
impl PeerAddrL {
#[doc = "Lower 16 bit of 48-bit address of the peer device."]
#[inline(always)]
pub fn peer_addr_l(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
PeerAddrL_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
PeerAddrL_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PeerAddrL {
#[inline(always)]
fn default() -> PeerAddrL {
<crate::RegValueT<PeerAddrL_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PeerAddrM_SPEC;
impl crate::sealed::RegSpec for PeerAddrM_SPEC {
type DataType = u32;
}
#[doc = "Middle 16 bit address of the peer device."]
pub type PeerAddrM = crate::RegValueT<PeerAddrM_SPEC>;
impl PeerAddrM {
#[doc = "Middle 16 bit of 48-bit address of the peer device."]
#[inline(always)]
pub fn peer_addr_m(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
PeerAddrM_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
PeerAddrM_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PeerAddrM {
#[inline(always)]
fn default() -> PeerAddrM {
<crate::RegValueT<PeerAddrM_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PeerAddrH_SPEC;
impl crate::sealed::RegSpec for PeerAddrH_SPEC {
type DataType = u32;
}
#[doc = "Higher 16 bit address of the peer device."]
pub type PeerAddrH = crate::RegValueT<PeerAddrH_SPEC>;
impl PeerAddrH {
#[doc = "Higher 16 bit of 48-bit address of the peer device.\nThe peer address registers are used for multiple purposes. The register is written by firmware to provide the peer address to be used for a hardware procedure. When firmware reads the register, it reads back peer address values updated by hardware. \n\nWhile doing directed Advertising, the firmware writes the peer address of the device specified by the Di-rect_Address parameter of the LE_Set_Advertising_Parameters command. \n\nIn non MMMS mode, While device is configured as an initiator without white list filtering, the peer address specified in the peer_address field of the create connection command is programmed into this register, which is used by hard-ware procedures.\n\nIn non MMMS mode, While device is configured as an initiator and white list is enabled, firmware can read this register to get the address of the peer device from which connectable ADV packet was received and to which the connection is created. \n\nWhen a connection is created as a slave, the firmware can read this register to get the address of the peer de-vice to which connection is created."]
#[inline(always)]
pub fn peer_addr_h(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
PeerAddrH_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
PeerAddrH_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PeerAddrH {
#[inline(always)]
fn default() -> PeerAddrH {
<crate::RegValueT<PeerAddrH_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WlAddrType_SPEC;
impl crate::sealed::RegSpec for WlAddrType_SPEC {
type DataType = u32;
}
#[doc = "whitelist address type"]
pub type WlAddrType = crate::RegValueT<WlAddrType_SPEC>;
impl WlAddrType {
#[doc = "8 address type bits corresponding to the device address stored.\n1 - Address type is random.\n0 - Address type is public."]
#[inline(always)]
pub fn wl_addr_type(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
WlAddrType_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
WlAddrType_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for WlAddrType {
#[inline(always)]
fn default() -> WlAddrType {
<crate::RegValueT<WlAddrType_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WlEnable_SPEC;
impl crate::sealed::RegSpec for WlEnable_SPEC {
type DataType = u32;
}
#[doc = "whitelist valid entry bit"]
pub type WlEnable = crate::RegValueT<WlEnable_SPEC>;
impl WlEnable {
#[doc = "Stores the valid entry bit corresponding to each of the eight device address stored in the whitelist.\n1 - White list entry is Valid\n0 - White list entry is Invalid"]
#[inline(always)]
pub fn wl_enable(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, WlEnable_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
WlEnable_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for WlEnable {
#[inline(always)]
fn default() -> WlEnable {
<crate::RegValueT<WlEnable_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TransmitWindowOffset_SPEC;
impl crate::sealed::RegSpec for TransmitWindowOffset_SPEC {
type DataType = u32;
}
#[doc = "Transmit window offset"]
pub type TransmitWindowOffset = crate::RegValueT<TransmitWindowOffset_SPEC>;
impl TransmitWindowOffset {
#[doc = "This is used to determine the first anchor point for the master transmission, from the time of connection creation.\nRange: This shall be a multiple of 1.25 ms in the range of 0 ms to connInterval value."]
#[inline(always)]
pub fn tx_window_offset(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
TransmitWindowOffset_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
TransmitWindowOffset_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for TransmitWindowOffset {
#[inline(always)]
fn default() -> TransmitWindowOffset {
<crate::RegValueT<TransmitWindowOffset_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TransmitWindowSize_SPEC;
impl crate::sealed::RegSpec for TransmitWindowSize_SPEC {
type DataType = u32;
}
#[doc = "Transmit window size"]
pub type TransmitWindowSize = crate::RegValueT<TransmitWindowSize_SPEC>;
impl TransmitWindowSize {
#[doc = "window_size along with the window_offset is used to calculate the first connection point anchor point for the master.\nThis shall be a multiple of 1.25 ms in the range of 1.25 ms to the lesser of 10 ms and (connInterval - 1.25 ms).\nValues range from 0 to 10 ms."]
#[inline(always)]
pub fn tx_window_size(
self,
) -> crate::common::RegisterField<
0,
0xff,
1,
0,
u8,
u8,
TransmitWindowSize_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xff,
1,
0,
u8,
u8,
TransmitWindowSize_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for TransmitWindowSize {
#[inline(always)]
fn default() -> TransmitWindowSize {
<crate::RegValueT<TransmitWindowSize_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DataChannelsL0_SPEC;
impl crate::sealed::RegSpec for DataChannelsL0_SPEC {
type DataType = u32;
}
#[doc = "Data channel map 0 (lower word)"]
pub type DataChannelsL0 = crate::RegValueT<DataChannelsL0_SPEC>;
impl DataChannelsL0 {
#[doc = "This register field indicates which of the data channels are in use. This stores the information for the lower 16 (15:0) data channel indices.\n\'1\' indicates the corresponding data channel is used and \'0\' indicates the channel is unused."]
#[inline(always)]
pub fn data_channels_l0(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
DataChannelsL0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
DataChannelsL0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DataChannelsL0 {
#[inline(always)]
fn default() -> DataChannelsL0 {
<crate::RegValueT<DataChannelsL0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DataChannelsM0_SPEC;
impl crate::sealed::RegSpec for DataChannelsM0_SPEC {
type DataType = u32;
}
#[doc = "Data channel map 0 (middle word)"]
pub type DataChannelsM0 = crate::RegValueT<DataChannelsM0_SPEC>;
impl DataChannelsM0 {
#[doc = "This register field indicates which of the data channels are in use. This stores the information for the middle 16 (32:16) data channel indices.\n\'1\' indicates the corresponding data channel is used and \'0\' indicates the channel is unused."]
#[inline(always)]
pub fn data_channels_m0(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
DataChannelsM0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
DataChannelsM0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DataChannelsM0 {
#[inline(always)]
fn default() -> DataChannelsM0 {
<crate::RegValueT<DataChannelsM0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DataChannelsH0_SPEC;
impl crate::sealed::RegSpec for DataChannelsH0_SPEC {
type DataType = u32;
}
#[doc = "Data channel map 0 (upper word)"]
pub type DataChannelsH0 = crate::RegValueT<DataChannelsH0_SPEC>;
impl DataChannelsH0 {
#[doc = "This register field indicates which of the data channels are in use. This stores the information for the upper 5 (36:32) data channel indices.\n\'1\' indicates the corresponding data channel is used and \'0\' indicates the channel is unused.\nNote: The Data channel map 0 and data channel map 1 are two sets of channel maps stored, common for all the connections. At any given time, only two maps can be maintained and the connections will use one of the two sets as indicated by the channel map index field in the CE_CNFG_STS registers specific to the link. Firmware must also manage to update this field along with the map."]
#[inline(always)]
pub fn data_channels_h0(
self,
) -> crate::common::RegisterField<
0,
0x1f,
1,
0,
u8,
u8,
DataChannelsH0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1f,
1,
0,
u8,
u8,
DataChannelsH0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DataChannelsH0 {
#[inline(always)]
fn default() -> DataChannelsH0 {
<crate::RegValueT<DataChannelsH0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DataChannelsL1_SPEC;
impl crate::sealed::RegSpec for DataChannelsL1_SPEC {
type DataType = u32;
}
#[doc = "Data channel map 1 (lower word)"]
pub type DataChannelsL1 = crate::RegValueT<DataChannelsL1_SPEC>;
impl DataChannelsL1 {
#[doc = "This register field indicates which of the data channels are in use. This stores the information for the lower 16 (15:0) data channel indices.\n\'1\' indicates the corresponding data channel is used and \'0\' indicates the channel is unused."]
#[inline(always)]
pub fn data_channels_l1(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
DataChannelsL1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
DataChannelsL1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DataChannelsL1 {
#[inline(always)]
fn default() -> DataChannelsL1 {
<crate::RegValueT<DataChannelsL1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DataChannelsM1_SPEC;
impl crate::sealed::RegSpec for DataChannelsM1_SPEC {
type DataType = u32;
}
#[doc = "Data channel map 1 (middle word)"]
pub type DataChannelsM1 = crate::RegValueT<DataChannelsM1_SPEC>;
impl DataChannelsM1 {
#[doc = "This register field indicates which of the data channels are in use. This stores the information for the middle 16 (32:16) data channel indices.\n\'1\' indicates the corresponding data channel is used and \'0\' indicates the channel is unused."]
#[inline(always)]
pub fn data_channels_m1(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
DataChannelsM1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
DataChannelsM1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DataChannelsM1 {
#[inline(always)]
fn default() -> DataChannelsM1 {
<crate::RegValueT<DataChannelsM1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DataChannelsH1_SPEC;
impl crate::sealed::RegSpec for DataChannelsH1_SPEC {
type DataType = u32;
}
#[doc = "Data channel map 1 (upper word)"]
pub type DataChannelsH1 = crate::RegValueT<DataChannelsH1_SPEC>;
impl DataChannelsH1 {
#[doc = "This register field indicates which of the data channels are in use. This stores the information for the upper 5 data channel indices.\n\'1\' indicates the corresponding data channel is used and \'0\' indicates the channel is unused.\nNote: The Data channel map 0 and data channel map 1 are two sets of channel maps stored, common for all the connections. At any given time, only two maps can be maintained and the connections will use one of the two sets as indicated by the channel map index field in the CE_CNFG_STS registers specific to the link. Firmware must also manage to update this field along with the map."]
#[inline(always)]
pub fn data_channels_h1(
self,
) -> crate::common::RegisterField<
0,
0x1f,
1,
0,
u8,
u8,
DataChannelsH1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1f,
1,
0,
u8,
u8,
DataChannelsH1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DataChannelsH1 {
#[inline(always)]
fn default() -> DataChannelsH1 {
<crate::RegValueT<DataChannelsH1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnIntr_SPEC;
impl crate::sealed::RegSpec for ConnIntr_SPEC {
type DataType = u32;
}
#[doc = "Connection interrupt status and Clear register"]
pub type ConnIntr = crate::RegValueT<ConnIntr_SPEC>;
impl ConnIntr {
#[doc = "If this bit is set it indicates that the link is disconnected.\nIf this bit is written with 1, it clears the connection updated interrupt."]
#[inline(always)]
pub fn conn_closed(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ConnIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ConnIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that the connection has been established. The bit is also set when a connection update procedure is complet-ed, at the start of the first anchor point with the updated parameters.\nIf this bit is written with 1, it clears the connection established interrupt."]
#[inline(always)]
pub fn conn_estb(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ConnIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ConnIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that the channel map update is completed at the instant specified by the firmware.\nIf this bit is written with 1, it clears the map update done interrupt."]
#[inline(always)]
pub fn map_updt_done(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ConnIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,ConnIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that the connection event started interrupt has happened.\nIf this bit is written with 1, it clears the connection event started interrupt."]
#[inline(always)]
pub fn start_ce(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ConnIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,ConnIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that the connection event closed interrupt has happened.\nIf this bit is written with 1, it clears the connection event closed interrupt."]
#[inline(always)]
pub fn close_ce(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ConnIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,ConnIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that the connection event transmission acknowledgement is received for the previous non-empty packet transmitted.\nIf this bit is written with 1, it clears the ce transmission acknowledgement interrupt."]
#[inline(always)]
pub fn ce_tx_ack(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ConnIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,ConnIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that a packet is received in the connection event.\nIf this bit is written with 1, it clears the connection event received interrupt."]
#[inline(always)]
pub fn ce_rx(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, ConnIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,ConnIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is set when the last connection event with previous connec-tion parameters is reached. The bit is set immediately after the re-ceive operation at the anchor point of the last connection event.\nIf this bit is written with 1, it clears the connection updated interrupt."]
#[inline(always)]
pub fn con_updt_done(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, ConnIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,ConnIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Reason for disconnect - indicates the reason the link is disconnected by hardware.\n001 - connection failed to be established\n010 - supervision timeout \n011 - kill connection by host\n100 - kill connection after ACK transmitted\n101 - PDU response timer expired"]
#[inline(always)]
pub fn discon_status(
self,
) -> crate::common::RegisterField<8, 0x7, 1, 0, u8, u8, ConnIntr_SPEC, crate::common::R>
{
crate::common::RegisterField::<8,0x7,1,0,u8,u8,ConnIntr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Status of PDU received. This information is valid along with receive interrupt.\nxx1 - Bad Packet (packet with CRC error)\n000 - empty PDU\n010 - new data (non-empty) PDU\n110 - Duplicate Packet"]
#[inline(always)]
pub fn rx_pdu_status(
self,
) -> crate::common::RegisterField<11, 0x7, 1, 0, u8, u8, ConnIntr_SPEC, crate::common::R>
{
crate::common::RegisterField::<11,0x7,1,0,u8,u8,ConnIntr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "If this is set, it indicates that ping timer has expired.\nIf this bit is written with 1, it clears the interrupt."]
#[inline(always)]
pub fn ping_timer_expird_intr(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, ConnIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<14,1,0,ConnIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this is set, it indicates that ping timer has nearly expired.\nIf this bit is written with 1, it clears the interrupt."]
#[inline(always)]
pub fn ping_nearly_expird_intr(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, ConnIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<15,1,0,ConnIntr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ConnIntr {
#[inline(always)]
fn default() -> ConnIntr {
<crate::RegValueT<ConnIntr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnStatus_SPEC;
impl crate::sealed::RegSpec for ConnStatus_SPEC {
type DataType = u32;
}
#[doc = "Connection channel status"]
pub type ConnStatus = crate::RegValueT<ConnStatus_SPEC>;
impl ConnStatus {
#[doc = "This field stores the count for the number of receive packets in the receive FIFO that are still not ready by firmware.\nThe counter value is incremented by hardware for every good packet it stores in the FIFO.\nAfter firmware reads a packet, it decrements the counter by issuing the PACKET_RECEIVED command from the commander."]
#[inline(always)]
pub fn receive_packet_count(
self,
) -> crate::common::RegisterField<12, 0xf, 1, 0, u8, u8, ConnStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<12,0xf,1,0,u8,u8,ConnStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for ConnStatus {
#[inline(always)]
fn default() -> ConnStatus {
<crate::RegValueT<ConnStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnIndex_SPEC;
impl crate::sealed::RegSpec for ConnIndex_SPEC {
type DataType = u32;
}
#[doc = "Connection Index register"]
pub type ConnIndex = crate::RegValueT<ConnIndex_SPEC>;
impl ConnIndex {
#[doc = "This field is used to index the multiple connections existing. Range is 0 to maximum number of connections supported.\nFor a single connection device, conn_index is 0."]
#[inline(always)]
pub fn conn_index(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnIndex_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnIndex_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnIndex {
#[inline(always)]
fn default() -> ConnIndex {
<crate::RegValueT<ConnIndex_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WakeupConfig_SPEC;
impl crate::sealed::RegSpec for WakeupConfig_SPEC {
type DataType = u32;
}
#[doc = "Wakeup configuration"]
pub type WakeupConfig = crate::RegValueT<WakeupConfig_SPEC>;
impl WakeupConfig {
#[doc = "Oscillator stabilization/startup delay. This is in X.Y for-mat where X is in terms of number of BT slots (625 us) and Y is in terms of number of clock periods of 16KHz clock input, required for RF oscillator to stabilize the clock output to the controller on its output pin, after oscillator is turned ON. In this period the clock is as-sumed to be unstable, and so the controller does not turn on the clock to internal logic till this period is over. This means, the wake up from deep sleep mode must account for this delay before the wakeup instant.\nOsc_startup_delay\\[7:5\\] is number of slots(625us)\nOsc_startup_delay\\[4:0 is number of clock periods of 16KHz clock\n(Warning: Min. value of Osc_startup_delay \\[4:0\\] sup-ported is 1 and Max. value is 9. Therefore programma-ble range is 1 to 9)"]
#[inline(always)]
pub fn osc_startup_delay(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, WakeupConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xff,
1,
0,
u8,
u8,
WakeupConfig_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Number of \'slots\' before the wake up instant before which the hardware needs to exit from deep sleep mode. The slot is of 0.625ms period. This is a onetime configuration field, which is used every time hardware does an auto-wakeup before the next wakeup instant."]
#[inline(always)]
pub fn dsm_offset_to_wakeup_instant(
self,
) -> crate::common::RegisterField<
10,
0x3f,
1,
0,
u8,
u8,
WakeupConfig_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
10,
0x3f,
1,
0,
u8,
u8,
WakeupConfig_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for WakeupConfig {
#[inline(always)]
fn default() -> WakeupConfig {
<crate::RegValueT<WakeupConfig_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WakeupControl_SPEC;
impl crate::sealed::RegSpec for WakeupControl_SPEC {
type DataType = u32;
}
#[doc = "Wakeup control"]
pub type WakeupControl = crate::RegValueT<WakeupControl_SPEC>;
impl WakeupControl {
#[doc = "Instant, with reference to the internal 16-bit clock reference, at which the hardware must wakeup from deep sleep mode. This is calculated by firmware based on the next closest instant where a controller operation is required (like advertiser/scanner). Firmware reads the next instant of the procedures in the corresponding *_NEXT_INSTANT registers. This value is used only when hardware auto wakeup from deep sleep mode is enabled in the clock control register.\nNote: it is recommended to program wakeup_instant such a way that the actual instant to wakeup shall be at least two counts (two slots of 625 us) ahead of reference clock when entering DSM. The actual instant to wakeup is \'wakeup_instant - dsm_offset_to_wakeup_instant - osc_startup_delay, and it shall be greater than \'reference clock + 2\'"]
#[inline(always)]
pub fn wakeup_instant(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
WakeupControl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
WakeupControl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for WakeupControl {
#[inline(always)]
fn default() -> WakeupControl {
<crate::RegValueT<WakeupControl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClockConfig_SPEC;
impl crate::sealed::RegSpec for ClockConfig_SPEC {
type DataType = u32;
}
#[doc = "Clock control"]
pub type ClockConfig = crate::RegValueT<ClockConfig_SPEC>;
impl ClockConfig {
#[doc = "Advertiser block clock gate enable. 1 - enable, 0 - disable.\nEnables gating of clock to the advertiser module (llh_adv) in hardware. If 1, the sleep mode logic can control the clock gate to shutdown/wakeup the clock to the module. If 0, the logic has no control and clock to the module is always turned ON."]
#[inline(always)]
pub fn adv_clk_gate_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ClockConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ClockConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Scan block clock gate enable. 1 - enable, 0 - disable.\nEnables gating of clock to the scanner module (llh_scan) in hardware. If 1, the sleep mode logic can control the clock gate to shutdown/wakeup the clock to the module. If 0, the logic has no control and clock to the module is always turned ON."]
#[inline(always)]
pub fn scan_clk_gate_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ClockConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,ClockConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Initiator block clock gate enable. 1 - enable, 0 - disable.\nEnables gating of clock to the initiator module (llh_init). If 1, the sleep mode logic can control the clock gate to shutdown/wakeup the clock to the module. If 0, the logic has no control and clock to the module is always turned ON."]
#[inline(always)]
pub fn init_clk_gate_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ClockConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,ClockConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Connection block clock gate enable. 1 - enable, 0 - disable.\nEnables gating of clock to the connection module (llh_connch_top) in hardware. If 1, the sleep mode logic can control the clock gate to shutdown/wakeup the clock to the engine. If 0, the logic has no control and clock to the module is always turned ON."]
#[inline(always)]
pub fn conn_clk_gate_en(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ClockConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,ClockConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Core clock gate enable. 1 - enable, 0 - disable.\nEnables gating of clock to the llh_core module in hard-ware. If 1, the sleep mode/deep sleep mode logic can control the clock gate to shutdown/wakeup the clock to the module. If 0, the logic has no control and clock is always turned ON."]
#[inline(always)]
pub fn coreclk_gate_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ClockConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,ClockConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sysclk gate enable. 1- enable, 0 - disable.\nEnables clock gating of system clock input to the link layer. If 1, it enables the DSM logic to control the clock gate for system clock input from pin. If 0, the DSM logic has no control and the system clock is always ON."]
#[inline(always)]
pub fn sysclk_gate_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ClockConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,ClockConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Digital PHY clock enable. 1- enable, 0-disable.\nEnable the Digital PHY to shutdown the clock. When 1, it indicates that controller has an upcoming activity so PHY clock must be turned ON. When 0, it indicates inactivity in the controller."]
#[inline(always)]
pub fn phy_clk_gate_en(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, ClockConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,ClockConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates if hardware is doing any transmit/receive operation. This information is used by firmware to decide to program the hardware into deep sleep mode.\n1 - LL hardware is idle.\n0 - LL hardware is busy. In this case LL hardware will not enter deep sleep mode, even if firmware gives an enter DSM command. (In this situation hardware generates dsm exit interrupt to inform firmware that DSM entry was not successful)."]
#[inline(always)]
pub fn llh_idle(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, ClockConfig_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<7,1,0,ClockConfig_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Clock frequency select. 0 - 32KHz, 1 - 32.768KHz.\nBase frequency of the sleep_clk input used for generat-ing the internal reference clock of approximate 16Khz frequency."]
#[inline(always)]
pub fn lpo_clk_freq_sel(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, ClockConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<8,1,0,ClockConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select external sleep clock. 1 - External clock, 0 - inter-nal generated clock.\nThe field is used to select either the low power clock in-put on sleep_clk input pin(of frequency 16.384KHz) di-rectly to run the DSM logic or to use the internal gener-ated reference clock(of 16KHz) for the same."]
#[inline(always)]
pub fn lpo_sel_external(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, ClockConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<9,1,0,ClockConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable sleep mode auto wakeup enable. 1- enable, 0 - disable.\nEnables hardware to automatically wakeup from sleep mode at the instant = wakeup_instant - sm_offset_to_wakeup_instant. The wakeup_insant is the field in the wakeup control register described earlier. The sm_offset_to_wakeup_instant value is the field described in the wakeup configuration register."]
#[inline(always)]
pub fn sm_auto_wkup_en(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, ClockConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<10,1,0,ClockConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable SM exit interrupt. 1 - enable, 0 - disable.\nEnables hardware to generate an interrupt while exiting sleep mode - irrespective of whether it is initiated by hardware or firmware. The interrupt is captured and stored till it gets cleared. Disabling this bit mask the sleep mode exit event from hardware & firmware.\nThis feature is not available. FW should never set this bit"]
#[inline(always)]
pub fn sm_intr_en(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, ClockConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<12,1,0,ClockConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Disable Auto Wakeup in DEEP_SLEEP mode.\n1 - Disable Auto Wakeup\n0 - Auto Wakeup enabled"]
#[inline(always)]
pub fn deep_sleep_auto_wkup_disable(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, ClockConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<13,1,0,ClockConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable sleep mode. 1 - enable, 0 - disable.\nEnables hardware to control sleep mode operation.\nThis feature is not available. FW should never set this bit"]
#[inline(always)]
pub fn sleep_mode_en(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, ClockConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<14,1,0,ClockConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable deep sleep mode. 1 - enable, 0 - disable.\nEnables hardware logic related to deep sleep mode to control the deep sleep mode operation. If disabled, the related logic is not executed and hardware cannot enter deep sleep mode."]
#[inline(always)]
pub fn deep_sleep_mode_en(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, ClockConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<15,1,0,ClockConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ClockConfig {
#[inline(always)]
fn default() -> ClockConfig {
<crate::RegValueT<ClockConfig_SPEC> as RegisterValue<_>>::new(128)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TimCounterL_SPEC;
impl crate::sealed::RegSpec for TimCounterL_SPEC {
type DataType = u32;
}
#[doc = "Reference Clock"]
pub type TimCounterL = crate::RegValueT<TimCounterL_SPEC>;
impl TimCounterL {
#[doc = "16-bit internal reference clock. The clock is a free run-ning clock, incremented by a 0.625ms periodic pulse. It is used as a reference clock to derive all the timing required as per protocol."]
#[inline(always)]
pub fn tim_ref_clock(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
TimCounterL_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
TimCounterL_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for TimCounterL {
#[inline(always)]
fn default() -> TimCounterL {
<crate::RegValueT<TimCounterL_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WakeupConfigExtd_SPEC;
impl crate::sealed::RegSpec for WakeupConfigExtd_SPEC {
type DataType = u32;
}
#[doc = "Wakeup configuration extended"]
pub type WakeupConfigExtd = crate::RegValueT<WakeupConfigExtd_SPEC>;
impl WakeupConfigExtd {
#[doc = "Number of \'LF slots\' before the wake up instant before which the hardware needs to exit from deep sleep mode. The LF slot is of 62.5us period. This is a onetime configuration field, which is used every time hardware does an auto-wakeup before the next wakeup instant. This is in addition to the LF slots calculated by HW window widening logic."]
#[inline(always)]
pub fn dsm_lf_offset(
self,
) -> crate::common::RegisterField<
0,
0x1f,
1,
0,
u8,
u8,
WakeupConfigExtd_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1f,
1,
0,
u8,
u8,
WakeupConfigExtd_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for WakeupConfigExtd {
#[inline(always)]
fn default() -> WakeupConfigExtd {
<crate::RegValueT<WakeupConfigExtd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PocRegTimControl_SPEC;
impl crate::sealed::RegSpec for PocRegTimControl_SPEC {
type DataType = u32;
}
#[doc = "BLE Time Control"]
pub type PocRegTimControl = crate::RegValueT<PocRegTimControl_SPEC>;
impl PocRegTimControl {
#[doc = "LLH clock configuration. The clock frequency of the clock input to this design is configured in this register. This is used to derive a 1MHz clock."]
#[inline(always)]
pub fn bb_clk_freq_minus_1(
self,
) -> crate::common::RegisterField<
3,
0x1f,
1,
0,
u8,
u8,
PocRegTimControl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
3,
0x1f,
1,
0,
u8,
u8,
PocRegTimControl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "LLH clock configuration. The start of slot signal is offset by this value. If value is 0, the start of slot signal is generated at the 625us. The offset value is in terms of us."]
#[inline(always)]
pub fn start_slot_offset(
self,
) -> crate::common::RegisterField<
8,
0xf,
1,
0,
u8,
u8,
PocRegTimControl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0xf,
1,
0,
u8,
u8,
PocRegTimControl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PocRegTimControl {
#[inline(always)]
fn default() -> PocRegTimControl {
<crate::RegValueT<PocRegTimControl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AdvTxDataFifo_SPEC;
impl crate::sealed::RegSpec for AdvTxDataFifo_SPEC {
type DataType = u32;
}
#[doc = "Advertising data transmit FIFO. Access ADVCH_TX_FIFO."]
pub type AdvTxDataFifo = crate::RegValueT<AdvTxDataFifo_SPEC>;
impl AdvTxDataFifo {
#[doc = "IO mapped FIFO of depth 16 (2 byte wide), to store ADV data of maximum length 31 bytes for transmitting. Firmware writes consecutive words by writing to the same address location.\nNote: ADV_TX_DATA_FIFO and ADV_SCN_RSP_TX_FIFO shares same physical FIFO of depth 32. 16 locations for each FIFO are allocated.\nReading this location resets the FIFO pointer."]
#[inline(always)]
pub fn adv_tx_data(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
AdvTxDataFifo_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
AdvTxDataFifo_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for AdvTxDataFifo {
#[inline(always)]
fn default() -> AdvTxDataFifo {
<crate::RegValueT<AdvTxDataFifo_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AdvScnRspTxFifo_SPEC;
impl crate::sealed::RegSpec for AdvScnRspTxFifo_SPEC {
type DataType = u32;
}
#[doc = "Advertising scan response data transmit FIFO. Access ADVCH_TX_FIFO."]
pub type AdvScnRspTxFifo = crate::RegValueT<AdvScnRspTxFifo_SPEC>;
impl AdvScnRspTxFifo {
#[doc = "IO mapped FIFO of depth 16 (2 byte wide), to store scan response data of maximum length 31 bytes for transmitting. Firmware writes consecutive words by writing to the same location.\nNote: ADV_TX_DATA_FIFO and ADV_SCN_RSP_TX_FIFO shares same physical FIFO of depth 32. 16 locations for each FIFO are allocated.\nReading this location resets the FIFO pointer."]
#[inline(always)]
pub fn scan_rsp_data(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
AdvScnRspTxFifo_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
AdvScnRspTxFifo_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for AdvScnRspTxFifo {
#[inline(always)]
fn default() -> AdvScnRspTxFifo {
<crate::RegValueT<AdvScnRspTxFifo_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InitScnAdvRxFifo_SPEC;
impl crate::sealed::RegSpec for InitScnAdvRxFifo_SPEC {
type DataType = u32;
}
#[doc = "advertising scan response data receive data FIFO. Access ADVRX_FIFO."]
pub type InitScnAdvRxFifo = crate::RegValueT<InitScnAdvRxFifo_SPEC>;
impl InitScnAdvRxFifo {
#[doc = "IO mapped FIFO of depth 64, to store ADV and SCAN_RSP header and payload received by the scanner. The RSSI value at the time of reception of this packet is also stored. Firmware reads from the same address to read out consecutive words of data.\nNote: The 16 bit header is first loaded to the advertise channel data receive FIFO followed by the payload data and then 16 bit RSSI."]
#[inline(always)]
pub fn adv_scan_rsp_rx_data(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
InitScnAdvRxFifo_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
InitScnAdvRxFifo_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for InitScnAdvRxFifo {
#[inline(always)]
fn default() -> InitScnAdvRxFifo {
<crate::RegValueT<InitScnAdvRxFifo_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnInterval_SPEC;
impl crate::sealed::RegSpec for ConnInterval_SPEC {
type DataType = u32;
}
#[doc = "Connection Interval"]
pub type ConnInterval = crate::RegValueT<ConnInterval_SPEC>;
impl ConnInterval {
#[doc = "The value configured in this register determines the spacing be-tween the connection events. \nThis shall be a multiple of 1.25 ms in the range of 7.5 ms to 4.0 s."]
#[inline(always)]
pub fn connection_interval(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnInterval_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnInterval_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnInterval {
#[inline(always)]
fn default() -> ConnInterval {
<crate::RegValueT<ConnInterval_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SupTimeout_SPEC;
impl crate::sealed::RegSpec for SupTimeout_SPEC {
type DataType = u32;
}
#[doc = "Supervision timeout"]
pub type SupTimeout = crate::RegValueT<SupTimeout_SPEC>;
impl SupTimeout {
#[doc = "This field defines the maximum time between two received Data packet PDUs before the connection is considered lost. \nThis shall be a multiple of 10 ms in the range of 100 ms to 32.0 s and it shall be larger than (1+connSlaveLatency)*connInterval."]
#[inline(always)]
pub fn supervision_timeout(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
SupTimeout_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
SupTimeout_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for SupTimeout {
#[inline(always)]
fn default() -> SupTimeout {
<crate::RegValueT<SupTimeout_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SlaveLatency_SPEC;
impl crate::sealed::RegSpec for SlaveLatency_SPEC {
type DataType = u32;
}
#[doc = "Slave Latency"]
pub type SlaveLatency = crate::RegValueT<SlaveLatency_SPEC>;
impl SlaveLatency {
#[doc = "The value configured in this field defines the number of consecutive connection events that the slave device is not required to listen for master.\nThe value of connSlaveLatency should not cause a Supervision Timeout.\nThis shall be an integer in the range of 0 to ((connSupervision Timeout/connInterval)-1). connSlaveLatency shall also be less than 500."]
#[inline(always)]
pub fn slave_latency(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
SlaveLatency_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
SlaveLatency_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for SlaveLatency {
#[inline(always)]
fn default() -> SlaveLatency {
<crate::RegValueT<SlaveLatency_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CeLength_SPEC;
impl crate::sealed::RegSpec for CeLength_SPEC {
type DataType = u32;
}
#[doc = "Connection event length"]
pub type CeLength = crate::RegValueT<CeLength_SPEC>;
impl CeLength {
#[doc = "This field defines the length of Connection event. This value is derived from the CE length HCI parameters received from the host. This determines the number of master transmit slots in a connection event, subject to either of the MD bits being set. If both MD bits are set to 0, this has no effect. Units: 625us\nNote:\nThe connection event length as specified by the CE_LENGTH shall not exceed CONN_INTERVAL - 1.25 ms.\nThe CE-length parameter, according to the Bluetooth specification, is the length of the connection event.\nTake an example to illustrate this scenario:\nAssume a connection with interval = 100ms. that the application has put allowed 20ms of CE-length.\nHere, the CE-length can be upto 100ms (100ms - 150us to be exact).\nIf the connection is maintained for 5 minutes, there could be 10*60*5 = 3000 connection-intervals. \nThe CE-length need not be maintained constant during all the 3000 connection events. \nHere are the typical cases that determine the value of CE-length:\n(1) No data packets exchanged. we are just maintaining time and frequency synchronization. In this case, only a packet pair will be exchanged every connection interval. Here, CE-length = 1.\n\n(2) Average of 10 packets to be sent per connection event. \nWe can pump data in multiple ways here:\n2.1: Send data at uniform rate : In this case, the CE-length will be enough to accommodate 10 packets, which will take about 7ms. As this is less than application enforced limit of 20ms, we can comfortably push all the 10 data packets in this connection interval. So data will be pumped to the other BT device at the same rate as is received from my application.\n2.2: Can send data in bursts. Assume that we accumulate data for 1 second and pump out at the end of 1 second(this is not done by our Bluetooth stack, the application needs to buffer the data). So, at 10th connection interval, we have 100 packets accumulated. We are now ready to pump this data. 100 packets take about 70 ms. This is above the application enforced 20ms. So, the hardware can pump data that can fill up 20ms. The remaining data will be deferred to the next connection interval. \n\nSo, in this case, you would see a CE-length spread over time like this (Per connection interval):\n0,0,0,0,0,0,0,0,0,0, 20,20,20,10,0,0,0,0,0,0, 20,20,20,10,0,0,0,0,0,0, 20,20,20,10,0,0,0,0,0,0, \nand so on.\n(3) We are receiving data at the same rate as in (2). This case is to honor data sent by the other BT-device by giving it more time in the current connection interval.\nIn (2) and (3) you will see non-empty packets either transmitted or received. We can also utilize the CE-length for different reasons:\n(4) A transaction is in progress, and we are expecting a response packet very soon. In this case, we may be exchanging only empty packets now, and in the next few packet-pairs. \nIn this case, you will the CE-length to be large, and a non-empty packet may not be exchanged in all the slots."]
#[inline(always)]
pub fn connection_event_length(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, CeLength_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
CeLength_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CeLength {
#[inline(always)]
fn default() -> CeLength {
<crate::RegValueT<CeLength_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PduAccessAddrLRegister_SPEC;
impl crate::sealed::RegSpec for PduAccessAddrLRegister_SPEC {
type DataType = u32;
}
#[doc = "Access address (lower)"]
pub type PduAccessAddrLRegister = crate::RegValueT<PduAccessAddrLRegister_SPEC>;
impl PduAccessAddrLRegister {
#[doc = "This field defines the lower 16 bits of the access address for each Link layer connection between any two devices."]
#[inline(always)]
pub fn pdu_access_address_lower_bits(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
PduAccessAddrLRegister_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
PduAccessAddrLRegister_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PduAccessAddrLRegister {
#[inline(always)]
fn default() -> PduAccessAddrLRegister {
<crate::RegValueT<PduAccessAddrLRegister_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PduAccessAddrHRegister_SPEC;
impl crate::sealed::RegSpec for PduAccessAddrHRegister_SPEC {
type DataType = u32;
}
#[doc = "Access address (upper)"]
pub type PduAccessAddrHRegister = crate::RegValueT<PduAccessAddrHRegister_SPEC>;
impl PduAccessAddrHRegister {
#[doc = "This field defines the higher 16 bits of the access address for each Link layer connection between any two devices."]
#[inline(always)]
pub fn pdu_access_address_higher_bits(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
PduAccessAddrHRegister_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
PduAccessAddrHRegister_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PduAccessAddrHRegister {
#[inline(always)]
fn default() -> PduAccessAddrHRegister {
<crate::RegValueT<PduAccessAddrHRegister_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnCeInstant_SPEC;
impl crate::sealed::RegSpec for ConnCeInstant_SPEC {
type DataType = u32;
}
#[doc = "Connection event instant"]
pub type ConnCeInstant = crate::RegValueT<ConnCeInstant_SPEC>;
impl ConnCeInstant {
#[doc = "This is the value of the free running Connection Event counter when the new parameters of \'connection update\' and/or \'Channel map update\' will be effective.\nRange : 0x0000 to 0xFFFF"]
#[inline(always)]
pub fn ce_instant(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnCeInstant_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnCeInstant_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnCeInstant {
#[inline(always)]
fn default() -> ConnCeInstant {
<crate::RegValueT<ConnCeInstant_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CeCnfgStsRegister_SPEC;
impl crate::sealed::RegSpec for CeCnfgStsRegister_SPEC {
type DataType = u32;
}
#[doc = "connection configuration & status register"]
pub type CeCnfgStsRegister = crate::RegValueT<CeCnfgStsRegister_SPEC>;
impl CeCnfgStsRegister {
#[doc = "Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded.\nThe default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4.\nHardware will start the next data transmission from the index indicated by this field."]
#[inline(always)]
pub fn data_list_index_last_ack_index(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
CeCnfgStsRegister_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
CeCnfgStsRegister_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause.\nThe bit must be toggled every time the firmware needs to indicate the start/resume. This requires a read modify write operation."]
#[inline(always)]
pub fn data_list_head_up(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, CeCnfgStsRegister_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,CeCnfgStsRegister_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is unused"]
#[inline(always)]
pub fn spare(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, CeCnfgStsRegister_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,CeCnfgStsRegister_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "MD bit set to \'1\' indicates device has more data to be sent."]
#[inline(always)]
pub fn md(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, CeCnfgStsRegister_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,CeCnfgStsRegister_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Written by firmware to select the map index to be used by hardware for this connection. \n1 - use channel map register set 1. \n0 - use channel map register set 0.\nWhen firmware reads this field, it returns the current map index being used in hardware."]
#[inline(always)]
pub fn map_index__curr_index(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, CeCnfgStsRegister_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<7,1,0,CeCnfgStsRegister_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Pause data. \n1 - pause data, \n0 - do not pause.\nThe current_pdu_index in hardware does not move to next in-dex until pause_data is cleared.\nBut if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out"]
#[inline(always)]
pub fn pause_data(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, CeCnfgStsRegister_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<8,1,0,CeCnfgStsRegister_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is \'1\' whenever the connection is active."]
#[inline(always)]
pub fn conn_active(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, CeCnfgStsRegister_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<10,1,0,CeCnfgStsRegister_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "The index of the transmit packet buffer that is currently in transmission/waiting for transmission."]
#[inline(always)]
pub fn current_pdu_index(
self,
) -> crate::common::RegisterField<
12,
0xf,
1,
0,
u8,
u8,
CeCnfgStsRegister_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
12,
0xf,
1,
0,
u8,
u8,
CeCnfgStsRegister_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CeCnfgStsRegister {
#[inline(always)]
fn default() -> CeCnfgStsRegister {
<crate::RegValueT<CeCnfgStsRegister_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct NextCeInstant_SPEC;
impl crate::sealed::RegSpec for NextCeInstant_SPEC {
type DataType = u32;
}
#[doc = "Next connection event instant"]
pub type NextCeInstant = crate::RegValueT<NextCeInstant_SPEC>;
impl NextCeInstant {
#[doc = "16-bit internal reference clock value at which the next connection event will occur on a connection. The connection index register must be programmed with index of the connection, before reading the register.\nThe reset value is 0x0000. After reset deassertion, then the very next clock, the value assigned to the registers is 0xFFFF."]
#[inline(always)]
pub fn next_ce_instant(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
NextCeInstant_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
NextCeInstant_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for NextCeInstant {
#[inline(always)]
fn default() -> NextCeInstant {
<crate::RegValueT<NextCeInstant_SPEC> as RegisterValue<_>>::new(65535)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnCeCounter_SPEC;
impl crate::sealed::RegSpec for ConnCeCounter_SPEC {
type DataType = u32;
}
#[doc = "connection event counter"]
pub type ConnCeCounter = crate::RegValueT<ConnCeCounter_SPEC>;
impl ConnCeCounter {
#[doc = "This is the free running counter, connEventCounter as defined by Bluetooth spec.\nFirmware will read the instantaneous Event counter from this register, during connection update and channel map update procedure. Firmware will use this value to calculate the instant from which the new parameters (for connection update and channel map update) will be effective."]
#[inline(always)]
pub fn connection_event_counter(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnCeCounter_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnCeCounter_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnCeCounter {
#[inline(always)]
fn default() -> ConnCeCounter {
<crate::RegValueT<ConnCeCounter_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DataListSentUpdateStatus_SPEC;
impl crate::sealed::RegSpec for DataListSentUpdateStatus_SPEC {
type DataType = u32;
}
#[doc = "data list sent update and status"]
pub type DataListSentUpdateStatus = crate::RegValueT<DataListSentUpdateStatus_SPEC>;
impl DataListSentUpdateStatus {
#[doc = "Write:Indicates the buffer index for which the SENT bit is being updated by firmware.\nThe default number of buffers in the IP is 4. The index range is 0-3.\n\nRead: Reads TX_SENT\\[3:0\\].\nThe bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are\n1 - queued\n0 - no packet / packet ack received by hardware \nExample1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement.\nNOTE:\nThe SENT status bit and ACK status bit have to be taken together to understand the meaning of packet status. The table below describes how the two bits are sequentially updated by either hardware/firmware to complete one data transmission.\nSENT ACK Description\n0 0 Buffer is empty. No packet is queued in the buffer\n1 0 Packet is queued by firmware.\n1 1 Packet is transmitted by hardware. Hardware is waiting for acknowledgement.\n0 1 Hardware has received ACK. Firmware has not yet processed the ACK.\n0 0 Firmware has processed the ack. The buffer is again empty."]
#[inline(always)]
pub fn list_index__tx_sent_3_0(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
DataListSentUpdateStatus_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
DataListSentUpdateStatus_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Write: Used to set the SENT bit in hardware for the selected packet buffer.\n1 - packet queued\nWhen firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted. \nThe SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device. \nFirmware typically does not clear the bit. However, It only clears the bit on its own if it needs to \'flush\' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified."]
#[inline(always)]
pub fn set_clear(
self,
) -> crate::common::RegisterFieldBool<
7,
1,
0,
DataListSentUpdateStatus_SPEC,
crate::common::W,
> {
crate::common::RegisterFieldBool::<
7,
1,
0,
DataListSentUpdateStatus_SPEC,
crate::common::W,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DataListSentUpdateStatus {
#[inline(always)]
fn default() -> DataListSentUpdateStatus {
<crate::RegValueT<DataListSentUpdateStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DataListAckUpdateStatus_SPEC;
impl crate::sealed::RegSpec for DataListAckUpdateStatus_SPEC {
type DataType = u32;
}
#[doc = "data list ack update and status"]
pub type DataListAckUpdateStatus = crate::RegValueT<DataListAckUpdateStatus_SPEC>;
impl DataListAckUpdateStatus {
#[doc = "Write: Indicates the buffer index for which the ACK bit is being updated by firmware.\nThe default number of buffers in the IP is 5. The index range is 0-4.\n\nRead: Reads TX_ACK\\[3:0\\]\nIf a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement. \nExample1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware.\nExample2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware.\nNOTE:\nThe SENT status bit and ACK status bit have to be taken together to understand the meaning of packet status. The table below describes how the two bits are sequentially updated by either hardware/firmware to complete one data transmission.\nSENT ACK Description\n0 0 Buffer is empty. No packet is queued in the buffer\n1 0 Packet is queued by firmware.\n1 1 Packet is transmitted by hardware. Hardware is waiting for acknowledgement.\n0 1 Hardware has received ACK. Firmware has not yet processed the ACK.\n0 0 Firmware has processed the ack. The buffer is again empty."]
#[inline(always)]
pub fn list_index__tx_ack_3_0(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
DataListAckUpdateStatus_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
DataListAckUpdateStatus_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware.\nFirmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware.\nFor clearing ack for a packet transmitted in fifo-index : \'3\', firm-ware will write \'3\' in the \'list-index\' field and set this bit (BIT7) to 0. \nThis is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on.\nThe ACK bit in hardware is set by hardware when it has success-fully transmitted a packet."]
#[inline(always)]
pub fn set_clear(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, DataListAckUpdateStatus_SPEC, crate::common::W>
{
crate::common::RegisterFieldBool::<
7,
1,
0,
DataListAckUpdateStatus_SPEC,
crate::common::W,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DataListAckUpdateStatus {
#[inline(always)]
fn default() -> DataListAckUpdateStatus {
<crate::RegValueT<DataListAckUpdateStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CeCnfgStsRegisterExt_SPEC;
impl crate::sealed::RegSpec for CeCnfgStsRegisterExt_SPEC {
type DataType = u32;
}
#[doc = "connection configuration & status register"]
pub type CeCnfgStsRegisterExt = crate::RegValueT<CeCnfgStsRegisterExt_SPEC>;
impl CeCnfgStsRegisterExt {
#[doc = "transmittion on 2M"]
#[inline(always)]
pub fn tx_2m(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, CeCnfgStsRegisterExt_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,CeCnfgStsRegisterExt_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "receiving on 2M"]
#[inline(always)]
pub fn rx_2m(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, CeCnfgStsRegisterExt_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,CeCnfgStsRegisterExt_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sequence number for next scheduled connection index"]
#[inline(always)]
pub fn sn(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, CeCnfgStsRegisterExt_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,CeCnfgStsRegisterExt_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Next Sequence number for next scheduled connection index"]
#[inline(always)]
pub fn nesn(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, CeCnfgStsRegisterExt_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,CeCnfgStsRegisterExt_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Last unmapped channel for next scheduled connection index"]
#[inline(always)]
pub fn last_unmapped_channel(
self,
) -> crate::common::RegisterField<
8,
0x3f,
1,
0,
u8,
u8,
CeCnfgStsRegisterExt_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0x3f,
1,
0,
u8,
u8,
CeCnfgStsRegisterExt_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for CeCnfgStsRegisterExt {
#[inline(always)]
fn default() -> CeCnfgStsRegisterExt {
<crate::RegValueT<CeCnfgStsRegisterExt_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnExtIntr_SPEC;
impl crate::sealed::RegSpec for ConnExtIntr_SPEC {
type DataType = u32;
}
#[doc = "Connection extended interrupt status and Clear register"]
pub type ConnExtIntr = crate::RegValueT<ConnExtIntr_SPEC>;
impl ConnExtIntr {
#[doc = "If this bit is set it indicates that the data rate is updated\nIf this bit is written with 1, it clears the interrupt status bit"]
#[inline(always)]
pub fn datarate_update(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ConnExtIntr_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ConnExtIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "For master this bit is set on start_ce\nFor Slave this bit is set on slave_timer_adj"]
#[inline(always)]
pub fn early_intr(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ConnExtIntr_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,ConnExtIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set it indicates that the generic timer (PDU response timer reconfigured in MMMS mode) has expired\nIf this bit is written with 1, it clears the interrupt status bit"]
#[inline(always)]
pub fn gen_timer_intr(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ConnExtIntr_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,ConnExtIntr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ConnExtIntr {
#[inline(always)]
fn default() -> ConnExtIntr {
<crate::RegValueT<ConnExtIntr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnExtIntrMask_SPEC;
impl crate::sealed::RegSpec for ConnExtIntrMask_SPEC {
type DataType = u32;
}
#[doc = "Connection Extended Interrupt mask"]
pub type ConnExtIntrMask = crate::RegValueT<ConnExtIntrMask_SPEC>;
impl ConnExtIntrMask {
#[doc = "If this bit is set connection data rate update interrupt is enabled."]
#[inline(always)]
pub fn datarate_update(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ConnExtIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ConnExtIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set connection early interrupt is enabled."]
#[inline(always)]
pub fn early_intr(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ConnExtIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,ConnExtIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Generic timer (PDU response timer reconfigured in MMMS mode) expiry interrupt"]
#[inline(always)]
pub fn gen_timer_intr(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ConnExtIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,ConnExtIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ConnExtIntrMask {
#[inline(always)]
fn default() -> ConnExtIntrMask {
<crate::RegValueT<ConnExtIntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DataMemDescriptor_SPEC;
impl crate::sealed::RegSpec for DataMemDescriptor_SPEC {
type DataType = u32;
}
#[doc = "Data buffer descriptor 0 to 4"]
pub type DataMemDescriptor = crate::RegValueT<DataMemDescriptor_SPEC>;
impl DataMemDescriptor {
#[doc = "N/A"]
#[inline(always)]
pub fn llid(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
u8,
u8,
DataMemDescriptor_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
u8,
u8,
DataMemDescriptor_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This field indicates the length of the data packet. Bits \\[9:7\\] are valid only if DLE is set.\nRange 0x00 to 0xFF."]
#[inline(always)]
pub fn data_length(
self,
) -> crate::common::RegisterField<
2,
0xff,
1,
0,
u8,
u8,
DataMemDescriptor_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0xff,
1,
0,
u8,
u8,
DataMemDescriptor_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DataMemDescriptor {
#[inline(always)]
fn default() -> DataMemDescriptor {
<crate::RegValueT<DataMemDescriptor_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WindowWidenIntvl_SPEC;
impl crate::sealed::RegSpec for WindowWidenIntvl_SPEC {
type DataType = u32;
}
#[doc = "Window widen for interval"]
pub type WindowWidenIntvl = crate::RegValueT<WindowWidenIntvl_SPEC>;
impl WindowWidenIntvl {
#[doc = "This value defines the increased listening time for the slave.\nThe window widening shall be smaller than ((connInterval/2)-T_IFS us)\nThis value is calculated by firmware based on the drift, the connec-tion interval value. The value is the unit widening value for one con-nection interval duration. In case of slave latency, this value is accu-mulated till the next anchor point at which the slave will listen."]
#[inline(always)]
pub fn window_widen_intvl(
self,
) -> crate::common::RegisterField<
0,
0xfff,
1,
0,
u16,
u16,
WindowWidenIntvl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xfff,
1,
0,
u16,
u16,
WindowWidenIntvl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for WindowWidenIntvl {
#[inline(always)]
fn default() -> WindowWidenIntvl {
<crate::RegValueT<WindowWidenIntvl_SPEC> as RegisterValue<_>>::new(10)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WindowWidenWinoff_SPEC;
impl crate::sealed::RegSpec for WindowWidenWinoff_SPEC {
type DataType = u32;
}
#[doc = "Window widen for offset"]
pub type WindowWidenWinoff = crate::RegValueT<WindowWidenWinoff_SPEC>;
impl WindowWidenWinoff {
#[doc = "This field stores the additional number of microseconds the slave must extend its listening window to listen for a master packet. This value is calculated based on the window offset value. This is used at connection setup directly. During connection setup, this value is added with window_widen_intvl register value to calculate the win-dow widening size."]
#[inline(always)]
pub fn window_widen_winoff(
self,
) -> crate::common::RegisterField<
0,
0xfff,
1,
0,
u16,
u16,
WindowWidenWinoff_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xfff,
1,
0,
u16,
u16,
WindowWidenWinoff_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for WindowWidenWinoff {
#[inline(always)]
fn default() -> WindowWidenWinoff {
<crate::RegValueT<WindowWidenWinoff_SPEC> as RegisterValue<_>>::new(10)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LeRfTestMode_SPEC;
impl crate::sealed::RegSpec for LeRfTestMode_SPEC {
type DataType = u32;
}
#[doc = "Direct Test Mode control"]
pub type LeRfTestMode = crate::RegValueT<LeRfTestMode_SPEC>;
impl LeRfTestMode {
#[doc = "N = (F - 2402) / 2\nRange: 0x00 - 0x27. Frequency Range : 2402 MHz to 2480 MHz"]
#[inline(always)]
pub fn test_frequency(
self,
) -> crate::common::RegisterField<0, 0x3f, 1, 0, u8, u8, LeRfTestMode_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0x3f,
1,
0,
u8,
u8,
LeRfTestMode_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This bit is overloaded.\nThe read operation returns the staus of the DTM\n1 - DTM test ON\n0 - DTM test OFF\nThe write operation contrls the DTM RX mode\n0: DTM run at normal DTMRX burst mode\n1: DTM run at continuous RX DTM mode"]
#[inline(always)]
pub fn dtm_status__dtm_cont_rxen(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, LeRfTestMode_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,LeRfTestMode_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn pkt_payload(
self,
) -> crate::common::RegisterField<7, 0x7, 1, 0, u8, u8, LeRfTestMode_SPEC, crate::common::RW>
{
crate::common::RegisterField::<7,0x7,1,0,u8,u8,LeRfTestMode_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "0: DTM run at normal DTMTX burst mode\n1: DTM run at continuous TX DTM mode"]
#[inline(always)]
pub fn dtm_cont_txen(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, LeRfTestMode_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<13,1,0,LeRfTestMode_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "0: DTM run at 1M bps data rate\n1: DTM run at 2M bps data rate"]
#[inline(always)]
pub fn dtm_data_2mbps(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, LeRfTestMode_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<15,1,0,LeRfTestMode_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for LeRfTestMode {
#[inline(always)]
fn default() -> LeRfTestMode {
<crate::RegValueT<LeRfTestMode_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DtmRxPktCount_SPEC;
impl crate::sealed::RegSpec for DtmRxPktCount_SPEC {
type DataType = u32;
}
#[doc = "Direct Test Mode receive packet count"]
pub type DtmRxPktCount = crate::RegValueT<DtmRxPktCount_SPEC>;
impl DtmRxPktCount {
#[doc = "Number of packets received in receive test mode."]
#[inline(always)]
pub fn rx_packet_count(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
DtmRxPktCount_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
DtmRxPktCount_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DtmRxPktCount {
#[inline(always)]
fn default() -> DtmRxPktCount {
<crate::RegValueT<DtmRxPktCount_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LeRfTestModeExt_SPEC;
impl crate::sealed::RegSpec for LeRfTestModeExt_SPEC {
type DataType = u32;
}
#[doc = "Direct Test Mode control"]
pub type LeRfTestModeExt = crate::RegValueT<LeRfTestModeExt_SPEC>;
impl LeRfTestModeExt {
#[doc = "DTM TX packet length.\nBits \\[7:6\\] are accessible onle when DLE is enabled"]
#[inline(always)]
pub fn dtm_packet_length(
self,
) -> crate::common::RegisterField<
0,
0xff,
1,
0,
u8,
u8,
LeRfTestModeExt_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xff,
1,
0,
u8,
u8,
LeRfTestModeExt_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for LeRfTestModeExt {
#[inline(always)]
fn default() -> LeRfTestModeExt {
<crate::RegValueT<LeRfTestModeExt_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxrxHop_SPEC;
impl crate::sealed::RegSpec for TxrxHop_SPEC {
type DataType = u32;
}
#[doc = "Channel Address register"]
pub type TxrxHop = crate::RegValueT<TxrxHop_SPEC>;
impl TxrxHop {
#[doc = "Transmit channel index. Channel index on which previous packet is transmitted."]
#[inline(always)]
pub fn hop_ch_tx(
self,
) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, TxrxHop_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x7f,1,0,u8,u8,TxrxHop_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Receive channel index. Channel index on which previous packet is received."]
#[inline(always)]
pub fn hop_ch_rx(
self,
) -> crate::common::RegisterField<8, 0x7f, 1, 0, u8, u8, TxrxHop_SPEC, crate::common::R>
{
crate::common::RegisterField::<8,0x7f,1,0,u8,u8,TxrxHop_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for TxrxHop {
#[inline(always)]
fn default() -> TxrxHop {
<crate::RegValueT<TxrxHop_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxRxOnDelay_SPEC;
impl crate::sealed::RegSpec for TxRxOnDelay_SPEC {
type DataType = u32;
}
#[doc = "Transmit/Receive data delay"]
pub type TxRxOnDelay = crate::RegValueT<TxRxOnDelay_SPEC>;
impl TxRxOnDelay {
#[doc = "Receive delay - Delay from start of receive to expected first bit of receive packet at the controller. Used to control the turn on time of radio to optimize on power. The delay is in resolution of 1 microsecond."]
#[inline(always)]
pub fn rxon_delay(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, TxRxOnDelay_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,TxRxOnDelay_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Transmit delay - Delay from start of transmit to transmission of first bit on air. It is used to control the T_IFS. The delay is in resolution of 1 microsecond."]
#[inline(always)]
pub fn txon_delay(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, TxRxOnDelay_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,TxRxOnDelay_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TxRxOnDelay {
#[inline(always)]
fn default() -> TxRxOnDelay {
<crate::RegValueT<TxRxOnDelay_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AdvAccaddrL_SPEC;
impl crate::sealed::RegSpec for AdvAccaddrL_SPEC {
type DataType = u32;
}
#[doc = "ADV packet access code low word"]
pub type AdvAccaddrL = crate::RegValueT<AdvAccaddrL_SPEC>;
impl AdvAccaddrL {
#[doc = "Lower 16 bit of ADV packet access code"]
#[inline(always)]
pub fn adv_accaddr_l(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
AdvAccaddrL_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
AdvAccaddrL_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for AdvAccaddrL {
#[inline(always)]
fn default() -> AdvAccaddrL {
<crate::RegValueT<AdvAccaddrL_SPEC> as RegisterValue<_>>::new(48854)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AdvAccaddrH_SPEC;
impl crate::sealed::RegSpec for AdvAccaddrH_SPEC {
type DataType = u32;
}
#[doc = "ADV packet access code high word"]
pub type AdvAccaddrH = crate::RegValueT<AdvAccaddrH_SPEC>;
impl AdvAccaddrH {
#[doc = "higher 16 bit of ADV packet access code"]
#[inline(always)]
pub fn adv_accaddr_h(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
AdvAccaddrH_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
AdvAccaddrH_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for AdvAccaddrH {
#[inline(always)]
fn default() -> AdvAccaddrH {
<crate::RegValueT<AdvAccaddrH_SPEC> as RegisterValue<_>>::new(36489)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AdvChTxPowerLvlLs_SPEC;
impl crate::sealed::RegSpec for AdvChTxPowerLvlLs_SPEC {
type DataType = u32;
}
#[doc = "Advertising channel transmit power setting"]
pub type AdvChTxPowerLvlLs = crate::RegValueT<AdvChTxPowerLvlLs_SPEC>;
impl AdvChTxPowerLvlLs {
#[doc = "When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 1, this field represents the Advertising channel transmit power setting Least Significant 16 bits.\nWhen LL_CONFIG.TX_PA_PWR_LVL_TYPE is 0, the LS 4 bits represents the Advertising channel transmit power code 4 bits."]
#[inline(always)]
pub fn adv_transmit_power_lvl_ls(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
AdvChTxPowerLvlLs_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
AdvChTxPowerLvlLs_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for AdvChTxPowerLvlLs {
#[inline(always)]
fn default() -> AdvChTxPowerLvlLs {
<crate::RegValueT<AdvChTxPowerLvlLs_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AdvChTxPowerLvlMs_SPEC;
impl crate::sealed::RegSpec for AdvChTxPowerLvlMs_SPEC {
type DataType = u32;
}
#[doc = "Advertising channel transmit power setting extension"]
pub type AdvChTxPowerLvlMs = crate::RegValueT<AdvChTxPowerLvlMs_SPEC>;
impl AdvChTxPowerLvlMs {
#[doc = "Advertising channel transmit power setting Most Significant 2 bits."]
#[inline(always)]
pub fn adv_transmit_power_lvl_ms(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
u8,
u8,
AdvChTxPowerLvlMs_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
u8,
u8,
AdvChTxPowerLvlMs_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for AdvChTxPowerLvlMs {
#[inline(always)]
fn default() -> AdvChTxPowerLvlMs {
<crate::RegValueT<AdvChTxPowerLvlMs_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnChTxPowerLvlLs_SPEC;
impl crate::sealed::RegSpec for ConnChTxPowerLvlLs_SPEC {
type DataType = u32;
}
#[doc = "Connection channel transmit power setting"]
pub type ConnChTxPowerLvlLs = crate::RegValueT<ConnChTxPowerLvlLs_SPEC>;
impl ConnChTxPowerLvlLs {
#[doc = "When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 1, this field represents the Connection channel transmit power setting Least Significant 16 bits.\nWhen LL_CONFIG.TX_PA_PWR_LVL_TYPE is 0, the LS 4 bits represents the Connection channel transmit power code 4 bits."]
#[inline(always)]
pub fn connch_transmit_power_lvl_ls(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnChTxPowerLvlLs_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnChTxPowerLvlLs_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnChTxPowerLvlLs {
#[inline(always)]
fn default() -> ConnChTxPowerLvlLs {
<crate::RegValueT<ConnChTxPowerLvlLs_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnChTxPowerLvlMs_SPEC;
impl crate::sealed::RegSpec for ConnChTxPowerLvlMs_SPEC {
type DataType = u32;
}
#[doc = "Connection channel transmit power setting extension"]
pub type ConnChTxPowerLvlMs = crate::RegValueT<ConnChTxPowerLvlMs_SPEC>;
impl ConnChTxPowerLvlMs {
#[doc = "Connection channel transmit power setting Most Significant 2 bits."]
#[inline(always)]
pub fn connch_transmit_power_lvl_ms(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
u8,
u8,
ConnChTxPowerLvlMs_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
u8,
u8,
ConnChTxPowerLvlMs_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnChTxPowerLvlMs {
#[inline(always)]
fn default() -> ConnChTxPowerLvlMs {
<crate::RegValueT<ConnChTxPowerLvlMs_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DevPubAddrL_SPEC;
impl crate::sealed::RegSpec for DevPubAddrL_SPEC {
type DataType = u32;
}
#[doc = "Device public address lower register"]
pub type DevPubAddrL = crate::RegValueT<DevPubAddrL_SPEC>;
impl DevPubAddrL {
#[doc = "Lower 16 bit of 48-bit public address of the device."]
#[inline(always)]
pub fn dev_pub_addr_l(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
DevPubAddrL_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
DevPubAddrL_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DevPubAddrL {
#[inline(always)]
fn default() -> DevPubAddrL {
<crate::RegValueT<DevPubAddrL_SPEC> as RegisterValue<_>>::new(13330)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DevPubAddrM_SPEC;
impl crate::sealed::RegSpec for DevPubAddrM_SPEC {
type DataType = u32;
}
#[doc = "Device public address middle register"]
pub type DevPubAddrM = crate::RegValueT<DevPubAddrM_SPEC>;
impl DevPubAddrM {
#[doc = "Middle 16 bit of 48-bit public address of the device."]
#[inline(always)]
pub fn dev_pub_addr_m(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
DevPubAddrM_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
DevPubAddrM_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DevPubAddrM {
#[inline(always)]
fn default() -> DevPubAddrM {
<crate::RegValueT<DevPubAddrM_SPEC> as RegisterValue<_>>::new(86)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DevPubAddrH_SPEC;
impl crate::sealed::RegSpec for DevPubAddrH_SPEC {
type DataType = u32;
}
#[doc = "Device public address higher register"]
pub type DevPubAddrH = crate::RegValueT<DevPubAddrH_SPEC>;
impl DevPubAddrH {
#[doc = "Higher 16 bit of 48-bit public address of the device."]
#[inline(always)]
pub fn dev_pub_addr_h(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
DevPubAddrH_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
DevPubAddrH_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DevPubAddrH {
#[inline(always)]
fn default() -> DevPubAddrH {
<crate::RegValueT<DevPubAddrH_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct OffsetToFirstInstant_SPEC;
impl crate::sealed::RegSpec for OffsetToFirstInstant_SPEC {
type DataType = u32;
}
#[doc = "Offset to first instant"]
pub type OffsetToFirstInstant = crate::RegValueT<OffsetToFirstInstant_SPEC>;
impl OffsetToFirstInstant {
#[doc = "The offset w.r.t the internal reference clock at which instant the first event occurs.\nThis register will give flexibility to the firmware to position the con-nection at a desired point with respect to the internal free running clock. It is optional to be updated by firmware. This is not updated in the current firmware."]
#[inline(always)]
pub fn offset_to_first_event(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
OffsetToFirstInstant_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
OffsetToFirstInstant_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for OffsetToFirstInstant {
#[inline(always)]
fn default() -> OffsetToFirstInstant {
<crate::RegValueT<OffsetToFirstInstant_SPEC> as RegisterValue<_>>::new(6)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AdvConfig_SPEC;
impl crate::sealed::RegSpec for AdvConfig_SPEC {
type DataType = u32;
}
#[doc = "Advertiser configuration register"]
pub type AdvConfig = crate::RegValueT<AdvConfig_SPEC>;
impl AdvConfig {
#[doc = "Enable advertising event start interrupt."]
#[inline(always)]
pub fn adv_strt_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, AdvConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,AdvConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable advertising event stop interrupt."]
#[inline(always)]
pub fn adv_cls_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, AdvConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,AdvConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable adv packet transmitted interrupt."]
#[inline(always)]
pub fn adv_tx_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, AdvConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,AdvConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable scan response packet transmitted interrupt."]
#[inline(always)]
pub fn scn_rsp_tx_en(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, AdvConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,AdvConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable scan request packet received interrupt."]
#[inline(always)]
pub fn adv_scn_req_rx_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, AdvConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,AdvConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable connect request packet received interrupt."]
#[inline(always)]
pub fn adv_conn_req_rx_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, AdvConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,AdvConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable slave connected interrupt."]
#[inline(always)]
pub fn slv_connected_en(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, AdvConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,AdvConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable adv_timeout interrupt. Applicable in adv_direct_ind advertising."]
#[inline(always)]
pub fn adv_timeout_en(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, AdvConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,AdvConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Disable randomization of adv interval. When disabled, interval is same as programmed in adv_interval register."]
#[inline(always)]
pub fn adv_rand_disable(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, AdvConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,AdvConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable scan request packet received with peer device address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_1_2 and PRIV_1_2_ADV are set."]
#[inline(always)]
pub fn adv_scn_peer_rpa_unmch_en(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, AdvConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,AdvConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable connect request packet received with peer device address unmatched interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set."]
#[inline(always)]
pub fn adv_conn_peer_rpa_unmch_en(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, AdvConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,AdvConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Time between the beginning of two consecutive advertising PDU\'s.\nTime = N * 0.625 msec\nTime Range: <=10msec."]
#[inline(always)]
pub fn adv_pkt_interval(
self,
) -> crate::common::RegisterField<11, 0x1f, 1, 0, u8, u8, AdvConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<11,0x1f,1,0,u8,u8,AdvConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for AdvConfig {
#[inline(always)]
fn default() -> AdvConfig {
<crate::RegValueT<AdvConfig_SPEC> as RegisterValue<_>>::new(8447)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ScanConfig_SPEC;
impl crate::sealed::RegSpec for ScanConfig_SPEC {
type DataType = u32;
}
#[doc = "Scan configuration register"]
pub type ScanConfig = crate::RegValueT<ScanConfig_SPEC>;
impl ScanConfig {
#[doc = "Enable scan event start interrupt."]
#[inline(always)]
pub fn scn_strt_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ScanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ScanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable scan event close interrupt."]
#[inline(always)]
pub fn scn_close_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ScanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,ScanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable scan request packet transmitted interrupt."]
#[inline(always)]
pub fn scn_tx_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ScanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,ScanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable adv packet received interrupt ."]
#[inline(always)]
pub fn adv_rx_en(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ScanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,ScanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable scan_rsp packet received interrupt ."]
#[inline(always)]
pub fn scn_rsp_rx_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ScanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,ScanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable ADV peer address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_1_2 and PRIV_1_2_SCAN are set."]
#[inline(always)]
pub fn scn_adv_rx_intr_peer_rpa_unmch_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ScanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,ScanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable ADV self address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_1_2 and PRIV_1_2_SCAN are set."]
#[inline(always)]
pub fn scn_adv_rx_intr_self_rpa_unmch_en(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, ScanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,ScanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable SCANA RPA TX not set interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set."]
#[inline(always)]
pub fn scana_tx_addr_not_set_intr_en(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, ScanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,ScanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit controls the SCAN engine behavior when an self address match occurs but a privacy mismatch occurs\n0 - The packet is aborted\n1 - The packet is received and reported to the Link Layer firmware\nThis bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set."]
#[inline(always)]
pub fn rpt_self_addr_match_priv_mismatch_scn(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, ScanConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,ScanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable random backoff feature in scanner.\n1 - enable\n0 - disable"]
#[inline(always)]
pub fn backoff_enable(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, ScanConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<11,1,0,ScanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Advertising channels that are enabled for scanning operation.\nBit 15: setting 1 - enables channel 39 for use.\nBit 14: setting 1 - enables channel 38 for use.\nBit 13: setting 1 - enables channel 37 for use."]
#[inline(always)]
pub fn scan_channel_map(
self,
) -> crate::common::RegisterField<13, 0x7, 1, 0, u8, u8, ScanConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<13,0x7,1,0,u8,u8,ScanConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ScanConfig {
#[inline(always)]
fn default() -> ScanConfig {
<crate::RegValueT<ScanConfig_SPEC> as RegisterValue<_>>::new(57375)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InitConfig_SPEC;
impl crate::sealed::RegSpec for InitConfig_SPEC {
type DataType = u32;
}
#[doc = "Initiator configuration register"]
pub type InitConfig = crate::RegValueT<InitConfig_SPEC>;
impl InitConfig {
#[doc = "Enable Initiator event start interrupt."]
#[inline(always)]
pub fn init_strt_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, InitConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,InitConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable Initiator event close interrupt."]
#[inline(always)]
pub fn init_close_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, InitConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,InitConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables connection request packet transmission start interrupt."]
#[inline(always)]
pub fn conn_req_tx_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, InitConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,InitConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable master connection created interrupt"]
#[inline(always)]
pub fn conn_created(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, InitConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,InitConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable ADV self address RPA unresolved interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set."]
#[inline(always)]
pub fn init_adv_rx_intr_self_rpa_unres_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, InitConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,InitConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable ADV peer address RPA unresolved interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set."]
#[inline(always)]
pub fn init_adv_rx_intr_peer_rpa_unres_en(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, InitConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,InitConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable INITA RPA TX not set interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set."]
#[inline(always)]
pub fn inita_tx_addr_not_set_intr_en(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, InitConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,InitConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Advertising channels that are enabled for initiator scanning operation.\nBit 15: setting 1 - enables channel 39 for use.\nBit 14: setting 1 - enables channel 38 for use.\nBit 13: setting 1 - enables channel 37 for use."]
#[inline(always)]
pub fn init_channel_map(
self,
) -> crate::common::RegisterField<13, 0x7, 1, 0, u8, u8, InitConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<13,0x7,1,0,u8,u8,InitConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for InitConfig {
#[inline(always)]
fn default() -> InitConfig {
<crate::RegValueT<InitConfig_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnConfig_SPEC;
impl crate::sealed::RegSpec for ConnConfig_SPEC {
type DataType = u32;
}
#[doc = "Connection configuration register"]
pub type ConnConfig = crate::RegValueT<ConnConfig_SPEC>;
impl ConnConfig {
#[doc = "Defines a limit for the number of Rx packets that can be re-ceived by the LLH. Default maximum value is 0xF.Minimum value shall be \'1\' or no packet will be stored in the Rx FIFO."]
#[inline(always)]
pub fn rx_pkt_limit(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, ConnConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,ConnConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register field allows setting a threshold for the packet received interrupt to the firmware.\nFor example if the value programmed is\n0x2 - then HW will generate interrupt only on receiving the second packet. \nIn any case if the received number of packets in a conn event is less than the threshold or there are still packets (less than threshold) pending in the Rx FIFO, HW will generate the interrupt at the ce_close.\nMin value possible is 1. Max value depends on the Rx FIFO capacity."]
#[inline(always)]
pub fn rx_intr_threshold(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, ConnConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0xf,1,0,u8,u8,ConnConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register field indicates whether the MD (More Data) bit needs to be controlled by \'software\' or, \'hardware and soft-ware logic combined\'.\n1 - MD bit is exclusively controlled by software, ie based on status of CE_CNFG_STS_REGISTER\\[6\\] - md bit.\n0 - MD Bit in the transmitted pdu is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the md bit in CE_CNFG_STS_REGISTER\\[6\\] and either of the following conditions is true,\na) If there are packets queued for transmission.\nb) If there is an acknowledgement awaited from the remote side for the packet transmitted."]
#[inline(always)]
pub fn md_bit_clear(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, ConnConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,ConnConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit configures the DSM slot counting mode.\n0 - The DSM slot count variance with respect to actual time is less than 1 slot\n1 - The DSM slot count variance with respect to actual time is more than 1 slot &less that 2 slots"]
#[inline(always)]
pub fn dsm_slot_variance(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, ConnConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<11,1,0,ConnConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is set to configure the MD bit control when IUT is in slave role.\n1 - MD bit will be decided on packet pending status\n0 - MD bit will be decided on packet queued in next buffer status\nThis bit has effect only when \'CONN_CONFIG.md_bit_ctr\' bit is not set ."]
#[inline(always)]
pub fn slv_md_config(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, ConnConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<12,1,0,ConnConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used to enable/disable extending the additional rx window on slave side during connection update in event of packet miss at the update instant.\n1 - Enable\n0 - Disable"]
#[inline(always)]
pub fn extend_cu_tx_win(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, ConnConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<13,1,0,ConnConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used to enable/disable masking of internal hardware supervision timeout trigger when switching from old connection parameters to new parameters. \n1 - Enable\n0 - Disable"]
#[inline(always)]
pub fn mask_suto_at_updt(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, ConnConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<14,1,0,ConnConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used to enable extension of the Conn Request to arbiter to 1 slot early. When enabled the request length is 2 slots.\n1 - Enable\n0 - Disable"]
#[inline(always)]
pub fn conn_req_1slot_early(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, ConnConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<15,1,0,ConnConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ConnConfig {
#[inline(always)]
fn default() -> ConnConfig {
<crate::RegValueT<ConnConfig_SPEC> as RegisterValue<_>>::new(57631)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnParam1_SPEC;
impl crate::sealed::RegSpec for ConnParam1_SPEC {
type DataType = u32;
}
#[doc = "Connection parameter 1"]
pub type ConnParam1 = crate::RegValueT<ConnParam1_SPEC>;
impl ConnParam1 {
#[doc = "Sleep Clock Accuracy"]
#[inline(always)]
pub fn sca_param(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, ConnParam1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,ConnParam1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Hop increment for connection channel."]
#[inline(always)]
pub fn hop_increment_param(
self,
) -> crate::common::RegisterField<3, 0x1f, 1, 0, u8, u8, ConnParam1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<3,0x1f,1,0,u8,u8,ConnParam1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field defines the lower byte (7:0) of the CRC initialization vector."]
#[inline(always)]
pub fn crc_init_l(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, ConnParam1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,ConnParam1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ConnParam1 {
#[inline(always)]
fn default() -> ConnParam1 {
<crate::RegValueT<ConnParam1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnParam2_SPEC;
impl crate::sealed::RegSpec for ConnParam2_SPEC {
type DataType = u32;
}
#[doc = "Connection parameter 2"]
pub type ConnParam2 = crate::RegValueT<ConnParam2_SPEC>;
impl ConnParam2 {
#[doc = "This field defines the upper two bytes (23:8) of the CRC initialization vector."]
#[inline(always)]
pub fn crc_init_h(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnParam2_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnParam2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnParam2 {
#[inline(always)]
fn default() -> ConnParam2 {
<crate::RegValueT<ConnParam2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnIntrMask_SPEC;
impl crate::sealed::RegSpec for ConnIntrMask_SPEC {
type DataType = u32;
}
#[doc = "Connection Interrupt mask"]
pub type ConnIntrMask = crate::RegValueT<ConnIntrMask_SPEC>;
impl ConnIntrMask {
#[doc = "If this bit is set connection closed interrupt is enabled."]
#[inline(always)]
pub fn conn_cl_int_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ConnIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ConnIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set connection establishment interrupt is enabled."]
#[inline(always)]
pub fn conn_estb_int_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ConnIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,ConnIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set, channel map update interrupt is enabled."]
#[inline(always)]
pub fn map_updt_int_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ConnIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,ConnIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set connection event start interrupt is enabled"]
#[inline(always)]
pub fn start_ce_int_en(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ConnIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,ConnIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set connection event closed interrupt is enabled."]
#[inline(always)]
pub fn close_ce_int_en(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ConnIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,ConnIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set transmission acknowledgement interrupt is enabled: \nThis interrupt is generated to indicate to the firmware that a non-empty packet transmitted is successfully acknowledged by the remote device.\nFor negative acknowledgements from remote device, this interrupt indication is not generated."]
#[inline(always)]
pub fn ce_tx_ack_int_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ConnIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,ConnIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set interrupt is enabled for reception of packet in a connection event."]
#[inline(always)]
pub fn ce_rx_int_en(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, ConnIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,ConnIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set connection update interrupt is enabled."]
#[inline(always)]
pub fn conn_update_intr_en(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, ConnIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<7,1,0,ConnIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set packet receive good pdu interrupt is enabled. Effective only when bit 6 is set."]
#[inline(always)]
pub fn rx_good_pdu_int_en(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, ConnIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<8,1,0,ConnIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set packet receive bad pdu interrupt is enabled. Effective only when bit 6 is set."]
#[inline(always)]
pub fn rx_bad_pdu_int_en(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, ConnIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<9,1,0,ConnIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this but us set, the RX interrupt is triggerred for an end of connection event with a null packet"]
#[inline(always)]
pub fn ce_close_null_rx_int_en(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, ConnIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<13,1,0,ConnIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set ping timer expired interrupt is enabled."]
#[inline(always)]
pub fn ping_timer_expird_intr(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, ConnIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<14,1,0,ConnIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If this bit is set ping timer nearly expired interrupt is enabled"]
#[inline(always)]
pub fn ping_nearly_expird_intr(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, ConnIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<15,1,0,ConnIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ConnIntrMask {
#[inline(always)]
fn default() -> ConnIntrMask {
<crate::RegValueT<ConnIntrMask_SPEC> as RegisterValue<_>>::new(8192)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SlaveTimingControl_SPEC;
impl crate::sealed::RegSpec for SlaveTimingControl_SPEC {
type DataType = u32;
}
#[doc = "slave timing control"]
pub type SlaveTimingControl = crate::RegValueT<SlaveTimingControl_SPEC>;
impl SlaveTimingControl {
#[doc = "Programmable adjust value to the clock counter when slave is connected"]
#[inline(always)]
pub fn slave_time_set_val(
self,
) -> crate::common::RegisterField<
0,
0xff,
1,
0,
u8,
u8,
SlaveTimingControl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xff,
1,
0,
u8,
u8,
SlaveTimingControl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Timing adjust value. The internal micro second counter is adjusted to this value whenever slave receives a good access address match at connection anchor point. This will ensure the slave gets synchronized to master timing."]
#[inline(always)]
pub fn slave_time_adj_val(
self,
) -> crate::common::RegisterField<
8,
0xff,
1,
0,
u8,
u8,
SlaveTimingControl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0xff,
1,
0,
u8,
u8,
SlaveTimingControl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for SlaveTimingControl {
#[inline(always)]
fn default() -> SlaveTimingControl {
<crate::RegValueT<SlaveTimingControl_SPEC> as RegisterValue<_>>::new(48790)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ReceiveTrigCtrl_SPEC;
impl crate::sealed::RegSpec for ReceiveTrigCtrl_SPEC {
type DataType = u32;
}
#[doc = "Receive trigger control"]
pub type ReceiveTrigCtrl = crate::RegValueT<ReceiveTrigCtrl_SPEC>;
impl ReceiveTrigCtrl {
#[doc = "Access address match threshold value. Number of bits of ac-cess address that should match with the expected access ad-dress to trigger an access code match. \n\nMax value : 32 (for 32-bit access address)\nLower values may be programmed for bad radios or channels but care must be taken to ensure there are no \'false\' matches due to reduced number of bits required to match."]
#[inline(always)]
pub fn acc_trigger_threshold(
self,
) -> crate::common::RegisterField<
0,
0x3f,
1,
0,
u8,
u8,
ReceiveTrigCtrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3f,
1,
0,
u8,
u8,
ReceiveTrigCtrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "If access address match does not occur then within this time from the start of receive operation, the receive operation times out and stops. An internal counter value of 1usec resolution is continuously compared with the value programmed.\nMax value :0xFF"]
#[inline(always)]
pub fn acc_trigger_timeout(
self,
) -> crate::common::RegisterField<
8,
0xff,
1,
0,
u8,
u8,
ReceiveTrigCtrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0xff,
1,
0,
u8,
u8,
ReceiveTrigCtrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ReceiveTrigCtrl {
#[inline(always)]
fn default() -> ReceiveTrigCtrl {
<crate::RegValueT<ReceiveTrigCtrl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LlDbg1_SPEC;
impl crate::sealed::RegSpec for LlDbg1_SPEC {
type DataType = u32;
}
#[doc = "LL debug register 1"]
pub type LlDbg1 = crate::RegValueT<LlDbg1_SPEC>;
impl LlDbg1 {
#[doc = "Connection receive FIFO write pointer"]
#[inline(always)]
pub fn conn_rx_wr_ptr(
self,
) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, LlDbg1_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x3ff,1,0,u16,u16,LlDbg1_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for LlDbg1 {
#[inline(always)]
fn default() -> LlDbg1 {
<crate::RegValueT<LlDbg1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LlDbg2_SPEC;
impl crate::sealed::RegSpec for LlDbg2_SPEC {
type DataType = u32;
}
#[doc = "LL debug register 2"]
pub type LlDbg2 = crate::RegValueT<LlDbg2_SPEC>;
impl LlDbg2 {
#[doc = "Connection receive FIFO read pointer"]
#[inline(always)]
pub fn conn_rx_rd_ptr(
self,
) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, LlDbg2_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x3ff,1,0,u16,u16,LlDbg2_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for LlDbg2 {
#[inline(always)]
fn default() -> LlDbg2 {
<crate::RegValueT<LlDbg2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LlDbg3_SPEC;
impl crate::sealed::RegSpec for LlDbg3_SPEC {
type DataType = u32;
}
#[doc = "LL debug register 3"]
pub type LlDbg3 = crate::RegValueT<LlDbg3_SPEC>;
impl LlDbg3 {
#[doc = "Connection receive FIFO stored write pointer for pointer restore"]
#[inline(always)]
pub fn conn_rx_wr_ptr_store(
self,
) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, LlDbg3_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x3ff,1,0,u16,u16,LlDbg3_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for LlDbg3 {
#[inline(always)]
fn default() -> LlDbg3 {
<crate::RegValueT<LlDbg3_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LlDbg4_SPEC;
impl crate::sealed::RegSpec for LlDbg4_SPEC {
type DataType = u32;
}
#[doc = "LL debug register 4"]
pub type LlDbg4 = crate::RegValueT<LlDbg4_SPEC>;
impl LlDbg4 {
#[doc = "Connection FSM state"]
#[inline(always)]
pub fn connection_fsm_state(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, LlDbg4_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,LlDbg4_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Slave Latency FSM state"]
#[inline(always)]
pub fn slave_latency_fsm_state(
self,
) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, LlDbg4_SPEC, crate::common::R>
{
crate::common::RegisterField::<4,0x3,1,0,u8,u8,LlDbg4_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Advertiser FSM state"]
#[inline(always)]
pub fn advertiser_fsm_state(
self,
) -> crate::common::RegisterField<6, 0x1f, 1, 0, u8, u8, LlDbg4_SPEC, crate::common::R>
{
crate::common::RegisterField::<6,0x1f,1,0,u8,u8,LlDbg4_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for LlDbg4 {
#[inline(always)]
fn default() -> LlDbg4 {
<crate::RegValueT<LlDbg4_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LlDbg5_SPEC;
impl crate::sealed::RegSpec for LlDbg5_SPEC {
type DataType = u32;
}
#[doc = "LL debug register 5"]
pub type LlDbg5 = crate::RegValueT<LlDbg5_SPEC>;
impl LlDbg5 {
#[doc = "Initiator FSM state"]
#[inline(always)]
pub fn init_fsm_state(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, LlDbg5_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,LlDbg5_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Scanner FSM state"]
#[inline(always)]
pub fn scan_fsm_state(
self,
) -> crate::common::RegisterField<5, 0x1f, 1, 0, u8, u8, LlDbg5_SPEC, crate::common::R>
{
crate::common::RegisterField::<5,0x1f,1,0,u8,u8,LlDbg5_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for LlDbg5 {
#[inline(always)]
fn default() -> LlDbg5 {
<crate::RegValueT<LlDbg5_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LlDbg6_SPEC;
impl crate::sealed::RegSpec for LlDbg6_SPEC {
type DataType = u32;
}
#[doc = "LL debug register 6"]
pub type LlDbg6 = crate::RegValueT<LlDbg6_SPEC>;
impl LlDbg6 {
#[doc = "Advertiser Transmit FIFO write pointer"]
#[inline(always)]
pub fn adv_tx_wr_ptr(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, LlDbg6_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,LlDbg6_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Scan Response Transmit FIFO write pointer"]
#[inline(always)]
pub fn scan_rsp_tx_wr_ptr(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, LlDbg6_SPEC, crate::common::R>
{
crate::common::RegisterField::<4,0xf,1,0,u8,u8,LlDbg6_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Advertiser/ Scan Response FIFO read pointer"]
#[inline(always)]
pub fn adv_tx_rd_ptr(
self,
) -> crate::common::RegisterField<8, 0x3f, 1, 0, u8, u8, LlDbg6_SPEC, crate::common::R>
{
crate::common::RegisterField::<8,0x3f,1,0,u8,u8,LlDbg6_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for LlDbg6 {
#[inline(always)]
fn default() -> LlDbg6 {
<crate::RegValueT<LlDbg6_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LlDbg7_SPEC;
impl crate::sealed::RegSpec for LlDbg7_SPEC {
type DataType = u32;
}
#[doc = "LL debug register 7"]
pub type LlDbg7 = crate::RegValueT<LlDbg7_SPEC>;
impl LlDbg7 {
#[doc = "Advertiser Receive FIFO write pointer"]
#[inline(always)]
pub fn adv_rx_wr_ptr(
self,
) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, LlDbg7_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x7f,1,0,u8,u8,LlDbg7_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Advertiser Receive FIFO read pointer"]
#[inline(always)]
pub fn adv_rx_rd_ptr(
self,
) -> crate::common::RegisterField<7, 0x7f, 1, 0, u8, u8, LlDbg7_SPEC, crate::common::R>
{
crate::common::RegisterField::<7,0x7f,1,0,u8,u8,LlDbg7_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for LlDbg7 {
#[inline(always)]
fn default() -> LlDbg7 {
<crate::RegValueT<LlDbg7_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LlDbg8_SPEC;
impl crate::sealed::RegSpec for LlDbg8_SPEC {
type DataType = u32;
}
#[doc = "LL debug register 8"]
pub type LlDbg8 = crate::RegValueT<LlDbg8_SPEC>;
impl LlDbg8 {
#[doc = "Advertiser Receive FIFO stored write pointer for pointer restore"]
#[inline(always)]
pub fn adv_rx_wr_ptr_store(
self,
) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, LlDbg8_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x7f,1,0,u8,u8,LlDbg8_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Whitelist FIFO pointer"]
#[inline(always)]
pub fn wlf_ptr(
self,
) -> crate::common::RegisterField<7, 0x7f, 1, 0, u8, u8, LlDbg8_SPEC, crate::common::R>
{
crate::common::RegisterField::<7,0x7f,1,0,u8,u8,LlDbg8_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for LlDbg8 {
#[inline(always)]
fn default() -> LlDbg8 {
<crate::RegValueT<LlDbg8_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LlDbg9_SPEC;
impl crate::sealed::RegSpec for LlDbg9_SPEC {
type DataType = u32;
}
#[doc = "LL debug register 9"]
pub type LlDbg9 = crate::RegValueT<LlDbg9_SPEC>;
impl LlDbg9 {
#[doc = "Window Widening value in us. The reset value of this register is 0x0000. After reset de-assertion, at the first clock cycle, the value 0x0010 is assigned to the register."]
#[inline(always)]
pub fn window_widen(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, LlDbg9_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,LlDbg9_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for LlDbg9 {
#[inline(always)]
fn default() -> LlDbg9 {
<crate::RegValueT<LlDbg9_SPEC> as RegisterValue<_>>::new(16)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LlDbg10_SPEC;
impl crate::sealed::RegSpec for LlDbg10_SPEC {
type DataType = u32;
}
#[doc = "LL debug register 10"]
pub type LlDbg10 = crate::RegValueT<LlDbg10_SPEC>;
impl LlDbg10 {
#[doc = "Active channel number"]
#[inline(always)]
pub fn rf_channel_num(
self,
) -> crate::common::RegisterField<0, 0x3f, 1, 0, u8, u8, LlDbg10_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x3f,1,0,u8,u8,LlDbg10_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for LlDbg10 {
#[inline(always)]
fn default() -> LlDbg10 {
<crate::RegValueT<LlDbg10_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PeerAddrInitL_SPEC;
impl crate::sealed::RegSpec for PeerAddrInitL_SPEC {
type DataType = u32;
}
#[doc = "Lower 16 bit address of the peer device for INIT."]
pub type PeerAddrInitL = crate::RegValueT<PeerAddrInitL_SPEC>;
impl PeerAddrInitL {
#[doc = "Lower 16 bit of 48-bit address of the peer device. This is used only in MMMS mode\n\nThe peer address registers are used for multiple purposes. The register is written by firmware to provide the peer address to be used for a hardware procedure. When firmware reads the register, it reads back peer address values updated by hardware. \n\nWhile device is configured as an initiator without white list filtering, the peer address specified in the peer_address field of the create connection command is programmed into this register, which is used by hard-ware procedures.\n\nWhile device is configured as an initiator and white list is enabled, firmware can read this register to get the address of the peer device from which connectable ADV packet was received and to which the connection is created."]
#[inline(always)]
pub fn peer_addr_l(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
PeerAddrInitL_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
PeerAddrInitL_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PeerAddrInitL {
#[inline(always)]
fn default() -> PeerAddrInitL {
<crate::RegValueT<PeerAddrInitL_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PeerAddrInitM_SPEC;
impl crate::sealed::RegSpec for PeerAddrInitM_SPEC {
type DataType = u32;
}
#[doc = "Middle 16 bit address of the peer device for INIT."]
pub type PeerAddrInitM = crate::RegValueT<PeerAddrInitM_SPEC>;
impl PeerAddrInitM {
#[doc = "Middle 16 bit of 48-bit address of the peer device. This is used only in MMMS mode\n\nThe peer address registers are used for multiple purposes. The register is written by firmware to provide the peer address to be used for a hardware procedure. When firmware reads the register, it reads back peer address values updated by hardware. \n\nWhile device is configured as an initiator without white list filtering, the peer address specified in the peer_address field of the create connection command is programmed into this register, which is used by hard-ware procedures.\n\nWhile device is configured as an initiator and white list is enabled, firmware can read this register to get the address of the peer device from which connectable ADV packet was received and to which the connection is created."]
#[inline(always)]
pub fn peer_addr_m(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
PeerAddrInitM_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
PeerAddrInitM_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PeerAddrInitM {
#[inline(always)]
fn default() -> PeerAddrInitM {
<crate::RegValueT<PeerAddrInitM_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PeerAddrInitH_SPEC;
impl crate::sealed::RegSpec for PeerAddrInitH_SPEC {
type DataType = u32;
}
#[doc = "Higher 16 bit address of the peer device for INIT."]
pub type PeerAddrInitH = crate::RegValueT<PeerAddrInitH_SPEC>;
impl PeerAddrInitH {
#[doc = "Higher 16 bit of 48-bit address of the peer device. This is used only in MMMS mode\n\nThe peer address registers are used for multiple purposes. The register is written by firmware to provide the peer address to be used for a hardware procedure. When firmware reads the register, it reads back peer address values updated by hardware. \n\nWhile device is configured as an initiator without white list filtering, the peer address specified in the peer_address field of the create connection command is programmed into this register, which is used by hard-ware procedures.\n\nWhile device is configured as an initiator and white list is enabled, firmware can read this register to get the address of the peer device from which connectable ADV packet was received and to which the connection is created."]
#[inline(always)]
pub fn peer_addr_h(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
PeerAddrInitH_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
PeerAddrInitH_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PeerAddrInitH {
#[inline(always)]
fn default() -> PeerAddrInitH {
<crate::RegValueT<PeerAddrInitH_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PeerSecAddrAdvL_SPEC;
impl crate::sealed::RegSpec for PeerSecAddrAdvL_SPEC {
type DataType = u32;
}
#[doc = "Lower 16 bits of the secondary address of the peer device for ADV_DIR."]
pub type PeerSecAddrAdvL = crate::RegValueT<PeerSecAddrAdvL_SPEC>;
impl PeerSecAddrAdvL {
#[doc = "Lower 16 bit of 48-bit secondary address of the peer device for ADV_DIR."]
#[inline(always)]
pub fn peer_sec_addr_l(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
PeerSecAddrAdvL_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
PeerSecAddrAdvL_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PeerSecAddrAdvL {
#[inline(always)]
fn default() -> PeerSecAddrAdvL {
<crate::RegValueT<PeerSecAddrAdvL_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PeerSecAddrAdvM_SPEC;
impl crate::sealed::RegSpec for PeerSecAddrAdvM_SPEC {
type DataType = u32;
}
#[doc = "Middle 16 bits of the secondary address of the peer device for ADV_DIR."]
pub type PeerSecAddrAdvM = crate::RegValueT<PeerSecAddrAdvM_SPEC>;
impl PeerSecAddrAdvM {
#[doc = "Middle 16 bit of 48-bit secondary address of the peer device for ADV_DIR."]
#[inline(always)]
pub fn peer_sec_addr_m(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
PeerSecAddrAdvM_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
PeerSecAddrAdvM_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PeerSecAddrAdvM {
#[inline(always)]
fn default() -> PeerSecAddrAdvM {
<crate::RegValueT<PeerSecAddrAdvM_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PeerSecAddrAdvH_SPEC;
impl crate::sealed::RegSpec for PeerSecAddrAdvH_SPEC {
type DataType = u32;
}
#[doc = "Higher 16 bits of the secondary address of the peer device for ADV_DIR."]
pub type PeerSecAddrAdvH = crate::RegValueT<PeerSecAddrAdvH_SPEC>;
impl PeerSecAddrAdvH {
#[doc = "Higher 16 bit of 48-bit secondary address of the peer device for ADV_DIR.\n\nWhile doing directed Advertising in device privacy mode, if the peer device has shared its IRK, then the peer device RPA is written into the PEER_ADDR registers and the peer device identity address is written into this register. If the peer device has not shared its IRK, then the peer identity address is written into the PEER_ADDR registers and this register must be cleared."]
#[inline(always)]
pub fn peer_sec_addr_h(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
PeerSecAddrAdvH_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
PeerSecAddrAdvH_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PeerSecAddrAdvH {
#[inline(always)]
fn default() -> PeerSecAddrAdvH {
<crate::RegValueT<PeerSecAddrAdvH_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InitWindowTimerCtrl_SPEC;
impl crate::sealed::RegSpec for InitWindowTimerCtrl_SPEC {
type DataType = u32;
}
#[doc = "Initiator Window NI timer control"]
pub type InitWindowTimerCtrl = crate::RegValueT<InitWindowTimerCtrl_SPEC>;
impl InitWindowTimerCtrl {
#[doc = "Controls the INIT Window offset source\n1 - Pick INIT Window Offset from HW calculated INIT_WINDOW_OFFSET\n0 - Pick INIT Window Offset from FW loaded register"]
#[inline(always)]
pub fn init_window_offset_sel(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, InitWindowTimerCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,InitWindowTimerCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for InitWindowTimerCtrl {
#[inline(always)]
fn default() -> InitWindowTimerCtrl {
<crate::RegValueT<InitWindowTimerCtrl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnConfigExt_SPEC;
impl crate::sealed::RegSpec for ConnConfigExt_SPEC {
type DataType = u32;
}
#[doc = "Connection extended configuration register"]
pub type ConnConfigExt = crate::RegValueT<ConnConfigExt_SPEC>;
impl ConnConfigExt {
#[doc = "This bit is used to enable extension of the Conn Request to arbiter to 2 slot early. When enabled the request length is 3 slots, irrespective of the status of CONN_REQ_1SLOT_EARLY bit.\n1 - Enable\n0 - Disable"]
#[inline(always)]
pub fn conn_req_2slot_early(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ConnConfigExt_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,ConnConfigExt_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used to enable extension of the Conn Request to arbiter to 3 slot early. When enabled the request length is 4 slots, irrespective of the status of CONN_REQ_1SLOT_EARLY & CONN_REQ_2SLOT_EARLY bits.\n1 - Enable\n0 - Disable"]
#[inline(always)]
pub fn conn_req_3slot_early(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ConnConfigExt_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,ConnConfigExt_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Connection Index for which the FW generates Packet Received Command. In MMMS mode, FW should write this field before giving PKT_RECEIVE_COMMAND to HW."]
#[inline(always)]
pub fn fw_pkt_rcv_conn_index(
self,
) -> crate::common::RegisterField<
2,
0x1f,
1,
0,
u8,
u8,
ConnConfigExt_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0x1f,
1,
0,
u8,
u8,
ConnConfigExt_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Receive Packet Limit for MMMS mode. This is the RX_FIFO Limit and applies to all connections together"]
#[inline(always)]
pub fn mmms_rx_pkt_limit(
self,
) -> crate::common::RegisterField<
8,
0x3f,
1,
0,
u8,
u8,
ConnConfigExt_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0x3f,
1,
0,
u8,
u8,
ConnConfigExt_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "MMMS CE expire control bit"]
#[inline(always)]
pub fn debug_ce_expire(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, ConnConfigExt_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<14,1,0,ConnConfigExt_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "MMMS empty PDU CE expire handling control bit"]
#[inline(always)]
pub fn mt_pdu_ce_expire(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, ConnConfigExt_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<15,1,0,ConnConfigExt_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ConnConfigExt {
#[inline(always)]
fn default() -> ConnConfigExt {
<crate::RegValueT<ConnConfigExt_SPEC> as RegisterValue<_>>::new(40960)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DpllConfig_SPEC;
impl crate::sealed::RegSpec for DpllConfig_SPEC {
type DataType = u32;
}
#[doc = "DPLL & CY Correlator configuration register"]
pub type DpllConfig = crate::RegValueT<DpllConfig_SPEC>;
impl DpllConfig {
#[doc = "If MXD_IF_OPTION is 0:\nNot used\n\nIf CY_CORREL_EN is 1:\n\\[11:0\\] CY correl Access address compare mask for LSB 12 bits. Ideal value is 0xFFF\n\\[15:12\\] CY correl maximum number of allowed mismatched bits in access address. Ideal value is 0x0."]
#[inline(always)]
pub fn dpll_correl_config(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
DpllConfig_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
DpllConfig_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DpllConfig {
#[inline(always)]
fn default() -> DpllConfig {
<crate::RegValueT<DpllConfig_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InitNiVal_SPEC;
impl crate::sealed::RegSpec for InitNiVal_SPEC {
type DataType = u32;
}
#[doc = "Initiator Window NI instant"]
pub type InitNiVal = crate::RegValueT<InitNiVal_SPEC>;
impl InitNiVal {
#[doc = "Initiator window Next Instant value used for spacing Master connections in time, to minimize connection contention. This value is in 625us slots.\nThe read value corresponds to the hardware updated Interval value"]
#[inline(always)]
pub fn init_ni_val(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
InitNiVal_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
InitNiVal_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for InitNiVal {
#[inline(always)]
fn default() -> InitNiVal {
<crate::RegValueT<InitNiVal_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InitWindowOffset_SPEC;
impl crate::sealed::RegSpec for InitWindowOffset_SPEC {
type DataType = u32;
}
#[doc = "Initiator Window offset captured at conn request"]
pub type InitWindowOffset = crate::RegValueT<InitWindowOffset_SPEC>;
impl InitWindowOffset {
#[doc = "Initiator Window offset captured at conn request. This value is in 1.25ms slots"]
#[inline(always)]
pub fn init_window_ni(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
InitWindowOffset_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
InitWindowOffset_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for InitWindowOffset {
#[inline(always)]
fn default() -> InitWindowOffset {
<crate::RegValueT<InitWindowOffset_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InitWindowNiAnchorPt_SPEC;
impl crate::sealed::RegSpec for InitWindowNiAnchorPt_SPEC {
type DataType = u32;
}
#[doc = "Initiator Window NI anchor point captured at conn request"]
pub type InitWindowNiAnchorPt = crate::RegValueT<InitWindowNiAnchorPt_SPEC>;
impl InitWindowNiAnchorPt {
#[doc = "Initiator interval offset captured at conn request. The value indicates the master connection anchor point. This value is in 625us slots"]
#[inline(always)]
pub fn init_int_off_capt(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
InitWindowNiAnchorPt_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
InitWindowNiAnchorPt_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for InitWindowNiAnchorPt {
#[inline(always)]
fn default() -> InitWindowNiAnchorPt {
<crate::RegValueT<InitWindowNiAnchorPt_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnUpdateNewInterval_SPEC;
impl crate::sealed::RegSpec for ConnUpdateNewInterval_SPEC {
type DataType = u32;
}
#[doc = "Connection update new interval"]
pub type ConnUpdateNewInterval = crate::RegValueT<ConnUpdateNewInterval_SPEC>;
impl ConnUpdateNewInterval {
#[doc = "This register will have the new connection interval that the hardware will use after the connection update instant. Before the instant, the connection interval in the register CONN_INTERVAL will be used by hardware."]
#[inline(always)]
pub fn conn_updt_interval(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnUpdateNewInterval_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnUpdateNewInterval_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnUpdateNewInterval {
#[inline(always)]
fn default() -> ConnUpdateNewInterval {
<crate::RegValueT<ConnUpdateNewInterval_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnUpdateNewLatency_SPEC;
impl crate::sealed::RegSpec for ConnUpdateNewLatency_SPEC {
type DataType = u32;
}
#[doc = "Connection update new latency"]
pub type ConnUpdateNewLatency = crate::RegValueT<ConnUpdateNewLatency_SPEC>;
impl ConnUpdateNewLatency {
#[doc = "This register will have the new slave latency parameter that the hardware will use after the connection update instant. Before the instant, the connection interval in the register SLAVE_LATENCY will be used by hardware."]
#[inline(always)]
pub fn conn_updt_slv_latency(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnUpdateNewLatency_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnUpdateNewLatency_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnUpdateNewLatency {
#[inline(always)]
fn default() -> ConnUpdateNewLatency {
<crate::RegValueT<ConnUpdateNewLatency_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnUpdateNewSupTo_SPEC;
impl crate::sealed::RegSpec for ConnUpdateNewSupTo_SPEC {
type DataType = u32;
}
#[doc = "Connection update new supervision timeout"]
pub type ConnUpdateNewSupTo = crate::RegValueT<ConnUpdateNewSupTo_SPEC>;
impl ConnUpdateNewSupTo {
#[doc = "This register will have the new supervision timeout that the hardware will use after the connection update instant. Before the instant, the connection interval in the register SUP_TIMEOUT will be used by hardware."]
#[inline(always)]
pub fn conn_updt_sup_to(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnUpdateNewSupTo_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnUpdateNewSupTo_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnUpdateNewSupTo {
#[inline(always)]
fn default() -> ConnUpdateNewSupTo {
<crate::RegValueT<ConnUpdateNewSupTo_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnUpdateNewSlInterval_SPEC;
impl crate::sealed::RegSpec for ConnUpdateNewSlInterval_SPEC {
type DataType = u32;
}
#[doc = "Connection update new Slave Latency X Conn interval Value"]
pub type ConnUpdateNewSlInterval = crate::RegValueT<ConnUpdateNewSlInterval_SPEC>;
impl ConnUpdateNewSlInterval {
#[doc = "This register will have the new Slave Latency * Conn Interval value that the hardware will use after the connection update instant. Before the instant, the connection interval in the register SL_CONN_INTERVAL will be used by hardware."]
#[inline(always)]
pub fn sl_conn_interval_val(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnUpdateNewSlInterval_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnUpdateNewSlInterval_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnUpdateNewSlInterval {
#[inline(always)]
fn default() -> ConnUpdateNewSlInterval {
<crate::RegValueT<ConnUpdateNewSlInterval_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnReqWord0_SPEC;
impl crate::sealed::RegSpec for ConnReqWord0_SPEC {
type DataType = u32;
}
#[doc = "Connection request address word 0"]
pub type ConnReqWord0 = crate::RegValueT<ConnReqWord0_SPEC>;
impl ConnReqWord0 {
#[doc = "This field defines the lower 16 bits of the access address that is to be sent in the connect request packet of the initiator."]
#[inline(always)]
pub fn access_addr_lower(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnReqWord0 {
#[inline(always)]
fn default() -> ConnReqWord0 {
<crate::RegValueT<ConnReqWord0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnReqWord1_SPEC;
impl crate::sealed::RegSpec for ConnReqWord1_SPEC {
type DataType = u32;
}
#[doc = "Connection request address word 1"]
pub type ConnReqWord1 = crate::RegValueT<ConnReqWord1_SPEC>;
impl ConnReqWord1 {
#[doc = "This field defines the upper16 bits of the access address that is to be sent in the connect request packet of the initiator."]
#[inline(always)]
pub fn access_addr_upper(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnReqWord1 {
#[inline(always)]
fn default() -> ConnReqWord1 {
<crate::RegValueT<ConnReqWord1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnReqWord2_SPEC;
impl crate::sealed::RegSpec for ConnReqWord2_SPEC {
type DataType = u32;
}
#[doc = "Connection request address word 2"]
pub type ConnReqWord2 = crate::RegValueT<ConnReqWord2_SPEC>;
impl ConnReqWord2 {
#[doc = "window_size along with the window_offset is used to calculate the first connection point anchor point for the master.\nThis shall be a multiple of 1.25 ms in the range of 1.25 ms to the lesser of 10 ms and (connInterval - 1.25 ms).\nValues range from 0 to 10 ms."]
#[inline(always)]
pub fn tx_window_size_val(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, ConnReqWord2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xff,
1,
0,
u8,
u8,
ConnReqWord2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This field defines the lower byte \\[7:0\\] of the CRC initialization value."]
#[inline(always)]
pub fn crc_init_lower(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, ConnReqWord2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
8,
0xff,
1,
0,
u8,
u8,
ConnReqWord2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnReqWord2 {
#[inline(always)]
fn default() -> ConnReqWord2 {
<crate::RegValueT<ConnReqWord2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnReqWord3_SPEC;
impl crate::sealed::RegSpec for ConnReqWord3_SPEC {
type DataType = u32;
}
#[doc = "Connection request address word 3"]
pub type ConnReqWord3 = crate::RegValueT<ConnReqWord3_SPEC>;
impl ConnReqWord3 {
#[doc = "This field defines the upper byte \\[23:8\\] of the CRC initialization value that is to be sent in the connect request packet of the initiator."]
#[inline(always)]
pub fn crc_init_upper(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord3_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord3_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnReqWord3 {
#[inline(always)]
fn default() -> ConnReqWord3 {
<crate::RegValueT<ConnReqWord3_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnReqWord4_SPEC;
impl crate::sealed::RegSpec for ConnReqWord4_SPEC {
type DataType = u32;
}
#[doc = "Connection request address word 4"]
pub type ConnReqWord4 = crate::RegValueT<ConnReqWord4_SPEC>;
impl ConnReqWord4 {
#[doc = "This is used to determine the anchor point for the master transmission.\nRange: This shall be a multiple of 1.25 ms in the range of 0 ms to connInterval value."]
#[inline(always)]
pub fn tx_window_offset(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord4_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord4_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnReqWord4 {
#[inline(always)]
fn default() -> ConnReqWord4 {
<crate::RegValueT<ConnReqWord4_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnReqWord5_SPEC;
impl crate::sealed::RegSpec for ConnReqWord5_SPEC {
type DataType = u32;
}
#[doc = "Connection request address word 5"]
pub type ConnReqWord5 = crate::RegValueT<ConnReqWord5_SPEC>;
impl ConnReqWord5 {
#[doc = "The value configured in this register determines the spacing between the connection events.\nThis shall be a multiple of 1.25 ms in the range of 7.5 ms to 4.0 s."]
#[inline(always)]
pub fn connection_interval_val(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord5_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord5_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnReqWord5 {
#[inline(always)]
fn default() -> ConnReqWord5 {
<crate::RegValueT<ConnReqWord5_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnReqWord6_SPEC;
impl crate::sealed::RegSpec for ConnReqWord6_SPEC {
type DataType = u32;
}
#[doc = "Connection request address word 6"]
pub type ConnReqWord6 = crate::RegValueT<ConnReqWord6_SPEC>;
impl ConnReqWord6 {
#[doc = "The value configured in this field defines the number of consecutive connection events that the slave device is not required to listen for master. The value of connSlaveLatency should not cause a Supervision Timeout. This shall be an integer in the range of 0 to ((connSupervision Timeout/connInterval)-1). connSlaveLatency shall also be less than 500."]
#[inline(always)]
pub fn slave_latency_val(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord6_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord6_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnReqWord6 {
#[inline(always)]
fn default() -> ConnReqWord6 {
<crate::RegValueT<ConnReqWord6_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnReqWord7_SPEC;
impl crate::sealed::RegSpec for ConnReqWord7_SPEC {
type DataType = u32;
}
#[doc = "Connection request address word 7"]
pub type ConnReqWord7 = crate::RegValueT<ConnReqWord7_SPEC>;
impl ConnReqWord7 {
#[doc = "This field defines the maximum time between two received Data packet PDUs before the connection is considered lost.\nThis shall be a multiple of 10 ms in the range of 100 ms to 32.0 s and it shall be larger than (1+connSlaveLatency)*connInterval."]
#[inline(always)]
pub fn supervision_timeout_val(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord7_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord7_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnReqWord7 {
#[inline(always)]
fn default() -> ConnReqWord7 {
<crate::RegValueT<ConnReqWord7_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnReqWord8_SPEC;
impl crate::sealed::RegSpec for ConnReqWord8_SPEC {
type DataType = u32;
}
#[doc = "Connection request address word 8"]
pub type ConnReqWord8 = crate::RegValueT<ConnReqWord8_SPEC>;
impl ConnReqWord8 {
#[doc = "This register field indicates which of the data channels are in use. This stores the information for the lower 16 (15:0) data channel indices.\n1\' indicates the corresponding data channel is used and \'0\' indicates the channel is unused."]
#[inline(always)]
pub fn data_channels_lower(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord8_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord8_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnReqWord8 {
#[inline(always)]
fn default() -> ConnReqWord8 {
<crate::RegValueT<ConnReqWord8_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnReqWord9_SPEC;
impl crate::sealed::RegSpec for ConnReqWord9_SPEC {
type DataType = u32;
}
#[doc = "Connection request address word 9"]
pub type ConnReqWord9 = crate::RegValueT<ConnReqWord9_SPEC>;
impl ConnReqWord9 {
#[doc = "This register field indicates which of the data channels are in use. This stores the information for the middle 16 (31:16) data channel indices.\n\'1\' indicates the corresponding data channel is used and \'0\' indicates the channel is unused."]
#[inline(always)]
pub fn data_channels_mid(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord9_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnReqWord9_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnReqWord9 {
#[inline(always)]
fn default() -> ConnReqWord9 {
<crate::RegValueT<ConnReqWord9_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnReqWord10_SPEC;
impl crate::sealed::RegSpec for ConnReqWord10_SPEC {
type DataType = u32;
}
#[doc = "Connection request address word 10"]
pub type ConnReqWord10 = crate::RegValueT<ConnReqWord10_SPEC>;
impl ConnReqWord10 {
#[doc = "This register field indicates which of the data channels are in use. This stores the information for the upper 5 (36:32) data channel indices.\n\'1\' indicates the corresponding data channel is used and \'0\' indicates the channel is unused."]
#[inline(always)]
pub fn data_channels_upper(
self,
) -> crate::common::RegisterField<
0,
0x1f,
1,
0,
u8,
u8,
ConnReqWord10_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1f,
1,
0,
u8,
u8,
ConnReqWord10_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnReqWord10 {
#[inline(always)]
fn default() -> ConnReqWord10 {
<crate::RegValueT<ConnReqWord10_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnReqWord11_SPEC;
impl crate::sealed::RegSpec for ConnReqWord11_SPEC {
type DataType = u32;
}
#[doc = "Connection request address word 11"]
pub type ConnReqWord11 = crate::RegValueT<ConnReqWord11_SPEC>;
impl ConnReqWord11 {
#[doc = "This field is used for the data channel selection process."]
#[inline(always)]
pub fn hop_increment_2(
self,
) -> crate::common::RegisterField<
0,
0x1f,
1,
0,
u8,
u8,
ConnReqWord11_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1f,
1,
0,
u8,
u8,
ConnReqWord11_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This field defines the sleep clock accuracies given in ppm."]
#[inline(always)]
pub fn sca_2(
self,
) -> crate::common::RegisterField<5, 0x7, 1, 0, u8, u8, ConnReqWord11_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
5,
0x7,
1,
0,
u8,
u8,
ConnReqWord11_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnReqWord11 {
#[inline(always)]
fn default() -> ConnReqWord11 {
<crate::RegValueT<ConnReqWord11_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PduRespTimer_SPEC;
impl crate::sealed::RegSpec for PduRespTimer_SPEC {
type DataType = u32;
}
#[doc = "PDU response timer/Generic Timer (MMMS mode)"]
pub type PduRespTimer = crate::RegValueT<PduRespTimer_SPEC>;
impl PduRespTimer {
#[doc = "Non MMMS mode: This register is loaded with the count value to monitor the time to get a response for a PDU from peer device.\nFirmware starts the timer by issuing the command, RESP_TIMER_ON, after it has queued a PDU for transmission, that requires a response. \nIf a response is received, firmware stops and clears the timer by issuing the command RESP_TIMER_OFF.\nIf this timer expires, it results in hardware closing the connection and triggering a conn_closed interrupt.\nThe discon_status field in the Connection status register is set with the appropriate reason.\nUnits : Milliseconds.\nResolution : 1.25 ms\n\nMMMS mode: This register is loaded with a count value, which when matched by the internal timer, triggers the GEN_TIMER_INTR. This is recommended to be used as a one shot timer and not as a periodic timer.\nFirmware starts the timer by loading the expiry time and issuing the command, RESP_TIMER_ON.\nOnce the timer expiry is triggered with the interrupt GEN_TIMER_INTR, the firmware stops the timer by issuing the command RESP_TIMER_OFF.\nResolution : 625 us"]
#[inline(always)]
pub fn pdu_resp_time_val(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
PduRespTimer_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
PduRespTimer_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PduRespTimer {
#[inline(always)]
fn default() -> PduRespTimer {
<crate::RegValueT<PduRespTimer_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct NextRespTimerExp_SPEC;
impl crate::sealed::RegSpec for NextRespTimerExp_SPEC {
type DataType = u32;
}
#[doc = "Next response timeout instant"]
pub type NextRespTimerExp = crate::RegValueT<NextRespTimerExp_SPEC>;
impl NextRespTimerExp {
#[doc = "This field defines the clock instant at which the next PDU response timeout event will occur on a connection.\nThis is with reference to the 16-bit internal reference clock."]
#[inline(always)]
pub fn next_response_instant(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
NextRespTimerExp_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
NextRespTimerExp_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for NextRespTimerExp {
#[inline(always)]
fn default() -> NextRespTimerExp {
<crate::RegValueT<NextRespTimerExp_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct NextSupTo_SPEC;
impl crate::sealed::RegSpec for NextSupTo_SPEC {
type DataType = u32;
}
#[doc = "Next supervision timeout instant"]
pub type NextSupTo = crate::RegValueT<NextSupTo_SPEC>;
impl NextSupTo {
#[doc = "This field defines the clock instant at which the next connection supervision timeout event will occur on a connection\nThis is with reference to the 16-bit internal reference clock."]
#[inline(always)]
pub fn next_timeout_instant(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, NextSupTo_SPEC, crate::common::R>
{
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
NextSupTo_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for NextSupTo {
#[inline(always)]
fn default() -> NextSupTo {
<crate::RegValueT<NextSupTo_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LlhFeatureConfig_SPEC;
impl crate::sealed::RegSpec for LlhFeatureConfig_SPEC {
type DataType = u32;
}
#[doc = "Feature enable"]
pub type LlhFeatureConfig = crate::RegValueT<LlhFeatureConfig_SPEC>;
impl LlhFeatureConfig {
#[doc = "Quick transmit feature in slave latency is enabled by setting this bit.\nWhen slave latency is enabled, this feature enables the slave to transmit in the immediate connection interval, in case required, instead of waiting till the end of slave latency"]
#[inline(always)]
pub fn quick_transmit(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, LlhFeatureConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,LlhFeatureConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable/Disable Slave Latency Period DSM."]
#[inline(always)]
pub fn sl_dsm_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, LlhFeatureConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,LlhFeatureConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable/Disable the connection US counter offset adjust. For non-MMMS mode, this bit must be tied to 1."]
#[inline(always)]
pub fn us_counter_offset_adj(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, LlhFeatureConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,LlhFeatureConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for LlhFeatureConfig {
#[inline(always)]
fn default() -> LlhFeatureConfig {
<crate::RegValueT<LlhFeatureConfig_SPEC> as RegisterValue<_>>::new(6)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WinMinStepSize_SPEC;
impl crate::sealed::RegSpec for WinMinStepSize_SPEC {
type DataType = u32;
}
#[doc = "Window minimum step size"]
pub type WinMinStepSize = crate::RegValueT<WinMinStepSize_SPEC>;
impl WinMinStepSize {
#[doc = "After receiving 2 consecutive good packets the reference window is gradually decremented by step down size until it reaches window minimum. The unit is in microseconds"]
#[inline(always)]
pub fn stepdn(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
WinMinStepSize_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
WinMinStepSize_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "If packets are missed, the reference window is gradually increased by step up size, until it receives 2 consecutive good packets. The unit is in microseconds"]
#[inline(always)]
pub fn stepup(
self,
) -> crate::common::RegisterField<
4,
0xf,
1,
0,
u8,
u8,
WinMinStepSize_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0xf,
1,
0,
u8,
u8,
WinMinStepSize_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Minimum window interval value programmed by firmware. While the slave receive window is decremented, the windows_min_fw sets the lowest value of the window widen value to ensure packets are not missed. The unit is in microseconds."]
#[inline(always)]
pub fn window_min_fw(
self,
) -> crate::common::RegisterField<
8,
0xff,
1,
0,
u8,
u8,
WinMinStepSize_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0xff,
1,
0,
u8,
u8,
WinMinStepSize_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for WinMinStepSize {
#[inline(always)]
fn default() -> WinMinStepSize {
<crate::RegValueT<WinMinStepSize_SPEC> as RegisterValue<_>>::new(8292)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SlvWinAdj_SPEC;
impl crate::sealed::RegSpec for SlvWinAdj_SPEC {
type DataType = u32;
}
#[doc = "Slave window adjustment"]
pub type SlvWinAdj = crate::RegValueT<SlvWinAdj_SPEC>;
impl SlvWinAdj {
#[doc = "Window Adjust value. This value is added to the calculated slave window widening value to be used as final window widen value."]
#[inline(always)]
pub fn slv_win_adj(
self,
) -> crate::common::RegisterField<0, 0x7ff, 1, 0, u16, u16, SlvWinAdj_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0x7ff,
1,
0,
u16,
u16,
SlvWinAdj_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for SlvWinAdj {
#[inline(always)]
fn default() -> SlvWinAdj {
<crate::RegValueT<SlvWinAdj_SPEC> as RegisterValue<_>>::new(16)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SlConnInterval_SPEC;
impl crate::sealed::RegSpec for SlConnInterval_SPEC {
type DataType = u32;
}
#[doc = "Slave Latency X Conn Interval Value"]
pub type SlConnInterval = crate::RegValueT<SlConnInterval_SPEC>;
impl SlConnInterval {
#[doc = "This field defines the (SL*CI) product for the ongoing connection. This value is used in calculation of next connection instant during slave latency."]
#[inline(always)]
pub fn sl_conn_interval_val(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
SlConnInterval_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
SlConnInterval_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for SlConnInterval {
#[inline(always)]
fn default() -> SlConnInterval {
<crate::RegValueT<SlConnInterval_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LePingTimerAddr_SPEC;
impl crate::sealed::RegSpec for LePingTimerAddr_SPEC {
type DataType = u32;
}
#[doc = "LE Ping connection timer address"]
pub type LePingTimerAddr = crate::RegValueT<LePingTimerAddr_SPEC>;
impl LePingTimerAddr {
#[doc = "The register used to configure the LE Au-thenticated payload Timeout (LE APTO) which is the Maximum amount of time specified between packets authenticated by a MIC.\nThis value of ping timer is in the order of 10ms, valid range 0x1 ~ 0xFFFF"]
#[inline(always)]
pub fn conn_ping_timer_addr(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
LePingTimerAddr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
LePingTimerAddr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for LePingTimerAddr {
#[inline(always)]
fn default() -> LePingTimerAddr {
<crate::RegValueT<LePingTimerAddr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LePingTimerOffset_SPEC;
impl crate::sealed::RegSpec for LePingTimerOffset_SPEC {
type DataType = u32;
}
#[doc = "LE Ping connection timer offset"]
pub type LePingTimerOffset = crate::RegValueT<LePingTimerOffset_SPEC>;
impl LePingTimerOffset {
#[doc = "The value of ping timer nearly expired offset in the order of 10ms, valid range 0x0 ~ 0xFFFF. This is the time period after which the ping timer nearly expired interrupt is generated."]
#[inline(always)]
pub fn conn_ping_timer_offset(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
LePingTimerOffset_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
LePingTimerOffset_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for LePingTimerOffset {
#[inline(always)]
fn default() -> LePingTimerOffset {
<crate::RegValueT<LePingTimerOffset_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LePingTimerNextExp_SPEC;
impl crate::sealed::RegSpec for LePingTimerNextExp_SPEC {
type DataType = u32;
}
#[doc = "LE Ping timer next expiry instant"]
pub type LePingTimerNextExp = crate::RegValueT<LePingTimerNextExp_SPEC>;
impl LePingTimerNextExp {
#[doc = "The value of ping timer next expiry instant in the terms of native clock value (least 16 bit value of the 17 bit ping counter).\n This together with CONN_PING_TIMER_NEXT_EXP_WRAP will provide the correct status of ping timer duration."]
#[inline(always)]
pub fn conn_ping_timer_next_exp(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
LePingTimerNextExp_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
LePingTimerNextExp_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for LePingTimerNextExp {
#[inline(always)]
fn default() -> LePingTimerNextExp {
<crate::RegValueT<LePingTimerNextExp_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LePingTimerWrapCount_SPEC;
impl crate::sealed::RegSpec for LePingTimerWrapCount_SPEC {
type DataType = u32;
}
#[doc = "LE Ping Timer wrap count"]
pub type LePingTimerWrapCount = crate::RegValueT<LePingTimerWrapCount_SPEC>;
impl LePingTimerWrapCount {
#[doc = "This register holds the current position of the Ping timer."]
#[inline(always)]
pub fn conn_sec_current_wrap(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
LePingTimerWrapCount_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
LePingTimerWrapCount_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for LePingTimerWrapCount {
#[inline(always)]
fn default() -> LePingTimerWrapCount {
<crate::RegValueT<LePingTimerWrapCount_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxEnExtDelay_SPEC;
impl crate::sealed::RegSpec for TxEnExtDelay_SPEC {
type DataType = u32;
}
#[doc = "Transmit enable extension delay"]
pub type TxEnExtDelay = crate::RegValueT<TxEnExtDelay_SPEC>;
impl TxEnExtDelay {
#[doc = "Transmit enable extension delay. This is to extend the active state (high) of rif_tx_en signal after the last bit is sent out from LLH. The unit is in microsecond and the supported range is 00 - 31 us."]
#[inline(always)]
pub fn txen_ext_delay(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, TxEnExtDelay_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,TxEnExtDelay_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "receiver enable extension delay. This is to extend the active state (high) of dbus_rx_en signal after the last bit is received from demod. The unit is in microsecond and the supported range is 00 - 31 us."]
#[inline(always)]
pub fn rxen_ext_delay(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, TxEnExtDelay_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0xf,1,0,u8,u8,TxEnExtDelay_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "2Mbps demod delay delta compare to 1Mbps demod delay. This data is 2\'s comp data."]
#[inline(always)]
pub fn demod_2m_comp_dly(
self,
) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, TxEnExtDelay_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xf,1,0,u8,u8,TxEnExtDelay_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "2Mbps modulation delay delta compare to 1Mbps demod delay. This data is 2\'s comp data."]
#[inline(always)]
pub fn mod_2m_comp_dly(
self,
) -> crate::common::RegisterField<12, 0xf, 1, 0, u8, u8, TxEnExtDelay_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
12,
0xf,
1,
0,
u8,
u8,
TxEnExtDelay_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for TxEnExtDelay {
#[inline(always)]
fn default() -> TxEnExtDelay {
<crate::RegValueT<TxEnExtDelay_SPEC> as RegisterValue<_>>::new(4933)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxRxSynthDelay_SPEC;
impl crate::sealed::RegSpec for TxRxSynthDelay_SPEC {
type DataType = u32;
}
#[doc = "Transmit/Receive enable delay"]
pub type TxRxSynthDelay = crate::RegValueT<TxRxSynthDelay_SPEC>;
impl TxRxSynthDelay {
#[doc = "The delay used to assert rif_rx_en, Rx_tRamp micro-seconds, ahead of first bit of the expected rx_data, which can be used to turn on the Radio receiver.\nThe value to be programmed to the Rx_en_delay \\[7:0\\] = rx_on_delay - Rx_tRamp\nrx_on_delay\\[7:0\\] = TX_RX_ON_DELAY\\[7:0\\])\nRx_tRamp = Radio receiver rampup time"]
#[inline(always)]
pub fn rx_en_delay(
self,
) -> crate::common::RegisterField<
0,
0xff,
1,
0,
u8,
u8,
TxRxSynthDelay_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xff,
1,
0,
u8,
u8,
TxRxSynthDelay_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "The delay used to assert rif_tx_en exactly Tx_tRamp micro-seconds ahead of the first bit of the tx_data, which can be used to turn on the Radio transmitter.\nThe value to be programmed to the Tx_en_delay \\[7:0\\] = tx_on_delay - Tx_tRamp\ntx_on_delay\\[7:0\\] = TX_RX_ON_DELAY\\[15:8\\])\nTx_tRamp = Radio transmitter ramp_up"]
#[inline(always)]
pub fn tx_en_delay(
self,
) -> crate::common::RegisterField<
8,
0xff,
1,
0,
u8,
u8,
TxRxSynthDelay_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0xff,
1,
0,
u8,
u8,
TxRxSynthDelay_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for TxRxSynthDelay {
#[inline(always)]
fn default() -> TxRxSynthDelay {
<crate::RegValueT<TxRxSynthDelay_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ExtPaLnaDlyCnfg_SPEC;
impl crate::sealed::RegSpec for ExtPaLnaDlyCnfg_SPEC {
type DataType = u32;
}
#[doc = "External TX PA and RX LNA delay configuration"]
pub type ExtPaLnaDlyCnfg = crate::RegValueT<ExtPaLnaDlyCnfg_SPEC>;
impl ExtPaLnaDlyCnfg {
#[doc = "The delay used to assert LNA_CTL, LNA_tRamp micro-seconds, ahead of first bit of the expected rx_data, which can be used to turn on the external Low Noise Amplifier.\nThe value to be programmed to the lna_ctl_delay \\[7:0\\] = rx_on_delay - LNA_tRamp\nrx_on_delay\\[7:0\\] = TX_RX_ON_DELAY\\[7:0\\])\nLNA_tRamp = External Low Noise Amplifier startup time"]
#[inline(always)]
pub fn lna_ctl_delay(
self,
) -> crate::common::RegisterField<
0,
0xff,
1,
0,
u8,
u8,
ExtPaLnaDlyCnfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xff,
1,
0,
u8,
u8,
ExtPaLnaDlyCnfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "The delay used to assert PA_CTL exactly PA_tRamp micro-seconds ahead of the first bit of the tx_data, which can be used to turn on the external power amplifier.\nThe value to be programmed to the pa_ctl_delay \\[7:0\\] = tx_on_delay - PA_tRamp\ntx_on_delay\\[7:0\\] = TX_RX_ON_DELAY\\[15:8\\])\nPA_tRamp = External Power Amplifier ramp time"]
#[inline(always)]
pub fn pa_ctl_delay(
self,
) -> crate::common::RegisterField<
8,
0xff,
1,
0,
u8,
u8,
ExtPaLnaDlyCnfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0xff,
1,
0,
u8,
u8,
ExtPaLnaDlyCnfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ExtPaLnaDlyCnfg {
#[inline(always)]
fn default() -> ExtPaLnaDlyCnfg {
<crate::RegValueT<ExtPaLnaDlyCnfg_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LlConfig_SPEC;
impl crate::sealed::RegSpec for LlConfig_SPEC {
type DataType = u32;
}
#[doc = "Link Layer additional configuration"]
pub type LlConfig = crate::RegValueT<LlConfig_SPEC>;
impl LlConfig {
#[doc = "Controls the RSSI reads. When this bit is 1, the bit RSSI_INTR_SEL is don\'t care.\n0 - RSSI read is initiated after the the packet is received\n1 - RSSI read is completed before the packet is received.\nWhen RCB Interface is operating 4Mhz are lower this bit should be set to 1\'b0."]
#[inline(always)]
pub fn rssi_sel(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, LlConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,LlConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the mode of issueing TX_EN & RX_EN to the Radio\n1 - TX_EN and RX_EN are issued through direct pins\n0 - TX_EN and RX_EN are issued through RCB writes"]
#[inline(always)]
pub fn tx_rx_ctrl_sel(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, LlConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,LlConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Setting this bit enables the tx 1MHz pulse to match the received bpktctl from CYBLERD55. This will result is reduced TIFS variation"]
#[inline(always)]
pub fn tifs_enable(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, LlConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,LlConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the wakeup timer configuration\n1 - Wakeup time is compensated with the LF_OFFSET\n0 - Wakeup time is not compensated with the LF_OFFSET as in legacy mode"]
#[inline(always)]
pub fn timer_lf_slot_enable(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, LlConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,LlConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the engine interrupt generation based on RSSI reads. This is valid only if RSSI_SEL is 0.\n0 - Receive interrupts are triggerred after the RSSI read is complete\n1 - Receive interrupts are triggerred after the last bit of CRC"]
#[inline(always)]
pub fn rssi_intr_sel(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, LlConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,LlConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the early RSSI reads. This is applicable only when RSSI_SEL is 1.\n1 - RSSI read is initiated during the first CRC byte reception.\n0 - RSSI read is initiated during the third CRC byte reception."]
#[inline(always)]
pub fn rssi_early_cnfg(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, LlConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,LlConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the delay from DBUS_TX, DBUS_RX assertion to the assertion on the pins. This is applicable only when TX_RX_CTRL_SEL is set.\n0 - The pin assertion is delayed by 4 cycles.\n1 - The pin assertion is delayed by 8 cycles."]
#[inline(always)]
pub fn tx_rx_pin_dly(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, LlConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,LlConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the TX power level format given to the CYBLERD55 chip.\n0 - The power level given to CYBLERD55 is in 4 bit code format from ADV_CH_TX_POWER for advertising channel and DTM packets & from CONN_CH_TX_POWER for connection channel packets. The power level setting is decoded and given to the PA.\n1 - The power level given to CYBLERD55 is in 18 bit power level setting format from {ADV_CH_TX_POWER_LVL_MS, ADV_CH_TX_POWER_LVL_LS} channel and DTM packets & from {CONN_CH_TX_POWER_LVL_MS, CONN_CH_TX_POWER_LVL_LS} for connection channel packets. This setting is directly given to the PA."]
#[inline(always)]
pub fn tx_pa_pwr_lvl_type(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, LlConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,LlConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the RSSI reads.\n0 - Channel Energy read is not initiated if no packet is received during a receive cycle\n1 - Channel Energy read is initiated at the end of the receive cycle if no packet is received"]
#[inline(always)]
pub fn rssi_energy_rd(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, LlConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,LlConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the RSSI reads.\n0 - RSSI read is not initiated for zero length and aborted packets\n1 - RSSI read is initiated for zero length and aborted packets"]
#[inline(always)]
pub fn rssi_each_pkt(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, LlConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,LlConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the RCB update to radio on TX/RX enable. Applicable only when TX_RX_CTRL_SEL is 1\'b1\n0 - RCB update is triggerred only when the fields change on rising edge of TX/RX enable\n1 - RCB update is force triggerred on rising edge of TX/RX enable\nIf TX_RX_CTRL_SEL is 1\'b1 and ENABLE_RADIO_BOD is 1\'b1, this bit needs to be set to 1\'b1"]
#[inline(always)]
pub fn force_trig_rcb_update(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, LlConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,LlConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the duplicate connection checkin ADV and INIT\n0 - Does not check if the peer is already connection before a new connection is created\n1 - Checks if the peer is already connection before a new connection is created and aborts a duplicate connection creation"]
#[inline(always)]
pub fn check_dup_conn(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, LlConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,LlConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the LPM entry condition\n0 - Legacy mode LPM entry check\n1 - MMMS mode LPM entry check"]
#[inline(always)]
pub fn multi_engine_lpm(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, LlConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<13,1,0,LlConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the ADV behavior while advertising ADV_DIR and only device privacy is set. When the ADV is transmitting INITA RPA, the bahavior when an Identity address in received from the Initiator in the CONN_REQ is given below\n0 - Abort the CONN_REQ and continue with advertisement\n1 - Check the address against PEER_SEC_ADDR_ADV and create connection on a match."]
#[inline(always)]
pub fn adv_dir_device_priv_en(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, LlConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<14,1,0,LlConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for LlConfig {
#[inline(always)]
fn default() -> LlConfig {
<crate::RegValueT<LlConfig_SPEC> as RegisterValue<_>>::new(19456)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LlControl_SPEC;
impl crate::sealed::RegSpec for LlControl_SPEC {
type DataType = u32;
}
#[doc = "LL Backward compatibility"]
pub type LlControl = crate::RegValueT<LlControl_SPEC>;
impl LlControl {
#[doc = "Enables Privacy 1.2 Feature."]
#[inline(always)]
pub fn priv_1_2(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, LlControl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,LlControl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables Data Length extension feature in DTM, connection and encryption modules.\nThis bit should always be set to 1\'b1. 1\'b0 is not supported."]
#[inline(always)]
pub fn dle(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, LlControl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,LlControl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The Whilelist read logic is controlled using this bit.\n0 - The reads to the whitelist address range is treated as FIFO reads and the pointers are reset by issueing the RESET_READ_PTR command.\n1 - The reads to the whitelist address range is treated an memory reads. Any whilelist entry can be read."]
#[inline(always)]
pub fn wl_read_as_mem(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, LlControl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,LlControl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the ADVCH FIFO flushing when PRIV_1_2 is enabled. \n0 - Flushes all ADV & INIT packets, as in non privacy 1.2 mode, except those with unresolved peer or self RPA.\n1 - Does not flush any CRC good packets"]
#[inline(always)]
pub fn advch_fifo_priv_1_2_flush_ctrl(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, LlControl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,LlControl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit indicates that the resolving list in the hardware is full and the list is extended in the FW. This will affect the behavior of address resolution.\n0 - The resolving list in the hardware is not fully filled. When Whitelist is disabled and a peer identity address not in the resolving list is received, the packet is responded to by the hardware.\n1 - The resolving list in the hardware is fully filled. All address comparisons must be extended to the Firmware list as well, Any match in the Firmware list should be followed by copying the matching entry into the hardware resolving list."]
#[inline(always)]
pub fn hw_rslv_list_full(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, LlControl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,LlControl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit controls the ADV engine behavior when an initiator address match occurs but a privacy mismatch occurs\n0 - The packet is aborted\n1 - The packet is received and reported to the Link Layer firmware"]
#[inline(always)]
pub fn rpt_init_addr_match_priv_mismatch_adv(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, LlControl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,LlControl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit controls the ADV engine behavior when a scanner address match occurs but a privacy mismatch occurs\n0 - The packet is aborted\n1 - The packet is received and reported to the Link Layer firmware"]
#[inline(always)]
pub fn rpt_scan_addr_match_priv_mismatch_adv(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, LlControl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,LlControl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit controls the SCAN engine behavior when an peer address match occurs but a privacy mismatch occurs\n0 - The packet is aborted\n1 - The packet is received and reported to the Link Layer firmware"]
#[inline(always)]
pub fn rpt_peer_addr_match_priv_mismatch_scn(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, LlControl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,LlControl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit controls the INIT engine behavior when an peer address match occurs but a privacy mismatch occurs\n0 - The packet is aborted\n1 - The packet is received and reported to the Link Layer firmware"]
#[inline(always)]
pub fn rpt_peer_addr_match_priv_mismatch_ini(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, LlControl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,LlControl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit controls the INIT engine behavior when a self address match occurs but a privacy mismatch occurs\n0 - The packet is aborted\n1 - The packet is received and reported to the Link Layer firmware"]
#[inline(always)]
pub fn rpt_self_addr_match_priv_mismatch_ini(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, LlControl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,LlControl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables Privacy 1.2 for ADV engine"]
#[inline(always)]
pub fn priv_1_2_adv(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, LlControl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,LlControl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables Privacy 1.2 for SCAN engine"]
#[inline(always)]
pub fn priv_1_2_scan(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, LlControl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,LlControl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables Privacy 1.2 for INIT engine"]
#[inline(always)]
pub fn priv_1_2_init(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, LlControl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,LlControl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit controls the Connection RX enable modification mode when SLV_CONN_PEER_RPA_NOT_RSLVD is set.\n1\'b0 - The Connection RX enable is unmodified\n1\'b1 - The Connection RX enable is during the Peer INIT RPA unresolved state is modified, until it is resolved."]
#[inline(always)]
pub fn en_conn_rx_en_mod(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, LlControl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<13,1,0,LlControl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is asserted when SLV_CONN_PEER_RPA_UNMCH_INTR is set. The device does not enter into Connection established state until this bit is cleared after the RPA is resoved by the firmware. If the firmware is not able to resolve the RPA within the supervision timeout, the device aborts the connection establishement and this bit is cleared by the hardware.\nThis bit is valid only if PRIV_1_2 is set."]
#[inline(always)]
pub fn slv_conn_peer_rpa_not_rslvd(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, LlControl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<14,1,0,LlControl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When set, flushes the ADVCH FIFO. The bit is auto cleared. \nNote that this should be used only when the FIFO is not read by the firmware. If firmware has started reading the FIFO, then the FIFO must be emptied exclusively by firmware reads"]
#[inline(always)]
pub fn advch_fifo_flush(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, LlControl_SPEC, crate::common::W> {
crate::common::RegisterFieldBool::<15,1,0,LlControl_SPEC,crate::common::W>::from_register(self,0)
}
}
impl ::core::default::Default for LlControl {
#[inline(always)]
fn default() -> LlControl {
<crate::RegValueT<LlControl_SPEC> as RegisterValue<_>>::new(2)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DevPaAddrL_SPEC;
impl crate::sealed::RegSpec for DevPaAddrL_SPEC {
type DataType = u32;
}
#[doc = "Device Resolvable/Non-Resolvable Private address lower register"]
pub type DevPaAddrL = crate::RegValueT<DevPaAddrL_SPEC>;
impl DevPaAddrL {
#[doc = "Lower 16 bit of 48-bit Random Private address of the device."]
#[inline(always)]
pub fn dev_pa_addr_l(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
DevPaAddrL_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
DevPaAddrL_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DevPaAddrL {
#[inline(always)]
fn default() -> DevPaAddrL {
<crate::RegValueT<DevPaAddrL_SPEC> as RegisterValue<_>>::new(13330)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DevPaAddrM_SPEC;
impl crate::sealed::RegSpec for DevPaAddrM_SPEC {
type DataType = u32;
}
#[doc = "Device Resolvable/Non-Resolvable Private address middle register"]
pub type DevPaAddrM = crate::RegValueT<DevPaAddrM_SPEC>;
impl DevPaAddrM {
#[doc = "Middle 16 bit of 48-bit Random Private address of the device."]
#[inline(always)]
pub fn dev_pa_addr_m(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
DevPaAddrM_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
DevPaAddrM_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DevPaAddrM {
#[inline(always)]
fn default() -> DevPaAddrM {
<crate::RegValueT<DevPaAddrM_SPEC> as RegisterValue<_>>::new(86)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DevPaAddrH_SPEC;
impl crate::sealed::RegSpec for DevPaAddrH_SPEC {
type DataType = u32;
}
#[doc = "Device Resolvable/Non-Resolvable Private address higher register"]
pub type DevPaAddrH = crate::RegValueT<DevPaAddrH_SPEC>;
impl DevPaAddrH {
#[doc = "Higher 16 bit of 48-bit Random Private address of the device."]
#[inline(always)]
pub fn dev_pa_addr_h(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
DevPaAddrH_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
DevPaAddrH_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DevPaAddrH {
#[inline(always)]
fn default() -> DevPaAddrH {
<crate::RegValueT<DevPaAddrH_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RslvListEnable_SPEC;
impl crate::sealed::RegSpec for RslvListEnable_SPEC {
type DataType = u32;
}
#[doc = "Resolving list entry control bit"]
pub type RslvListEnable = crate::RegValueT<RslvListEnable_SPEC>;
impl RslvListEnable {
#[doc = "Indicates if the index is valid"]
#[inline(always)]
pub fn valid_entry(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, RslvListEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,RslvListEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates if the listed peer device has shared its IRK.\n0 - Identity address in a received packet is accepted. If a valid peer device RPA is available in the list, then the RPA in a received packet is accepted.\n1 - Only the peer device RPA, if available in the list, in a received packet is accepted. An Identity address in the received packet is reported as a privacy mismatch."]
#[inline(always)]
pub fn peer_addr_irk_set(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, RslvListEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,RslvListEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates if the local IRK has been shared with the listed peer device\n0 - Self Identity address in a received packet is accepted. If a valid self RPA is available in the list, then the RPA in a received packet is accepted.\n1 - Only the self device RPA, if available in the list, in a received packet is accepted. A Self Identity address in the received packet is reported as a privacy mismatch."]
#[inline(always)]
pub fn self_addr_irk_set_rx(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, RslvListEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,RslvListEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates if the listed peer device is in the whitelist"]
#[inline(always)]
pub fn whitelisted_peer(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, RslvListEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,RslvListEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates the address type of the listed peer device"]
#[inline(always)]
pub fn peer_addr_type(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, RslvListEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,RslvListEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates that the peer device RPA in the list is valid"]
#[inline(always)]
pub fn peer_addr_rpa_val(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, RslvListEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,RslvListEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates that the received self RPA in the list is valid"]
#[inline(always)]
pub fn self_addr_rxd_rpa_val(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, RslvListEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,RslvListEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates that the self RPA in the list to be transmitted is valid"]
#[inline(always)]
pub fn self_addr_tx_rpa_val(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, RslvListEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<7,1,0,RslvListEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When Initiator whitelist is disabled, this bit indicates the specific device to from which ADV packets will be accepted."]
#[inline(always)]
pub fn self_addr_init_rpa_sel(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, RslvListEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<8,1,0,RslvListEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates the TX addr type to be used for SCANA and INITA \n0 - Self Identity address is used in SCANA/INITA in SCAN_REQ/CONN_REQ packets\n1 - Self RPA address provided in RSLV_LIST_TX_INIT_RPA field in the resolving list with the associated valid bit in SELF_ADDR_TX_RPA_VAL above is used in SCANA/INITA in SCAN_REQ/CONN_REQ packets"]
#[inline(always)]
pub fn self_addr_type_tx(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, RslvListEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<9,1,0,RslvListEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates if the entry is already in connection with our device"]
#[inline(always)]
pub fn entry_connected(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, RslvListEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<10,1,0,RslvListEnable_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RslvListEnable {
#[inline(always)]
fn default() -> RslvListEnable {
<crate::RegValueT<RslvListEnable_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WlConnectionStatus_SPEC;
impl crate::sealed::RegSpec for WlConnectionStatus_SPEC {
type DataType = u32;
}
#[doc = "whitelist valid entry bit"]
pub type WlConnectionStatus = crate::RegValueT<WlConnectionStatus_SPEC>;
impl WlConnectionStatus {
#[doc = "Stores the connection status of each of the sixteen device address stored in the whitelist.\n1 - White list entry is already in a connection\n0 - White list entry is not in a connection"]
#[inline(always)]
pub fn wl_entry_connected(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
WlConnectionStatus_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
WlConnectionStatus_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for WlConnectionStatus {
#[inline(always)]
fn default() -> WlConnectionStatus {
<crate::RegValueT<WlConnectionStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnRxmemBaseAddrDle_SPEC;
impl crate::sealed::RegSpec for ConnRxmemBaseAddrDle_SPEC {
type DataType = u32;
}
#[doc = "DLE Connection RX memory base address"]
pub type ConnRxmemBaseAddrDle = crate::RegValueT<ConnRxmemBaseAddrDle_SPEC>;
impl ConnRxmemBaseAddrDle {
#[doc = "Data from Rx memory are read as 32-bit wide data. This memory is valid only if DLE is set."]
#[inline(always)]
pub fn conn_rx_mem_base_addr_dle(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
ConnRxmemBaseAddrDle_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
ConnRxmemBaseAddrDle_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnRxmemBaseAddrDle {
#[inline(always)]
fn default() -> ConnRxmemBaseAddrDle {
<crate::RegValueT<ConnRxmemBaseAddrDle_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnTxmemBaseAddrDle_SPEC;
impl crate::sealed::RegSpec for ConnTxmemBaseAddrDle_SPEC {
type DataType = u32;
}
#[doc = "DLE Connection TX memory base address"]
pub type ConnTxmemBaseAddrDle = crate::RegValueT<ConnTxmemBaseAddrDle_SPEC>;
impl ConnTxmemBaseAddrDle {
#[doc = "Data to Tx memory are written as 32-bit wide data. This memory is valid only if DLE is set."]
#[inline(always)]
pub fn conn_tx_mem_base_addr_dle(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
ConnTxmemBaseAddrDle_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
ConnTxmemBaseAddrDle_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnTxmemBaseAddrDle {
#[inline(always)]
fn default() -> ConnTxmemBaseAddrDle {
<crate::RegValueT<ConnTxmemBaseAddrDle_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Conn1ParamMemBaseAddr_SPEC;
impl crate::sealed::RegSpec for Conn1ParamMemBaseAddr_SPEC {
type DataType = u32;
}
#[doc = "Connection Parameter memory base address for connection 1"]
pub type Conn1ParamMemBaseAddr = crate::RegValueT<Conn1ParamMemBaseAddr_SPEC>;
impl Conn1ParamMemBaseAddr {
#[doc = "N/A"]
#[inline(always)]
pub fn conn_1_param(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
Conn1ParamMemBaseAddr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
Conn1ParamMemBaseAddr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Conn1ParamMemBaseAddr {
#[inline(always)]
fn default() -> Conn1ParamMemBaseAddr {
<crate::RegValueT<Conn1ParamMemBaseAddr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Conn2ParamMemBaseAddr_SPEC;
impl crate::sealed::RegSpec for Conn2ParamMemBaseAddr_SPEC {
type DataType = u32;
}
#[doc = "Connection Parameter memory base address for connection 2"]
pub type Conn2ParamMemBaseAddr = crate::RegValueT<Conn2ParamMemBaseAddr_SPEC>;
impl Conn2ParamMemBaseAddr {
#[doc = "N/A"]
#[inline(always)]
pub fn conn_2_param(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
Conn2ParamMemBaseAddr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
Conn2ParamMemBaseAddr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Conn2ParamMemBaseAddr {
#[inline(always)]
fn default() -> Conn2ParamMemBaseAddr {
<crate::RegValueT<Conn2ParamMemBaseAddr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Conn3ParamMemBaseAddr_SPEC;
impl crate::sealed::RegSpec for Conn3ParamMemBaseAddr_SPEC {
type DataType = u32;
}
#[doc = "Connection Parameter memory base address for connection 3"]
pub type Conn3ParamMemBaseAddr = crate::RegValueT<Conn3ParamMemBaseAddr_SPEC>;
impl Conn3ParamMemBaseAddr {
#[doc = "N/A"]
#[inline(always)]
pub fn conn_3_param(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
Conn3ParamMemBaseAddr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
Conn3ParamMemBaseAddr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Conn3ParamMemBaseAddr {
#[inline(always)]
fn default() -> Conn3ParamMemBaseAddr {
<crate::RegValueT<Conn3ParamMemBaseAddr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Conn4ParamMemBaseAddr_SPEC;
impl crate::sealed::RegSpec for Conn4ParamMemBaseAddr_SPEC {
type DataType = u32;
}
#[doc = "Connection Parameter memory base address for connection 4"]
pub type Conn4ParamMemBaseAddr = crate::RegValueT<Conn4ParamMemBaseAddr_SPEC>;
impl Conn4ParamMemBaseAddr {
#[doc = "N/A"]
#[inline(always)]
pub fn conn_4_param(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
Conn4ParamMemBaseAddr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
Conn4ParamMemBaseAddr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Conn4ParamMemBaseAddr {
#[inline(always)]
fn default() -> Conn4ParamMemBaseAddr {
<crate::RegValueT<Conn4ParamMemBaseAddr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct NiTimer_SPEC;
impl crate::sealed::RegSpec for NiTimer_SPEC {
type DataType = u32;
}
#[doc = "Next Instant Timer"]
pub type NiTimer = crate::RegValueT<NiTimer_SPEC>;
impl NiTimer {
#[doc = "BT Slot at which the next connection has to be serviced, granularity is 625us. The NI timer has to be programmed 1.25ms before the connection event"]
#[inline(always)]
pub fn ni_timer(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, NiTimer_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,NiTimer_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for NiTimer {
#[inline(always)]
fn default() -> NiTimer {
<crate::RegValueT<NiTimer_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UsOffset_SPEC;
impl crate::sealed::RegSpec for UsOffset_SPEC {
type DataType = u32;
}
#[doc = "Micro-second Offset"]
pub type UsOffset = crate::RegValueT<UsOffset_SPEC>;
impl UsOffset {
#[doc = "Micro Second Offset from the Slot Bounday at which the connection programmed in NEXT_CONN has to be serviced. This register along with NI_TIMER has to be programmed 1.25ms before the connection event. The granularity is 1us"]
#[inline(always)]
pub fn us_offset_slot_boundary(
self,
) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, UsOffset_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x3ff,1,0,u16,u16,UsOffset_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for UsOffset {
#[inline(always)]
fn default() -> UsOffset {
<crate::RegValueT<UsOffset_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct NextConn_SPEC;
impl crate::sealed::RegSpec for NextConn_SPEC {
type DataType = u32;
}
#[doc = "Next Connection"]
pub type NextConn = crate::RegValueT<NextConn_SPEC>;
impl NextConn {
#[doc = "Connection Index to be serviced. Allowed values are 0,1,2,3."]
#[inline(always)]
pub fn next_conn_index(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, NextConn_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,NextConn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Connection type\n1 - Master Connection\n0 - Slave Connection"]
#[inline(always)]
pub fn next_conn_type(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, NextConn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,NextConn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Flag indication if programmed NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the connection of if NI_TIMER is pointing to past value"]
#[inline(always)]
pub fn ni_valid(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, NextConn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,NextConn_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for NextConn {
#[inline(always)]
fn default() -> NextConn {
<crate::RegValueT<NextConn_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct NiAbort_SPEC;
impl crate::sealed::RegSpec for NiAbort_SPEC {
type DataType = u32;
}
#[doc = "Abort next scheduled connection"]
pub type NiAbort = crate::RegValueT<NiAbort_SPEC>;
impl NiAbort {
#[doc = "Setting this bit clears the schedule NI"]
#[inline(always)]
pub fn ni_abort(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, NiAbort_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,NiAbort_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit will set if the scheduled NI is aborted"]
#[inline(always)]
pub fn abort_ack(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, NiAbort_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,NiAbort_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for NiAbort {
#[inline(always)]
fn default() -> NiAbort {
<crate::RegValueT<NiAbort_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnNiStatus_SPEC;
impl crate::sealed::RegSpec for ConnNiStatus_SPEC {
type DataType = u32;
}
#[doc = "Connection NI Status"]
pub type ConnNiStatus = crate::RegValueT<ConnNiStatus_SPEC>;
impl ConnNiStatus {
#[doc = "HW updates this register with the next Connection Instant for current serviced connection, granularity is 625us. The reset value is 0x0000. After reset deassertion, then the very next clock, the value assigned to the registers is 0xFFFF."]
#[inline(always)]
pub fn conn_ni(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnNiStatus_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnNiStatus_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnNiStatus {
#[inline(always)]
fn default() -> ConnNiStatus {
<crate::RegValueT<ConnNiStatus_SPEC> as RegisterValue<_>>::new(65535)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct NextSupToStatus_SPEC;
impl crate::sealed::RegSpec for NextSupToStatus_SPEC {
type DataType = u32;
}
#[doc = "Next Supervision timeout Status"]
pub type NextSupToStatus = crate::RegValueT<NextSupToStatus_SPEC>;
impl NextSupToStatus {
#[doc = "HW updates this register for the SuperVision timeout next instant, granularity is 625us"]
#[inline(always)]
pub fn next_sup_to(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
NextSupToStatus_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
NextSupToStatus_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for NextSupToStatus {
#[inline(always)]
fn default() -> NextSupToStatus {
<crate::RegValueT<NextSupToStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MmmsConnStatus_SPEC;
impl crate::sealed::RegSpec for MmmsConnStatus_SPEC {
type DataType = u32;
}
#[doc = "Connection Status"]
pub type MmmsConnStatus = crate::RegValueT<MmmsConnStatus_SPEC>;
impl MmmsConnStatus {
#[doc = "Connection Index that was serviced. Legal values are 0,1,2,3."]
#[inline(always)]
pub fn curr_conn_index(
self,
) -> crate::common::RegisterField<
0,
0x1f,
1,
0,
u8,
u8,
MmmsConnStatus_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0x1f,
1,
0,
u8,
u8,
MmmsConnStatus_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "Connection type\n1 - Master Connection\n0 - Slave Connection"]
#[inline(always)]
pub fn curr_conn_type(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, MmmsConnStatus_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<5,1,0,MmmsConnStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Sequence Number of Packets exchanged"]
#[inline(always)]
pub fn sn_curr(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, MmmsConnStatus_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<6,1,0,MmmsConnStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Next Sequence Number"]
#[inline(always)]
pub fn nesn_curr(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, MmmsConnStatus_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<7,1,0,MmmsConnStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Last Unmapped Channel"]
#[inline(always)]
pub fn last_unmapped_channel(
self,
) -> crate::common::RegisterField<
8,
0x3f,
1,
0,
u8,
u8,
MmmsConnStatus_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
8,
0x3f,
1,
0,
u8,
u8,
MmmsConnStatus_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "1 - Packet Missed\n0 - Connection exchanged packets"]
#[inline(always)]
pub fn pkt_miss(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, MmmsConnStatus_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<14,1,0,MmmsConnStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Anchor Point State\n0 - Anchor point missed\n1 - Anchor point established"]
#[inline(always)]
pub fn anchor_pt_state(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, MmmsConnStatus_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<15,1,0,MmmsConnStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for MmmsConnStatus {
#[inline(always)]
fn default() -> MmmsConnStatus {
<crate::RegValueT<MmmsConnStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct BtSlotCaptStatus_SPEC;
impl crate::sealed::RegSpec for BtSlotCaptStatus_SPEC {
type DataType = u32;
}
#[doc = "BT Slot Captured Status"]
pub type BtSlotCaptStatus = crate::RegValueT<BtSlotCaptStatus_SPEC>;
impl BtSlotCaptStatus {
#[doc = "During slave connection event, HW updates this register with the captured BT_SLOT at anchor point, granularity is 625us"]
#[inline(always)]
pub fn bt_slot(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
BtSlotCaptStatus_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
BtSlotCaptStatus_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for BtSlotCaptStatus {
#[inline(always)]
fn default() -> BtSlotCaptStatus {
<crate::RegValueT<BtSlotCaptStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UsCaptStatus_SPEC;
impl crate::sealed::RegSpec for UsCaptStatus_SPEC {
type DataType = u32;
}
#[doc = "Micro-second Capture Status"]
pub type UsCaptStatus = crate::RegValueT<UsCaptStatus_SPEC>;
impl UsCaptStatus {
#[doc = "During slave connection event, HW updates this register with the captured microsecond at anchor point, granularity is 1us"]
#[inline(always)]
pub fn us_capt(
self,
) -> crate::common::RegisterField<
0,
0x3ff,
1,
0,
u16,
u16,
UsCaptStatus_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0x3ff,
1,
0,
u16,
u16,
UsCaptStatus_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for UsCaptStatus {
#[inline(always)]
fn default() -> UsCaptStatus {
<crate::RegValueT<UsCaptStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UsOffsetStatus_SPEC;
impl crate::sealed::RegSpec for UsOffsetStatus_SPEC {
type DataType = u32;
}
#[doc = "Micro-second Offset Status"]
pub type UsOffsetStatus = crate::RegValueT<UsOffsetStatus_SPEC>;
impl UsOffsetStatus {
#[doc = "During slave connection event, HW updates this register with the calculated us_offset at anchor point, granularity is 1us. The reset value is 0x0000. After reset deassertion, then the very next clock, the value assigned to the registers is 0x00D5."]
#[inline(always)]
pub fn us_offset(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
UsOffsetStatus_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
UsOffsetStatus_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for UsOffsetStatus {
#[inline(always)]
fn default() -> UsOffsetStatus {
<crate::RegValueT<UsOffsetStatus_SPEC> as RegisterValue<_>>::new(213)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AccuWindowWidenStatus_SPEC;
impl crate::sealed::RegSpec for AccuWindowWidenStatus_SPEC {
type DataType = u32;
}
#[doc = "Accumulated Window Widen Status"]
pub type AccuWindowWidenStatus = crate::RegValueT<AccuWindowWidenStatus_SPEC>;
impl AccuWindowWidenStatus {
#[doc = "Accumulated Window Widen Value. HW updates this register at the close of slave connection event"]
#[inline(always)]
pub fn accu_window_widen(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
AccuWindowWidenStatus_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
AccuWindowWidenStatus_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for AccuWindowWidenStatus {
#[inline(always)]
fn default() -> AccuWindowWidenStatus {
<crate::RegValueT<AccuWindowWidenStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EarlyIntrStatus_SPEC;
impl crate::sealed::RegSpec for EarlyIntrStatus_SPEC {
type DataType = u32;
}
#[doc = "Status when early interrupt is raised"]
pub type EarlyIntrStatus = crate::RegValueT<EarlyIntrStatus_SPEC>;
impl EarlyIntrStatus {
#[doc = "Connection Index for which early interrupt is raised"]
#[inline(always)]
pub fn conn_index_for_early_intr(
self,
) -> crate::common::RegisterField<
0,
0x1f,
1,
0,
u8,
u8,
EarlyIntrStatus_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0x1f,
1,
0,
u8,
u8,
EarlyIntrStatus_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "Connection type for which early interrupt is raised."]
#[inline(always)]
pub fn conn_type_for_early_intr(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, EarlyIntrStatus_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<5,1,0,EarlyIntrStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "US offset when early interrupt is raised"]
#[inline(always)]
pub fn us_for_early_intr(
self,
) -> crate::common::RegisterField<
6,
0x3ff,
1,
0,
u16,
u16,
EarlyIntrStatus_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
6,
0x3ff,
1,
0,
u16,
u16,
EarlyIntrStatus_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for EarlyIntrStatus {
#[inline(always)]
fn default() -> EarlyIntrStatus {
<crate::RegValueT<EarlyIntrStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MmmsConfig_SPEC;
impl crate::sealed::RegSpec for MmmsConfig_SPEC {
type DataType = u32;
}
#[doc = "Multi-Master Multi-Slave Config"]
pub type MmmsConfig = crate::RegValueT<MmmsConfig_SPEC>;
impl MmmsConfig {
#[doc = "Configuration bit to enable MMMS functionality"]
#[inline(always)]
pub fn mmms_enable(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, MmmsConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,MmmsConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If set to 1\'b1 and MMMS enabled, then the parameters received in connection request are not stored in CONN_REQ_PARAM memory. By default this bit is 1\'b0 and the connection request parameters are stored in connection memory.\nThis bit is intended as a fail-safe. Should not be changed dynamically during runtime"]
#[inline(always)]
pub fn disable_conn_req_param_in_mem(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, MmmsConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,MmmsConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "By default on end_ce, the connection parameters memory is loaded with the updated connection parameters. Setting this bit prevent\'s this update.\nThis bit is intended as a fail-safe. Should not be changed dynamically during runtime"]
#[inline(always)]
pub fn disable_conn_param_mem_wr(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, MmmsConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,MmmsConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "By default the parameters for the connection are picked up from the connection parameters memory. Setting this bit disables this and the parameters are picked up from registers\n0 - HW loads the parameters from connection memory\n1 - Firmware should program the paramters for the connection event\nThis bit is intended as a fail-safe. Should not be changed dynamically during runtime"]
#[inline(always)]
pub fn conn_param_from_reg(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, MmmsConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,MmmsConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field specifies the connection index for which ADV is enabled"]
#[inline(always)]
pub fn adv_conn_index(
self,
) -> crate::common::RegisterField<4, 0x1f, 1, 0, u8, u8, MmmsConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0x1f,1,0,u8,u8,MmmsConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable for CE length immediate expiry"]
#[inline(always)]
pub fn ce_len_immediate_expire(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, MmmsConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,MmmsConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Setting this bit resets the receive FIFO pointers"]
#[inline(always)]
pub fn reset_rx_fifo_ptr(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, MmmsConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<10,1,0,MmmsConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for MmmsConfig {
#[inline(always)]
fn default() -> MmmsConfig {
<crate::RegValueT<MmmsConfig_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UsCounter_SPEC;
impl crate::sealed::RegSpec for UsCounter_SPEC {
type DataType = u32;
}
#[doc = "Running US of the current BT Slot"]
pub type UsCounter = crate::RegValueT<UsCounter_SPEC>;
impl UsCounter {
#[doc = "Current value of the US Counter"]
#[inline(always)]
pub fn us_counter(
self,
) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, UsCounter_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x3ff,1,0,u16,u16,UsCounter_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for UsCounter {
#[inline(always)]
fn default() -> UsCounter {
<crate::RegValueT<UsCounter_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UsCaptPrev_SPEC;
impl crate::sealed::RegSpec for UsCaptPrev_SPEC {
type DataType = u32;
}
#[doc = "Previous captured US of the BT Slot"]
pub type UsCaptPrev = crate::RegValueT<UsCaptPrev_SPEC>;
impl UsCaptPrev {
#[doc = "HW uses this register to load the us_offset from connection parameter memory. This can be used by firmware as a fail safe option if the HW load from memory is disabled. In alll other conditions firmware should not use this register."]
#[inline(always)]
pub fn us_capt_load(
self,
) -> crate::common::RegisterField<
0,
0x3ff,
1,
0,
u16,
u16,
UsCaptPrev_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3ff,
1,
0,
u16,
u16,
UsCaptPrev_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for UsCaptPrev {
#[inline(always)]
fn default() -> UsCaptPrev {
<crate::RegValueT<UsCaptPrev_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EarlyIntrNi_SPEC;
impl crate::sealed::RegSpec for EarlyIntrNi_SPEC {
type DataType = u32;
}
#[doc = "NI at early interrupt"]
pub type EarlyIntrNi = crate::RegValueT<EarlyIntrNi_SPEC>;
impl EarlyIntrNi {
#[doc = "Connection Next instant when the early interrupt is triggered"]
#[inline(always)]
pub fn early_intr_ni(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
EarlyIntrNi_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
EarlyIntrNi_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for EarlyIntrNi {
#[inline(always)]
fn default() -> EarlyIntrNi {
<crate::RegValueT<EarlyIntrNi_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MmmsMasterCreateBtCapt_SPEC;
impl crate::sealed::RegSpec for MmmsMasterCreateBtCapt_SPEC {
type DataType = u32;
}
#[doc = "BT slot capture for master connection creation"]
pub type MmmsMasterCreateBtCapt = crate::RegValueT<MmmsMasterCreateBtCapt_SPEC>;
impl MmmsMasterCreateBtCapt {
#[doc = "This register captures the BT_SLOT when master connection is created, granularity is 625us"]
#[inline(always)]
pub fn bt_slot(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
MmmsMasterCreateBtCapt_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
MmmsMasterCreateBtCapt_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for MmmsMasterCreateBtCapt {
#[inline(always)]
fn default() -> MmmsMasterCreateBtCapt {
<crate::RegValueT<MmmsMasterCreateBtCapt_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MmmsSlaveCreateBtCapt_SPEC;
impl crate::sealed::RegSpec for MmmsSlaveCreateBtCapt_SPEC {
type DataType = u32;
}
#[doc = "BT slot capture for slave connection creation"]
pub type MmmsSlaveCreateBtCapt = crate::RegValueT<MmmsSlaveCreateBtCapt_SPEC>;
impl MmmsSlaveCreateBtCapt {
#[doc = "This register captures the BT_SLOT when slave connection is created, granularity is 625us"]
#[inline(always)]
pub fn us_capt(
self,
) -> crate::common::RegisterField<
0,
0x3ff,
1,
0,
u16,
u16,
MmmsSlaveCreateBtCapt_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0x3ff,
1,
0,
u16,
u16,
MmmsSlaveCreateBtCapt_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for MmmsSlaveCreateBtCapt {
#[inline(always)]
fn default() -> MmmsSlaveCreateBtCapt {
<crate::RegValueT<MmmsSlaveCreateBtCapt_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MmmsSlaveCreateUsCapt_SPEC;
impl crate::sealed::RegSpec for MmmsSlaveCreateUsCapt_SPEC {
type DataType = u32;
}
#[doc = "Micro second capture for slave connection creation"]
pub type MmmsSlaveCreateUsCapt = crate::RegValueT<MmmsSlaveCreateUsCapt_SPEC>;
impl MmmsSlaveCreateUsCapt {
#[doc = "This register captures the us when slave connection is created, granularity is 1us"]
#[inline(always)]
pub fn us_offset_slave_created(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
MmmsSlaveCreateUsCapt_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
MmmsSlaveCreateUsCapt_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for MmmsSlaveCreateUsCapt {
#[inline(always)]
fn default() -> MmmsSlaveCreateUsCapt {
<crate::RegValueT<MmmsSlaveCreateUsCapt_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MmmsDataMemDescriptor_SPEC;
impl crate::sealed::RegSpec for MmmsDataMemDescriptor_SPEC {
type DataType = u32;
}
#[doc = "Data buffer descriptor 0 to 15"]
pub type MmmsDataMemDescriptor = crate::RegValueT<MmmsDataMemDescriptor_SPEC>;
impl MmmsDataMemDescriptor {
#[doc = "N/A"]
#[inline(always)]
pub fn llid_c1(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
u8,
u8,
MmmsDataMemDescriptor_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
u8,
u8,
MmmsDataMemDescriptor_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This field indicates the length of the data packet. Bits \\[9:7\\] are valid only if DLE is set.\nRange 0x00 to 0xFF."]
#[inline(always)]
pub fn data_length_c1(
self,
) -> crate::common::RegisterField<
2,
0xff,
1,
0,
u8,
u8,
MmmsDataMemDescriptor_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0xff,
1,
0,
u8,
u8,
MmmsDataMemDescriptor_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for MmmsDataMemDescriptor {
#[inline(always)]
fn default() -> MmmsDataMemDescriptor {
<crate::RegValueT<MmmsDataMemDescriptor_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Conn1DataListSent_SPEC;
impl crate::sealed::RegSpec for Conn1DataListSent_SPEC {
type DataType = u32;
}
#[doc = "data list sent update and status for connection 1"]
pub type Conn1DataListSent = crate::RegValueT<Conn1DataListSent_SPEC>;
impl Conn1DataListSent {
#[doc = "Write:Indicates the buffer index for which the SENT bit is being updated by firmware.\nThe default number of buffers in the IP is 5. The index range is 0-3.\n\nRead: Reads TX_SENT\\[3:0\\].\nThe bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are\n1 - queued\n0 - no packet / packet ack received by hardware \nExample1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement."]
#[inline(always)]
pub fn list_index__tx_sent_3_0_c1(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
Conn1DataListSent_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
Conn1DataListSent_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Write: Used to set the SENT bit in hardware for the selected packet buffer.\n1 - packet queued\nWhen firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted. \nThe SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device. \nFirmware typically does not clear the bit. However, It only clears the bit on its own if it needs to \'flush\' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified."]
#[inline(always)]
pub fn set_clear_c1(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Conn1DataListSent_SPEC, crate::common::W>
{
crate::common::RegisterFieldBool::<7,1,0,Conn1DataListSent_SPEC,crate::common::W>::from_register(self,0)
}
#[doc = "Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16, can be shared with up to 8 connections"]
#[inline(always)]
pub fn buffer_num_tx_sent_3_0_c1(
self,
) -> crate::common::RegisterField<
8,
0xf,
1,
0,
u8,
u8,
Conn1DataListSent_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0xf,
1,
0,
u8,
u8,
Conn1DataListSent_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Conn1DataListSent {
#[inline(always)]
fn default() -> Conn1DataListSent {
<crate::RegValueT<Conn1DataListSent_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Conn1DataListAck_SPEC;
impl crate::sealed::RegSpec for Conn1DataListAck_SPEC {
type DataType = u32;
}
#[doc = "data list ack update and status for connection 1"]
pub type Conn1DataListAck = crate::RegValueT<Conn1DataListAck_SPEC>;
impl Conn1DataListAck {
#[doc = "Write: Indicates the buffer index for which the ACK bit is being updated by firmware.\nThe default number of buffers in the IP is 5. The index range is 0-3.\n\nRead: Reads TX_ACK\\[3:0\\]\nIf a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement. \nExample1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware.\nExample2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware."]
#[inline(always)]
pub fn list_index__tx_ack_3_0_c1(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
Conn1DataListAck_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
Conn1DataListAck_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware.\nFirmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware.\nFor clearing ack for a packet transmitted in fifo-index : \'3\', firm-ware will write \'3\' in the \'list-index\' field and set this bit (BIT7) to 0. \nThis is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on.\nThe ACK bit in hardware is set by hardware when it has success-fully transmitted a packet."]
#[inline(always)]
pub fn set_clear_c1(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Conn1DataListAck_SPEC, crate::common::W>
{
crate::common::RegisterFieldBool::<7,1,0,Conn1DataListAck_SPEC,crate::common::W>::from_register(self,0)
}
}
impl ::core::default::Default for Conn1DataListAck {
#[inline(always)]
fn default() -> Conn1DataListAck {
<crate::RegValueT<Conn1DataListAck_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Conn1CeDataListCfg_SPEC;
impl crate::sealed::RegSpec for Conn1CeDataListCfg_SPEC {
type DataType = u32;
}
#[doc = "Connection specific pause resume for connection 1"]
pub type Conn1CeDataListCfg = crate::RegValueT<Conn1CeDataListCfg_SPEC>;
impl Conn1CeDataListCfg {
#[doc = "Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded.\nThe default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4.\nHardware will start the next data transmission from the index indicated by this field."]
#[inline(always)]
pub fn data_list_index_last_ack_index_c1(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
Conn1CeDataListCfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
Conn1CeDataListCfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause.\nThe bit must be set every time the firmware needs to indicate the start/resume."]
#[inline(always)]
pub fn data_list_head_up_c1(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Conn1CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,Conn1CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is set to configure the MD bit control when the design is in slave mode.\n1 - MD bit will be decided on packet pending status\n0 - MD bit will be decided on packet queued in next buffer status\nThis bit has valid only when MD_BIT_CLEAR bit is not set"]
#[inline(always)]
pub fn slv_md_config_c1(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Conn1CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,Conn1CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "MD bit set to \'1\' indicates device has more data to be sent."]
#[inline(always)]
pub fn md_c1(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, Conn1CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,Conn1CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register field indicates whether the MD (More Data) bit needs to be controlled by \'software\' or, \'hardware and software logic combined\'\n\n1 - MD bit is exclusively controlled by software, based on status of bit \\[6\\].\n\n0 - MD Bit in the transmitted PDU is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the MD in bit \\[6\\] and either of the following conditions is true,\na) If there are packets queued for transmission.\nb) If there is an acknowledgement awaited from the remote side for the packet transmitted."]
#[inline(always)]
pub fn md_bit_clear_c1(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Conn1CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<7,1,0,Conn1CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Pause data. \n1 - pause data, \n0 - do not pause.\nThe current_pdu_index in hardware does not move to next in-dex until pause_data is cleared.\nBut if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out"]
#[inline(always)]
pub fn pause_data_c1(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Conn1CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<8,1,0,Conn1CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Kills the connection immediately when the connection event is active"]
#[inline(always)]
pub fn kill_conn(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, Conn1CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<9,1,0,Conn1CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Kills the connection when the connection event is active and a TX is completed"]
#[inline(always)]
pub fn kill_conn_after_tx(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, Conn1CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<10,1,0,Conn1CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW"]
#[inline(always)]
pub fn emptypdu_sent(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, Conn1CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<11,1,0,Conn1CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The index of the transmit packet buffer that is currently in transmission/waiting for transmission."]
#[inline(always)]
pub fn current_pdu_index_c1(
self,
) -> crate::common::RegisterField<
12,
0xf,
1,
0,
u8,
u8,
Conn1CeDataListCfg_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
12,
0xf,
1,
0,
u8,
u8,
Conn1CeDataListCfg_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Conn1CeDataListCfg {
#[inline(always)]
fn default() -> Conn1CeDataListCfg {
<crate::RegValueT<Conn1CeDataListCfg_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Conn2DataListSent_SPEC;
impl crate::sealed::RegSpec for Conn2DataListSent_SPEC {
type DataType = u32;
}
#[doc = "data list sent update and status for connection 2"]
pub type Conn2DataListSent = crate::RegValueT<Conn2DataListSent_SPEC>;
impl Conn2DataListSent {
#[doc = "Write:Indicates the buffer index for which the SENT bit is being updated by firmware.\nThe default number of buffers in the IP is 5. The index range is 0-3.\n\nRead: Reads TX_SENT\\[3:0\\].\nThe bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are\n1 - queued\n0 - no packet / packet ack received by hardware \nExample1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement."]
#[inline(always)]
pub fn list_index__tx_sent_3_0_c1(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
Conn2DataListSent_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
Conn2DataListSent_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Write: Used to set the SENT bit in hardware for the selected packet buffer.\n1 - packet queued\nWhen firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted. \nThe SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device. \nFirmware typically does not clear the bit. However, It only clears the bit on its own if it needs to \'flush\' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified."]
#[inline(always)]
pub fn set_clear_c1(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Conn2DataListSent_SPEC, crate::common::W>
{
crate::common::RegisterFieldBool::<7,1,0,Conn2DataListSent_SPEC,crate::common::W>::from_register(self,0)
}
#[doc = "Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16, can be shared with up to 8 connections"]
#[inline(always)]
pub fn buffer_num_tx_sent_3_0_c1(
self,
) -> crate::common::RegisterField<
8,
0xf,
1,
0,
u8,
u8,
Conn2DataListSent_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0xf,
1,
0,
u8,
u8,
Conn2DataListSent_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Conn2DataListSent {
#[inline(always)]
fn default() -> Conn2DataListSent {
<crate::RegValueT<Conn2DataListSent_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Conn2DataListAck_SPEC;
impl crate::sealed::RegSpec for Conn2DataListAck_SPEC {
type DataType = u32;
}
#[doc = "data list ack update and status for connection 2"]
pub type Conn2DataListAck = crate::RegValueT<Conn2DataListAck_SPEC>;
impl Conn2DataListAck {
#[doc = "Write: Indicates the buffer index for which the ACK bit is being updated by firmware.\nThe default number of buffers in the IP is 5. The index range is 0-3.\n\nRead: Reads TX_ACK\\[3:0\\]\nIf a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement. \nExample1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware.\nExample2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware."]
#[inline(always)]
pub fn list_index__tx_ack_3_0_c1(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
Conn2DataListAck_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
Conn2DataListAck_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware.\nFirmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware.\nFor clearing ack for a packet transmitted in fifo-index : \'3\', firm-ware will write \'3\' in the \'list-index\' field and set this bit (BIT7) to 0. \nThis is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on.\nThe ACK bit in hardware is set by hardware when it has success-fully transmitted a packet."]
#[inline(always)]
pub fn set_clear_c1(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Conn2DataListAck_SPEC, crate::common::W>
{
crate::common::RegisterFieldBool::<7,1,0,Conn2DataListAck_SPEC,crate::common::W>::from_register(self,0)
}
}
impl ::core::default::Default for Conn2DataListAck {
#[inline(always)]
fn default() -> Conn2DataListAck {
<crate::RegValueT<Conn2DataListAck_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Conn2CeDataListCfg_SPEC;
impl crate::sealed::RegSpec for Conn2CeDataListCfg_SPEC {
type DataType = u32;
}
#[doc = "Connection specific pause resume for connection 2"]
pub type Conn2CeDataListCfg = crate::RegValueT<Conn2CeDataListCfg_SPEC>;
impl Conn2CeDataListCfg {
#[doc = "Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded.\nThe default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4.\nHardware will start the next data transmission from the index indicated by this field."]
#[inline(always)]
pub fn data_list_index_last_ack_index_c1(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
Conn2CeDataListCfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
Conn2CeDataListCfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause.\nThe bit must be set every time the firmware needs to indicate the start/resume."]
#[inline(always)]
pub fn data_list_head_up_c1(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Conn2CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,Conn2CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is set to configure the MD bit control when the design is in slave mode.\n1 - MD bit will be decided on packet pending status\n0 - MD bit will be decided on packet queued in next buffer status\nThis bit has valid only when MD_BIT_CLEAR bit is not set"]
#[inline(always)]
pub fn slv_md_config_c1(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Conn2CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,Conn2CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "MD bit set to \'1\' indicates device has more data to be sent."]
#[inline(always)]
pub fn md_c1(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, Conn2CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,Conn2CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register field indicates whether the MD (More Data) bit needs to be controlled by \'software\' or, \'hardware and software logic combined\'\n\n1 - MD bit is exclusively controlled by software, based on status of bit \\[6\\].\n\n0 - MD Bit in the transmitted PDU is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the MD in bit \\[6\\] and either of the following conditions is true,\na) If there are packets queued for transmission.\nb) If there is an acknowledgement awaited from the remote side for the packet transmitted."]
#[inline(always)]
pub fn md_bit_clear_c1(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Conn2CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<7,1,0,Conn2CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Pause data. \n1 - pause data, \n0 - do not pause.\nThe current_pdu_index in hardware does not move to next in-dex until pause_data is cleared.\nBut if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out"]
#[inline(always)]
pub fn pause_data_c1(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Conn2CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<8,1,0,Conn2CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Kills the connection immediately when the connection event is active"]
#[inline(always)]
pub fn kill_conn(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, Conn2CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<9,1,0,Conn2CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Kills the connection when the connection event is active and a TX is completed"]
#[inline(always)]
pub fn kill_conn_after_tx(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, Conn2CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<10,1,0,Conn2CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW"]
#[inline(always)]
pub fn emptypdu_sent(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, Conn2CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<11,1,0,Conn2CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The index of the transmit packet buffer that is currently in transmission/waiting for transmission."]
#[inline(always)]
pub fn current_pdu_index_c1(
self,
) -> crate::common::RegisterField<
12,
0xf,
1,
0,
u8,
u8,
Conn2CeDataListCfg_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
12,
0xf,
1,
0,
u8,
u8,
Conn2CeDataListCfg_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Conn2CeDataListCfg {
#[inline(always)]
fn default() -> Conn2CeDataListCfg {
<crate::RegValueT<Conn2CeDataListCfg_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Conn3DataListSent_SPEC;
impl crate::sealed::RegSpec for Conn3DataListSent_SPEC {
type DataType = u32;
}
#[doc = "data list sent update and status for connection 3"]
pub type Conn3DataListSent = crate::RegValueT<Conn3DataListSent_SPEC>;
impl Conn3DataListSent {
#[doc = "Write:Indicates the buffer index for which the SENT bit is being updated by firmware.\nThe default number of buffers in the IP is 5. The index range is 0-3.\n\nRead: Reads TX_SENT\\[3:0\\].\nThe bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are\n1 - queued\n0 - no packet / packet ack received by hardware \nExample1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement."]
#[inline(always)]
pub fn list_index__tx_sent_3_0_c1(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
Conn3DataListSent_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
Conn3DataListSent_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Write: Used to set the SENT bit in hardware for the selected packet buffer.\n1 - packet queued\nWhen firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted. \nThe SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device. \nFirmware typically does not clear the bit. However, It only clears the bit on its own if it needs to \'flush\' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified."]
#[inline(always)]
pub fn set_clear_c1(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Conn3DataListSent_SPEC, crate::common::W>
{
crate::common::RegisterFieldBool::<7,1,0,Conn3DataListSent_SPEC,crate::common::W>::from_register(self,0)
}
#[doc = "Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16, can be shared with up to 8 connections"]
#[inline(always)]
pub fn buffer_num_tx_sent_3_0_c1(
self,
) -> crate::common::RegisterField<
8,
0xf,
1,
0,
u8,
u8,
Conn3DataListSent_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0xf,
1,
0,
u8,
u8,
Conn3DataListSent_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Conn3DataListSent {
#[inline(always)]
fn default() -> Conn3DataListSent {
<crate::RegValueT<Conn3DataListSent_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Conn3DataListAck_SPEC;
impl crate::sealed::RegSpec for Conn3DataListAck_SPEC {
type DataType = u32;
}
#[doc = "data list ack update and status for connection 3"]
pub type Conn3DataListAck = crate::RegValueT<Conn3DataListAck_SPEC>;
impl Conn3DataListAck {
#[doc = "Write: Indicates the buffer index for which the ACK bit is being updated by firmware.\nThe default number of buffers in the IP is 5. The index range is 0-3.\n\nRead: Reads TX_ACK\\[3:0\\]\nIf a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement. \nExample1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware.\nExample2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware."]
#[inline(always)]
pub fn list_index__tx_ack_3_0_c1(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
Conn3DataListAck_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
Conn3DataListAck_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware.\nFirmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware.\nFor clearing ack for a packet transmitted in fifo-index : \'3\', firm-ware will write \'3\' in the \'list-index\' field and set this bit (BIT7) to 0. \nThis is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on.\nThe ACK bit in hardware is set by hardware when it has success-fully transmitted a packet."]
#[inline(always)]
pub fn set_clear_c1(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Conn3DataListAck_SPEC, crate::common::W>
{
crate::common::RegisterFieldBool::<7,1,0,Conn3DataListAck_SPEC,crate::common::W>::from_register(self,0)
}
}
impl ::core::default::Default for Conn3DataListAck {
#[inline(always)]
fn default() -> Conn3DataListAck {
<crate::RegValueT<Conn3DataListAck_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Conn3CeDataListCfg_SPEC;
impl crate::sealed::RegSpec for Conn3CeDataListCfg_SPEC {
type DataType = u32;
}
#[doc = "Connection specific pause resume for connection 3"]
pub type Conn3CeDataListCfg = crate::RegValueT<Conn3CeDataListCfg_SPEC>;
impl Conn3CeDataListCfg {
#[doc = "Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded.\nThe default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4.\nHardware will start the next data transmission from the index indicated by this field."]
#[inline(always)]
pub fn data_list_index_last_ack_index_c1(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
Conn3CeDataListCfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
Conn3CeDataListCfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause.\nThe bit must be set every time the firmware needs to indicate the start/resume."]
#[inline(always)]
pub fn data_list_head_up_c1(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Conn3CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,Conn3CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is set to configure the MD bit control when the design is in slave mode.\n1 - MD bit will be decided on packet pending status\n0 - MD bit will be decided on packet queued in next buffer status\nThis bit has valid only when MD_BIT_CLEAR bit is not set"]
#[inline(always)]
pub fn slv_md_config_c1(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Conn3CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,Conn3CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "MD bit set to \'1\' indicates device has more data to be sent."]
#[inline(always)]
pub fn md_c1(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, Conn3CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,Conn3CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register field indicates whether the MD (More Data) bit needs to be controlled by \'software\' or, \'hardware and software logic combined\'\n\n1 - MD bit is exclusively controlled by software, based on status of bit \\[6\\].\n\n0 - MD Bit in the transmitted PDU is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the MD in bit \\[6\\] and either of the following conditions is true,\na) If there are packets queued for transmission.\nb) If there is an acknowledgement awaited from the remote side for the packet transmitted."]
#[inline(always)]
pub fn md_bit_clear_c1(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Conn3CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<7,1,0,Conn3CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Pause data. \n1 - pause data, \n0 - do not pause.\nThe current_pdu_index in hardware does not move to next in-dex until pause_data is cleared.\nBut if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out"]
#[inline(always)]
pub fn pause_data_c1(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Conn3CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<8,1,0,Conn3CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Kills the connection immediately when the connection event is active"]
#[inline(always)]
pub fn kill_conn(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, Conn3CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<9,1,0,Conn3CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Kills the connection when the connection event is active and a TX is completed"]
#[inline(always)]
pub fn kill_conn_after_tx(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, Conn3CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<10,1,0,Conn3CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW"]
#[inline(always)]
pub fn emptypdu_sent(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, Conn3CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<11,1,0,Conn3CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The index of the transmit packet buffer that is currently in transmission/waiting for transmission."]
#[inline(always)]
pub fn current_pdu_index_c1(
self,
) -> crate::common::RegisterField<
12,
0xf,
1,
0,
u8,
u8,
Conn3CeDataListCfg_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
12,
0xf,
1,
0,
u8,
u8,
Conn3CeDataListCfg_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Conn3CeDataListCfg {
#[inline(always)]
fn default() -> Conn3CeDataListCfg {
<crate::RegValueT<Conn3CeDataListCfg_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Conn4DataListSent_SPEC;
impl crate::sealed::RegSpec for Conn4DataListSent_SPEC {
type DataType = u32;
}
#[doc = "data list sent update and status for connection 4"]
pub type Conn4DataListSent = crate::RegValueT<Conn4DataListSent_SPEC>;
impl Conn4DataListSent {
#[doc = "Write:Indicates the buffer index for which the SENT bit is being updated by firmware.\nThe default number of buffers in the IP is 5. The index range is 0-3.\n\nRead: Reads TX_SENT\\[3:0\\].\nThe bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are\n1 - queued\n0 - no packet / packet ack received by hardware \nExample1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement."]
#[inline(always)]
pub fn list_index__tx_sent_3_0_c1(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
Conn4DataListSent_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
Conn4DataListSent_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Write: Used to set the SENT bit in hardware for the selected packet buffer.\n1 - packet queued\nWhen firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted. \nThe SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device. \nFirmware typically does not clear the bit. However, It only clears the bit on its own if it needs to \'flush\' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified."]
#[inline(always)]
pub fn set_clear_c1(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Conn4DataListSent_SPEC, crate::common::W>
{
crate::common::RegisterFieldBool::<7,1,0,Conn4DataListSent_SPEC,crate::common::W>::from_register(self,0)
}
#[doc = "Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16, can be shared with up to 8 connections"]
#[inline(always)]
pub fn buffer_num_tx_sent_3_0_c1(
self,
) -> crate::common::RegisterField<
8,
0xf,
1,
0,
u8,
u8,
Conn4DataListSent_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0xf,
1,
0,
u8,
u8,
Conn4DataListSent_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Conn4DataListSent {
#[inline(always)]
fn default() -> Conn4DataListSent {
<crate::RegValueT<Conn4DataListSent_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Conn4DataListAck_SPEC;
impl crate::sealed::RegSpec for Conn4DataListAck_SPEC {
type DataType = u32;
}
#[doc = "data list ack update and status for connection 4"]
pub type Conn4DataListAck = crate::RegValueT<Conn4DataListAck_SPEC>;
impl Conn4DataListAck {
#[doc = "Write: Indicates the buffer index for which the ACK bit is being updated by firmware.\nThe default number of buffers in the IP is 5. The index range is 0-3.\n\nRead: Reads TX_ACK\\[3:0\\]\nIf a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement. \nExample1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware.\nExample2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware."]
#[inline(always)]
pub fn list_index__tx_ack_3_0_c1(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
Conn4DataListAck_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
Conn4DataListAck_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware.\nFirmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware.\nFor clearing ack for a packet transmitted in fifo-index : \'3\', firm-ware will write \'3\' in the \'list-index\' field and set this bit (BIT7) to 0. \nThis is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on.\nThe ACK bit in hardware is set by hardware when it has success-fully transmitted a packet."]
#[inline(always)]
pub fn set_clear_c1(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Conn4DataListAck_SPEC, crate::common::W>
{
crate::common::RegisterFieldBool::<7,1,0,Conn4DataListAck_SPEC,crate::common::W>::from_register(self,0)
}
}
impl ::core::default::Default for Conn4DataListAck {
#[inline(always)]
fn default() -> Conn4DataListAck {
<crate::RegValueT<Conn4DataListAck_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Conn4CeDataListCfg_SPEC;
impl crate::sealed::RegSpec for Conn4CeDataListCfg_SPEC {
type DataType = u32;
}
#[doc = "Connection specific pause resume for connection 4"]
pub type Conn4CeDataListCfg = crate::RegValueT<Conn4CeDataListCfg_SPEC>;
impl Conn4CeDataListCfg {
#[doc = "Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded.\nThe default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4.\nHardware will start the next data transmission from the index indicated by this field."]
#[inline(always)]
pub fn data_list_index_last_ack_index_c1(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
Conn4CeDataListCfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
Conn4CeDataListCfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause.\nThe bit must be set every time the firmware needs to indicate the start/resume."]
#[inline(always)]
pub fn data_list_head_up_c1(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Conn4CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,Conn4CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is set to configure the MD bit control when the design is in slave mode.\n1 - MD bit will be decided on packet pending status\n0 - MD bit will be decided on packet queued in next buffer status\nThis bit has valid only when MD_BIT_CLEAR bit is not set"]
#[inline(always)]
pub fn slv_md_config_c1(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Conn4CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,Conn4CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "MD bit set to \'1\' indicates device has more data to be sent."]
#[inline(always)]
pub fn md_c1(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, Conn4CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,Conn4CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register field indicates whether the MD (More Data) bit needs to be controlled by \'software\' or, \'hardware and software logic combined\'\n\n1 - MD bit is exclusively controlled by software, based on status of bit \\[6\\].\n\n0 - MD Bit in the transmitted PDU is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the MD in bit \\[6\\] and either of the following conditions is true,\na) If there are packets queued for transmission.\nb) If there is an acknowledgement awaited from the remote side for the packet transmitted."]
#[inline(always)]
pub fn md_bit_clear_c1(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Conn4CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<7,1,0,Conn4CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Pause data. \n1 - pause data, \n0 - do not pause.\nThe current_pdu_index in hardware does not move to next in-dex until pause_data is cleared.\nBut if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out"]
#[inline(always)]
pub fn pause_data_c1(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Conn4CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<8,1,0,Conn4CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Kills the connection immediately when the connection event is active"]
#[inline(always)]
pub fn kill_conn(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, Conn4CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<9,1,0,Conn4CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Kills the connection when the connection event is active and a TX is completed"]
#[inline(always)]
pub fn kill_conn_after_tx(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, Conn4CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<10,1,0,Conn4CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW"]
#[inline(always)]
pub fn emptypdu_sent(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, Conn4CeDataListCfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<11,1,0,Conn4CeDataListCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The index of the transmit packet buffer that is currently in transmission/waiting for transmission."]
#[inline(always)]
pub fn current_pdu_index_c1(
self,
) -> crate::common::RegisterField<
12,
0xf,
1,
0,
u8,
u8,
Conn4CeDataListCfg_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
12,
0xf,
1,
0,
u8,
u8,
Conn4CeDataListCfg_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Conn4CeDataListCfg {
#[inline(always)]
fn default() -> Conn4CeDataListCfg {
<crate::RegValueT<Conn4CeDataListCfg_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MmmsAdvchNiEnable_SPEC;
impl crate::sealed::RegSpec for MmmsAdvchNiEnable_SPEC {
type DataType = u32;
}
#[doc = "Enable bits for ADV_NI, SCAN_NI and INIT_NI"]
pub type MmmsAdvchNiEnable = crate::RegValueT<MmmsAdvchNiEnable_SPEC>;
impl MmmsAdvchNiEnable {
#[doc = "This bit is used to enable the Advertisement NI timer and is valid when MMMS_ENABLE=1.\n0 - ADV_NI timer is disabled\n1 - ADV_NI timer is enabled\n\nIn this mode, the adv engine next instant is scheduled by firmware"]
#[inline(always)]
pub fn adv_ni_enable(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, MmmsAdvchNiEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,MmmsAdvchNiEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used to enable the SCAN NI timer and is valid when MMMS_ENABLE=1.\n0 - SCAN_NI timer is disabled\n1 - SCAN_NI timer is enabled\n\nIn this mode, the scan engine next instant is scheduled by firmware"]
#[inline(always)]
pub fn scan_ni_enable(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, MmmsAdvchNiEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,MmmsAdvchNiEnable_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used to enable the INIT NI timer and is valid when MMMS_ENABLE=1.\n0 - INIT_NI timer is disabled\n1 - INIT_NI timer is enabled\n\nIn this mode, the init engine next instant is scheduled by firmware"]
#[inline(always)]
pub fn init_ni_enable(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, MmmsAdvchNiEnable_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,MmmsAdvchNiEnable_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for MmmsAdvchNiEnable {
#[inline(always)]
fn default() -> MmmsAdvchNiEnable {
<crate::RegValueT<MmmsAdvchNiEnable_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MmmsAdvchNiValid_SPEC;
impl crate::sealed::RegSpec for MmmsAdvchNiValid_SPEC {
type DataType = u32;
}
#[doc = "Next instant valid for ADV, SCAN, INIT"]
pub type MmmsAdvchNiValid = crate::RegValueT<MmmsAdvchNiValid_SPEC>;
impl MmmsAdvchNiValid {
#[doc = "This bit indicates if the programmed advertisement NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the advertisment event\n0 - ADV_NI timer is not valid \n1 - ADV_NI timer is valid"]
#[inline(always)]
pub fn adv_ni_valid(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, MmmsAdvchNiValid_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,MmmsAdvchNiValid_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit indicates if the programmed scan NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the scanner event\n0 - SCAN_NI timer is not valid \n1 - SCAN_NI timer is valid"]
#[inline(always)]
pub fn scan_ni_valid(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, MmmsAdvchNiValid_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,MmmsAdvchNiValid_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit indicates if the programmed initiator NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the initiator event\n0 - INIT_NI timer is not valid \n1 - INIT_NI timer is valid"]
#[inline(always)]
pub fn init_ni_valid(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, MmmsAdvchNiValid_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,MmmsAdvchNiValid_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for MmmsAdvchNiValid {
#[inline(always)]
fn default() -> MmmsAdvchNiValid {
<crate::RegValueT<MmmsAdvchNiValid_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MmmsAdvchNiAbort_SPEC;
impl crate::sealed::RegSpec for MmmsAdvchNiAbort_SPEC {
type DataType = u32;
}
#[doc = "Abort the next instant of ADV, SCAN, INIT"]
pub type MmmsAdvchNiAbort = crate::RegValueT<MmmsAdvchNiAbort_SPEC>;
impl MmmsAdvchNiAbort {
#[doc = "FW can use this bit to clear an unserviced NI_VALID for Advertisement or scanner or initiator. HW will clear NI_VALID for ADV/SCAN/INIT if the event has not yet started"]
#[inline(always)]
pub fn advch_ni_abort(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, MmmsAdvchNiAbort_SPEC, crate::common::W>
{
crate::common::RegisterFieldBool::<0,1,0,MmmsAdvchNiAbort_SPEC,crate::common::W>::from_register(self,0)
}
#[doc = "The link layer hardware logic will set this bit when the NI_TIMER is aborted. Firmware to clear this by writing 1\'b1 to this register bit"]
#[inline(always)]
pub fn advch_abort_status(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, MmmsAdvchNiAbort_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,MmmsAdvchNiAbort_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for MmmsAdvchNiAbort {
#[inline(always)]
fn default() -> MmmsAdvchNiAbort {
<crate::RegValueT<MmmsAdvchNiAbort_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnParamNextSupTo_SPEC;
impl crate::sealed::RegSpec for ConnParamNextSupTo_SPEC {
type DataType = u32;
}
#[doc = "Register to configure the supervision timeout for next scheduled connection"]
pub type ConnParamNextSupTo = crate::RegValueT<ConnParamNextSupTo_SPEC>;
impl ConnParamNextSupTo {
#[doc = "HW uses this register to load the Supervision timeout Next instant from the connection memory. This can be used by firmware as a failsafe option when the hardware load is disabled. In all other conditions, this register should not be updated by firmware."]
#[inline(always)]
pub fn next_sup_to_load(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
ConnParamNextSupTo_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
ConnParamNextSupTo_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnParamNextSupTo {
#[inline(always)]
fn default() -> ConnParamNextSupTo {
<crate::RegValueT<ConnParamNextSupTo_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnParamAccWinWiden_SPEC;
impl crate::sealed::RegSpec for ConnParamAccWinWiden_SPEC {
type DataType = u32;
}
#[doc = "Register to configure Accumulated window widening for next scheduled connection"]
pub type ConnParamAccWinWiden = crate::RegValueT<ConnParamAccWinWiden_SPEC>;
impl ConnParamAccWinWiden {
#[doc = "HW uses this register to load the accumulated window windeing value from the connection memory. This can be used by firmware as a failsafe option when the hardware load is disabled. In all other conditions, this register should not be updated by firmware."]
#[inline(always)]
pub fn acc_window_widen(
self,
) -> crate::common::RegisterField<
0,
0x3ff,
1,
0,
u16,
u16,
ConnParamAccWinWiden_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3ff,
1,
0,
u16,
u16,
ConnParamAccWinWiden_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnParamAccWinWiden {
#[inline(always)]
fn default() -> ConnParamAccWinWiden {
<crate::RegValueT<ConnParamAccWinWiden_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HwLoadOffset_SPEC;
impl crate::sealed::RegSpec for HwLoadOffset_SPEC {
type DataType = u32;
}
#[doc = "Register to configure offset from connection anchor point at which connection parameter memory should be read"]
pub type HwLoadOffset = crate::RegValueT<HwLoadOffset_SPEC>;
impl HwLoadOffset {
#[doc = "Load Offset in us before connection event at which the connection parameters are loaded from memory, granularity is in 1us"]
#[inline(always)]
pub fn load_offset(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, HwLoadOffset_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0x1f,
1,
0,
u8,
u8,
HwLoadOffset_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for HwLoadOffset {
#[inline(always)]
fn default() -> HwLoadOffset {
<crate::RegValueT<HwLoadOffset_SPEC> as RegisterValue<_>>::new(4)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AdvRand_SPEC;
impl crate::sealed::RegSpec for AdvRand_SPEC {
type DataType = u32;
}
#[doc = "Random number generated by Hardware for ADV NI calculation"]
pub type AdvRand = crate::RegValueT<AdvRand_SPEC>;
impl AdvRand {
#[doc = "Random ADV delay, to be used for ADV next instant calculation. The granularity is in BT slot"]
#[inline(always)]
pub fn adv_rand(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, AdvRand_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,AdvRand_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for AdvRand {
#[inline(always)]
fn default() -> AdvRand {
<crate::RegValueT<AdvRand_SPEC> as RegisterValue<_>>::new(7)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MmmsRxPktCntr_SPEC;
impl crate::sealed::RegSpec for MmmsRxPktCntr_SPEC {
type DataType = u32;
}
#[doc = "Packet Counter of packets in RX FIFO in MMMS mode"]
pub type MmmsRxPktCntr = crate::RegValueT<MmmsRxPktCntr_SPEC>;
impl MmmsRxPktCntr {
#[doc = "Count of all packets in the RX FIFO in MMMS mode"]
#[inline(always)]
pub fn mmms_rx_pkt_cnt(
self,
) -> crate::common::RegisterField<0, 0x3f, 1, 0, u8, u8, MmmsRxPktCntr_SPEC, crate::common::R>
{
crate::common::RegisterField::<
0,
0x3f,
1,
0,
u8,
u8,
MmmsRxPktCntr_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for MmmsRxPktCntr {
#[inline(always)]
fn default() -> MmmsRxPktCntr {
<crate::RegValueT<MmmsRxPktCntr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ConnRxPktCntr_SPEC;
impl crate::sealed::RegSpec for ConnRxPktCntr_SPEC {
type DataType = u32;
}
#[doc = "Packet Counter for Individual connection index"]
pub type ConnRxPktCntr = crate::RegValueT<ConnRxPktCntr_SPEC>;
impl ConnRxPktCntr {
#[doc = "Number of packets received for the connection. Incremented when the packet is received during the connection event and decremented when firmware has processed the packet. The register field FW_PKT_RCV_CONN_INDEX should be programmed before firmware issues the packet received command"]
#[inline(always)]
pub fn rx_pkt_cnt(
self,
) -> crate::common::RegisterField<0, 0x3f, 1, 0, u8, u8, ConnRxPktCntr_SPEC, crate::common::R>
{
crate::common::RegisterField::<
0,
0x3f,
1,
0,
u8,
u8,
ConnRxPktCntr_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ConnRxPktCntr {
#[inline(always)]
fn default() -> ConnRxPktCntr {
<crate::RegValueT<ConnRxPktCntr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WhitelistBaseAddr_SPEC;
impl crate::sealed::RegSpec for WhitelistBaseAddr_SPEC {
type DataType = u32;
}
#[doc = "Whitelist base address"]
pub type WhitelistBaseAddr = crate::RegValueT<WhitelistBaseAddr_SPEC>;
impl WhitelistBaseAddr {
#[doc = "Device address values written to white list memory are written as 16-bit wide address."]
#[inline(always)]
pub fn wl_base_addr(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
WhitelistBaseAddr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
WhitelistBaseAddr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for WhitelistBaseAddr {
#[inline(always)]
fn default() -> WhitelistBaseAddr {
<crate::RegValueT<WhitelistBaseAddr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RslvListPeerIdnttBaseAddr_SPEC;
impl crate::sealed::RegSpec for RslvListPeerIdnttBaseAddr_SPEC {
type DataType = u32;
}
#[doc = "Resolving list base address for storing Peer Identity address"]
pub type RslvListPeerIdnttBaseAddr = crate::RegValueT<RslvListPeerIdnttBaseAddr_SPEC>;
impl RslvListPeerIdnttBaseAddr {
#[doc = "Device address values written to the list are written as 16-bit wide address."]
#[inline(always)]
pub fn rslv_list_peer_idntt_base_addr(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
RslvListPeerIdnttBaseAddr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
RslvListPeerIdnttBaseAddr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RslvListPeerIdnttBaseAddr {
#[inline(always)]
fn default() -> RslvListPeerIdnttBaseAddr {
<crate::RegValueT<RslvListPeerIdnttBaseAddr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RslvListPeerRpaBaseAddr_SPEC;
impl crate::sealed::RegSpec for RslvListPeerRpaBaseAddr_SPEC {
type DataType = u32;
}
#[doc = "Resolving list base address for storing resolved Peer RPA address"]
pub type RslvListPeerRpaBaseAddr = crate::RegValueT<RslvListPeerRpaBaseAddr_SPEC>;
impl RslvListPeerRpaBaseAddr {
#[doc = "Device address values written to the list are written as 16-bit wide address."]
#[inline(always)]
pub fn rslv_list_peer_rpa_base_addr(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
RslvListPeerRpaBaseAddr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
RslvListPeerRpaBaseAddr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RslvListPeerRpaBaseAddr {
#[inline(always)]
fn default() -> RslvListPeerRpaBaseAddr {
<crate::RegValueT<RslvListPeerRpaBaseAddr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RslvListRcvdInitRpaBaseAddr_SPEC;
impl crate::sealed::RegSpec for RslvListRcvdInitRpaBaseAddr_SPEC {
type DataType = u32;
}
#[doc = "Resolving list base address for storing Resolved received INITA RPA"]
pub type RslvListRcvdInitRpaBaseAddr = crate::RegValueT<RslvListRcvdInitRpaBaseAddr_SPEC>;
impl RslvListRcvdInitRpaBaseAddr {
#[doc = "Device address values written to the list are written as 16-bit wide address."]
#[inline(always)]
pub fn rslv_list_rcvd_init_rpa_base_addr(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
RslvListRcvdInitRpaBaseAddr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
RslvListRcvdInitRpaBaseAddr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RslvListRcvdInitRpaBaseAddr {
#[inline(always)]
fn default() -> RslvListRcvdInitRpaBaseAddr {
<crate::RegValueT<RslvListRcvdInitRpaBaseAddr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RslvListTxInitRpaBaseAddr_SPEC;
impl crate::sealed::RegSpec for RslvListTxInitRpaBaseAddr_SPEC {
type DataType = u32;
}
#[doc = "Resolving list base address for storing generated TX INITA RPA"]
pub type RslvListTxInitRpaBaseAddr = crate::RegValueT<RslvListTxInitRpaBaseAddr_SPEC>;
impl RslvListTxInitRpaBaseAddr {
#[doc = "Device address values written to the list are written as 16-bit wide address."]
#[inline(always)]
pub fn rslv_list_tx_init_rpa_base_addr(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
RslvListTxInitRpaBaseAddr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
RslvListTxInitRpaBaseAddr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RslvListTxInitRpaBaseAddr {
#[inline(always)]
fn default() -> RslvListTxInitRpaBaseAddr {
<crate::RegValueT<RslvListTxInitRpaBaseAddr_SPEC> as RegisterValue<_>>::new(0)
}
}
}
#[doc = "Bluetooth Low Energy Subsystem Miscellaneous"]
#[non_exhaustive]
pub struct _Bless;
#[doc = "Bluetooth Low Energy Subsystem Miscellaneous"]
pub type Bless = &'static _Bless;
unsafe impl ::core::marker::Sync for _Bless {}
impl _Bless {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "BLESS DDFT configuration register"]
#[inline(always)]
pub const fn ddft_config(
&self,
) -> &'static crate::common::Reg<bless::DdftConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::DdftConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(96usize),
)
}
}
#[doc = "Crystal clock divider configuration register"]
#[inline(always)]
pub const fn xtal_clk_div_config(
&self,
) -> &'static crate::common::Reg<bless::XtalClkDivConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::XtalClkDivConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(100usize),
)
}
}
#[doc = "Link Layer interrupt status register"]
#[inline(always)]
pub const fn intr_stat(
&self,
) -> &'static crate::common::Reg<bless::IntrStat_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::IntrStat_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(104usize),
)
}
}
#[doc = "Link Layer interrupt mask register"]
#[inline(always)]
pub const fn intr_mask(
&self,
) -> &'static crate::common::Reg<bless::IntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::IntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(108usize),
)
}
}
#[doc = "Link Layer primary clock enable"]
#[inline(always)]
pub const fn ll_clk_en(
&self,
) -> &'static crate::common::Reg<bless::LlClkEn_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::LlClkEn_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(112usize),
)
}
}
#[doc = "BLESS LF clock control and BLESS revision ID indicator"]
#[inline(always)]
pub const fn lf_clk_ctrl(
&self,
) -> &'static crate::common::Reg<bless::LfClkCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::LfClkCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(116usize),
)
}
}
#[doc = "External TX PA and RX LNA control"]
#[inline(always)]
pub const fn ext_pa_lna_ctrl(
&self,
) -> &'static crate::common::Reg<bless::ExtPaLnaCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::ExtPaLnaCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(120usize),
)
}
}
#[doc = "Link Layer Last Received packet RSSI/Channel energy and channel number"]
#[inline(always)]
pub const fn ll_pkt_rssi_ch_energy(
&self,
) -> &'static crate::common::Reg<bless::LlPktRssiChEnergy_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<bless::LlPktRssiChEnergy_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(128usize),
)
}
}
#[doc = "BT clock captured on an LL DSM exit"]
#[inline(always)]
pub const fn bt_clock_capt(
&self,
) -> &'static crate::common::Reg<bless::BtClockCapt_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<bless::BtClockCapt_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(132usize),
)
}
}
#[doc = "MT Configuration Register"]
#[inline(always)]
pub const fn mt_cfg(
&self,
) -> &'static crate::common::Reg<bless::MtCfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::MtCfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(160usize),
)
}
}
#[doc = "MT Delay configuration for state transitions"]
#[inline(always)]
pub const fn mt_delay_cfg(
&self,
) -> &'static crate::common::Reg<bless::MtDelayCfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::MtDelayCfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(164usize),
)
}
}
#[doc = "MT Delay configuration for state transitions"]
#[inline(always)]
pub const fn mt_delay_cfg2(
&self,
) -> &'static crate::common::Reg<bless::MtDelayCfg2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::MtDelayCfg2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(168usize),
)
}
}
#[doc = "MT Delay configuration for state transitions"]
#[inline(always)]
pub const fn mt_delay_cfg3(
&self,
) -> &'static crate::common::Reg<bless::MtDelayCfg3_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::MtDelayCfg3_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(172usize),
)
}
}
#[doc = "MT Configuration Register to control VIO switches"]
#[inline(always)]
pub const fn mt_vio_ctrl(
&self,
) -> &'static crate::common::Reg<bless::MtVioCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::MtVioCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(176usize),
)
}
}
#[doc = "MT Status Register"]
#[inline(always)]
pub const fn mt_status(
&self,
) -> &'static crate::common::Reg<bless::MtStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<bless::MtStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(180usize),
)
}
}
#[doc = "Link Layer Power Control FSM Status Register"]
#[inline(always)]
pub const fn pwr_ctrl_sm_st(
&self,
) -> &'static crate::common::Reg<bless::PwrCtrlSmSt_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<bless::PwrCtrlSmSt_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(184usize),
)
}
}
#[doc = "HVLDO Configuration register"]
#[inline(always)]
pub const fn hvldo_ctrl(
&self,
) -> &'static crate::common::Reg<bless::HvldoCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::HvldoCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(192usize),
)
}
}
#[doc = "Radio Buck and Active regulator enable control"]
#[inline(always)]
pub const fn misc_en_ctrl(
&self,
) -> &'static crate::common::Reg<bless::MiscEnCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::MiscEnCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(196usize),
)
}
}
#[doc = "EFUSE mode configuration register"]
#[inline(always)]
pub const fn efuse_config(
&self,
) -> &'static crate::common::Reg<bless::EfuseConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::EfuseConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(208usize),
)
}
}
#[doc = "EFUSE timing control register (common for Program and Read modes)"]
#[inline(always)]
pub const fn efuse_tim_ctrl1(
&self,
) -> &'static crate::common::Reg<bless::EfuseTimCtrl1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::EfuseTimCtrl1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(212usize),
)
}
}
#[doc = "EFUSE timing control Register (for Read)"]
#[inline(always)]
pub const fn efuse_tim_ctrl2(
&self,
) -> &'static crate::common::Reg<bless::EfuseTimCtrl2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::EfuseTimCtrl2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(216usize),
)
}
}
#[doc = "EFUSE timing control Register (for Program)"]
#[inline(always)]
pub const fn efuse_tim_ctrl3(
&self,
) -> &'static crate::common::Reg<bless::EfuseTimCtrl3_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::EfuseTimCtrl3_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(220usize),
)
}
}
#[doc = "EFUSE Lower read data"]
#[inline(always)]
pub const fn efuse_rdata_l(
&self,
) -> &'static crate::common::Reg<bless::EfuseRdataL_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<bless::EfuseRdataL_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(224usize),
)
}
}
#[doc = "EFUSE higher read data"]
#[inline(always)]
pub const fn efuse_rdata_h(
&self,
) -> &'static crate::common::Reg<bless::EfuseRdataH_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<bless::EfuseRdataH_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(228usize),
)
}
}
#[doc = "EFUSE lower write word"]
#[inline(always)]
pub const fn efuse_wdata_l(
&self,
) -> &'static crate::common::Reg<bless::EfuseWdataL_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::EfuseWdataL_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(232usize),
)
}
}
#[doc = "EFUSE higher write word"]
#[inline(always)]
pub const fn efuse_wdata_h(
&self,
) -> &'static crate::common::Reg<bless::EfuseWdataH_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::EfuseWdataH_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(236usize),
)
}
}
#[doc = "Divide by 625 for FW Use"]
#[inline(always)]
pub const fn div_by_625_cfg(
&self,
) -> &'static crate::common::Reg<bless::DivBy625Cfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::DivBy625Cfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(240usize),
)
}
}
#[doc = "Output of divide by 625 divider"]
#[inline(always)]
pub const fn div_by_625_sts(
&self,
) -> &'static crate::common::Reg<bless::DivBy625Sts_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<bless::DivBy625Sts_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(244usize),
)
}
}
#[doc = "Packet counter 0"]
#[inline(always)]
pub const fn packet_counter0(
&self,
) -> &'static crate::common::Reg<bless::PacketCounter0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::PacketCounter0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(256usize),
)
}
}
#[doc = "Packet counter 2"]
#[inline(always)]
pub const fn packet_counter2(
&self,
) -> &'static crate::common::Reg<bless::PacketCounter2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::PacketCounter2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(260usize),
)
}
}
#[doc = "Master Initialization Vector 0"]
#[inline(always)]
pub const fn iv_master0(
&self,
) -> &'static crate::common::Reg<bless::IvMaster0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::IvMaster0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(264usize),
)
}
}
#[doc = "Slave Initialization Vector 0"]
#[inline(always)]
pub const fn iv_slave0(
&self,
) -> &'static crate::common::Reg<bless::IvSlave0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::IvSlave0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(268usize),
)
}
}
#[doc = "Encryption Key register 0-3"]
#[inline(always)]
pub const fn enc_key(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<bless::EncKey_SPEC, crate::common::W>,
4,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x110usize))
}
}
#[doc = "MIC input register"]
#[inline(always)]
pub const fn mic_in0(
&self,
) -> &'static crate::common::Reg<bless::MicIn0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::MicIn0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(288usize),
)
}
}
#[doc = "MIC output register"]
#[inline(always)]
pub const fn mic_out0(
&self,
) -> &'static crate::common::Reg<bless::MicOut0_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<bless::MicOut0_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(292usize),
)
}
}
#[doc = "Encryption Parameter register"]
#[inline(always)]
pub const fn enc_params(
&self,
) -> &'static crate::common::Reg<bless::EncParams_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::EncParams_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(296usize),
)
}
}
#[doc = "Encryption Configuration"]
#[inline(always)]
pub const fn enc_config(
&self,
) -> &'static crate::common::Reg<bless::EncConfig_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::EncConfig_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(300usize),
)
}
}
#[doc = "Encryption Interrupt enable"]
#[inline(always)]
pub const fn enc_intr_en(
&self,
) -> &'static crate::common::Reg<bless::EncIntrEn_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::EncIntrEn_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(304usize),
)
}
}
#[doc = "Encryption Interrupt status and clear register"]
#[inline(always)]
pub const fn enc_intr(
&self,
) -> &'static crate::common::Reg<bless::EncIntr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::EncIntr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(308usize),
)
}
}
#[doc = "Programmable B1 Data register (0-3)"]
#[inline(always)]
pub const fn b1_data_reg(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<bless::B1DataReg_SPEC, crate::common::RW>,
4,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x140usize))
}
}
#[doc = "Encryption memory base address"]
#[inline(always)]
pub const fn enc_mem_base_addr(
&self,
) -> &'static crate::common::Reg<bless::EncMemBaseAddr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::EncMemBaseAddr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(336usize),
)
}
}
#[doc = "LDO Trim register 0"]
#[inline(always)]
pub const fn trim_ldo_0(
&self,
) -> &'static crate::common::Reg<bless::TrimLdo0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::TrimLdo0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3840usize),
)
}
}
#[doc = "LDO Trim register 1"]
#[inline(always)]
pub const fn trim_ldo_1(
&self,
) -> &'static crate::common::Reg<bless::TrimLdo1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::TrimLdo1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3844usize),
)
}
}
#[doc = "LDO Trim register 2"]
#[inline(always)]
pub const fn trim_ldo_2(
&self,
) -> &'static crate::common::Reg<bless::TrimLdo2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::TrimLdo2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3848usize),
)
}
}
#[doc = "LDO Trim register 3"]
#[inline(always)]
pub const fn trim_ldo_3(
&self,
) -> &'static crate::common::Reg<bless::TrimLdo3_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::TrimLdo3_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3852usize),
)
}
}
#[doc = "MXD die Trim registers"]
#[inline(always)]
pub const fn trim_mxd(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<bless::TrimMxd_SPEC, crate::common::RW>,
4,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xf10usize))
}
}
#[doc = "LDO Trim register 4"]
#[inline(always)]
pub const fn trim_ldo_4(
&self,
) -> &'static crate::common::Reg<bless::TrimLdo4_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::TrimLdo4_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3888usize),
)
}
}
#[doc = "LDO Trim register 5"]
#[inline(always)]
pub const fn trim_ldo_5(
&self,
) -> &'static crate::common::Reg<bless::TrimLdo5_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<bless::TrimLdo5_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3892usize),
)
}
}
}
pub mod bless {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DdftConfig_SPEC;
impl crate::sealed::RegSpec for DdftConfig_SPEC {
type DataType = u32;
}
#[doc = "BLESS DDFT configuration register"]
pub type DdftConfig = crate::RegValueT<DdftConfig_SPEC>;
impl DdftConfig {
#[doc = "Enables the DDFT output from BLESS\n1: DDFT is enabled\n0: DDFT is disabled"]
#[inline(always)]
pub fn ddft_enable(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, DdftConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,DdftConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables the DDFT inputs from CYBLERD55 chip\n1: DDFT inputs are enabled\n0: DDFT inputs are disabled"]
#[inline(always)]
pub fn blerd_ddft_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, DdftConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,DdftConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "dbg_mux_pin1 selection, combine with BLERD and BLESS\n5\'h00 blerd_ddft_out\\[0\\]\n5\'h01 rcb_tx_fifo_empty\n5\'h02 hv_ldo_lv_detect_raw\n5\'h03 dbus_rx_en\n5\'h04 1\'b0\n5\'h05 clk_switch_to_sysclk\n5\'h06 ll_clk_en_sync\n5\'h07 dsm_entry_stat\n5\'h08 proc_tx_en\n5\'h09 rssi_read_start\n5\'h0A tx_2mbps\n5\'h0B rcb_bus_busy\n5\'h0C hv_ldo_en_mt (act_stdbyb)\n5\'h0D ll_eco_clk_en\n5\'h0E blerd_reset_assert\n5\'h0F hv_ldo_byp_n\n5\'h10 hv_ldo_lv_detect_mt\n5\'h11 enable_ldo\n5\'h12 enable_ldo_dly\n5\'h13 bless_rcb_le_out\n5\'h14 bless_rcb_clk_out\n5\'h15 bless_dig_ldo_on_out\n5\'h16 bless_act_ldo_en_out\n5\'h17 bless_clk_en_out\n5\'h18 bless_buck_en_out\n5\'h19 bless_ret_switch_hv_out\n5\'h1A efuse_rw_out\n5\'h1B efuse_avdd_out\n5\'h1C efuse_config_efuse_mode\n5\'h1D bless_dbus_tx_en_pad\n5\'h1E bless_bpktctl_rd\n5\'h1F 1\'b0"]
#[inline(always)]
pub fn ddft_mux_cfg1(
self,
) -> crate::common::RegisterField<8, 0x1f, 1, 0, u8, u8, DdftConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x1f,1,0,u8,u8,DdftConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "dbg_mux_pin2 selection, combine with BLERD and BLESS\n5\'h00 blerd_ddft_out\\[1\\]\n5\'h01 rcb_rx_fifo_empty\n5\'h02 ll_decode_rxdata\n5\'h03 dbus_tx_en\n5\'h04 fw_clk_en\n5\'h05 interrupt_ll_n\n5\'h06 llh_st_sm\n5\'h07 llh_st_dsm\n5\'h08 proc_rx_en\n5\'h09 rssi_rx_done\n5\'h0A rx_2mbps\n5\'h0B rcb_ll_ctrl\n5\'h0C hv_ldo_byp_n\n5\'h0D reset_deassert\n5\'h0E rcb_intr\n5\'h0F rcb_ll_intr\n5\'h10 hv_ldo_en_mt (act_stdbyb)\n5\'h11 hv_ldo_lv_detect_raw\n5\'h12 bless_rcb_data_in\n5\'h13 bless_xtal_en_out \n5\'h14 bless_isolate_n_out \n5\'h15 bless_reset_n_out\n5\'h16 bless_ret_ldo_ol_hv_out\n5\'h17 bless_txd_rxd_out\n5\'h18 tx_rx_ctrl_sel\n5\'h19 bless_bpktctl_cy\n5\'h1A efuse_cs_out\n5\'h1B efuse_pgm_out \n5\'h1C efuse_sclk_out\n5\'h1D hv_ldo_lv_detect_mt\n5\'h1E enable_ldo\n5\'h1F enable_ldo_dly"]
#[inline(always)]
pub fn ddft_mux_cfg2(
self,
) -> crate::common::RegisterField<16, 0x1f, 1, 0, u8, u8, DdftConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x1f,1,0,u8,u8,DdftConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for DdftConfig {
#[inline(always)]
fn default() -> DdftConfig {
<crate::RegValueT<DdftConfig_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct XtalClkDivConfig_SPEC;
impl crate::sealed::RegSpec for XtalClkDivConfig_SPEC {
type DataType = u32;
}
#[doc = "Crystal clock divider configuration register"]
pub type XtalClkDivConfig = crate::RegValueT<XtalClkDivConfig_SPEC>;
impl XtalClkDivConfig {
#[doc = "System clock pre-divider value. The 24 MHz crystal clock is divided to generate the system clock.\n0: NO_DIV: SYSCLK= XTALCLK/1\n1: DIV_BY_2: SYSCLK= XTALCLK/2\n2: DIV_BY_4: SYSCLK= XTALCLK/4\n3: DIV_BY_8: SYSCLK= XTALCLK/8"]
#[inline(always)]
pub fn sysclk_div(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
u8,
u8,
XtalClkDivConfig_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
u8,
u8,
XtalClkDivConfig_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Link Layer clock pre-divider value. The 24 MHz crystal clock is divided to generate the Link Layer clock.\n0: NO_DIV: LLCLK= XTALCLK/1\n1: DIV_BY_2: LLCLK= XTALCLK/2\n2: DIV_BY_4: LLCLK= XTALCLK/4\n3: DIV_BY_8: LLCLK= XTALCLK/8"]
#[inline(always)]
pub fn llclk_div(
self,
) -> crate::common::RegisterField<
2,
0x3,
1,
0,
u8,
u8,
XtalClkDivConfig_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0x3,
1,
0,
u8,
u8,
XtalClkDivConfig_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for XtalClkDivConfig {
#[inline(always)]
fn default() -> XtalClkDivConfig {
<crate::RegValueT<XtalClkDivConfig_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrStat_SPEC;
impl crate::sealed::RegSpec for IntrStat_SPEC {
type DataType = u32;
}
#[doc = "Link Layer interrupt status register"]
pub type IntrStat = crate::RegValueT<IntrStat_SPEC>;
impl IntrStat {
#[doc = "On a firmware request to LL to enter into state machine, working on LF clock, LL transitions into Deep Sleep Mode and asserts this interrupt. The interrupt can be cleared by writing one into this location."]
#[inline(always)]
pub fn dsm_entered_intr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrStat_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrStat_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "On a firmware request to LL to exit from Deep Sleep Mode, working on LF clock, LL transitions from Deep Sleep Mode and asserts this interrupt when the Deep Sleep clock gater is turned ON. The interrupt can be cleared by writing one into this location."]
#[inline(always)]
pub fn dsm_exited_intr(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrStat_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,IntrStat_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "RCB transaction Complete"]
#[inline(always)]
pub fn rcbll_done_intr(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrStat_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,IntrStat_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "CYBLERD55 is in active mode. RF is active"]
#[inline(always)]
pub fn blerd_active_intr(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrStat_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,IntrStat_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "RCB controller Interrupt - Refer to RCB_INTR_STAT register"]
#[inline(always)]
pub fn rcb_intr(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrStat_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4,1,0,IntrStat_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "LL controller interrupt - Refer to EVENT_INTR register"]
#[inline(always)]
pub fn ll_intr(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrStat_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5,1,0,IntrStat_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "GPIO interrupt"]
#[inline(always)]
pub fn gpio_intr(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrStat_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,IntrStat_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit when set by efuse controller logic when the efuse read/write is completed"]
#[inline(always)]
pub fn efuse_intr(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrStat_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,IntrStat_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "enabled crystal stable signal rising edge interrupt. The interrupt can be cleared by writing one into this location."]
#[inline(always)]
pub fn xtal_on_intr(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrStat_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,IntrStat_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Encryption Interrupt Triggered"]
#[inline(always)]
pub fn enc_intr(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrStat_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<9,1,0,IntrStat_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This interrupt is set on HVLDO LV Detector Rise edge. There is a 1cycle AHB clock glitch filter on the HVLDO LV Detector output"]
#[inline(always)]
pub fn hvldo_lv_detect_pos(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrStat_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,IntrStat_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This interrupt is set on HVLDO LV Detector Fall edge. There is a 1cycle AHB clock glitch filter on the HVLDO LV Detector output"]
#[inline(always)]
pub fn hvldo_lv_detect_neg(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, IntrStat_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,IntrStat_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrStat {
#[inline(always)]
fn default() -> IntrStat {
<crate::RegValueT<IntrStat_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMask_SPEC;
impl crate::sealed::RegSpec for IntrMask_SPEC {
type DataType = u32;
}
#[doc = "Link Layer interrupt mask register"]
pub type IntrMask = crate::RegValueT<IntrMask_SPEC>;
impl IntrMask {
#[doc = "When the Link Layer is in Deep Sleep Mode, firmware can set this bit to wake the Link Layer."]
#[inline(always)]
pub fn dsm_exit(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Masks the DSM Entered Interrupt, when disabled."]
#[inline(always)]
pub fn dsm_entered_intr_mask(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Masks the DSM Exited Interrupt, when disabled."]
#[inline(always)]
pub fn dsm_exited_intr_mask(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Masks the Crystal Stable Interrupt, when disabled."]
#[inline(always)]
pub fn xtal_on_intr_mask(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask for RCBLL interrupt"]
#[inline(always)]
pub fn rcbll_intr_mask(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask for CYBLERD55 Active Interrupt"]
#[inline(always)]
pub fn blerd_active_intr_mask(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask for RCB interrupt"]
#[inline(always)]
pub fn rcb_intr_mask(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask for LL interrupt"]
#[inline(always)]
pub fn ll_intr_mask(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask for GPIO interrupt"]
#[inline(always)]
pub fn gpio_intr_mask(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit enables the efuse interrupt to firmware"]
#[inline(always)]
pub fn efuse_intr_mask(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask for Encryption interrupt"]
#[inline(always)]
pub fn enc_intr_mask(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask for HVLDO LV Detector Rise edge interrupt"]
#[inline(always)]
pub fn hvldo_lv_detect_pos_mask(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask for HVLDO LV Detector Fall edge interrupt"]
#[inline(always)]
pub fn hvldo_lv_detect_neg_mask(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMask {
#[inline(always)]
fn default() -> IntrMask {
<crate::RegValueT<IntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LlClkEn_SPEC;
impl crate::sealed::RegSpec for LlClkEn_SPEC {
type DataType = u32;
}
#[doc = "Link Layer primary clock enable"]
pub type LlClkEn = crate::RegValueT<LlClkEn_SPEC>;
impl LlClkEn {
#[doc = "Set this bit 1 to enable the clock to Link Layer."]
#[inline(always)]
pub fn clk_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, LlClkEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,LlClkEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "If MXD_IF option is 1, this bit needs to be set to enable configuring the correlator through BLELL.DPLL_CONFIG register"]
#[inline(always)]
pub fn cy_correl_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, LlClkEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,LlClkEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "1: MXD IF option 0: CYBLERD55 correlates Access Code\n0: MXD IF option 1: LL correlates Access Code"]
#[inline(always)]
pub fn mxd_if_option(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, LlClkEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,LlClkEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "0: AHB clock (clk_sys) is used as the clock for RCB access\n1: LL clock (clk_eco) is used as the clock for RCB access"]
#[inline(always)]
pub fn sel_rcb_clk(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, LlClkEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,LlClkEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "0: No Soft Reset\n1: Initiate Soft Reset\nSetting this bit will reset entire BLESS_VER3"]
#[inline(always)]
pub fn bless_reset(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, LlClkEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,LlClkEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the DPSLP entry and exit writes to RD and controls the active domain reset and clock.\n1 - LL HW controls the RD active domain reset and clock.\n0 - The RD active domain reset and clock. Must be controlled by the FW"]
#[inline(always)]
pub fn dpslp_hwrcb_en(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, LlClkEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,LlClkEn_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for LlClkEn {
#[inline(always)]
fn default() -> LlClkEn {
<crate::RegValueT<LlClkEn_SPEC> as RegisterValue<_>>::new(38)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LfClkCtrl_SPEC;
impl crate::sealed::RegSpec for LfClkCtrl_SPEC {
type DataType = u32;
}
#[doc = "BLESS LF clock control and BLESS revision ID indicator"]
pub type LfClkCtrl = crate::RegValueT<LfClkCtrl_SPEC>;
impl LfClkCtrl {
#[doc = "When set to 1, gates the LF clock input to the Link Layer. Ths is done for extended DSM mode where the DSM state machine needs to be forzen to prevent a default auto exit."]
#[inline(always)]
pub fn disable_lf_clk(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, LfClkCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,LfClkCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit is used to enable the clock to the encryption engine\n0 - Disable the clock to ENC engine\n1 - Enable the clock to ENC engine"]
#[inline(always)]
pub fn enable_enc_clk(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, LfClkCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,LfClkCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Indicates the m0s8bless IP revision."]
#[inline(always)]
pub fn m0s8bless_rev_id(
self,
) -> crate::common::RegisterField<29, 0x7, 1, 0, u8, u8, LfClkCtrl_SPEC, crate::common::R>
{
crate::common::RegisterField::<29,0x7,1,0,u8,u8,LfClkCtrl_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for LfClkCtrl {
#[inline(always)]
fn default() -> LfClkCtrl {
<crate::RegValueT<LfClkCtrl_SPEC> as RegisterValue<_>>::new(1073741824)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ExtPaLnaCtrl_SPEC;
impl crate::sealed::RegSpec for ExtPaLnaCtrl_SPEC {
type DataType = u32;
}
#[doc = "External TX PA and RX LNA control"]
pub type ExtPaLnaCtrl = crate::RegValueT<ExtPaLnaCtrl_SPEC>;
impl ExtPaLnaCtrl {
#[doc = "When set to 1, enables the external PA & LNA"]
#[inline(always)]
pub fn enable_ext_pa_lna(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ExtPaLnaCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,ExtPaLnaCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the polarity of the chip enable control signal\n0 - High enable, low disable\n1 - Low enable, High disable"]
#[inline(always)]
pub fn chip_en_pol(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ExtPaLnaCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,ExtPaLnaCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the polarity of the PA control signal\n0 - High enable, low disable\n1 - Low enable, High disable"]
#[inline(always)]
pub fn pa_ctrl_pol(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, ExtPaLnaCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,ExtPaLnaCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the polarity of the LNA control signal\n0 - High enable, low disable\n1 - Low enable, High disable"]
#[inline(always)]
pub fn lna_ctrl_pol(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, ExtPaLnaCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,ExtPaLnaCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Configures the drive value on the output enables of PA, LNA and CHI_EN signals\n0 - drive 0 on the output enable signals\n1 - drive 1 on the output enable signals"]
#[inline(always)]
pub fn out_en_drive_val(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, ExtPaLnaCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,ExtPaLnaCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ExtPaLnaCtrl {
#[inline(always)]
fn default() -> ExtPaLnaCtrl {
<crate::RegValueT<ExtPaLnaCtrl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct LlPktRssiChEnergy_SPEC;
impl crate::sealed::RegSpec for LlPktRssiChEnergy_SPEC {
type DataType = u32;
}
#[doc = "Link Layer Last Received packet RSSI/Channel energy and channel number"]
pub type LlPktRssiChEnergy = crate::RegValueT<LlPktRssiChEnergy_SPEC>;
impl LlPktRssiChEnergy {
#[doc = "This field captures the RSSI of the packet when a packet reception is complete or gives the Channel energy when a Receive cycle is over without packet reception."]
#[inline(always)]
pub fn rssi(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
LlPktRssiChEnergy_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
LlPktRssiChEnergy_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "This field indicates the last channel for which the RSSI is captured"]
#[inline(always)]
pub fn rx_channel(
self,
) -> crate::common::RegisterField<
16,
0x3f,
1,
0,
u8,
u8,
LlPktRssiChEnergy_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
16,
0x3f,
1,
0,
u8,
u8,
LlPktRssiChEnergy_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "This field indicates if the captured RSSI is for a received packet or is the channel energy"]
#[inline(always)]
pub fn pkt_rssi_or_ch_energy(
self,
) -> crate::common::RegisterFieldBool<22, 1, 0, LlPktRssiChEnergy_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<22,1,0,LlPktRssiChEnergy_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for LlPktRssiChEnergy {
#[inline(always)]
fn default() -> LlPktRssiChEnergy {
<crate::RegValueT<LlPktRssiChEnergy_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct BtClockCapt_SPEC;
impl crate::sealed::RegSpec for BtClockCapt_SPEC {
type DataType = u32;
}
#[doc = "BT clock captured on an LL DSM exit"]
pub type BtClockCapt = crate::RegValueT<BtClockCapt_SPEC>;
impl BtClockCapt {
#[doc = "This field captures the LF BT clock captured on an LL DSM exit. This register is valid only when MT_STATUS.LL_CLK_STATE is set. This value may be used to manage the low power entry."]
#[inline(always)]
pub fn bt_clock(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
BtClockCapt_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
BtClockCapt_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for BtClockCapt {
#[inline(always)]
fn default() -> BtClockCapt {
<crate::RegValueT<BtClockCapt_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MtCfg_SPEC;
impl crate::sealed::RegSpec for MtCfg_SPEC {
type DataType = u32;
}
#[doc = "MT Configuration Register"]
pub type MtCfg = crate::RegValueT<MtCfg_SPEC>;
impl MtCfg {
#[doc = "This register bit needs to be set to enable CYBLERD55\n1\'b1 - CYBLERD55 enabled\n1\'b0 - CYBLERD55 disabled\nOn power up this bit needs to be set to make CYBLERD55 active."]
#[inline(always)]
pub fn enable_blerd(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register bit indicates the source for PSoC DeepSleep exit to BLESS\n1\'b0 - act_power_good from SRSS indicates PSoC DeepSleep exit\n1\'b1 - MT_CFG.DEEPSLEEP_EXITED indicates PSoC DeepSleep exit"]
#[inline(always)]
pub fn deepsleep_exit_cfg(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register bit is used by FW to indicate that PSoC is out of DeepSleep\n1\'b0 - PSoC in DeepSleep\n1\'b1 - PSoC out of DeepSleep\nThis bit is cleared by HW on exit from DPSLP"]
#[inline(always)]
pub fn deepsleep_exited(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register bit specifies whether the Active LDO or BUCK in CYBLERD55 is used in active mode"]
#[inline(always)]
pub fn act_ldo_not_buck(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register should be set to override the HW generated signal to HVLDO. When set HVLDO_BYPASS is driven to the IP"]
#[inline(always)]
pub fn override_hvldo_bypass(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Override value for HVLDO BYPASS\n1\'b0: bypass the HVLDO\n1\'b1: Do not bypass the HVLDO"]
#[inline(always)]
pub fn hvldo_bypass(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register should be set to override the HW generated signal to enable ACTIVE_LDO/BUCK. When set ACT_REGULATOR_EN is driven to CYBLERD55"]
#[inline(always)]
pub fn override_act_regulator(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Override value for ACT_LDO_EN/BUCK_EN"]
#[inline(always)]
pub fn act_regulator_en(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register should be set to override the HW generated signal to Digital regulator of CYBLERD55. When set DIG_REGULATOR_EN is driven to CYBLERD55"]
#[inline(always)]
pub fn override_dig_regulator(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Override value for digital regulator of CYBLERD55"]
#[inline(always)]
pub fn dig_regulator_en(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register should be set to override the HW generated signal to the retention switch of CYBLERD55. When set OVERRIDE_RET_SWITCH is driven to the IP"]
#[inline(always)]
pub fn override_ret_switch(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Override value for RET_SWITCH"]
#[inline(always)]
pub fn ret_switch(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register should be set to override the HW generated isolation signal to CYBLERD55. When set ISOLATE_N is driven to the IP"]
#[inline(always)]
pub fn override_isolate(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Override value for isolation to CYBLERD55"]
#[inline(always)]
pub fn isolate_n(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<13,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register should be set to override the HW generated ECO Clock gate. When set LL_CLK_EN is used to gate the clock"]
#[inline(always)]
pub fn override_ll_clk_en(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<14,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Override value for LL Clock gate"]
#[inline(always)]
pub fn ll_clk_en(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<15,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register should be set to override the HW generated enable to HVLSO. When set HVLDO_EN is used."]
#[inline(always)]
pub fn override_hvldo_en(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Overrie value for HVLDO enable\n1\'b1: switch to Active LDO\n1\'b0: switch to standby LDO"]
#[inline(always)]
pub fn hvldo_en(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit when set indicates that ECO clock should be kept on even in BLESS DPSLP. This bit must be toggled only when the Link Layer is active."]
#[inline(always)]
pub fn dpslp_eco_on(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register should be set to override the HW generated reset to CYBLERD55. When set RESET_N is used."]
#[inline(always)]
pub fn override_reset_n(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Overrie value for CYBLERD55 RESET_N"]
#[inline(always)]
pub fn reset_n(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<20,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register should be set to override the HW generated XTAL_EN to CYBLERD55. When set XTAL_EN is used."]
#[inline(always)]
pub fn override_xtal_en(
self,
) -> crate::common::RegisterFieldBool<21, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<21,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Overrie value for CYBLERD55 XTAL_EN"]
#[inline(always)]
pub fn xtal_en(
self,
) -> crate::common::RegisterFieldBool<22, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<22,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register should be set to override the HW generated CLK_EN to CYBLERD55. When set CLK_EN is used."]
#[inline(always)]
pub fn override_clk_en(
self,
) -> crate::common::RegisterFieldBool<23, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<23,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Overrie value for CYBLERD55 CLK_EN"]
#[inline(always)]
pub fn blerd_clk_en(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register should be set to override the HW generated RET_LDO_OL_HV to CYBLERD55. When set CLK_EN is used."]
#[inline(always)]
pub fn override_ret_ldo_ol(
self,
) -> crate::common::RegisterFieldBool<25, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<25,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Overrie value for CYBLERD55 RET_LDO_OL_HV"]
#[inline(always)]
pub fn ret_ldo_ol(
self,
) -> crate::common::RegisterFieldBool<26, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<26,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Reset for HVLDO\n1\'b1 - HVLDO Disabled\n1\'b0 - HVLDO Enabled"]
#[inline(always)]
pub fn hvldo_por_hv(
self,
) -> crate::common::RegisterFieldBool<27, 1, 0, MtCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<27,1,0,MtCfg_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for MtCfg {
#[inline(always)]
fn default() -> MtCfg {
<crate::RegValueT<MtCfg_SPEC> as RegisterValue<_>>::new(135266304)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MtDelayCfg_SPEC;
impl crate::sealed::RegSpec for MtDelayCfg_SPEC {
type DataType = u32;
}
#[doc = "MT Delay configuration for state transitions"]
pub type MtDelayCfg = crate::RegValueT<MtDelayCfg_SPEC>;
impl MtDelayCfg {
#[doc = "This register specifies the startup delay for the HVLDO interms of number of LF Clock cycles. FW has to program this register based on the selected LF clock frequency"]
#[inline(always)]
pub fn hvldo_startup_delay(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, MtDelayCfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,MtDelayCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register specifies the time from switching the CYBLERD55 logic to Active regulator to removal of ISOLATE_N"]
#[inline(always)]
pub fn isolate_deassert_delay(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, MtDelayCfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,MtDelayCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register specifies the time from assertion of ISOLATE_N to switching the CYBLERD55 logic to Retention LDO"]
#[inline(always)]
pub fn act_to_switch_delay(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, MtDelayCfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,MtDelayCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register specifies the time from disabling XTAL to switching of the HVLDO."]
#[inline(always)]
pub fn hvldo_disable_delay(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, MtDelayCfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,MtDelayCfg_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for MtDelayCfg {
#[inline(always)]
fn default() -> MtDelayCfg {
<crate::RegValueT<MtDelayCfg_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MtDelayCfg2_SPEC;
impl crate::sealed::RegSpec for MtDelayCfg2_SPEC {
type DataType = u32;
}
#[doc = "MT Delay configuration for state transitions"]
pub type MtDelayCfg2 = crate::RegValueT<MtDelayCfg2_SPEC>;
impl MtDelayCfg2 {
#[doc = "This register specifies the time for OSC Startup. After this delay, clock is enabled to the link layer. Clock is enabled after OSC_STARTUP_DELAY + 1 LF clock cycles. If PSoC was in DPSLP when XTAL is enabled, then the wakeup delay will be OSC_STARTUP_DELAY + 1 + PSoC Wakeup time. Minimum value to be programmed in 1. This is equivalent to Link Layer register WAKEUP_CONFIG.OSC_STARTUP_DELAY, but is specified in LF cycles"]
#[inline(always)]
pub fn osc_startup_delay_lf(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, MtDelayCfg2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,MtDelayCfg2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register specifies the pre-processing time required in Link Layer. This is esentially the time from CLK_EN (ungating clock in CYBLERD55) to the time when logic in CYBLERD55 is switched to Active mode Regulator.The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. This is equivalent to Link Layer register WAKEUP_CONFIG.DSM_OFFSET_TO_WAKEUP_INSTANT_LF, but is specified in LF cycles."]
#[inline(always)]
pub fn dsm_offset_to_wakeup_instant_lf(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, MtDelayCfg2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,MtDelayCfg2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This register specifes the Active Regulator startup time in CYBLERD55. The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. The digital LDO will be turned on after this time elapses"]
#[inline(always)]
pub fn act_startup_delay(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, MtDelayCfg2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
16,
0xff,
1,
0,
u8,
u8,
MtDelayCfg2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This register specifes the Digital LDO startup time in CYBLERD55.The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. The logic in CYBLERD55 is switched to Active mode Regulator after this (ACT_STARTUP_DELAY + DIG_LDO_STARTUP_DELAY)"]
#[inline(always)]
pub fn dig_ldo_startup_delay(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, MtDelayCfg2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
24,
0xff,
1,
0,
u8,
u8,
MtDelayCfg2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for MtDelayCfg2 {
#[inline(always)]
fn default() -> MtDelayCfg2 {
<crate::RegValueT<MtDelayCfg2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MtDelayCfg3_SPEC;
impl crate::sealed::RegSpec for MtDelayCfg3_SPEC {
type DataType = u32;
}
#[doc = "MT Delay configuration for state transitions"]
pub type MtDelayCfg3 = crate::RegValueT<MtDelayCfg3_SPEC>;
impl MtDelayCfg3 {
#[doc = "This register specifies the time from switching of logic to Retention LDO in CYBLERD55 to XTAL Disable. This should include the post processing time\nThe delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency.\nAt the minimum XTAL_DISABLE_DELAY should be the sum of DIG_LDO_DISABLE_DELAY and the powerdown time of ACTIVE_LDO"]
#[inline(always)]
pub fn xtal_disable_delay(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, MtDelayCfg3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,MtDelayCfg3_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field holds the delay from the time of diabling Digital LDO to the time at which ACTIVE regulator is disabled"]
#[inline(always)]
pub fn dig_ldo_disable_delay(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, MtDelayCfg3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,MtDelayCfg3_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field holds the delay after HVLDO Startup to VDDR Stable. Refer to memo AKK-410"]
#[inline(always)]
pub fn vddr_stable_delay(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, MtDelayCfg3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
16,
0xff,
1,
0,
u8,
u8,
MtDelayCfg3_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for MtDelayCfg3 {
#[inline(always)]
fn default() -> MtDelayCfg3 {
<crate::RegValueT<MtDelayCfg3_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MtVioCtrl_SPEC;
impl crate::sealed::RegSpec for MtVioCtrl_SPEC {
type DataType = u32;
}
#[doc = "MT Configuration Register to control VIO switches"]
pub type MtVioCtrl = crate::RegValueT<MtVioCtrl_SPEC>;
impl MtVioCtrl {
#[doc = "Enable to turn on HVLDO (One leg)\n1\'b0 - Switch is turned off\n1\'b1 - Switch is turned on"]
#[inline(always)]
pub fn srss_switch_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, MtVioCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,MtVioCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable to turn on HVLDO (All legs). This must be enabled 64us after enabling SRSS_SWITCH_EN\n1\'b0 - Switch is turned off\n1\'b1 - Switch is turned on"]
#[inline(always)]
pub fn srss_switch_en_dly(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, MtVioCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,MtVioCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for MtVioCtrl {
#[inline(always)]
fn default() -> MtVioCtrl {
<crate::RegValueT<MtVioCtrl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MtStatus_SPEC;
impl crate::sealed::RegSpec for MtStatus_SPEC {
type DataType = u32;
}
#[doc = "MT Status Register"]
pub type MtStatus = crate::RegValueT<MtStatus_SPEC>;
impl MtStatus {
#[doc = "1\'b0 - BLESS in DPSLP state\n1\'b1 - BLESS in ACTIVE state"]
#[inline(always)]
pub fn bless_state(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, MtStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,MtStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This register reflects the current state of the MT FSM\n4\'h0 - IDLE\n4\'h1 - BLERD_DEEPSLEEP\n4\'h2 - HVLDO_STARTUP\n4\'h3 - WAIT_CLK\n4\'h4 - BLERD_IDLE\n4\'h5 - SWITCH_EN\n4\'h6 - ACTIVE\n4\'h7 - ISOLATE\n4\'h8 - WAIT_IDLE\n4\'h9 - XTAL_DISABLE\n4\'hA - HVLDO_DISABLE"]
#[inline(always)]
pub fn mt_curr_state(
self,
) -> crate::common::RegisterField<1, 0xf, 1, 0, u8, u8, MtStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<1,0xf,1,0,u8,u8,MtStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This register reflects the current state of the HVLDO Startup FSM\n3\'h0 - HVLDO_OFF\n3\'h1 - HVLDO_WAIT\n3\'h2 - HVLDO_SAMPLE\n3\'h3 - HVLDO_ENABLED\n3\'h4 - HVLDO_SET_BYPASS"]
#[inline(always)]
pub fn hvldo_startup_curr_state(
self,
) -> crate::common::RegisterField<5, 0x7, 1, 0, u8, u8, MtStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<5,0x7,1,0,u8,u8,MtStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit indicates when the Link Layer registers are accessible upon a DSM exit. This bit should not be used after a DSM entry command has been issued. \n1\'b0 - Link Layer clock is not available\n1\'b1 - Link Layer clock is active"]
#[inline(always)]
pub fn ll_clk_state(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, MtStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8,1,0,MtStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for MtStatus {
#[inline(always)]
fn default() -> MtStatus {
<crate::RegValueT<MtStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PwrCtrlSmSt_SPEC;
impl crate::sealed::RegSpec for PwrCtrlSmSt_SPEC {
type DataType = u32;
}
#[doc = "Link Layer Power Control FSM Status Register"]
pub type PwrCtrlSmSt = crate::RegValueT<PwrCtrlSmSt_SPEC>;
impl PwrCtrlSmSt {
#[doc = "This register reflects the current state of the LL Power Control FSM\n4\'h0 - IDLE\n4\'h1 - SLEEP\n4\'h2 - DEEP_SLEEP\n4\'h4 - WAIT_OSC_STABLE\n4\'h5 - INTR_GEN\n4\'h6 - ACTIVE\n4\'h7 - REQ_RF_OFF"]
#[inline(always)]
pub fn pwr_ctrl_sm_curr_state(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, PwrCtrlSmSt_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,PwrCtrlSmSt_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for PwrCtrlSmSt {
#[inline(always)]
fn default() -> PwrCtrlSmSt {
<crate::RegValueT<PwrCtrlSmSt_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HvldoCtrl_SPEC;
impl crate::sealed::RegSpec for HvldoCtrl_SPEC {
type DataType = u32;
}
#[doc = "HVLDO Configuration register"]
pub type HvldoCtrl = crate::RegValueT<HvldoCtrl_SPEC>;
impl HvldoCtrl {
#[doc = "ADFT enable"]
#[inline(always)]
pub fn adft_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, HvldoCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,HvldoCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "ADFT select"]
#[inline(always)]
pub fn adft_ctrl(
self,
) -> crate::common::RegisterField<1, 0xf, 1, 0, u8, u8, HvldoCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<1,0xf,1,0,u8,u8,HvldoCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Vref ext input enable."]
#[inline(always)]
pub fn vref_ext_en(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, HvldoCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,HvldoCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "hvldo LV detect status"]
#[inline(always)]
pub fn status(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, HvldoCtrl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31,1,0,HvldoCtrl_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for HvldoCtrl {
#[inline(always)]
fn default() -> HvldoCtrl {
<crate::RegValueT<HvldoCtrl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MiscEnCtrl_SPEC;
impl crate::sealed::RegSpec for MiscEnCtrl_SPEC {
type DataType = u32;
}
#[doc = "Radio Buck and Active regulator enable control"]
pub type MiscEnCtrl = crate::RegValueT<MiscEnCtrl_SPEC>;
impl MiscEnCtrl {
#[doc = "Buck enable control. This must be programmed before enabling the Radio.\n1\'b1 - Buck enable output to radio is tied to 0\n1\'b0 - Buck enable output to radio is controlled from Mode transition FSM"]
#[inline(always)]
pub fn buck_en_ctrl(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, MiscEnCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,MiscEnCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Active regulator enable control. This must be programmed before enabling the Radio.\n1\'b0 - Active regulator enable output to radio is tied to 0\n1\'b1 - Active regulator enable output to radio is controlled from Mode transition FSM"]
#[inline(always)]
pub fn act_reg_en_ctrl(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, MiscEnCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,MiscEnCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the LPM drift calculation.\n1 - Enables the LPM drift mod\n0 - Disables the LPM drift mod"]
#[inline(always)]
pub fn lpm_drift_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, MiscEnCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,MiscEnCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the LPM drift multi level compensation.\n1 - Enables the LPM drift multi comp\n0 - Disables the LPM drift multi comp"]
#[inline(always)]
pub fn lpm_drift_multi(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, MiscEnCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,MiscEnCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the LPM entry control mode\n1 - LPM can be entered in the same slot as the previous LPM exit\n0 - LPM must not be entered in the same slot or the subsequent slot as the last LPM exit"]
#[inline(always)]
pub fn lpm_entry_ctrl_mode(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, MiscEnCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,MiscEnCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for MiscEnCtrl {
#[inline(always)]
fn default() -> MiscEnCtrl {
<crate::RegValueT<MiscEnCtrl_SPEC> as RegisterValue<_>>::new(8)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EfuseConfig_SPEC;
impl crate::sealed::RegSpec for EfuseConfig_SPEC {
type DataType = u32;
}
#[doc = "EFUSE mode configuration register"]
pub type EfuseConfig = crate::RegValueT<EfuseConfig_SPEC>;
impl EfuseConfig {
#[doc = "This register enables the efuse mode in m0s8bless_ver3"]
#[inline(always)]
pub fn efuse_mode(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, EfuseConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,EfuseConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit when set by firmware enables the read from EFUSE macro. It is cleared when the efuse read is completed"]
#[inline(always)]
pub fn efuse_read(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, EfuseConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,EfuseConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This bit when set by firmware enables the write to EFUSE macro. It is cleared when the efuse write is completed"]
#[inline(always)]
pub fn efuse_write(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, EfuseConfig_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,EfuseConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for EfuseConfig {
#[inline(always)]
fn default() -> EfuseConfig {
<crate::RegValueT<EfuseConfig_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EfuseTimCtrl1_SPEC;
impl crate::sealed::RegSpec for EfuseTimCtrl1_SPEC {
type DataType = u32;
}
#[doc = "EFUSE timing control register (common for Program and Read modes)"]
pub type EfuseTimCtrl1 = crate::RegValueT<EfuseTimCtrl1_SPEC>;
impl EfuseTimCtrl1 {
#[doc = "Decides the duration of TPGM (in Program mode) or TCKHP (in Read mode)\nTPGM: Burning Time\nTCKHP : SCLK high Period"]
#[inline(always)]
pub fn sclk_high(
self,
) -> crate::common::RegisterField<
0,
0xff,
1,
0,
u8,
u8,
EfuseTimCtrl1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xff,
1,
0,
u8,
u8,
EfuseTimCtrl1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Duration of SCLK LOW (TCLKP_R) or TCKLP_P"]
#[inline(always)]
pub fn sclk_low(
self,
) -> crate::common::RegisterField<
8,
0xff,
1,
0,
u8,
u8,
EfuseTimCtrl1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0xff,
1,
0,
u8,
u8,
EfuseTimCtrl1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This register specifies the setup time between CS and SCLK (TSR_CLK)"]
#[inline(always)]
pub fn cs_sclk_setup_time(
self,
) -> crate::common::RegisterField<
16,
0xf,
1,
0,
u8,
u8,
EfuseTimCtrl1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0xf,
1,
0,
u8,
u8,
EfuseTimCtrl1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This register specifies the hold time between CS and SCLK\n(THR_CLK)"]
#[inline(always)]
pub fn cs_sclk_hold_time(
self,
) -> crate::common::RegisterField<
20,
0xf,
1,
0,
u8,
u8,
EfuseTimCtrl1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
20,
0xf,
1,
0,
u8,
u8,
EfuseTimCtrl1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This field decides setup time between RW & CS (TSR_RW: in read mode) or RW & AVDD (TSP_RW: in Program mode).\nTSR_RW: RW to CS setup time into Read mode \nTSP_RW: RW to AVDD setup time into program mode"]
#[inline(always)]
pub fn rw_cs_setup_time(
self,
) -> crate::common::RegisterField<
24,
0xf,
1,
0,
u8,
u8,
EfuseTimCtrl1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
24,
0xf,
1,
0,
u8,
u8,
EfuseTimCtrl1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This field decides hold time between RW & CS (THR_RW: in read mode) or RW & AVDD (THP_RW: in Program mode).\nTHR_RW: RW to CS hold time out of Read mode \nTHP_RW: RW to AVDD hold time out of program mode"]
#[inline(always)]
pub fn rw_cs_hold_time(
self,
) -> crate::common::RegisterField<
28,
0xf,
1,
0,
u8,
u8,
EfuseTimCtrl1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
28,
0xf,
1,
0,
u8,
u8,
EfuseTimCtrl1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for EfuseTimCtrl1 {
#[inline(always)]
fn default() -> EfuseTimCtrl1 {
<crate::RegValueT<EfuseTimCtrl1_SPEC> as RegisterValue<_>>::new(286392768)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EfuseTimCtrl2_SPEC;
impl crate::sealed::RegSpec for EfuseTimCtrl2_SPEC {
type DataType = u32;
}
#[doc = "EFUSE timing control Register (for Read)"]
pub type EfuseTimCtrl2 = crate::RegValueT<EfuseTimCtrl2_SPEC>;
impl EfuseTimCtrl2 {
#[doc = "This register specifies the time for data sampling from SCLK HIGH\n(TCKDQ_H)"]
#[inline(always)]
pub fn data_sample_time(
self,
) -> crate::common::RegisterField<
0,
0xff,
1,
0,
u8,
u8,
EfuseTimCtrl2_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xff,
1,
0,
u8,
u8,
EfuseTimCtrl2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Wait time \nDOUT to CS hold time out of read mode (TDQH)"]
#[inline(always)]
pub fn dout_cs_hold_time(
self,
) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, EfuseTimCtrl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
8,
0xf,
1,
0,
u8,
u8,
EfuseTimCtrl2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for EfuseTimCtrl2 {
#[inline(always)]
fn default() -> EfuseTimCtrl2 {
<crate::RegValueT<EfuseTimCtrl2_SPEC> as RegisterValue<_>>::new(258)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EfuseTimCtrl3_SPEC;
impl crate::sealed::RegSpec for EfuseTimCtrl3_SPEC {
type DataType = u32;
}
#[doc = "EFUSE timing control Register (for Program)"]
pub type EfuseTimCtrl3 = crate::RegValueT<EfuseTimCtrl3_SPEC>;
impl EfuseTimCtrl3 {
#[doc = "PGM to SCLK setup time (TS_PGM)\nPGM_SCLK_SETUP_TIME <CS_SCLK_SETUP_TIME"]
#[inline(always)]
pub fn pgm_sclk_setup_time(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, EfuseTimCtrl3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
EfuseTimCtrl3_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "PGM to SCLK hold time (TH_PGM)"]
#[inline(always)]
pub fn pgm_sclk_hold_time(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, EfuseTimCtrl3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
4,
0xf,
1,
0,
u8,
u8,
EfuseTimCtrl3_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "AVDD to CS setup time into program mode (TSP_AVDD_CS)"]
#[inline(always)]
pub fn avdd_cs_setup_time(
self,
) -> crate::common::RegisterField<
8,
0xff,
1,
0,
u8,
u8,
EfuseTimCtrl3_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0xff,
1,
0,
u8,
u8,
EfuseTimCtrl3_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "AVDD to CS hold time out of program mode (THP_AVDD_CS)"]
#[inline(always)]
pub fn avdd_cs_hold_time(
self,
) -> crate::common::RegisterField<
16,
0xff,
1,
0,
u8,
u8,
EfuseTimCtrl3_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0xff,
1,
0,
u8,
u8,
EfuseTimCtrl3_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for EfuseTimCtrl3 {
#[inline(always)]
fn default() -> EfuseTimCtrl3 {
<crate::RegValueT<EfuseTimCtrl3_SPEC> as RegisterValue<_>>::new(3815953)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EfuseRdataL_SPEC;
impl crate::sealed::RegSpec for EfuseRdataL_SPEC {
type DataType = u32;
}
#[doc = "EFUSE Lower read data"]
pub type EfuseRdataL = crate::RegValueT<EfuseRdataL_SPEC>;
impl EfuseRdataL {
#[doc = "This register has the read value from the Efuse macro, fuse bits\\[31:0\\]"]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
EfuseRdataL_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
EfuseRdataL_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for EfuseRdataL {
#[inline(always)]
fn default() -> EfuseRdataL {
<crate::RegValueT<EfuseRdataL_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EfuseRdataH_SPEC;
impl crate::sealed::RegSpec for EfuseRdataH_SPEC {
type DataType = u32;
}
#[doc = "EFUSE higher read data"]
pub type EfuseRdataH = crate::RegValueT<EfuseRdataH_SPEC>;
impl EfuseRdataH {
#[doc = "This register has the read value from the Efuse macro, fuse bits\\[63:32\\]"]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
EfuseRdataH_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
EfuseRdataH_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for EfuseRdataH {
#[inline(always)]
fn default() -> EfuseRdataH {
<crate::RegValueT<EfuseRdataH_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EfuseWdataL_SPEC;
impl crate::sealed::RegSpec for EfuseWdataL_SPEC {
type DataType = u32;
}
#[doc = "EFUSE lower write word"]
pub type EfuseWdataL = crate::RegValueT<EfuseWdataL_SPEC>;
impl EfuseWdataL {
#[doc = "This register has the write value to the Efuse macro, fuse bits\\[31:0\\]"]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
EfuseWdataL_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
EfuseWdataL_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for EfuseWdataL {
#[inline(always)]
fn default() -> EfuseWdataL {
<crate::RegValueT<EfuseWdataL_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EfuseWdataH_SPEC;
impl crate::sealed::RegSpec for EfuseWdataH_SPEC {
type DataType = u32;
}
#[doc = "EFUSE higher write word"]
pub type EfuseWdataH = crate::RegValueT<EfuseWdataH_SPEC>;
impl EfuseWdataH {
#[doc = "This register has the write value to the Efuse macro, fuse bits\\[63:32\\]"]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
EfuseWdataH_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
EfuseWdataH_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for EfuseWdataH {
#[inline(always)]
fn default() -> EfuseWdataH {
<crate::RegValueT<EfuseWdataH_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DivBy625Cfg_SPEC;
impl crate::sealed::RegSpec for DivBy625Cfg_SPEC {
type DataType = u32;
}
#[doc = "Divide by 625 for FW Use"]
pub type DivBy625Cfg = crate::RegValueT<DivBy625Cfg_SPEC>;
impl DivBy625Cfg {
#[doc = "This bit enables the divider for use by FW\n1\'b0 - divider used by LL\n1\'b1 - divider can be used by FW\nThis divider can only be used in MMMS mode. Do not enable for legacy operation"]
#[inline(always)]
pub fn enable(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, DivBy625Cfg_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,DivBy625Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field holds the dividend"]
#[inline(always)]
pub fn dividend(
self,
) -> crate::common::RegisterField<
8,
0xffff,
1,
0,
u16,
u16,
DivBy625Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0xffff,
1,
0,
u16,
u16,
DivBy625Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DivBy625Cfg {
#[inline(always)]
fn default() -> DivBy625Cfg {
<crate::RegValueT<DivBy625Cfg_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DivBy625Sts_SPEC;
impl crate::sealed::RegSpec for DivBy625Sts_SPEC {
type DataType = u32;
}
#[doc = "Output of divide by 625 divider"]
pub type DivBy625Sts = crate::RegValueT<DivBy625Sts_SPEC>;
impl DivBy625Sts {
#[doc = "Quotient value from the divider. Available 1 cycle after dividend is programmed."]
#[inline(always)]
pub fn quotient(
self,
) -> crate::common::RegisterField<0, 0x3f, 1, 0, u8, u8, DivBy625Sts_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x3f,1,0,u8,u8,DivBy625Sts_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Remainder value from the divider. Available 1 cycle after dividend is programmed."]
#[inline(always)]
pub fn remainder(
self,
) -> crate::common::RegisterField<
8,
0x3ff,
1,
0,
u16,
u16,
DivBy625Sts_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
8,
0x3ff,
1,
0,
u16,
u16,
DivBy625Sts_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for DivBy625Sts {
#[inline(always)]
fn default() -> DivBy625Sts {
<crate::RegValueT<DivBy625Sts_SPEC> as RegisterValue<_>>::new(256)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PacketCounter0_SPEC;
impl crate::sealed::RegSpec for PacketCounter0_SPEC {
type DataType = u32;
}
#[doc = "Packet counter 0"]
pub type PacketCounter0 = crate::RegValueT<PacketCounter0_SPEC>;
impl PacketCounter0 {
#[doc = "Lower 32-bits of the packet counter value passed as part of Nonce for the packet to be encrypted."]
#[inline(always)]
pub fn packet_counter_lower(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
PacketCounter0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
PacketCounter0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PacketCounter0 {
#[inline(always)]
fn default() -> PacketCounter0 {
<crate::RegValueT<PacketCounter0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct PacketCounter2_SPEC;
impl crate::sealed::RegSpec for PacketCounter2_SPEC {
type DataType = u32;
}
#[doc = "Packet counter 2"]
pub type PacketCounter2 = crate::RegValueT<PacketCounter2_SPEC>;
impl PacketCounter2 {
#[doc = "Upper 8 bits of the packet counter value passed as part of Nonce for the packet to be encrypted."]
#[inline(always)]
pub fn packet_counter_upper(
self,
) -> crate::common::RegisterField<
0,
0xff,
1,
0,
u8,
u8,
PacketCounter2_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xff,
1,
0,
u8,
u8,
PacketCounter2_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for PacketCounter2 {
#[inline(always)]
fn default() -> PacketCounter2 {
<crate::RegValueT<PacketCounter2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IvMaster0_SPEC;
impl crate::sealed::RegSpec for IvMaster0_SPEC {
type DataType = u32;
}
#[doc = "Master Initialization Vector 0"]
pub type IvMaster0 = crate::RegValueT<IvMaster0_SPEC>;
impl IvMaster0 {
#[doc = "This is the IVm field, which contains the master\'s portion of the initialization vector."]
#[inline(always)]
pub fn iv_master(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
IvMaster0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
IvMaster0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for IvMaster0 {
#[inline(always)]
fn default() -> IvMaster0 {
<crate::RegValueT<IvMaster0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IvSlave0_SPEC;
impl crate::sealed::RegSpec for IvSlave0_SPEC {
type DataType = u32;
}
#[doc = "Slave Initialization Vector 0"]
pub type IvSlave0 = crate::RegValueT<IvSlave0_SPEC>;
impl IvSlave0 {
#[doc = "This is the IVs field, which contains the slave\'s portion of the initialization vector."]
#[inline(always)]
pub fn iv_slave(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
IvSlave0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
IvSlave0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for IvSlave0 {
#[inline(always)]
fn default() -> IvSlave0 {
<crate::RegValueT<IvSlave0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EncKey_SPEC;
impl crate::sealed::RegSpec for EncKey_SPEC {
type DataType = u32;
}
#[doc = "Encryption Key register 0-3"]
pub type EncKey = crate::RegValueT<EncKey_SPEC>;
impl EncKey {
#[doc = "The encryption key / session key which is used in ECB encryption, CCM encryption and CCM decryption."]
#[inline(always)]
pub fn enc_key(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
EncKey_SPEC,
crate::common::W,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
EncKey_SPEC,
crate::common::W,
>::from_register(self, 0)
}
}
impl ::core::default::Default for EncKey {
#[inline(always)]
fn default() -> EncKey {
<crate::RegValueT<EncKey_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MicIn0_SPEC;
impl crate::sealed::RegSpec for MicIn0_SPEC {
type DataType = u32;
}
#[doc = "MIC input register"]
pub type MicIn0 = crate::RegValueT<MicIn0_SPEC>;
impl MicIn0 {
#[doc = "This is the MIC field used for CCM decryption."]
#[inline(always)]
pub fn mic_in(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
MicIn0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
MicIn0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for MicIn0 {
#[inline(always)]
fn default() -> MicIn0 {
<crate::RegValueT<MicIn0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MicOut0_SPEC;
impl crate::sealed::RegSpec for MicOut0_SPEC {
type DataType = u32;
}
#[doc = "MIC output register"]
pub type MicOut0 = crate::RegValueT<MicOut0_SPEC>;
impl MicOut0 {
#[doc = "This is the MIC generated during CCM encryption."]
#[inline(always)]
pub fn mic_out(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
MicOut0_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
MicOut0_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for MicOut0 {
#[inline(always)]
fn default() -> MicOut0 {
<crate::RegValueT<MicOut0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EncParams_SPEC;
impl crate::sealed::RegSpec for EncParams_SPEC {
type DataType = u32;
}
#[doc = "Encryption Parameter register"]
pub type EncParams = crate::RegValueT<EncParams_SPEC>;
impl EncParams {
#[doc = "LLID of the packet."]
#[inline(always)]
pub fn data_pdu_header(
self,
) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, EncParams_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x3,1,0,u8,u8,EncParams_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Length of the input data."]
#[inline(always)]
pub fn payload_length_lsb(
self,
) -> crate::common::RegisterField<2, 0x1f, 1, 0, u8, u8, EncParams_SPEC, crate::common::RW>
{
crate::common::RegisterField::<2,0x1f,1,0,u8,u8,EncParams_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "The directionBit shall be set to \'1\' for Data Channel PDUs sent by the master and set to \'0\' for Data Channel PDUs sent by the slave."]
#[inline(always)]
pub fn direction(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, EncParams_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,EncParams_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "3 Most significant bits of the LS byte of the length of the input data. Valid only when DLE is enabled. \nWhen DLE is enabled total ENC payload length = {PAYLOAD_LENGTH_LSB_EXT, PAYLOAD_LENGTH_LSB}"]
#[inline(always)]
pub fn payload_length_lsb_ext(
self,
) -> crate::common::RegisterField<8, 0x7, 1, 0, u8, u8, EncParams_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x7,1,0,u8,u8,EncParams_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls the encryption memory access mode. Valid only when DLE is enabled. \n0 - The AES is idle while memory fetch/store in progress.\n1- The AES is pipelined while memory fetch/store in progress."]
#[inline(always)]
pub fn mem_latency_hide(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, EncParams_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,EncParams_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for EncParams {
#[inline(always)]
fn default() -> EncParams {
<crate::RegValueT<EncParams_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EncConfig_SPEC;
impl crate::sealed::RegSpec for EncConfig_SPEC {
type DataType = u32;
}
#[doc = "Encryption Configuration"]
pub type EncConfig = crate::RegValueT<EncConfig_SPEC>;
impl EncConfig {
#[doc = "1 Start the AES processing"]
#[inline(always)]
pub fn start_proc(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, EncConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,EncConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "0 - CCM\n1 - ECB"]
#[inline(always)]
pub fn ecb_ccm(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, EncConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,EncConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Decryption/Encryption\n0 - Encrypt\n1 - Decrypt"]
#[inline(always)]
pub fn dec_enc(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, EncConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,EncConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "MS byte of the length of the input data when B0 needs to be completely configurable. Valid only when AES_B0_DATA_OVERRIDE is enabled. \nWhen AES_B0_DATA_OVERRIDE is enabled total ENC payload length = {PAYLOAD_LENGTH_MSB, PAYLOAD_LENGTH_MSB, PAYLOAD_LENGTH}"]
#[inline(always)]
pub fn payload_length_msb(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, EncConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,EncConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "LS byte of the input data when B0 needs to be completely configurable. Valid only when AES_B0_DATA_OVERRIDE is enabled."]
#[inline(always)]
pub fn b0_flags(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, EncConfig_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,EncConfig_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Configuration to use B0 DATA provided by FW for CCM computation"]
#[inline(always)]
pub fn aes_b0_data_override(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, EncConfig_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,EncConfig_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for EncConfig {
#[inline(always)]
fn default() -> EncConfig {
<crate::RegValueT<EncConfig_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EncIntrEn_SPEC;
impl crate::sealed::RegSpec for EncIntrEn_SPEC {
type DataType = u32;
}
#[doc = "Encryption Interrupt enable"]
pub type EncIntrEn = crate::RegValueT<EncIntrEn_SPEC>;
impl EncIntrEn {
#[doc = "Authentication interrupt enable\n0 - Disable\n1 - Enable"]
#[inline(always)]
pub fn auth_pass_intr_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, EncIntrEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,EncIntrEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "ECB processed interrupt enable\n0 - Disable\n1 - Enable"]
#[inline(always)]
pub fn ecb_proc_intr_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, EncIntrEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,EncIntrEn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "CCM processed interupt enable\n0 - Disable\n1 - Enable"]
#[inline(always)]
pub fn ccm_proc_intr_en(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, EncIntrEn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,EncIntrEn_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for EncIntrEn {
#[inline(always)]
fn default() -> EncIntrEn {
<crate::RegValueT<EncIntrEn_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EncIntr_SPEC;
impl crate::sealed::RegSpec for EncIntr_SPEC {
type DataType = u32;
}
#[doc = "Encryption Interrupt status and clear register"]
pub type EncIntr = crate::RegValueT<EncIntr_SPEC>;
impl EncIntr {
#[doc = "Authentication interrupt.\n0x1- indicates MIC matched\n0x0 -indicated MIC mismatched\nWriting 1 to this register clears the interrupt."]
#[inline(always)]
pub fn auth_pass_intr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, EncIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,EncIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "ECB processed interrupt.\nWriting 1 to this register clears the interrupt."]
#[inline(always)]
pub fn ecb_proc_intr(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, EncIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,EncIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "CCM processed interrupt.\nWriting 1 to this register clears the interrupt"]
#[inline(always)]
pub fn ccm_proc_intr(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, EncIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,EncIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Clears the input data. Used for Zero padding of encryption for less than block sized data."]
#[inline(always)]
pub fn in_data_clear(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, EncIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,EncIntr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for EncIntr {
#[inline(always)]
fn default() -> EncIntr {
<crate::RegValueT<EncIntr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct B1DataReg_SPEC;
impl crate::sealed::RegSpec for B1DataReg_SPEC {
type DataType = u32;
}
#[doc = "Programmable B1 Data register (0-3)"]
pub type B1DataReg = crate::RegValueT<B1DataReg_SPEC>;
impl B1DataReg {
#[doc = "Programmable B1 Data register"]
#[inline(always)]
pub fn b1_data(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
B1DataReg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
B1DataReg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for B1DataReg {
#[inline(always)]
fn default() -> B1DataReg {
<crate::RegValueT<B1DataReg_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct EncMemBaseAddr_SPEC;
impl crate::sealed::RegSpec for EncMemBaseAddr_SPEC {
type DataType = u32;
}
#[doc = "Encryption memory base address"]
pub type EncMemBaseAddr = crate::RegValueT<EncMemBaseAddr_SPEC>;
impl EncMemBaseAddr {
#[doc = "Data values written to Enc memory are written as 16-bit wide data. This memory is valid only if DLE is set."]
#[inline(always)]
pub fn enc_mem(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
EncMemBaseAddr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
EncMemBaseAddr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for EncMemBaseAddr {
#[inline(always)]
fn default() -> EncMemBaseAddr {
<crate::RegValueT<EncMemBaseAddr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrimLdo0_SPEC;
impl crate::sealed::RegSpec for TrimLdo0_SPEC {
type DataType = u32;
}
#[doc = "LDO Trim register 0"]
pub type TrimLdo0 = crate::RegValueT<TrimLdo0_SPEC>;
impl TrimLdo0 {
#[doc = "To trim the regulated voltage in steps of 25mV typically"]
#[inline(always)]
pub fn act_ldo_vreg(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, TrimLdo0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,TrimLdo0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "To trim the bias currents for all the active mode blocks"]
#[inline(always)]
pub fn act_ldo_itail(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, TrimLdo0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0xf,1,0,u8,u8,TrimLdo0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TrimLdo0 {
#[inline(always)]
fn default() -> TrimLdo0 {
<crate::RegValueT<TrimLdo0_SPEC> as RegisterValue<_>>::new(88)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrimLdo1_SPEC;
impl crate::sealed::RegSpec for TrimLdo1_SPEC {
type DataType = u32;
}
#[doc = "LDO Trim register 1"]
pub type TrimLdo1 = crate::RegValueT<TrimLdo1_SPEC>;
impl TrimLdo1 {
#[doc = "To trim active regulator reference voltage"]
#[inline(always)]
pub fn act_ref_bgr(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, TrimLdo1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,TrimLdo1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "To trim standby regulator reference voltage"]
#[inline(always)]
pub fn sb_bgres(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, TrimLdo1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0xf,1,0,u8,u8,TrimLdo1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TrimLdo1 {
#[inline(always)]
fn default() -> TrimLdo1 {
<crate::RegValueT<TrimLdo1_SPEC> as RegisterValue<_>>::new(8)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrimLdo2_SPEC;
impl crate::sealed::RegSpec for TrimLdo2_SPEC {
type DataType = u32;
}
#[doc = "LDO Trim register 2"]
pub type TrimLdo2 = crate::RegValueT<TrimLdo2_SPEC>;
impl TrimLdo2 {
#[doc = "To trim standby regulator beta-multiplier current"]
#[inline(always)]
pub fn sb_bmult_res(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, TrimLdo2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,TrimLdo2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "To trim standby regulator beta-multiplier current"]
#[inline(always)]
pub fn sb_bmult_nbias(
self,
) -> crate::common::RegisterField<5, 0x3, 1, 0, u8, u8, TrimLdo2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<5,0x3,1,0,u8,u8,TrimLdo2_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TrimLdo2 {
#[inline(always)]
fn default() -> TrimLdo2 {
<crate::RegValueT<TrimLdo2_SPEC> as RegisterValue<_>>::new(96)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrimLdo3_SPEC;
impl crate::sealed::RegSpec for TrimLdo3_SPEC {
type DataType = u32;
}
#[doc = "LDO Trim register 3"]
pub type TrimLdo3 = crate::RegValueT<TrimLdo3_SPEC>;
impl TrimLdo3 {
#[doc = "To trim the trip points of the LV-Detect block"]
#[inline(always)]
pub fn lvdet(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, TrimLdo3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,TrimLdo3_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "To trim standby regulator beta-multiplier temp-co slope"]
#[inline(always)]
pub fn slope_sb_bmult(
self,
) -> crate::common::RegisterField<5, 0x3, 1, 0, u8, u8, TrimLdo3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<5,0x3,1,0,u8,u8,TrimLdo3_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TrimLdo3 {
#[inline(always)]
fn default() -> TrimLdo3 {
<crate::RegValueT<TrimLdo3_SPEC> as RegisterValue<_>>::new(16)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrimMxd_SPEC;
impl crate::sealed::RegSpec for TrimMxd_SPEC {
type DataType = u32;
}
#[doc = "MXD die Trim registers"]
pub type TrimMxd = crate::RegValueT<TrimMxd_SPEC>;
impl TrimMxd {
#[doc = "MXD trim bits"]
#[inline(always)]
pub fn mxd_trim_bits(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, TrimMxd_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,TrimMxd_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TrimMxd {
#[inline(always)]
fn default() -> TrimMxd {
<crate::RegValueT<TrimMxd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrimLdo4_SPEC;
impl crate::sealed::RegSpec for TrimLdo4_SPEC {
type DataType = u32;
}
#[doc = "LDO Trim register 4"]
pub type TrimLdo4 = crate::RegValueT<TrimLdo4_SPEC>;
impl TrimLdo4 {
#[doc = "To debug post layout or post silicon"]
#[inline(always)]
pub fn t_ldo(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, TrimLdo4_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,TrimLdo4_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TrimLdo4 {
#[inline(always)]
fn default() -> TrimLdo4 {
<crate::RegValueT<TrimLdo4_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrimLdo5_SPEC;
impl crate::sealed::RegSpec for TrimLdo5_SPEC {
type DataType = u32;
}
#[doc = "LDO Trim register 5"]
pub type TrimLdo5 = crate::RegValueT<TrimLdo5_SPEC>;
impl TrimLdo5 {
#[doc = "N/A"]
#[inline(always)]
pub fn rsvd(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, TrimLdo5_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,TrimLdo5_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TrimLdo5 {
#[inline(always)]
fn default() -> TrimLdo5 {
<crate::RegValueT<TrimLdo5_SPEC> as RegisterValue<_>>::new(0)
}
}
}