/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"Energy Profiler IP"]
unsafe impl ::core::marker::Send for super::Profile {}
unsafe impl ::core::marker::Sync for super::Profile {}
impl super::Profile {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "Profile control"]
#[inline(always)]
pub const fn ctl(&self) -> &'static crate::common::Reg<self::Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Profile status"]
#[inline(always)]
pub const fn status(&self) -> &'static crate::common::Reg<self::Status_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::Status_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "Profile command"]
#[inline(always)]
pub const fn cmd(&self) -> &'static crate::common::Reg<self::Cmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16usize),
)
}
}
#[doc = "Profile interrupt"]
#[inline(always)]
pub const fn intr(&self) -> &'static crate::common::Reg<self::Intr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Intr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1984usize),
)
}
}
#[doc = "Profile interrupt set"]
#[inline(always)]
pub const fn intr_set(
&self,
) -> &'static crate::common::Reg<self::IntrSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1988usize),
)
}
}
#[doc = "Profile interrupt mask"]
#[inline(always)]
pub const fn intr_mask(
&self,
) -> &'static crate::common::Reg<self::IntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1992usize),
)
}
}
#[doc = "Profile interrupt masked"]
#[inline(always)]
pub const fn intr_masked(
&self,
) -> &'static crate::common::Reg<self::IntrMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1996usize),
)
}
}
#[doc = "Profile counter structure"]
#[inline(always)]
pub fn cnt_struct(
self,
) -> &'static crate::common::ClusterRegisterArray<crate::profile::_CntStruct, 8, 0x10> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x800usize))
}
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctl_SPEC;
impl crate::sealed::RegSpec for Ctl_SPEC {
type DataType = u32;
}
#[doc = "Profile control"]
pub type Ctl = crate::RegValueT<Ctl_SPEC>;
impl Ctl {
#[doc = "Specifies the profiling time window mode:\n\'0\': Start / stop mode. The profiling time window is started when a rising edge of the start trigger signal occurs and stopped when a rising edge of the stop trigger signal occurs.\nIn case both rising edges (of start and stop trigger signals) occur in the same cycle, the profiling time window is stopped.\n\'1\': Enable mode. The profiling time window is active as long as the start \'trigger\' signal is active. The stop trigger signal has no effect."]
#[inline(always)]
pub fn win_mode(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Ctl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Enables the profiling block:\n\'0\': Disabled.\n\'1\': Enabled."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31, 1, 0, Ctl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Ctl {
#[inline(always)]
fn default() -> Ctl {
<crate::RegValueT<Ctl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Status_SPEC;
impl crate::sealed::RegSpec for Status_SPEC {
type DataType = u32;
}
#[doc = "Profile status"]
pub type Status = crate::RegValueT<Status_SPEC>;
impl Status {
#[doc = "Indicates if the profiling time window is active.\n\'0\': Not active.\n\'1\': Active."]
#[inline(always)]
pub fn win_active(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Status {
#[inline(always)]
fn default() -> Status {
<crate::RegValueT<Status_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cmd_SPEC;
impl crate::sealed::RegSpec for Cmd_SPEC {
type DataType = u32;
}
#[doc = "Profile command"]
pub type Cmd = crate::RegValueT<Cmd_SPEC>;
impl Cmd {
#[doc = "Software start trigger for the profiling time window. When written with \'1\', the profiling time window is started.\nCan only be used in start / stop mode (PROFILE_WIN_MODE=0).\nHas no effect in enable mode (PROFILE_WIN_MODE=1)."]
#[inline(always)]
pub fn start_tr(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Cmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Cmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Software stop trigger for the profiling time window. When written with \'1\', the profiling time window is stopped.\nCan only be used in start / stop mode (PROFILE_WIN_MODE=0).\nHas no effect in enable mode (PROFILE_WIN_MODE=1)."]
#[inline(always)]
pub fn stop_tr(self) -> crate::common::RegisterFieldBool<1, 1, 0, Cmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Cmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Counter clear. When written with \'1\', all profiling counter registers are cleared to 0x00."]
#[inline(always)]
pub fn clr_all_cnt(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Cmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, Cmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Cmd {
#[inline(always)]
fn default() -> Cmd {
<crate::RegValueT<Cmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Intr_SPEC;
impl crate::sealed::RegSpec for Intr_SPEC {
type DataType = u32;
}
#[doc = "Profile interrupt"]
pub type Intr = crate::RegValueT<Intr_SPEC>;
impl Intr {
#[doc = "This interrupt cause field is activated (HW sets the field to \'1\') when an profiling counter overflow (from 0xFFFFFFFF to 0x00000000) is captured. There is one bit per profling counter.\n\nSW writes a \'1\' to a bit of this field to clear this bit to \'0\' (writing 0xFFFFFFFF clears all interrupt causes to \'0\')."]
#[inline(always)]
pub fn cnt_ovflw(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Intr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Intr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Intr {
#[inline(always)]
fn default() -> Intr {
<crate::RegValueT<Intr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSet_SPEC;
impl crate::sealed::RegSpec for IntrSet_SPEC {
type DataType = u32;
}
#[doc = "Profile interrupt set"]
pub type IntrSet = crate::RegValueT<IntrSet_SPEC>;
impl IntrSet {
#[doc = "SW writes a \'1\' to a bit of this field to set the corresponding bit in the INTR register."]
#[inline(always)]
pub fn cnt_ovflw(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, IntrSet_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrSet {
#[inline(always)]
fn default() -> IntrSet {
<crate::RegValueT<IntrSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMask_SPEC;
impl crate::sealed::RegSpec for IntrMask_SPEC {
type DataType = u32;
}
#[doc = "Profile interrupt mask"]
pub type IntrMask = crate::RegValueT<IntrMask_SPEC>;
impl IntrMask {
#[doc = "Mask bit for corresponding field in the INTR register."]
#[inline(always)]
pub fn cnt_ovflw(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, IntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
IntrMask_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for IntrMask {
#[inline(always)]
fn default() -> IntrMask {
<crate::RegValueT<IntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMasked_SPEC;
impl crate::sealed::RegSpec for IntrMasked_SPEC {
type DataType = u32;
}
#[doc = "Profile interrupt masked"]
pub type IntrMasked = crate::RegValueT<IntrMasked_SPEC>;
impl IntrMasked {
#[doc = "Logical and of corresponding INTR and INTR_MASK fields."]
#[inline(always)]
pub fn cnt_ovflw(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
IntrMasked_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
IntrMasked_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for IntrMasked {
#[inline(always)]
fn default() -> IntrMasked {
<crate::RegValueT<IntrMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc = "Profile counter structure"]
#[non_exhaustive]
pub struct _CntStruct;
#[doc = "Profile counter structure"]
pub type CntStruct = &'static _CntStruct;
unsafe impl ::core::marker::Sync for _CntStruct {}
impl _CntStruct {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "Profile counter configuration"]
#[inline(always)]
pub const fn ctl(
&self,
) -> &'static crate::common::Reg<cnt_struct::Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<cnt_struct::Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Profile counter value"]
#[inline(always)]
pub const fn cnt(
&self,
) -> &'static crate::common::Reg<cnt_struct::Cnt_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<cnt_struct::Cnt_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(8usize),
)
}
}
}
pub mod cnt_struct {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctl_SPEC;
impl crate::sealed::RegSpec for Ctl_SPEC {
type DataType = u32;
}
#[doc = "Profile counter configuration"]
pub type Ctl = crate::RegValueT<Ctl_SPEC>;
impl Ctl {
#[doc = "This field specifies if events (edges) or a duration of the monitor signal is counted.\n\'0\': Events are monitored. An edge detection is done. All edges of the selected monitor signal are counted.\n\'1\': A duration is monitored. No edge detection is done. The monitored signal is taken as a (high active) level signal for enabling the profiling counter.\n\nNote: All monitor signals which only can represent events are edge encoded in hardware, therefore a selection of CTL.CNT_DURATION=1 will not produce meaningful results."]
#[inline(always)]
pub fn cnt_duration(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Ctl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0."]
#[inline(always)]
pub fn ref_clk_sel(
self,
) -> crate::common::RegisterField<
4,
0x7,
1,
0,
ctl::RefClkSel,
ctl::RefClkSel,
Ctl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x7,
1,
0,
ctl::RefClkSel,
ctl::RefClkSel,
Ctl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This field specifies the montior input signal to be observed by the profiling counter.\nThe monitor signals are product specific, see product definition spreadsheet tab \'Monitor\' for details."]
#[inline(always)]
pub fn mon_sel(
self,
) -> crate::common::RegisterField<16, 0x7f, 1, 0, u8, u8, Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x7f,1,0,u8,u8,Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables the profiling counter:\n\'0\': Disabled.\n\'1\': Enabled."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31, 1, 0, Ctl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Ctl {
#[inline(always)]
fn default() -> Ctl {
<crate::RegValueT<Ctl_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct RefClkSel_SPEC;
pub type RefClkSel = crate::EnumBitfieldStruct<u8, RefClkSel_SPEC>;
impl RefClkSel {
#[doc = "Timer clock (divided or undivided high frequency clock, e.g. from IMO). Selection is done in SRSS register CLK_TIMER_CTL.TIMER_SEL."]
pub const CLK_TIMER: Self = Self::new(0);
#[doc = "IMO - Internal Main Oscillator"]
pub const CLK_IMO: Self = Self::new(1);
#[doc = "ECO - External-Crystal Oscillator"]
pub const CLK_ECO: Self = Self::new(2);
#[doc = "Low frequency clock (ILO, WCO or ALTLF). \nSelection is done in SRSS register CLK_SELECT.LFCLK_SEL."]
pub const CLK_LF: Self = Self::new(3);
#[doc = "High frequuency clock (\'clk_hfx\')."]
pub const CLK_HF: Self = Self::new(4);
#[doc = "Peripheral clock (\'clk_peri\')."]
pub const CLK_PERI: Self = Self::new(5);
#[doc = "N/A"]
pub const RSVD_6: Self = Self::new(6);
#[doc = "N/A"]
pub const RSVD_7: Self = Self::new(7);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cnt_SPEC;
impl crate::sealed::RegSpec for Cnt_SPEC {
type DataType = u32;
}
#[doc = "Profile counter value"]
pub type Cnt = crate::RegValueT<Cnt_SPEC>;
impl Cnt {
#[doc = "This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter."]
#[inline(always)]
pub fn cnt(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Cnt_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Cnt_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cnt {
#[inline(always)]
fn default() -> Cnt {
<crate::RegValueT<Cnt_SPEC> as RegisterValue<_>>::new(0)
}
}
}