/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"GPIO port control/configuration"]
unsafe impl ::core::marker::Send for super::Gpio {}
unsafe impl ::core::marker::Sync for super::Gpio {}
impl super::Gpio {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "Interrupt port cause register 0"]
#[inline(always)]
pub const fn intr_cause0(
&self,
) -> &'static crate::common::Reg<self::IntrCause0_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrCause0_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(16384usize),
)
}
}
#[doc = "Interrupt port cause register 1"]
#[inline(always)]
pub const fn intr_cause1(
&self,
) -> &'static crate::common::Reg<self::IntrCause1_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrCause1_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(16388usize),
)
}
}
#[doc = "Interrupt port cause register 2"]
#[inline(always)]
pub const fn intr_cause2(
&self,
) -> &'static crate::common::Reg<self::IntrCause2_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrCause2_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(16392usize),
)
}
}
#[doc = "Interrupt port cause register 3"]
#[inline(always)]
pub const fn intr_cause3(
&self,
) -> &'static crate::common::Reg<self::IntrCause3_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrCause3_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(16396usize),
)
}
}
#[doc = "Extern power supply detection register"]
#[inline(always)]
pub const fn vdd_active(
&self,
) -> &'static crate::common::Reg<self::VddActive_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::VddActive_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(16400usize),
)
}
}
#[doc = "Supply detection interrupt register"]
#[inline(always)]
pub const fn vdd_intr(
&self,
) -> &'static crate::common::Reg<self::VddIntr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::VddIntr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16404usize),
)
}
}
#[doc = "Supply detection interrupt mask register"]
#[inline(always)]
pub const fn vdd_intr_mask(
&self,
) -> &'static crate::common::Reg<self::VddIntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::VddIntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16408usize),
)
}
}
#[doc = "Supply detection interrupt masked register"]
#[inline(always)]
pub const fn vdd_intr_masked(
&self,
) -> &'static crate::common::Reg<self::VddIntrMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::VddIntrMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(16412usize),
)
}
}
#[doc = "Supply detection interrupt set register"]
#[inline(always)]
pub const fn vdd_intr_set(
&self,
) -> &'static crate::common::Reg<self::VddIntrSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::VddIntrSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16416usize),
)
}
}
#[doc = "GPIO port registers"]
#[inline(always)]
pub fn prt(self) -> &'static crate::common::ClusterRegisterArray<crate::gpio::_Prt, 15, 0x80> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x0usize))
}
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrCause0_SPEC;
impl crate::sealed::RegSpec for IntrCause0_SPEC {
type DataType = u32;
}
#[doc = "Interrupt port cause register 0"]
pub type IntrCause0 = crate::RegValueT<IntrCause0_SPEC>;
impl IntrCause0 {
#[doc = "Each IO port has an associated bit field in this register. The bit field reflects the IO port\'s interrupt line (bit field i reflects \'gpio_interrupts\\[i\\]\' for IO port i). The register is used when the system uses a combined interrupt line \'gpio_interrupt\'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port\'s GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.\n\'0\': Port has no pending interrupt\n\'1\': Port has pending interrupt"]
#[inline(always)]
pub fn port_int(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
IntrCause0_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
IntrCause0_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for IntrCause0 {
#[inline(always)]
fn default() -> IntrCause0 {
<crate::RegValueT<IntrCause0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrCause1_SPEC;
impl crate::sealed::RegSpec for IntrCause1_SPEC {
type DataType = u32;
}
#[doc = "Interrupt port cause register 1"]
pub type IntrCause1 = crate::RegValueT<IntrCause1_SPEC>;
impl IntrCause1 {
#[doc = "Each IO port has an associated bit field in this register. The bit field reflects the IO port\'s interrupt line (bit field i reflects \'gpio_interrupts\\[i\\]\' for IO port i). The register is used when the system uses a combined interrupt line \'gpio_interrupt\'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port\'s GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.\n\'0\': Port has no pending interrupt\n\'1\': Port has pending interrupt"]
#[inline(always)]
pub fn port_int(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
IntrCause1_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
IntrCause1_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for IntrCause1 {
#[inline(always)]
fn default() -> IntrCause1 {
<crate::RegValueT<IntrCause1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrCause2_SPEC;
impl crate::sealed::RegSpec for IntrCause2_SPEC {
type DataType = u32;
}
#[doc = "Interrupt port cause register 2"]
pub type IntrCause2 = crate::RegValueT<IntrCause2_SPEC>;
impl IntrCause2 {
#[doc = "Each IO port has an associated bit field in this register. The bit field reflects the IO port\'s interrupt line (bit field i reflects \'gpio_interrupts\\[i\\]\' for IO port i). The register is used when the system uses a combined interrupt line \'gpio_interrupt\'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port\'s GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.\n\'0\': Port has no pending interrupt\n\'1\': Port has pending interrupt"]
#[inline(always)]
pub fn port_int(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
IntrCause2_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
IntrCause2_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for IntrCause2 {
#[inline(always)]
fn default() -> IntrCause2 {
<crate::RegValueT<IntrCause2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrCause3_SPEC;
impl crate::sealed::RegSpec for IntrCause3_SPEC {
type DataType = u32;
}
#[doc = "Interrupt port cause register 3"]
pub type IntrCause3 = crate::RegValueT<IntrCause3_SPEC>;
impl IntrCause3 {
#[doc = "Each IO port has an associated bit field in this register. The bit field reflects the IO port\'s interrupt line (bit field i reflects \'gpio_interrupts\\[i\\]\' for IO port i). The register is used when the system uses a combined interrupt line \'gpio_interrupt\'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port\'s GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.\n\'0\': Port has no pending interrupt\n\'1\': Port has pending interrupt"]
#[inline(always)]
pub fn port_int(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
IntrCause3_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
IntrCause3_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for IntrCause3 {
#[inline(always)]
fn default() -> IntrCause3 {
<crate::RegValueT<IntrCause3_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct VddActive_SPEC;
impl crate::sealed::RegSpec for VddActive_SPEC {
type DataType = u32;
}
#[doc = "Extern power supply detection register"]
pub type VddActive = crate::RegValueT<VddActive_SPEC>;
impl VddActive {
#[doc = "Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it. For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground. Any in-between voltage has an undefined result.\n\'0\': Supply is not present\n\'1\': Supply is present\n\nWhen multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation.\nFor example \'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1\' are present then they will be assigned to these bits as below:\n0: vbackup, \n1: vddio_0, \n2: vddio_1,\n3: vddio_a,\n4: vddio_r,\n5: vddusb\'"]
#[inline(always)]
pub fn vddio_active(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, VddActive_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,VddActive_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Same as VDDIO_ACTIVE for the analog supply VDDA."]
#[inline(always)]
pub fn vdda_active(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, VddActive_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<30,1,0,VddActive_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.)"]
#[inline(always)]
pub fn vddd_active(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, VddActive_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31,1,0,VddActive_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for VddActive {
#[inline(always)]
fn default() -> VddActive {
<crate::RegValueT<VddActive_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct VddIntr_SPEC;
impl crate::sealed::RegSpec for VddIntr_SPEC {
type DataType = u32;
}
#[doc = "Supply detection interrupt register"]
pub type VddIntr = crate::RegValueT<VddIntr_SPEC>;
impl VddIntr {
#[doc = "Supply state change detected.\n\'0\': No change to supply detected\n\'1\': Change to supply detected"]
#[inline(always)]
pub fn vddio_active(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, VddIntr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,VddIntr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Same as VDDIO_ACTIVE for the analog supply VDDA."]
#[inline(always)]
pub fn vdda_active(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, VddIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30, 1, 0, VddIntr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back \'1\'."]
#[inline(always)]
pub fn vddd_active(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, VddIntr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31, 1, 0, VddIntr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for VddIntr {
#[inline(always)]
fn default() -> VddIntr {
<crate::RegValueT<VddIntr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct VddIntrMask_SPEC;
impl crate::sealed::RegSpec for VddIntrMask_SPEC {
type DataType = u32;
}
#[doc = "Supply detection interrupt mask register"]
pub type VddIntrMask = crate::RegValueT<VddIntrMask_SPEC>;
impl VddIntrMask {
#[doc = "Masks supply interrupt on VDDIO.\n\'0\': VDDIO interrupt forwarding disabled\n\'1\': VDDIO interrupt forwarding enabled"]
#[inline(always)]
pub fn vddio_active(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, VddIntrMask_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,VddIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Same as VDDIO_ACTIVE for the analog supply VDDA."]
#[inline(always)]
pub fn vdda_active(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, VddIntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,VddIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Same as VDDIO_ACTIVE for the digital supply VDDD."]
#[inline(always)]
pub fn vddd_active(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, VddIntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,VddIntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for VddIntrMask {
#[inline(always)]
fn default() -> VddIntrMask {
<crate::RegValueT<VddIntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct VddIntrMasked_SPEC;
impl crate::sealed::RegSpec for VddIntrMasked_SPEC {
type DataType = u32;
}
#[doc = "Supply detection interrupt masked register"]
pub type VddIntrMasked = crate::RegValueT<VddIntrMasked_SPEC>;
impl VddIntrMasked {
#[doc = "Supply transition detected AND masked\n\'0\': Interrupt was not forwarded to CPU\n\'1\': Interrupt occurred and was forwarded to CPU"]
#[inline(always)]
pub fn vddio_active(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, VddIntrMasked_SPEC, crate::common::R>
{
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
VddIntrMasked_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "Same as VDDIO_ACTIVE for the analog supply VDDA."]
#[inline(always)]
pub fn vdda_active(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, VddIntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<30,1,0,VddIntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Same as VDDIO_ACTIVE for the digital supply VDDD."]
#[inline(always)]
pub fn vddd_active(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, VddIntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31,1,0,VddIntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for VddIntrMasked {
#[inline(always)]
fn default() -> VddIntrMasked {
<crate::RegValueT<VddIntrMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct VddIntrSet_SPEC;
impl crate::sealed::RegSpec for VddIntrSet_SPEC {
type DataType = u32;
}
#[doc = "Supply detection interrupt set register"]
pub type VddIntrSet = crate::RegValueT<VddIntrSet_SPEC>;
impl VddIntrSet {
#[doc = "Sets supply interrupt.\n\'0\': Interrupt state not affected\n\'1\': Interrupt set"]
#[inline(always)]
pub fn vddio_active(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, VddIntrSet_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,VddIntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Same as VDDIO_ACTIVE for the analog supply VDDA."]
#[inline(always)]
pub fn vdda_active(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, VddIntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,VddIntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Same as VDDIO_ACTIVE for the digital supply VDDD."]
#[inline(always)]
pub fn vddd_active(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, VddIntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,VddIntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for VddIntrSet {
#[inline(always)]
fn default() -> VddIntrSet {
<crate::RegValueT<VddIntrSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc = "GPIO port registers"]
#[non_exhaustive]
pub struct _Prt;
#[doc = "GPIO port registers"]
pub type Prt = &'static _Prt;
unsafe impl ::core::marker::Sync for _Prt {}
impl _Prt {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "Port output data register"]
#[inline(always)]
pub const fn out(&self) -> &'static crate::common::Reg<prt::Out_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::Out_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Port output data clear register"]
#[inline(always)]
pub const fn out_clr(
&self,
) -> &'static crate::common::Reg<prt::OutClr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::OutClr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "Port output data set register"]
#[inline(always)]
pub const fn out_set(
&self,
) -> &'static crate::common::Reg<prt::OutSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::OutSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(8usize),
)
}
}
#[doc = "Port output data invert register"]
#[inline(always)]
pub const fn out_inv(
&self,
) -> &'static crate::common::Reg<prt::OutInv_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::OutInv_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(12usize),
)
}
}
#[doc = "Port input state register"]
#[inline(always)]
pub const fn r#in(&self) -> &'static crate::common::Reg<prt::In_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<prt::In_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(16usize),
)
}
}
#[doc = "Port interrupt status register"]
#[inline(always)]
pub const fn intr(&self) -> &'static crate::common::Reg<prt::Intr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::Intr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(20usize),
)
}
}
#[doc = "Port interrupt mask register"]
#[inline(always)]
pub const fn intr_mask(
&self,
) -> &'static crate::common::Reg<prt::IntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::IntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(24usize),
)
}
}
#[doc = "Port interrupt masked status register"]
#[inline(always)]
pub const fn intr_masked(
&self,
) -> &'static crate::common::Reg<prt::IntrMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<prt::IntrMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(28usize),
)
}
}
#[doc = "Port interrupt set register"]
#[inline(always)]
pub const fn intr_set(
&self,
) -> &'static crate::common::Reg<prt::IntrSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::IntrSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "Port interrupt configuration register"]
#[inline(always)]
pub const fn intr_cfg(
&self,
) -> &'static crate::common::Reg<prt::IntrCfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::IntrCfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
#[doc = "Port configuration register"]
#[inline(always)]
pub const fn cfg(&self) -> &'static crate::common::Reg<prt::Cfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::Cfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(40usize),
)
}
}
#[doc = "Port input buffer configuration register"]
#[inline(always)]
pub const fn cfg_in(&self) -> &'static crate::common::Reg<prt::CfgIn_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::CfgIn_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(44usize),
)
}
}
#[doc = "Port output buffer configuration register"]
#[inline(always)]
pub const fn cfg_out(
&self,
) -> &'static crate::common::Reg<prt::CfgOut_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::CfgOut_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(48usize),
)
}
}
#[doc = "Port SIO configuration register"]
#[inline(always)]
pub const fn cfg_sio(
&self,
) -> &'static crate::common::Reg<prt::CfgSio_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::CfgSio_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(52usize),
)
}
}
#[doc = "Port GPIO5V input buffer configuration register"]
#[inline(always)]
pub const fn cfg_in_gpio5v(
&self,
) -> &'static crate::common::Reg<prt::CfgInGpio5V_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<prt::CfgInGpio5V_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(60usize),
)
}
}
}
pub mod prt {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Out_SPEC;
impl crate::sealed::RegSpec for Out_SPEC {
type DataType = u32;
}
#[doc = "Port output data register"]
pub type Out = crate::RegValueT<Out_SPEC>;
impl Out {
#[doc = "IO output data for pin 0\n\'0\': Output state set to \'0\'\n\'1\': Output state set to \'1\'"]
#[inline(always)]
pub fn out0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Out_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Out_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "IO output data for pin 1"]
#[inline(always)]
pub fn out1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Out_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Out_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "IO output data for pin 2"]
#[inline(always)]
pub fn out2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, Out_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, Out_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "IO output data for pin 3"]
#[inline(always)]
pub fn out3(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Out_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, Out_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "IO output data for pin 4"]
#[inline(always)]
pub fn out4(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Out_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, Out_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "IO output data for pin 5"]
#[inline(always)]
pub fn out5(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Out_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, Out_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "IO output data for pin 6"]
#[inline(always)]
pub fn out6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, Out_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, Out_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "IO output data for pin 7"]
#[inline(always)]
pub fn out7(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Out_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7, 1, 0, Out_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Out {
#[inline(always)]
fn default() -> Out {
<crate::RegValueT<Out_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct OutClr_SPEC;
impl crate::sealed::RegSpec for OutClr_SPEC {
type DataType = u32;
}
#[doc = "Port output data clear register"]
pub type OutClr = crate::RegValueT<OutClr_SPEC>;
impl OutClr {
#[doc = "IO clear output for pin 0:\n\'0\': Output state not affected.\n\'1\': Output state set to \'0\'."]
#[inline(always)]
pub fn out0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, OutClr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,OutClr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO clear output for pin 1"]
#[inline(always)]
pub fn out1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, OutClr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,OutClr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO clear output for pin 2"]
#[inline(always)]
pub fn out2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, OutClr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,OutClr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO clear output for pin 3"]
#[inline(always)]
pub fn out3(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, OutClr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,OutClr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO clear output for pin 4"]
#[inline(always)]
pub fn out4(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, OutClr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,OutClr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO clear output for pin 5"]
#[inline(always)]
pub fn out5(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, OutClr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,OutClr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO clear output for pin 6"]
#[inline(always)]
pub fn out6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, OutClr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,OutClr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO clear output for pin 7"]
#[inline(always)]
pub fn out7(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, OutClr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,OutClr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for OutClr {
#[inline(always)]
fn default() -> OutClr {
<crate::RegValueT<OutClr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct OutSet_SPEC;
impl crate::sealed::RegSpec for OutSet_SPEC {
type DataType = u32;
}
#[doc = "Port output data set register"]
pub type OutSet = crate::RegValueT<OutSet_SPEC>;
impl OutSet {
#[doc = "IO set output for pin 0:\n\'0\': Output state not affected.\n\'1\': Output state set to \'1\'."]
#[inline(always)]
pub fn out0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, OutSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,OutSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO set output for pin 1"]
#[inline(always)]
pub fn out1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, OutSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,OutSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO set output for pin 2"]
#[inline(always)]
pub fn out2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, OutSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,OutSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO set output for pin 3"]
#[inline(always)]
pub fn out3(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, OutSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,OutSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO set output for pin 4"]
#[inline(always)]
pub fn out4(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, OutSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,OutSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO set output for pin 5"]
#[inline(always)]
pub fn out5(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, OutSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,OutSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO set output for pin 6"]
#[inline(always)]
pub fn out6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, OutSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,OutSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO set output for pin 7"]
#[inline(always)]
pub fn out7(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, OutSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,OutSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for OutSet {
#[inline(always)]
fn default() -> OutSet {
<crate::RegValueT<OutSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct OutInv_SPEC;
impl crate::sealed::RegSpec for OutInv_SPEC {
type DataType = u32;
}
#[doc = "Port output data invert register"]
pub type OutInv = crate::RegValueT<OutInv_SPEC>;
impl OutInv {
#[doc = "IO invert output for pin 0:\n\'0\': Output state not affected.\n\'1\': Output state inverted (\'0\' => \'1\', \'1\' => \'0\')."]
#[inline(always)]
pub fn out0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, OutInv_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,OutInv_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO invert output for pin 1"]
#[inline(always)]
pub fn out1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, OutInv_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,OutInv_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO invert output for pin 2"]
#[inline(always)]
pub fn out2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, OutInv_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,OutInv_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO invert output for pin 3"]
#[inline(always)]
pub fn out3(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, OutInv_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,OutInv_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO invert output for pin 4"]
#[inline(always)]
pub fn out4(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, OutInv_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,OutInv_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO invert output for pin 5"]
#[inline(always)]
pub fn out5(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, OutInv_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,OutInv_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO invert output for pin 6"]
#[inline(always)]
pub fn out6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, OutInv_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,OutInv_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "IO invert output for pin 7"]
#[inline(always)]
pub fn out7(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, OutInv_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,OutInv_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for OutInv {
#[inline(always)]
fn default() -> OutInv {
<crate::RegValueT<OutInv_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct In_SPEC;
impl crate::sealed::RegSpec for In_SPEC {
type DataType = u32;
}
#[doc = "Port input state register"]
pub type In = crate::RegValueT<In_SPEC>;
impl In {
#[doc = "IO pin state for pin 0\n\'0\': Low logic level present on pin.\n\'1\': High logic level present on pin.\nOn reset assertion , IN register will get reset. The Pad value takes 2 clock cycles to be reflected into IN Register. It\'s value then depends on the external pin value."]
#[inline(always)]
pub fn in0(self) -> crate::common::RegisterFieldBool<0, 1, 0, In_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, In_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "IO pin state for pin 1"]
#[inline(always)]
pub fn in1(self) -> crate::common::RegisterFieldBool<1, 1, 0, In_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1, 1, 0, In_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "IO pin state for pin 2"]
#[inline(always)]
pub fn in2(self) -> crate::common::RegisterFieldBool<2, 1, 0, In_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2, 1, 0, In_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "IO pin state for pin 3"]
#[inline(always)]
pub fn in3(self) -> crate::common::RegisterFieldBool<3, 1, 0, In_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3, 1, 0, In_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "IO pin state for pin 4"]
#[inline(always)]
pub fn in4(self) -> crate::common::RegisterFieldBool<4, 1, 0, In_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4, 1, 0, In_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "IO pin state for pin 5"]
#[inline(always)]
pub fn in5(self) -> crate::common::RegisterFieldBool<5, 1, 0, In_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5, 1, 0, In_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "IO pin state for pin 6"]
#[inline(always)]
pub fn in6(self) -> crate::common::RegisterFieldBool<6, 1, 0, In_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<6, 1, 0, In_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "IO pin state for pin 7"]
#[inline(always)]
pub fn in7(self) -> crate::common::RegisterFieldBool<7, 1, 0, In_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<7, 1, 0, In_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register."]
#[inline(always)]
pub fn flt_in(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, In_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8, 1, 0, In_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for In {
#[inline(always)]
fn default() -> In {
<crate::RegValueT<In_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Intr_SPEC;
impl crate::sealed::RegSpec for Intr_SPEC {
type DataType = u32;
}
#[doc = "Port interrupt status register"]
pub type Intr = crate::RegValueT<Intr_SPEC>;
impl Intr {
#[doc = "Edge detect for IO pin 0\n\'0\': No edge was detected on pin.\n\'1\': An edge was detected on pin."]
#[inline(always)]
pub fn edge0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Edge detect for IO pin 1"]
#[inline(always)]
pub fn edge1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Edge detect for IO pin 2"]
#[inline(always)]
pub fn edge2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Edge detect for IO pin 3"]
#[inline(always)]
pub fn edge3(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Edge detect for IO pin 4"]
#[inline(always)]
pub fn edge4(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Edge detect for IO pin 5"]
#[inline(always)]
pub fn edge5(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Edge detect for IO pin 6"]
#[inline(always)]
pub fn edge6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Edge detect for IO pin 7"]
#[inline(always)]
pub fn edge7(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Edge detected on filtered pin selected by INTR_CFG.FLT_SEL"]
#[inline(always)]
pub fn flt_edge(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "IO pin state for pin 0"]
#[inline(always)]
pub fn in_in0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Intr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16, 1, 0, Intr_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "IO pin state for pin 1"]
#[inline(always)]
pub fn in_in1(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, Intr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<17, 1, 0, Intr_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "IO pin state for pin 2"]
#[inline(always)]
pub fn in_in2(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, Intr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<18, 1, 0, Intr_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "IO pin state for pin 3"]
#[inline(always)]
pub fn in_in3(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, Intr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<19, 1, 0, Intr_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "IO pin state for pin 4"]
#[inline(always)]
pub fn in_in4(
self,
) -> crate::common::RegisterFieldBool<20, 1, 0, Intr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<20, 1, 0, Intr_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "IO pin state for pin 5"]
#[inline(always)]
pub fn in_in5(
self,
) -> crate::common::RegisterFieldBool<21, 1, 0, Intr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<21, 1, 0, Intr_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "IO pin state for pin 6"]
#[inline(always)]
pub fn in_in6(
self,
) -> crate::common::RegisterFieldBool<22, 1, 0, Intr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<22, 1, 0, Intr_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "IO pin state for pin 7"]
#[inline(always)]
pub fn in_in7(
self,
) -> crate::common::RegisterFieldBool<23, 1, 0, Intr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<23, 1, 0, Intr_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Filtered pin state for pin selected by INTR_CFG.FLT_SEL"]
#[inline(always)]
pub fn flt_in_in(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, Intr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<24, 1, 0, Intr_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Intr {
#[inline(always)]
fn default() -> Intr {
<crate::RegValueT<Intr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMask_SPEC;
impl crate::sealed::RegSpec for IntrMask_SPEC {
type DataType = u32;
}
#[doc = "Port interrupt mask register"]
pub type IntrMask = crate::RegValueT<IntrMask_SPEC>;
impl IntrMask {
#[doc = "Masks edge interrupt on IO pin 0\n\'0\': Pin interrupt forwarding disabled\n\'1\': Pin interrupt forwarding enabled"]
#[inline(always)]
pub fn edge0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Masks edge interrupt on IO pin 1"]
#[inline(always)]
pub fn edge1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Masks edge interrupt on IO pin 2"]
#[inline(always)]
pub fn edge2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Masks edge interrupt on IO pin 3"]
#[inline(always)]
pub fn edge3(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Masks edge interrupt on IO pin 4"]
#[inline(always)]
pub fn edge4(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Masks edge interrupt on IO pin 5"]
#[inline(always)]
pub fn edge5(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Masks edge interrupt on IO pin 6"]
#[inline(always)]
pub fn edge6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Masks edge interrupt on IO pin 7"]
#[inline(always)]
pub fn edge7(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL"]
#[inline(always)]
pub fn flt_edge(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMask {
#[inline(always)]
fn default() -> IntrMask {
<crate::RegValueT<IntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMasked_SPEC;
impl crate::sealed::RegSpec for IntrMasked_SPEC {
type DataType = u32;
}
#[doc = "Port interrupt masked status register"]
pub type IntrMasked = crate::RegValueT<IntrMasked_SPEC>;
impl IntrMasked {
#[doc = "Edge detected AND masked on IO pin 0\n\'0\': Interrupt was not forwarded to CPU\n\'1\': Interrupt occurred and was forwarded to CPU"]
#[inline(always)]
pub fn edge0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Edge detected and masked on IO pin 1"]
#[inline(always)]
pub fn edge1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Edge detected and masked on IO pin 2"]
#[inline(always)]
pub fn edge2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Edge detected and masked on IO pin 3"]
#[inline(always)]
pub fn edge3(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Edge detected and masked on IO pin 4"]
#[inline(always)]
pub fn edge4(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Edge detected and masked on IO pin 5"]
#[inline(always)]
pub fn edge5(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Edge detected and masked on IO pin 6"]
#[inline(always)]
pub fn edge6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<6,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Edge detected and masked on IO pin 7"]
#[inline(always)]
pub fn edge7(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<7,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL"]
#[inline(always)]
pub fn flt_edge(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMasked {
#[inline(always)]
fn default() -> IntrMasked {
<crate::RegValueT<IntrMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSet_SPEC;
impl crate::sealed::RegSpec for IntrSet_SPEC {
type DataType = u32;
}
#[doc = "Port interrupt set register"]
pub type IntrSet = crate::RegValueT<IntrSet_SPEC>;
impl IntrSet {
#[doc = "Sets edge detect interrupt for IO pin 0\n\'0\': Interrupt state not affected\n\'1\': Interrupt set"]
#[inline(always)]
pub fn edge0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets edge detect interrupt for IO pin 1"]
#[inline(always)]
pub fn edge1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets edge detect interrupt for IO pin 2"]
#[inline(always)]
pub fn edge2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets edge detect interrupt for IO pin 3"]
#[inline(always)]
pub fn edge3(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets edge detect interrupt for IO pin 4"]
#[inline(always)]
pub fn edge4(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets edge detect interrupt for IO pin 5"]
#[inline(always)]
pub fn edge5(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets edge detect interrupt for IO pin 6"]
#[inline(always)]
pub fn edge6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets edge detect interrupt for IO pin 7"]
#[inline(always)]
pub fn edge7(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL"]
#[inline(always)]
pub fn flt_edge(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrSet {
#[inline(always)]
fn default() -> IntrSet {
<crate::RegValueT<IntrSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrCfg_SPEC;
impl crate::sealed::RegSpec for IntrCfg_SPEC {
type DataType = u32;
}
#[doc = "Port interrupt configuration register"]
pub type IntrCfg = crate::RegValueT<IntrCfg_SPEC>;
impl IntrCfg {
#[doc = "Sets which edge will trigger an IRQ for IO pin 0"]
#[inline(always)]
pub fn edge0_sel(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
intr_cfg::Edge0Sel,
intr_cfg::Edge0Sel,
IntrCfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
intr_cfg::Edge0Sel,
intr_cfg::Edge0Sel,
IntrCfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Sets which edge will trigger an IRQ for IO pin 1"]
#[inline(always)]
pub fn edge1_sel(
self,
) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, IntrCfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<2,0x3,1,0,u8,u8,IntrCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets which edge will trigger an IRQ for IO pin 2"]
#[inline(always)]
pub fn edge2_sel(
self,
) -> crate::common::RegisterField<4, 0x3, 1, 0, u8, u8, IntrCfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0x3,1,0,u8,u8,IntrCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets which edge will trigger an IRQ for IO pin 3"]
#[inline(always)]
pub fn edge3_sel(
self,
) -> crate::common::RegisterField<6, 0x3, 1, 0, u8, u8, IntrCfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<6,0x3,1,0,u8,u8,IntrCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets which edge will trigger an IRQ for IO pin 4"]
#[inline(always)]
pub fn edge4_sel(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, IntrCfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,IntrCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets which edge will trigger an IRQ for IO pin 5"]
#[inline(always)]
pub fn edge5_sel(
self,
) -> crate::common::RegisterField<10, 0x3, 1, 0, u8, u8, IntrCfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<10,0x3,1,0,u8,u8,IntrCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets which edge will trigger an IRQ for IO pin 6"]
#[inline(always)]
pub fn edge6_sel(
self,
) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, IntrCfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<12,0x3,1,0,u8,u8,IntrCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets which edge will trigger an IRQ for IO pin 7"]
#[inline(always)]
pub fn edge7_sel(
self,
) -> crate::common::RegisterField<14, 0x3, 1, 0, u8, u8, IntrCfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<14,0x3,1,0,u8,u8,IntrCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL"]
#[inline(always)]
pub fn flt_edge_sel(
self,
) -> crate::common::RegisterField<
16,
0x3,
1,
0,
intr_cfg::FltEdgeSel,
intr_cfg::FltEdgeSel,
IntrCfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0x3,
1,
0,
intr_cfg::FltEdgeSel,
intr_cfg::FltEdgeSel,
IntrCfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt."]
#[inline(always)]
pub fn flt_sel(
self,
) -> crate::common::RegisterField<18, 0x7, 1, 0, u8, u8, IntrCfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<18,0x7,1,0,u8,u8,IntrCfg_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrCfg {
#[inline(always)]
fn default() -> IntrCfg {
<crate::RegValueT<IntrCfg_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod intr_cfg {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Edge0Sel_SPEC;
pub type Edge0Sel = crate::EnumBitfieldStruct<u8, Edge0Sel_SPEC>;
impl Edge0Sel {
#[doc = "Disabled"]
pub const DISABLE: Self = Self::new(0);
#[doc = "Rising edge"]
pub const RISING: Self = Self::new(1);
#[doc = "Falling edge"]
pub const FALLING: Self = Self::new(2);
#[doc = "Both rising and falling edges"]
pub const BOTH: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct FltEdgeSel_SPEC;
pub type FltEdgeSel = crate::EnumBitfieldStruct<u8, FltEdgeSel_SPEC>;
impl FltEdgeSel {
#[doc = "Disabled"]
pub const DISABLE: Self = Self::new(0);
#[doc = "Rising edge"]
pub const RISING: Self = Self::new(1);
#[doc = "Falling edge"]
pub const FALLING: Self = Self::new(2);
#[doc = "Both rising and falling edges"]
pub const BOTH: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cfg_SPEC;
impl crate::sealed::RegSpec for Cfg_SPEC {
type DataType = u32;
}
#[doc = "Port configuration register"]
pub type Cfg = crate::RegValueT<Cfg_SPEC>;
impl Cfg {
#[doc = "The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode.\nNote: when initializing IO\'s that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus.\nNote: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF=\'0\'). \nNote: D_OUT, D_OUT_EN are pins of GPIO cell."]
#[inline(always)]
pub fn drive_mode0(
self,
) -> crate::common::RegisterField<
0,
0x7,
1,
0,
cfg::DriveMode0,
cfg::DriveMode0,
Cfg_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x7,
1,
0,
cfg::DriveMode0,
cfg::DriveMode0,
Cfg_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue.\n\'0\': Input buffer disabled\n\'1\': Input buffer enabled"]
#[inline(always)]
pub fn in_en0(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, Cfg_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "The GPIO drive mode for IO pin 1"]
#[inline(always)]
pub fn drive_mode1(
self,
) -> crate::common::RegisterField<4, 0x7, 1, 0, u8, u8, Cfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<4,0x7,1,0,u8,u8,Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables the input buffer for IO pin 1"]
#[inline(always)]
pub fn in_en1(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7, 1, 0, Cfg_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "The GPIO drive mode for IO pin 2"]
#[inline(always)]
pub fn drive_mode2(
self,
) -> crate::common::RegisterField<8, 0x7, 1, 0, u8, u8, Cfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x7,1,0,u8,u8,Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables the input buffer for IO pin 2"]
#[inline(always)]
pub fn in_en2(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11, 1, 0, Cfg_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "The GPIO drive mode for IO pin 3"]
#[inline(always)]
pub fn drive_mode3(
self,
) -> crate::common::RegisterField<12, 0x7, 1, 0, u8, u8, Cfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<12,0x7,1,0,u8,u8,Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables the input buffer for IO pin 3"]
#[inline(always)]
pub fn in_en3(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<15, 1, 0, Cfg_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "The GPIO drive mode for IO pin4"]
#[inline(always)]
pub fn drive_mode4(
self,
) -> crate::common::RegisterField<16, 0x7, 1, 0, u8, u8, Cfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x7,1,0,u8,u8,Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables the input buffer for IO pin 4"]
#[inline(always)]
pub fn in_en4(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19, 1, 0, Cfg_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "The GPIO drive mode for IO pin 5"]
#[inline(always)]
pub fn drive_mode5(
self,
) -> crate::common::RegisterField<20, 0x7, 1, 0, u8, u8, Cfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<20,0x7,1,0,u8,u8,Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables the input buffer for IO pin 5"]
#[inline(always)]
pub fn in_en5(
self,
) -> crate::common::RegisterFieldBool<23, 1, 0, Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<23, 1, 0, Cfg_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "The GPIO drive mode for IO pin 6"]
#[inline(always)]
pub fn drive_mode6(
self,
) -> crate::common::RegisterField<24, 0x7, 1, 0, u8, u8, Cfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0x7,1,0,u8,u8,Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables the input buffer for IO pin 6"]
#[inline(always)]
pub fn in_en6(
self,
) -> crate::common::RegisterFieldBool<27, 1, 0, Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<27, 1, 0, Cfg_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "The GPIO drive mode for IO pin 7"]
#[inline(always)]
pub fn drive_mode7(
self,
) -> crate::common::RegisterField<28, 0x7, 1, 0, u8, u8, Cfg_SPEC, crate::common::RW>
{
crate::common::RegisterField::<28,0x7,1,0,u8,u8,Cfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables the input buffer for IO pin 7"]
#[inline(always)]
pub fn in_en7(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Cfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31, 1, 0, Cfg_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Cfg {
#[inline(always)]
fn default() -> Cfg {
<crate::RegValueT<Cfg_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod cfg {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DriveMode0_SPEC;
pub type DriveMode0 = crate::EnumBitfieldStruct<u8, DriveMode0_SPEC>;
impl DriveMode0 {
#[doc = "Output buffer is off creating a high impedance input\nD_OUT = \'0\': High Impedance\nD_OUT = \'1\': High Impedance"]
pub const HIGHZ: Self = Self::new(0);
#[doc = "N/A"]
pub const RSVD: Self = Self::new(1);
#[doc = "Resistive pull up"]
pub const PULLUP: Self = Self::new(2);
#[doc = "Resistive pull down"]
pub const PULLDOWN: Self = Self::new(3);
#[doc = "Open drain, drives low"]
pub const OD_DRIVESLOW: Self = Self::new(4);
#[doc = "Open drain, drives high"]
pub const OD_DRIVESHIGH: Self = Self::new(5);
#[doc = "Strong D_OUTput buffer"]
pub const STRONG: Self = Self::new(6);
#[doc = "Pull up or pull down"]
pub const PULLUP_DOWN: Self = Self::new(7);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CfgIn_SPEC;
impl crate::sealed::RegSpec for CfgIn_SPEC {
type DataType = u32;
}
#[doc = "Port input buffer configuration register"]
pub type CfgIn = crate::RegValueT<CfgIn_SPEC>;
impl CfgIn {
#[doc = "N/A"]
#[inline(always)]
pub fn vtrip_sel0_0(
self,
) -> crate::common::RegisterField<
0,
0x1,
1,
0,
cfg_in::VtripSel00,
cfg_in::VtripSel00,
CfgIn_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1,
1,
0,
cfg_in::VtripSel00,
cfg_in::VtripSel00,
CfgIn_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vtrip_sel1_0(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, CfgIn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,CfgIn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vtrip_sel2_0(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, CfgIn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,CfgIn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vtrip_sel3_0(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, CfgIn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,CfgIn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vtrip_sel4_0(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, CfgIn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,CfgIn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vtrip_sel5_0(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, CfgIn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,CfgIn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vtrip_sel6_0(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, CfgIn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,CfgIn_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vtrip_sel7_0(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, CfgIn_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,CfgIn_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CfgIn {
#[inline(always)]
fn default() -> CfgIn {
<crate::RegValueT<CfgIn_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod cfg_in {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct VtripSel00_SPEC;
pub type VtripSel00 = crate::EnumBitfieldStruct<u8, VtripSel00_SPEC>;
impl VtripSel00 {
#[doc = "S40S: Input buffer compatible with CMOS and I2C interfaces"]
pub const CMOS: Self = Self::new(0);
#[doc = "S40S: Input buffer compatible with TTL and MediaLB interfaces"]
pub const TTL: Self = Self::new(1);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CfgOut_SPEC;
impl crate::sealed::RegSpec for CfgOut_SPEC {
type DataType = u32;
}
#[doc = "Port output buffer configuration register"]
pub type CfgOut = crate::RegValueT<CfgOut_SPEC>;
impl CfgOut {
#[doc = "Enables slow slew rate for IO pin 0\n\'0\': Fast slew rate\n\'1\': Slow slew rate"]
#[inline(always)]
pub fn slow0(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, CfgOut_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,CfgOut_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables slow slew rate for IO pin 1"]
#[inline(always)]
pub fn slow1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, CfgOut_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,CfgOut_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables slow slew rate for IO pin 2"]
#[inline(always)]
pub fn slow2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, CfgOut_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,CfgOut_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables slow slew rate for IO pin 3"]
#[inline(always)]
pub fn slow3(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, CfgOut_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,CfgOut_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables slow slew rate for IO pin 4"]
#[inline(always)]
pub fn slow4(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, CfgOut_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,CfgOut_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables slow slew rate for IO pin 5"]
#[inline(always)]
pub fn slow5(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, CfgOut_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,CfgOut_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables slow slew rate for IO pin 6"]
#[inline(always)]
pub fn slow6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, CfgOut_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,CfgOut_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enables slow slew rate for IO pin 7"]
#[inline(always)]
pub fn slow7(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, CfgOut_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,CfgOut_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets the GPIO drive strength for IO pin 0"]
#[inline(always)]
pub fn drive_sel0(
self,
) -> crate::common::RegisterField<
16,
0x3,
1,
0,
cfg_out::DriveSel0,
cfg_out::DriveSel0,
CfgOut_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0x3,
1,
0,
cfg_out::DriveSel0,
cfg_out::DriveSel0,
CfgOut_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Sets the GPIO drive strength for IO pin 1"]
#[inline(always)]
pub fn drive_sel1(
self,
) -> crate::common::RegisterField<18, 0x3, 1, 0, u8, u8, CfgOut_SPEC, crate::common::RW>
{
crate::common::RegisterField::<18,0x3,1,0,u8,u8,CfgOut_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets the GPIO drive strength for IO pin 2"]
#[inline(always)]
pub fn drive_sel2(
self,
) -> crate::common::RegisterField<20, 0x3, 1, 0, u8, u8, CfgOut_SPEC, crate::common::RW>
{
crate::common::RegisterField::<20,0x3,1,0,u8,u8,CfgOut_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets the GPIO drive strength for IO pin 3"]
#[inline(always)]
pub fn drive_sel3(
self,
) -> crate::common::RegisterField<22, 0x3, 1, 0, u8, u8, CfgOut_SPEC, crate::common::RW>
{
crate::common::RegisterField::<22,0x3,1,0,u8,u8,CfgOut_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets the GPIO drive strength for IO pin 4"]
#[inline(always)]
pub fn drive_sel4(
self,
) -> crate::common::RegisterField<24, 0x3, 1, 0, u8, u8, CfgOut_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0x3,1,0,u8,u8,CfgOut_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets the GPIO drive strength for IO pin 5"]
#[inline(always)]
pub fn drive_sel5(
self,
) -> crate::common::RegisterField<26, 0x3, 1, 0, u8, u8, CfgOut_SPEC, crate::common::RW>
{
crate::common::RegisterField::<26,0x3,1,0,u8,u8,CfgOut_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets the GPIO drive strength for IO pin 6"]
#[inline(always)]
pub fn drive_sel6(
self,
) -> crate::common::RegisterField<28, 0x3, 1, 0, u8, u8, CfgOut_SPEC, crate::common::RW>
{
crate::common::RegisterField::<28,0x3,1,0,u8,u8,CfgOut_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sets the GPIO drive strength for IO pin 7"]
#[inline(always)]
pub fn drive_sel7(
self,
) -> crate::common::RegisterField<30, 0x3, 1, 0, u8, u8, CfgOut_SPEC, crate::common::RW>
{
crate::common::RegisterField::<30,0x3,1,0,u8,u8,CfgOut_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CfgOut {
#[inline(always)]
fn default() -> CfgOut {
<crate::RegValueT<CfgOut_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod cfg_out {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct DriveSel0_SPEC;
pub type DriveSel0 = crate::EnumBitfieldStruct<u8, DriveSel0_SPEC>;
impl DriveSel0 {
#[doc = "Full drive strength: GPIO drives current at its max rated spec."]
pub const FULL_DRIVE: Self = Self::new(0);
#[doc = "1/2 drive strength: GPIO drives current at 1/2 of its max rated spec"]
pub const ONE_HALF_DRIVE: Self = Self::new(1);
#[doc = "1/4 drive strength: GPIO drives current at 1/4 of its max rated spec."]
pub const ONE_QUARTER_DRIVE: Self = Self::new(2);
#[doc = "1/8 drive strength: GPIO drives current at 1/8 of its max rated spec."]
pub const ONE_EIGHTH_DRIVE: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CfgSio_SPEC;
impl crate::sealed::RegSpec for CfgSio_SPEC {
type DataType = u32;
}
#[doc = "Port SIO configuration register"]
pub type CfgSio = crate::RegValueT<CfgSio_SPEC>;
impl CfgSio {
#[doc = "The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = \'5\') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used."]
#[inline(always)]
pub fn vreg_en01(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, CfgSio_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn ibuf_sel01(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, CfgSio_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vtrip_sel01(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, CfgSio_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vref_sel01(
self,
) -> crate::common::RegisterField<3, 0x3, 1, 0, u8, u8, CfgSio_SPEC, crate::common::RW>
{
crate::common::RegisterField::<3,0x3,1,0,u8,u8,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = \'0\'):\n0: input buffer functions as a CMOS input buffer.\n1: input buffer functions as a LVTTL input buffer.\nIn differential input buffer mode (IBUF01_SEL = \'1\'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio\nb) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered)\nc) VREF_SEL=01, VOH_SEL=\\[1-7\\] -> Input buffer functions as CMOS input buffer. \nd) VREF_SEL=10/11, VOH_SEL=000 -> Trip point=Amuxbus_a/b (buffered)\ne) VREF_SEL=10/11, VOH_SEL=\\[1-7\\] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio\nb) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref\nc) VREF_SEL=01, VOH_SEL=\\[1-7\\] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip point=0.5*Amuxbus_a/b (buffered)\ne) VREF_SEL=10/11, VOH_SEL=\\[1-7\\] -> Input buffer functions as LVTTL input buffer."]
#[inline(always)]
pub fn voh_sel01(
self,
) -> crate::common::RegisterField<5, 0x7, 1, 0, u8, u8, CfgSio_SPEC, crate::common::RW>
{
crate::common::RegisterField::<5,0x7,1,0,u8,u8,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vreg_en23(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, CfgSio_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn ibuf_sel23(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, CfgSio_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vtrip_sel23(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, CfgSio_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vref_sel23(
self,
) -> crate::common::RegisterField<11, 0x3, 1, 0, u8, u8, CfgSio_SPEC, crate::common::RW>
{
crate::common::RegisterField::<11,0x3,1,0,u8,u8,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn voh_sel23(
self,
) -> crate::common::RegisterField<13, 0x7, 1, 0, u8, u8, CfgSio_SPEC, crate::common::RW>
{
crate::common::RegisterField::<13,0x7,1,0,u8,u8,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vreg_en45(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, CfgSio_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn ibuf_sel45(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, CfgSio_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vtrip_sel45(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, CfgSio_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vref_sel45(
self,
) -> crate::common::RegisterField<19, 0x3, 1, 0, u8, u8, CfgSio_SPEC, crate::common::RW>
{
crate::common::RegisterField::<19,0x3,1,0,u8,u8,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn voh_sel45(
self,
) -> crate::common::RegisterField<21, 0x7, 1, 0, u8, u8, CfgSio_SPEC, crate::common::RW>
{
crate::common::RegisterField::<21,0x7,1,0,u8,u8,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vreg_en67(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, CfgSio_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn ibuf_sel67(
self,
) -> crate::common::RegisterFieldBool<25, 1, 0, CfgSio_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<25,1,0,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vtrip_sel67(
self,
) -> crate::common::RegisterFieldBool<26, 1, 0, CfgSio_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<26,1,0,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn vref_sel67(
self,
) -> crate::common::RegisterField<27, 0x3, 1, 0, u8, u8, CfgSio_SPEC, crate::common::RW>
{
crate::common::RegisterField::<27,0x3,1,0,u8,u8,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn voh_sel67(
self,
) -> crate::common::RegisterField<29, 0x7, 1, 0, u8, u8, CfgSio_SPEC, crate::common::RW>
{
crate::common::RegisterField::<29,0x7,1,0,u8,u8,CfgSio_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CfgSio {
#[inline(always)]
fn default() -> CfgSio {
<crate::RegValueT<CfgSio_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CfgInGpio5V_SPEC;
impl crate::sealed::RegSpec for CfgInGpio5V_SPEC {
type DataType = u32;
}
#[doc = "Port GPIO5V input buffer configuration register"]
pub type CfgInGpio5V = crate::RegValueT<CfgInGpio5V_SPEC>;
impl CfgInGpio5V {
#[doc = "Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field.\n0: input buffer is not compatible with automotive.\n1: input buffer is compatible with automotive.\n\nUse CFG_IN.VTRIP_SEL0_0 fields set as CMOS only when this bit needs to be set."]
#[inline(always)]
pub fn vtrip_sel0_1(
self,
) -> crate::common::RegisterField<
0,
0x1,
1,
0,
cfg_in_gpio5v::VtripSel01,
cfg_in_gpio5v::VtripSel01,
CfgInGpio5V_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x1,
1,
0,
cfg_in_gpio5v::VtripSel01,
cfg_in_gpio5v::VtripSel01,
CfgInGpio5V_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Input buffer compatible with automotive (elevated Vil) interfaces."]
#[inline(always)]
pub fn vtrip_sel1_1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, CfgInGpio5V_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,CfgInGpio5V_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Input buffer compatible with automotive (elevated Vil) interfaces."]
#[inline(always)]
pub fn vtrip_sel2_1(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, CfgInGpio5V_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,CfgInGpio5V_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Input buffer compatible with automotive (elevated Vil) interfaces."]
#[inline(always)]
pub fn vtrip_sel3_1(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, CfgInGpio5V_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,CfgInGpio5V_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Input buffer compatible with automotive (elevated Vil) interfaces."]
#[inline(always)]
pub fn vtrip_sel4_1(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, CfgInGpio5V_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,CfgInGpio5V_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Input buffer compatible with automotive (elevated Vil) interfaces."]
#[inline(always)]
pub fn vtrip_sel5_1(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, CfgInGpio5V_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,CfgInGpio5V_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Input buffer compatible with automotive (elevated Vil) interfaces."]
#[inline(always)]
pub fn vtrip_sel6_1(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, CfgInGpio5V_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,CfgInGpio5V_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Input buffer compatible with automotive (elevated Vil) interfaces."]
#[inline(always)]
pub fn vtrip_sel7_1(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, CfgInGpio5V_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<7,1,0,CfgInGpio5V_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CfgInGpio5V {
#[inline(always)]
fn default() -> CfgInGpio5V {
<crate::RegValueT<CfgInGpio5V_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod cfg_in_gpio5v {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct VtripSel01_SPEC;
pub type VtripSel01 = crate::EnumBitfieldStruct<u8, VtripSel01_SPEC>;
impl VtripSel01 {
#[doc = "Input buffer not compatible with automotive (elevated Vil) interfaces."]
pub const DISABLE: Self = Self::new(0);
#[doc = "Input buffer compatible with automotive (elevated Vil) interfaces."]
pub const AUTO: Self = Self::new(1);
}
}
}