mtb_pac_psoc6_01 0.1.1

/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)

    or an affiliate of Cypress Semiconductor Corporation.



    SPDX-License-Identifier: Apache-2.0



    Licensed under the Apache License, Version 2.0 (the "License");

    you may not use this file except in compliance with the License.

    You may obtain a copy of the License at



      http://www.apache.org/licenses/LICENSE-2.0



    Unless required by applicable law or agreed to in writing, software

    distributed under the License is distributed on an "AS IS" BASIS,

    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

    See the License for the specific language governing permissions and

    limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000

#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"High Speed IO Matrix (HSIOM)"]
unsafe impl ::core::marker::Send for super::Hsiom {}
unsafe impl ::core::marker::Sync for super::Hsiom {}
impl super::Hsiom {
    #[allow(unused)]
    #[inline(always)]
    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
        self.ptr
    }

    #[doc = "AMUX splitter cell control"]
    #[inline(always)]
    pub const fn amux_split_ctl(
        &self,
    ) -> &'static crate::common::ClusterRegisterArray<
        crate::common::Reg<self::AmuxSplitCtl_SPEC, crate::common::RW>,
        64,
        0x4,
    > {
        unsafe {
            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x2000usize))
        }
    }

    #[doc = "HSIOM port registers"]
    #[inline(always)]
    pub fn prt(self) -> &'static crate::common::ClusterRegisterArray<crate::hsiom::_Prt, 15, 0x10> {
        unsafe {
            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x0usize))
        }
    }
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AmuxSplitCtl_SPEC;
impl crate::sealed::RegSpec for AmuxSplitCtl_SPEC {
    type DataType = u32;
}

#[doc = "AMUX splitter cell control"]
pub type AmuxSplitCtl = crate::RegValueT<AmuxSplitCtl_SPEC>;

impl AmuxSplitCtl {
    #[doc = "T-switch control for Left AMUXBUSA switch:\n\'0\': switch open.\n\'1\': switch closed."]
    #[inline(always)]
    pub fn switch_aa_sl(
        self,
    ) -> crate::common::RegisterFieldBool<0, 1, 0, AmuxSplitCtl_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<0,1,0,AmuxSplitCtl_SPEC,crate::common::RW>::from_register(self,0)
    }

    #[doc = "T-switch control for Right AMUXBUSA switch:\n\'0\': switch open.\n\'1\': switch closed."]
    #[inline(always)]
    pub fn switch_aa_sr(
        self,
    ) -> crate::common::RegisterFieldBool<1, 1, 0, AmuxSplitCtl_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<1,1,0,AmuxSplitCtl_SPEC,crate::common::RW>::from_register(self,0)
    }

    #[doc = "T-switch control for AMUXBUSA vssa/ground switch:\n\'0\': switch open.\n\'1\': switch closed."]
    #[inline(always)]
    pub fn switch_aa_s0(
        self,
    ) -> crate::common::RegisterFieldBool<2, 1, 0, AmuxSplitCtl_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<2,1,0,AmuxSplitCtl_SPEC,crate::common::RW>::from_register(self,0)
    }

    #[doc = "T-switch control for Left AMUXBUSB switch."]
    #[inline(always)]
    pub fn switch_bb_sl(
        self,
    ) -> crate::common::RegisterFieldBool<4, 1, 0, AmuxSplitCtl_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<4,1,0,AmuxSplitCtl_SPEC,crate::common::RW>::from_register(self,0)
    }

    #[doc = "T-switch control for Right AMUXBUSB switch."]
    #[inline(always)]
    pub fn switch_bb_sr(
        self,
    ) -> crate::common::RegisterFieldBool<5, 1, 0, AmuxSplitCtl_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<5,1,0,AmuxSplitCtl_SPEC,crate::common::RW>::from_register(self,0)
    }

    #[doc = "T-switch control for AMUXBUSB vssa/ground switch."]
    #[inline(always)]
    pub fn switch_bb_s0(
        self,
    ) -> crate::common::RegisterFieldBool<6, 1, 0, AmuxSplitCtl_SPEC, crate::common::RW> {
        crate::common::RegisterFieldBool::<6,1,0,AmuxSplitCtl_SPEC,crate::common::RW>::from_register(self,0)
    }
}
impl ::core::default::Default for AmuxSplitCtl {
    #[inline(always)]
    fn default() -> AmuxSplitCtl {
        <crate::RegValueT<AmuxSplitCtl_SPEC> as RegisterValue<_>>::new(0)
    }
}

#[doc = "HSIOM port registers"]
#[non_exhaustive]
pub struct _Prt;

#[doc = "HSIOM port registers"]
pub type Prt = &'static _Prt;

unsafe impl ::core::marker::Sync for _Prt {}
impl _Prt {
    #[allow(unused)]
    #[inline(always)]
    pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
        &*(ptr as *const _)
    }

    #[allow(unused)]
    #[inline(always)]
    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
        self as *const Self as *mut u8
    }

    #[doc = "Port selection 0"]
    #[inline(always)]
    pub const fn port_sel0(
        &self,
    ) -> &'static crate::common::Reg<prt::PortSel0_SPEC, crate::common::RW> {
        unsafe {
            crate::common::Reg::<prt::PortSel0_SPEC, crate::common::RW>::from_ptr(
                self._svd2pac_as_ptr().add(0usize),
            )
        }
    }

    #[doc = "Port selection 1"]
    #[inline(always)]
    pub const fn port_sel1(
        &self,
    ) -> &'static crate::common::Reg<prt::PortSel1_SPEC, crate::common::RW> {
        unsafe {
            crate::common::Reg::<prt::PortSel1_SPEC, crate::common::RW>::from_ptr(
                self._svd2pac_as_ptr().add(4usize),
            )
        }
    }
}
pub mod prt {
    #[allow(unused_imports)]
    use crate::common::*;
    #[doc(hidden)]
    #[derive(Copy, Clone, Eq, PartialEq)]
    pub struct PortSel0_SPEC;
    impl crate::sealed::RegSpec for PortSel0_SPEC {
        type DataType = u32;
    }

    #[doc = "Port selection 0"]
    pub type PortSel0 = crate::RegValueT<PortSel0_SPEC>;

    impl PortSel0 {
        #[doc = "Selects the peripheral connections of Pin 0. Note that available connectivity options vary depending on the device, port and the pin. See the device Datasheet for a list of peripheral connections available at each pin."]
        #[inline(always)]
        pub fn io0_sel(
            self,
        ) -> crate::common::RegisterField<
            0,
            0x1f,
            1,
            0,
            port_sel0::Io0Sel,
            port_sel0::Io0Sel,
            PortSel0_SPEC,
            crate::common::RW,
        > {
            crate::common::RegisterField::<
                0,
                0x1f,
                1,
                0,
                port_sel0::Io0Sel,
                port_sel0::Io0Sel,
                PortSel0_SPEC,
                crate::common::RW,
            >::from_register(self, 0)
        }

        #[doc = "Selects the peripheral connections of Pin 1."]
        #[inline(always)]
        pub fn io1_sel(
            self,
        ) -> crate::common::RegisterField<8, 0x1f, 1, 0, u8, u8, PortSel0_SPEC, crate::common::RW>
        {
            crate::common::RegisterField::<8,0x1f,1,0,u8,u8,PortSel0_SPEC,crate::common::RW>::from_register(self,0)
        }

        #[doc = "Selects the peripheral connections of Pin 2."]
        #[inline(always)]
        pub fn io2_sel(
            self,
        ) -> crate::common::RegisterField<16, 0x1f, 1, 0, u8, u8, PortSel0_SPEC, crate::common::RW>
        {
            crate::common::RegisterField::<16,0x1f,1,0,u8,u8,PortSel0_SPEC,crate::common::RW>::from_register(self,0)
        }

        #[doc = "Selects the peripheral connections of Pin 3."]
        #[inline(always)]
        pub fn io3_sel(
            self,
        ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, PortSel0_SPEC, crate::common::RW>
        {
            crate::common::RegisterField::<24,0x1f,1,0,u8,u8,PortSel0_SPEC,crate::common::RW>::from_register(self,0)
        }
    }
    impl ::core::default::Default for PortSel0 {
        #[inline(always)]
        fn default() -> PortSel0 {
            <crate::RegValueT<PortSel0_SPEC> as RegisterValue<_>>::new(0)
        }
    }
    pub mod port_sel0 {

        #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
        pub struct Io0Sel_SPEC;
        pub type Io0Sel = crate::EnumBitfieldStruct<u8, Io0Sel_SPEC>;
        impl Io0Sel {
            #[doc = "GPIO controls \'out\'"]
            pub const GPIO: Self = Self::new(0);

            #[doc = "GPIO controls \'out\', DSI controls \'output enable\'"]
            pub const GPIO_DSI: Self = Self::new(1);

            #[doc = "DSI controls \'out\' and \'output enable\'"]
            pub const DSI_DSI: Self = Self::new(2);

            #[doc = "DSI controls \'out\', GPIO controls \'output enable\'"]
            pub const DSI_GPIO: Self = Self::new(3);

            #[doc = "Analog mux bus A"]
            pub const AMUXA: Self = Self::new(4);

            #[doc = "Analog mux bus B"]
            pub const AMUXB: Self = Self::new(5);

            #[doc = "Analog mux bus A, DSI control"]
            pub const AMUXA_DSI: Self = Self::new(6);

            #[doc = "Analog mux bus B, DSI control"]
            pub const AMUXB_DSI: Self = Self::new(7);

            #[doc = "Active functionality 0"]
            pub const ACT_0: Self = Self::new(8);

            #[doc = "Active functionality 1"]
            pub const ACT_1: Self = Self::new(9);

            #[doc = "Active functionality 2"]
            pub const ACT_2: Self = Self::new(10);

            #[doc = "Active functionality 3"]
            pub const ACT_3: Self = Self::new(11);

            #[doc = "DeepSleep functionality 0"]
            pub const DS_0: Self = Self::new(12);

            #[doc = "DeepSleep functionality 1"]
            pub const DS_1: Self = Self::new(13);

            #[doc = "DeepSleep functionality 2"]
            pub const DS_2: Self = Self::new(14);

            #[doc = "DeepSleep functionality 3"]
            pub const DS_3: Self = Self::new(15);

            #[doc = "Active functionality 4"]
            pub const ACT_4: Self = Self::new(16);

            #[doc = "Active functionality 5"]
            pub const ACT_5: Self = Self::new(17);

            #[doc = "Active functionality 6"]
            pub const ACT_6: Self = Self::new(18);

            #[doc = "Active functionality 7"]
            pub const ACT_7: Self = Self::new(19);

            #[doc = "Active functionality 8"]
            pub const ACT_8: Self = Self::new(20);

            #[doc = "Active functionality 9"]
            pub const ACT_9: Self = Self::new(21);

            #[doc = "Active functionality 10"]
            pub const ACT_10: Self = Self::new(22);

            #[doc = "Active functionality 11"]
            pub const ACT_11: Self = Self::new(23);

            #[doc = "Active functionality 12"]
            pub const ACT_12: Self = Self::new(24);

            #[doc = "Active functionality 13"]
            pub const ACT_13: Self = Self::new(25);

            #[doc = "Active functionality 14"]
            pub const ACT_14: Self = Self::new(26);

            #[doc = "Active functionality 15"]
            pub const ACT_15: Self = Self::new(27);

            #[doc = "DeepSleep functionality 4"]
            pub const DS_4: Self = Self::new(28);

            #[doc = "DeepSleep functionality 5"]
            pub const DS_5: Self = Self::new(29);

            #[doc = "DeepSleep functionality 6"]
            pub const DS_6: Self = Self::new(30);

            #[doc = "DeepSleep functionality 7"]
            pub const DS_7: Self = Self::new(31);
        }
    }
    #[doc(hidden)]
    #[derive(Copy, Clone, Eq, PartialEq)]
    pub struct PortSel1_SPEC;
    impl crate::sealed::RegSpec for PortSel1_SPEC {
        type DataType = u32;
    }

    #[doc = "Port selection 1"]
    pub type PortSel1 = crate::RegValueT<PortSel1_SPEC>;

    impl PortSel1 {
        #[doc = "Selects the peripheral connections of Pin 4. See PORT_SEL0 for connection details."]
        #[inline(always)]
        pub fn io4_sel(
            self,
        ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, PortSel1_SPEC, crate::common::RW>
        {
            crate::common::RegisterField::<0,0x1f,1,0,u8,u8,PortSel1_SPEC,crate::common::RW>::from_register(self,0)
        }

        #[doc = "Selects the peripheral connections of Pin 4."]
        #[inline(always)]
        pub fn io5_sel(
            self,
        ) -> crate::common::RegisterField<8, 0x1f, 1, 0, u8, u8, PortSel1_SPEC, crate::common::RW>
        {
            crate::common::RegisterField::<8,0x1f,1,0,u8,u8,PortSel1_SPEC,crate::common::RW>::from_register(self,0)
        }

        #[doc = "Selects the peripheral connections of Pin 5."]
        #[inline(always)]
        pub fn io6_sel(
            self,
        ) -> crate::common::RegisterField<16, 0x1f, 1, 0, u8, u8, PortSel1_SPEC, crate::common::RW>
        {
            crate::common::RegisterField::<16,0x1f,1,0,u8,u8,PortSel1_SPEC,crate::common::RW>::from_register(self,0)
        }

        #[doc = "Selects the peripheral connections of Pin 6."]
        #[inline(always)]
        pub fn io7_sel(
            self,
        ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, PortSel1_SPEC, crate::common::RW>
        {
            crate::common::RegisterField::<24,0x1f,1,0,u8,u8,PortSel1_SPEC,crate::common::RW>::from_register(self,0)
        }
    }
    impl ::core::default::Default for PortSel1 {
        #[inline(always)]
        fn default() -> PortSel1 {
            <crate::RegValueT<PortSel1_SPEC> as RegisterValue<_>>::new(0)
        }
    }
}