/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"LCD Controller Block"]
unsafe impl ::core::marker::Send for super::Lcd {}
unsafe impl ::core::marker::Sync for super::Lcd {}
impl super::Lcd {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "ID & Revision"]
#[inline(always)]
pub const fn id(&self) -> &'static crate::common::Reg<self::Id_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::Id_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "LCD Divider Register"]
#[inline(always)]
pub const fn divider(
&self,
) -> &'static crate::common::Reg<self::Divider_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Divider_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "LCD Configuration Register"]
#[inline(always)]
pub const fn control(
&self,
) -> &'static crate::common::Reg<self::Control_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Control_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(8usize),
)
}
}
#[doc = "LCD Pin Data Registers"]
#[inline(always)]
pub const fn data0(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::Data0_SPEC, crate::common::RW>,
8,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x100usize))
}
}
#[doc = "LCD Pin Data Registers"]
#[inline(always)]
pub const fn data1(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::Data1_SPEC, crate::common::RW>,
8,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x200usize))
}
}
#[doc = "LCD Pin Data Registers"]
#[inline(always)]
pub const fn data2(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::Data2_SPEC, crate::common::RW>,
8,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x300usize))
}
}
#[doc = "LCD Pin Data Registers"]
#[inline(always)]
pub const fn data3(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::Data3_SPEC, crate::common::RW>,
8,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x400usize))
}
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Id_SPEC;
impl crate::sealed::RegSpec for Id_SPEC {
type DataType = u32;
}
#[doc = "ID & Revision"]
pub type Id = crate::RegValueT<Id_SPEC>;
impl Id {
#[doc = "the ID of LCD controller peripheral is 0xF0F0"]
#[inline(always)]
pub fn id(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Id_SPEC, crate::common::R> {
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Id_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "the version number is 0x0001"]
#[inline(always)]
pub fn revision(
self,
) -> crate::common::RegisterField<16, 0xffff, 1, 0, u16, u16, Id_SPEC, crate::common::R> {
crate::common::RegisterField::<16,0xffff,1,0,u16,u16,Id_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Id {
#[inline(always)]
fn default() -> Id {
<crate::RegValueT<Id_SPEC> as RegisterValue<_>>::new(127216)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Divider_SPEC;
impl crate::sealed::RegSpec for Divider_SPEC {
type DataType = u32;
}
#[doc = "LCD Divider Register"]
pub type Divider = crate::RegValueT<Divider_SPEC>;
impl Divider {
#[doc = "Input clock frequency divide value, to generate the 1/4 sub-frame period. The sub-frame period is 4*(SUBFR_DIV+1) cycles long."]
#[inline(always)]
pub fn subfr_div(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Divider_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Divider_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Length of the dead time period in cycles. When set to zero, no dead time period exists."]
#[inline(always)]
pub fn dead_div(
self,
) -> crate::common::RegisterField<16, 0xffff, 1, 0, u16, u16, Divider_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xffff,1,0,u16,u16,Divider_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Divider {
#[inline(always)]
fn default() -> Divider {
<crate::RegValueT<Divider_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Control_SPEC;
impl crate::sealed::RegSpec for Control_SPEC {
type DataType = u32;
}
#[doc = "LCD Configuration Register"]
pub type Control = crate::RegValueT<Control_SPEC>;
impl Control {
#[doc = "Low speed (LS) generator enable\n1: enable\n0: disable"]
#[inline(always)]
pub fn ls_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Control_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Control_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "High speed (HS) generator enable\n1: enable\n0: disable"]
#[inline(always)]
pub fn hs_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Control_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Control_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "HS/LS Mode selection"]
#[inline(always)]
pub fn lcd_mode(
self,
) -> crate::common::RegisterField<
2,
0x1,
1,
0,
control::LcdMode,
control::LcdMode,
Control_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
2,
0x1,
1,
0,
control::LcdMode,
control::LcdMode,
Control_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "LCD driving waveform type configuration."]
#[inline(always)]
pub fn r#type(
self,
) -> crate::common::RegisterField<
3,
0x1,
1,
0,
control::Type,
control::Type,
Control_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
3,
0x1,
1,
0,
control::Type,
control::Type,
Control_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Driving mode configuration"]
#[inline(always)]
pub fn op_mode(
self,
) -> crate::common::RegisterField<
4,
0x1,
1,
0,
control::OpMode,
control::OpMode,
Control_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x1,
1,
0,
control::OpMode,
control::OpMode,
Control_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "PWM bias selection"]
#[inline(always)]
pub fn bias(
self,
) -> crate::common::RegisterField<
5,
0x3,
1,
0,
control::Bias,
control::Bias,
Control_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
5,
0x3,
1,
0,
control::Bias,
control::Bias,
Control_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "The number of COM connections minus 2. So:\n0: 2 COM\'s\n1: 3 COM\'s\n...\n13: 15 COM\'s\n14: 16 COM\'s\n15: undefined"]
#[inline(always)]
pub fn com_num(
self,
) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, Control_SPEC, crate::common::RW> {
crate::common::RegisterField::<8,0xf,1,0,u8,u8,Control_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "LS enable status bit. This bit is a copy of LS_EN that is synchronized to the low speed clock domain and back to the system clock domain. Firmware can use this bit to observe whether LS_EN has taken effect in the low speed clock domain. Firmware should never change the configuration for the LS generator without ensuring this bit is 0.\nThe following procedure should be followed to disable the LS generator:\n1. If LS_EN=0 we are done. Exit the procedure.\n2. Check that LS_EN_STAT=1. If not, wait until it is. This will catch the case of a recent enable (LS_EN=1) that has not taken effect yet.\n3. Set LS_EN=0.\n4. Wait until LS_EN_STAT=0."]
#[inline(always)]
pub fn ls_en_stat(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Control_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31, 1, 0, Control_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Control {
#[inline(always)]
fn default() -> Control {
<crate::RegValueT<Control_SPEC> as RegisterValue<_>>::new(0)
}
}
pub mod control {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct LcdMode_SPEC;
pub type LcdMode = crate::EnumBitfieldStruct<u8, LcdMode_SPEC>;
impl LcdMode {
#[doc = "Select Low Speed (32kHz) Generator (Works in Active, Sleep and DeepSleep power modes)."]
pub const LS: Self = Self::new(0);
#[doc = "Select High Speed (system clock) Generator (Works in Active and Sleep power modes only)."]
pub const HS: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Type_SPEC;
pub type Type = crate::EnumBitfieldStruct<u8, Type_SPEC>;
impl Type {
#[doc = "Type A - Each frame addresses each COM pin only once with a balanced (DC=0) waveform."]
pub const TYPE_A: Self = Self::new(0);
#[doc = "Type B - Each frame addresses each COM pin twice in sequence with a positive and negative waveform that together are balanced (DC=0)."]
pub const TYPE_B: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct OpMode_SPEC;
pub type OpMode = crate::EnumBitfieldStruct<u8, OpMode_SPEC>;
impl OpMode {
#[doc = "PWM Mode"]
pub const PWM: Self = Self::new(0);
#[doc = "Digital Correlation Mode"]
pub const CORRELATION: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Bias_SPEC;
pub type Bias = crate::EnumBitfieldStruct<u8, Bias_SPEC>;
impl Bias {
#[doc = "1/2 Bias"]
pub const HALF: Self = Self::new(0);
#[doc = "1/3 Bias"]
pub const THIRD: Self = Self::new(1);
#[doc = "1/4 Bias (not supported by LS generator)"]
pub const FOURTH: Self = Self::new(2);
#[doc = "1/5 Bias (not supported by LS generator)"]
pub const FIFTH: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Data0_SPEC;
impl crate::sealed::RegSpec for Data0_SPEC {
type DataType = u32;
}
#[doc = "LCD Pin Data Registers"]
pub type Data0 = crate::RegValueT<Data0_SPEC>;
impl Data0 {
#[doc = "Bits \\[4i+3:4i\\] represent the pin data for pin \\[i\\] for COMS 1-4 (COM1 is lsb)."]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Data0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Data0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Data0 {
#[inline(always)]
fn default() -> Data0 {
<crate::RegValueT<Data0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Data1_SPEC;
impl crate::sealed::RegSpec for Data1_SPEC {
type DataType = u32;
}
#[doc = "LCD Pin Data Registers"]
pub type Data1 = crate::RegValueT<Data1_SPEC>;
impl Data1 {
#[doc = "Bits \\[4i+3:4i\\] represent the pin data for pin \\[i\\] for COMS 5-8 (COM5 is lsb)."]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Data1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Data1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Data1 {
#[inline(always)]
fn default() -> Data1 {
<crate::RegValueT<Data1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Data2_SPEC;
impl crate::sealed::RegSpec for Data2_SPEC {
type DataType = u32;
}
#[doc = "LCD Pin Data Registers"]
pub type Data2 = crate::RegValueT<Data2_SPEC>;
impl Data2 {
#[doc = "Bits \\[4i+3:4i\\] represent the pin data for pin \\[i\\] for COMS 9-12 (COM9 is lsb)."]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Data2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Data2_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Data2 {
#[inline(always)]
fn default() -> Data2 {
<crate::RegValueT<Data2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Data3_SPEC;
impl crate::sealed::RegSpec for Data3_SPEC {
type DataType = u32;
}
#[doc = "LCD Pin Data Registers"]
pub type Data3 = crate::RegValueT<Data3_SPEC>;
impl Data3 {
#[doc = "Bits \\[4i+3:4i\\] represent the pin data for pin \\[i\\] for COMS 13-16 (COM13 is lsb)."]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Data3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Data3_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Data3 {
#[inline(always)]
fn default() -> Data3 {
<crate::RegValueT<Data3_SPEC> as RegisterValue<_>>::new(0)
}
}