mtb_pac_psoc6_01 0.1.1

/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)

    or an affiliate of Cypress Semiconductor Corporation.



    SPDX-License-Identifier: Apache-2.0



    Licensed under the Apache License, Version 2.0 (the "License");

    you may not use this file except in compliance with the License.

    You may obtain a copy of the License at



      http://www.apache.org/licenses/LICENSE-2.0



    Unless required by applicable law or agreed to in writing, software

    distributed under the License is distributed on an "AS IS" BASIS,

    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

    See the License for the specific language governing permissions and

    limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![no_std]
#![allow(non_camel_case_types)]
#![doc = "PSOC6_01"]
pub mod common;
pub use common::*;

#[cfg(feature = "backup")]
pub mod backup;
#[cfg(feature = "ble")]
pub mod ble;
#[cfg(feature = "cpuss")]
pub mod cpuss;
#[cfg(feature = "crypto")]
pub mod crypto;
#[cfg(feature = "csd0")]
pub mod csd;
#[cfg(feature = "ctbm0")]
pub mod ctbm;
#[cfg(feature = "ctdac0")]
pub mod ctdac;
#[cfg(feature = "dw0")]
pub mod dw;
#[cfg(feature = "efuse")]
pub mod efuse;
#[cfg(feature = "fault")]
pub mod fault;
#[cfg(feature = "flashc")]
pub mod flashc;
#[cfg(feature = "gpio")]
pub mod gpio;
#[cfg(feature = "hsiom")]
pub mod hsiom;
#[cfg(feature = "i2s0")]
pub mod i2s;
#[cfg(feature = "ipc")]
pub mod ipc;
#[cfg(feature = "lcd0")]
pub mod lcd;
#[cfg(feature = "lpcomp")]
pub mod lpcomp;
#[cfg(feature = "pass")]
pub mod pass;
#[cfg(feature = "pdm0")]
pub mod pdm;
#[cfg(feature = "peri")]
pub mod peri;
#[cfg(feature = "profile")]
pub mod profile;
#[cfg(feature = "prot")]
pub mod prot;
#[cfg(feature = "sar")]
pub mod sar;
#[cfg(feature = "scb0")]
pub mod scb;
#[cfg(feature = "smartio")]
pub mod smartio;
#[cfg(feature = "smif0")]
pub mod smif;
#[cfg(feature = "srss")]
pub mod srss;
#[cfg(feature = "tcpwm0")]
pub mod tcpwm;
#[cfg(feature = "usbfs0")]
pub mod usbfs;

#[cfg(feature = "peri")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Peri {
    ptr: *mut u8,
}
#[cfg(feature = "peri")]
pub const PERI: self::Peri = self::Peri {
    ptr: 0x40010000u32 as _,
};
#[cfg(feature = "crypto")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Crypto {
    ptr: *mut u8,
}
#[cfg(feature = "crypto")]
pub const CRYPTO: self::Crypto = self::Crypto {
    ptr: 0x40110000u32 as _,
};
#[cfg(feature = "cpuss")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cpuss {
    ptr: *mut u8,
}
#[cfg(feature = "cpuss")]
pub const CPUSS: self::Cpuss = self::Cpuss {
    ptr: 0x40210000u32 as _,
};
#[cfg(feature = "fault")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Fault {
    ptr: *mut u8,
}
#[cfg(feature = "fault")]
pub const FAULT: self::Fault = self::Fault {
    ptr: 0x40220000u32 as _,
};
#[cfg(feature = "ipc")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ipc {
    ptr: *mut u8,
}
#[cfg(feature = "ipc")]
pub const IPC: self::Ipc = self::Ipc {
    ptr: 0x40230000u32 as _,
};
#[cfg(feature = "prot")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Prot {
    ptr: *mut u8,
}
#[cfg(feature = "prot")]
pub const PROT: self::Prot = self::Prot {
    ptr: 0x40240000u32 as _,
};
#[cfg(feature = "flashc")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Flashc {
    ptr: *mut u8,
}
#[cfg(feature = "flashc")]
pub const FLASHC: self::Flashc = self::Flashc {
    ptr: 0x40250000u32 as _,
};
#[cfg(feature = "srss")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Srss {
    ptr: *mut u8,
}
#[cfg(feature = "srss")]
pub const SRSS: self::Srss = self::Srss {
    ptr: 0x40260000u32 as _,
};
#[cfg(feature = "backup")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Backup {
    ptr: *mut u8,
}
#[cfg(feature = "backup")]
pub const BACKUP: self::Backup = self::Backup {
    ptr: 0x40270000u32 as _,
};
#[cfg(feature = "dw0")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Dw {
    ptr: *mut u8,
}
#[cfg(feature = "dw0")]
pub const DW0: self::Dw = self::Dw {
    ptr: 0x40280000u32 as _,
};
#[cfg(feature = "dw1")]
pub const DW1: self::Dw = self::Dw {
    ptr: 0x40281000u32 as _,
};
#[cfg(feature = "efuse")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Efuse {
    ptr: *mut u8,
}
#[cfg(feature = "efuse")]
pub const EFUSE: self::Efuse = self::Efuse {
    ptr: 0x402c0000u32 as _,
};
#[cfg(feature = "profile")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Profile {
    ptr: *mut u8,
}
#[cfg(feature = "profile")]
pub const PROFILE: self::Profile = self::Profile {
    ptr: 0x402d0000u32 as _,
};
#[cfg(feature = "hsiom")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Hsiom {
    ptr: *mut u8,
}
#[cfg(feature = "hsiom")]
pub const HSIOM: self::Hsiom = self::Hsiom {
    ptr: 0x40310000u32 as _,
};
#[cfg(feature = "gpio")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Gpio {
    ptr: *mut u8,
}
#[cfg(feature = "gpio")]
pub const GPIO: self::Gpio = self::Gpio {
    ptr: 0x40320000u32 as _,
};
#[cfg(feature = "smartio")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Smartio {
    ptr: *mut u8,
}
#[cfg(feature = "smartio")]
pub const SMARTIO: self::Smartio = self::Smartio {
    ptr: 0x40330000u32 as _,
};
#[cfg(feature = "lpcomp")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Lpcomp {
    ptr: *mut u8,
}
#[cfg(feature = "lpcomp")]
pub const LPCOMP: self::Lpcomp = self::Lpcomp {
    ptr: 0x40350000u32 as _,
};
#[cfg(feature = "csd0")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Csd {
    ptr: *mut u8,
}
#[cfg(feature = "csd0")]
pub const CSD0: self::Csd = self::Csd {
    ptr: 0x40360000u32 as _,
};
#[cfg(feature = "tcpwm0")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Tcpwm {
    ptr: *mut u8,
}
#[cfg(feature = "tcpwm0")]
pub const TCPWM0: self::Tcpwm = self::Tcpwm {
    ptr: 0x40380000u32 as _,
};
#[cfg(feature = "tcpwm1")]
pub const TCPWM1: self::Tcpwm = self::Tcpwm {
    ptr: 0x40390000u32 as _,
};
#[cfg(feature = "lcd0")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Lcd {
    ptr: *mut u8,
}
#[cfg(feature = "lcd0")]
pub const LCD0: self::Lcd = self::Lcd {
    ptr: 0x403b0000u32 as _,
};
#[cfg(feature = "ble")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ble {
    ptr: *mut u8,
}
#[cfg(feature = "ble")]
pub const BLE: self::Ble = self::Ble {
    ptr: 0x403c0000u32 as _,
};
#[cfg(feature = "usbfs0")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Usbfs {
    ptr: *mut u8,
}
#[cfg(feature = "usbfs0")]
pub const USBFS0: self::Usbfs = self::Usbfs {
    ptr: 0x403f0000u32 as _,
};
#[cfg(feature = "smif0")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Smif {
    ptr: *mut u8,
}
#[cfg(feature = "smif0")]
pub const SMIF0: self::Smif = self::Smif {
    ptr: 0x40420000u32 as _,
};
#[cfg(feature = "scb0")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Scb {
    ptr: *mut u8,
}
#[cfg(feature = "scb0")]
pub const SCB0: self::Scb = self::Scb {
    ptr: 0x40610000u32 as _,
};
#[cfg(feature = "scb1")]
pub const SCB1: self::Scb = self::Scb {
    ptr: 0x40620000u32 as _,
};
#[cfg(feature = "scb2")]
pub const SCB2: self::Scb = self::Scb {
    ptr: 0x40630000u32 as _,
};
#[cfg(feature = "scb3")]
pub const SCB3: self::Scb = self::Scb {
    ptr: 0x40640000u32 as _,
};
#[cfg(feature = "scb4")]
pub const SCB4: self::Scb = self::Scb {
    ptr: 0x40650000u32 as _,
};
#[cfg(feature = "scb5")]
pub const SCB5: self::Scb = self::Scb {
    ptr: 0x40660000u32 as _,
};
#[cfg(feature = "scb6")]
pub const SCB6: self::Scb = self::Scb {
    ptr: 0x40670000u32 as _,
};
#[cfg(feature = "scb7")]
pub const SCB7: self::Scb = self::Scb {
    ptr: 0x40680000u32 as _,
};
#[cfg(feature = "scb8")]
pub const SCB8: self::Scb = self::Scb {
    ptr: 0x40690000u32 as _,
};
#[cfg(feature = "ctbm0")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctbm {
    ptr: *mut u8,
}
#[cfg(feature = "ctbm0")]
pub const CTBM0: self::Ctbm = self::Ctbm {
    ptr: 0x41100000u32 as _,
};
#[cfg(feature = "ctdac0")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctdac {
    ptr: *mut u8,
}
#[cfg(feature = "ctdac0")]
pub const CTDAC0: self::Ctdac = self::Ctdac {
    ptr: 0x41140000u32 as _,
};
#[cfg(feature = "sar")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Sar {
    ptr: *mut u8,
}
#[cfg(feature = "sar")]
pub const SAR: self::Sar = self::Sar {
    ptr: 0x411d0000u32 as _,
};
#[cfg(feature = "pass")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Pass {
    ptr: *mut u8,
}
#[cfg(feature = "pass")]
pub const PASS: self::Pass = self::Pass {
    ptr: 0x411f0000u32 as _,
};
#[cfg(feature = "i2s0")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct I2S {
    ptr: *mut u8,
}
#[cfg(feature = "i2s0")]
pub const I2S0: self::I2S = self::I2S {
    ptr: 0x42a10000u32 as _,
};
#[cfg(feature = "pdm0")]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Pdm {
    ptr: *mut u8,
}
#[cfg(feature = "pdm0")]
pub const PDM0: self::Pdm = self::Pdm {
    ptr: 0x42a20000u32 as _,
};

pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[doc = "Number available in the NVIC for configuring priority"]
pub const NVIC_PRIO_BITS: u8 = 3;
#[doc(hidden)]
pub union Vector {
    _handler: unsafe extern "C" fn(),
    _reserved: u32,
}
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[cfg(feature = "rt")]
pub mod interrupt_handlers {
    extern "C" {
        pub fn IOSS_INTERRUPTS_GPIO_0();
        pub fn IOSS_INTERRUPTS_GPIO_1();
        pub fn IOSS_INTERRUPTS_GPIO_2();
        pub fn IOSS_INTERRUPTS_GPIO_3();
        pub fn IOSS_INTERRUPTS_GPIO_4();
        pub fn IOSS_INTERRUPTS_GPIO_5();
        pub fn IOSS_INTERRUPTS_GPIO_6();
        pub fn IOSS_INTERRUPTS_GPIO_7();
        pub fn IOSS_INTERRUPTS_GPIO_8();
        pub fn IOSS_INTERRUPTS_GPIO_9();
        pub fn IOSS_INTERRUPTS_GPIO_10();
        pub fn IOSS_INTERRUPTS_GPIO_11();
        pub fn IOSS_INTERRUPTS_GPIO_12();
        pub fn IOSS_INTERRUPTS_GPIO_13();
        pub fn IOSS_INTERRUPTS_GPIO_14();
        pub fn IOSS_INTERRUPT_GPIO();
        pub fn IOSS_INTERRUPT_VDD();
        pub fn LPCOMP_INTERRUPT();
        pub fn SCB_8_INTERRUPT();
        pub fn SRSS_INTERRUPT_MCWDT_0();
        pub fn SRSS_INTERRUPT_MCWDT_1();
        pub fn SRSS_INTERRUPT_BACKUP();
        pub fn SRSS_INTERRUPT();
        pub fn PASS_INTERRUPT_CTBS();
        pub fn BLESS_INTERRUPT();
        pub fn CPUSS_INTERRUPTS_IPC_0();
        pub fn CPUSS_INTERRUPTS_IPC_1();
        pub fn CPUSS_INTERRUPTS_IPC_2();
        pub fn CPUSS_INTERRUPTS_IPC_3();
        pub fn CPUSS_INTERRUPTS_IPC_4();
        pub fn CPUSS_INTERRUPTS_IPC_5();
        pub fn CPUSS_INTERRUPTS_IPC_6();
        pub fn CPUSS_INTERRUPTS_IPC_7();
        pub fn CPUSS_INTERRUPTS_IPC_8();
        pub fn CPUSS_INTERRUPTS_IPC_9();
        pub fn CPUSS_INTERRUPTS_IPC_10();
        pub fn CPUSS_INTERRUPTS_IPC_11();
        pub fn CPUSS_INTERRUPTS_IPC_12();
        pub fn CPUSS_INTERRUPTS_IPC_13();
        pub fn CPUSS_INTERRUPTS_IPC_14();
        pub fn CPUSS_INTERRUPTS_IPC_15();
        pub fn SCB_0_INTERRUPT();
        pub fn SCB_1_INTERRUPT();
        pub fn SCB_2_INTERRUPT();
        pub fn SCB_3_INTERRUPT();
        pub fn SCB_4_INTERRUPT();
        pub fn SCB_5_INTERRUPT();
        pub fn SCB_6_INTERRUPT();
        pub fn SCB_7_INTERRUPT();
        pub fn CSD_INTERRUPT();
        pub fn CPUSS_INTERRUPTS_DW0_0();
        pub fn CPUSS_INTERRUPTS_DW0_1();
        pub fn CPUSS_INTERRUPTS_DW0_2();
        pub fn CPUSS_INTERRUPTS_DW0_3();
        pub fn CPUSS_INTERRUPTS_DW0_4();
        pub fn CPUSS_INTERRUPTS_DW0_5();
        pub fn CPUSS_INTERRUPTS_DW0_6();
        pub fn CPUSS_INTERRUPTS_DW0_7();
        pub fn CPUSS_INTERRUPTS_DW0_8();
        pub fn CPUSS_INTERRUPTS_DW0_9();
        pub fn CPUSS_INTERRUPTS_DW0_10();
        pub fn CPUSS_INTERRUPTS_DW0_11();
        pub fn CPUSS_INTERRUPTS_DW0_12();
        pub fn CPUSS_INTERRUPTS_DW0_13();
        pub fn CPUSS_INTERRUPTS_DW0_14();
        pub fn CPUSS_INTERRUPTS_DW0_15();
        pub fn CPUSS_INTERRUPTS_DW1_0();
        pub fn CPUSS_INTERRUPTS_DW1_1();
        pub fn CPUSS_INTERRUPTS_DW1_2();
        pub fn CPUSS_INTERRUPTS_DW1_3();
        pub fn CPUSS_INTERRUPTS_DW1_4();
        pub fn CPUSS_INTERRUPTS_DW1_5();
        pub fn CPUSS_INTERRUPTS_DW1_6();
        pub fn CPUSS_INTERRUPTS_DW1_7();
        pub fn CPUSS_INTERRUPTS_DW1_8();
        pub fn CPUSS_INTERRUPTS_DW1_9();
        pub fn CPUSS_INTERRUPTS_DW1_10();
        pub fn CPUSS_INTERRUPTS_DW1_11();
        pub fn CPUSS_INTERRUPTS_DW1_12();
        pub fn CPUSS_INTERRUPTS_DW1_13();
        pub fn CPUSS_INTERRUPTS_DW1_14();
        pub fn CPUSS_INTERRUPTS_DW1_15();
        pub fn CPUSS_INTERRUPTS_FAULT_0();
        pub fn CPUSS_INTERRUPTS_FAULT_1();
        pub fn CPUSS_INTERRUPT_CRYPTO();
        pub fn CPUSS_INTERRUPT_FM();
        pub fn CPUSS_INTERRUPTS_CM0_CTI_0();
        pub fn CPUSS_INTERRUPTS_CM0_CTI_1();
        pub fn CPUSS_INTERRUPTS_CM4_CTI_0();
        pub fn CPUSS_INTERRUPTS_CM4_CTI_1();
        pub fn TCPWM_0_INTERRUPTS_0();
        pub fn TCPWM_0_INTERRUPTS_1();
        pub fn TCPWM_0_INTERRUPTS_2();
        pub fn TCPWM_0_INTERRUPTS_3();
        pub fn TCPWM_0_INTERRUPTS_4();
        pub fn TCPWM_0_INTERRUPTS_5();
        pub fn TCPWM_0_INTERRUPTS_6();
        pub fn TCPWM_0_INTERRUPTS_7();
        pub fn TCPWM_1_INTERRUPTS_0();
        pub fn TCPWM_1_INTERRUPTS_1();
        pub fn TCPWM_1_INTERRUPTS_2();
        pub fn TCPWM_1_INTERRUPTS_3();
        pub fn TCPWM_1_INTERRUPTS_4();
        pub fn TCPWM_1_INTERRUPTS_5();
        pub fn TCPWM_1_INTERRUPTS_6();
        pub fn TCPWM_1_INTERRUPTS_7();
        pub fn TCPWM_1_INTERRUPTS_8();
        pub fn TCPWM_1_INTERRUPTS_9();
        pub fn TCPWM_1_INTERRUPTS_10();
        pub fn TCPWM_1_INTERRUPTS_11();
        pub fn TCPWM_1_INTERRUPTS_12();
        pub fn TCPWM_1_INTERRUPTS_13();
        pub fn TCPWM_1_INTERRUPTS_14();
        pub fn TCPWM_1_INTERRUPTS_15();
        pub fn TCPWM_1_INTERRUPTS_16();
        pub fn TCPWM_1_INTERRUPTS_17();
        pub fn TCPWM_1_INTERRUPTS_18();
        pub fn TCPWM_1_INTERRUPTS_19();
        pub fn TCPWM_1_INTERRUPTS_20();
        pub fn TCPWM_1_INTERRUPTS_21();
        pub fn TCPWM_1_INTERRUPTS_22();
        pub fn TCPWM_1_INTERRUPTS_23();
        pub fn UDB_INTERRUPTS_0();
        pub fn UDB_INTERRUPTS_1();
        pub fn UDB_INTERRUPTS_2();
        pub fn UDB_INTERRUPTS_3();
        pub fn UDB_INTERRUPTS_4();
        pub fn UDB_INTERRUPTS_5();
        pub fn UDB_INTERRUPTS_6();
        pub fn UDB_INTERRUPTS_7();
        pub fn UDB_INTERRUPTS_8();
        pub fn UDB_INTERRUPTS_9();
        pub fn UDB_INTERRUPTS_10();
        pub fn UDB_INTERRUPTS_11();
        pub fn UDB_INTERRUPTS_12();
        pub fn UDB_INTERRUPTS_13();
        pub fn UDB_INTERRUPTS_14();
        pub fn UDB_INTERRUPTS_15();
        pub fn PASS_INTERRUPT_SAR();
        pub fn AUDIOSS_INTERRUPT_I2S();
        pub fn AUDIOSS_INTERRUPT_PDM();
        pub fn PROFILE_INTERRUPT();
        pub fn SMIF_INTERRUPT();
        pub fn USB_INTERRUPT_HI();
        pub fn USB_INTERRUPT_MED();
        pub fn USB_INTERRUPT_LO();
        pub fn PASS_INTERRUPT_DACS();
    }
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 147] = [
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_0,
    },
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_1,
    },
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_2,
    },
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_3,
    },
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_4,
    },
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_5,
    },
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_6,
    },
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_7,
    },
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_8,
    },
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_9,
    },
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_10,
    },
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_11,
    },
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_12,
    },
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_13,
    },
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_14,
    },
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPT_GPIO,
    },
    Vector {
        _handler: interrupt_handlers::IOSS_INTERRUPT_VDD,
    },
    Vector {
        _handler: interrupt_handlers::LPCOMP_INTERRUPT,
    },
    Vector {
        _handler: interrupt_handlers::SCB_8_INTERRUPT,
    },
    Vector {
        _handler: interrupt_handlers::SRSS_INTERRUPT_MCWDT_0,
    },
    Vector {
        _handler: interrupt_handlers::SRSS_INTERRUPT_MCWDT_1,
    },
    Vector {
        _handler: interrupt_handlers::SRSS_INTERRUPT_BACKUP,
    },
    Vector {
        _handler: interrupt_handlers::SRSS_INTERRUPT,
    },
    Vector {
        _handler: interrupt_handlers::PASS_INTERRUPT_CTBS,
    },
    Vector {
        _handler: interrupt_handlers::BLESS_INTERRUPT,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_0,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_1,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_2,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_3,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_4,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_5,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_6,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_7,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_8,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_9,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_10,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_11,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_12,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_13,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_14,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_15,
    },
    Vector {
        _handler: interrupt_handlers::SCB_0_INTERRUPT,
    },
    Vector {
        _handler: interrupt_handlers::SCB_1_INTERRUPT,
    },
    Vector {
        _handler: interrupt_handlers::SCB_2_INTERRUPT,
    },
    Vector {
        _handler: interrupt_handlers::SCB_3_INTERRUPT,
    },
    Vector {
        _handler: interrupt_handlers::SCB_4_INTERRUPT,
    },
    Vector {
        _handler: interrupt_handlers::SCB_5_INTERRUPT,
    },
    Vector {
        _handler: interrupt_handlers::SCB_6_INTERRUPT,
    },
    Vector {
        _handler: interrupt_handlers::SCB_7_INTERRUPT,
    },
    Vector {
        _handler: interrupt_handlers::CSD_INTERRUPT,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_0,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_1,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_2,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_3,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_4,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_5,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_6,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_7,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_8,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_9,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_10,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_11,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_12,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_13,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_14,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_15,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_0,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_1,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_2,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_3,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_4,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_5,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_6,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_7,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_8,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_9,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_10,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_11,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_12,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_13,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_14,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_15,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_FAULT_0,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_FAULT_1,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPT_CRYPTO,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPT_FM,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_CM0_CTI_0,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_CM0_CTI_1,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_CM4_CTI_0,
    },
    Vector {
        _handler: interrupt_handlers::CPUSS_INTERRUPTS_CM4_CTI_1,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_0,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_1,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_2,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_3,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_4,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_5,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_6,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_7,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_0,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_1,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_2,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_3,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_4,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_5,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_6,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_7,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_8,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_9,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_10,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_11,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_12,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_13,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_14,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_15,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_16,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_17,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_18,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_19,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_20,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_21,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_22,
    },
    Vector {
        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_23,
    },
    Vector {
        _handler: interrupt_handlers::UDB_INTERRUPTS_0,
    },
    Vector {
        _handler: interrupt_handlers::UDB_INTERRUPTS_1,
    },
    Vector {
        _handler: interrupt_handlers::UDB_INTERRUPTS_2,
    },
    Vector {
        _handler: interrupt_handlers::UDB_INTERRUPTS_3,
    },
    Vector {
        _handler: interrupt_handlers::UDB_INTERRUPTS_4,
    },
    Vector {
        _handler: interrupt_handlers::UDB_INTERRUPTS_5,
    },
    Vector {
        _handler: interrupt_handlers::UDB_INTERRUPTS_6,
    },
    Vector {
        _handler: interrupt_handlers::UDB_INTERRUPTS_7,
    },
    Vector {
        _handler: interrupt_handlers::UDB_INTERRUPTS_8,
    },
    Vector {
        _handler: interrupt_handlers::UDB_INTERRUPTS_9,
    },
    Vector {
        _handler: interrupt_handlers::UDB_INTERRUPTS_10,
    },
    Vector {
        _handler: interrupt_handlers::UDB_INTERRUPTS_11,
    },
    Vector {
        _handler: interrupt_handlers::UDB_INTERRUPTS_12,
    },
    Vector {
        _handler: interrupt_handlers::UDB_INTERRUPTS_13,
    },
    Vector {
        _handler: interrupt_handlers::UDB_INTERRUPTS_14,
    },
    Vector {
        _handler: interrupt_handlers::UDB_INTERRUPTS_15,
    },
    Vector {
        _handler: interrupt_handlers::PASS_INTERRUPT_SAR,
    },
    Vector {
        _handler: interrupt_handlers::AUDIOSS_INTERRUPT_I2S,
    },
    Vector {
        _handler: interrupt_handlers::AUDIOSS_INTERRUPT_PDM,
    },
    Vector {
        _handler: interrupt_handlers::PROFILE_INTERRUPT,
    },
    Vector {
        _handler: interrupt_handlers::SMIF_INTERRUPT,
    },
    Vector {
        _handler: interrupt_handlers::USB_INTERRUPT_HI,
    },
    Vector {
        _handler: interrupt_handlers::USB_INTERRUPT_MED,
    },
    Vector {
        _handler: interrupt_handlers::USB_INTERRUPT_LO,
    },
    Vector {
        _handler: interrupt_handlers::PASS_INTERRUPT_DACS,
    },
];
#[doc = "Enumeration of all the interrupts."]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
    #[doc = "GPIO Port Interrupt #0"]
    IOSS_INTERRUPTS_GPIO_0 = 0,

    #[doc = "GPIO Port Interrupt #1"]
    IOSS_INTERRUPTS_GPIO_1 = 1,

    #[doc = "GPIO Port Interrupt #2"]
    IOSS_INTERRUPTS_GPIO_2 = 2,

    #[doc = "GPIO Port Interrupt #3"]
    IOSS_INTERRUPTS_GPIO_3 = 3,

    #[doc = "GPIO Port Interrupt #4"]
    IOSS_INTERRUPTS_GPIO_4 = 4,

    #[doc = "GPIO Port Interrupt #5"]
    IOSS_INTERRUPTS_GPIO_5 = 5,

    #[doc = "GPIO Port Interrupt #6"]
    IOSS_INTERRUPTS_GPIO_6 = 6,

    #[doc = "GPIO Port Interrupt #7"]
    IOSS_INTERRUPTS_GPIO_7 = 7,

    #[doc = "GPIO Port Interrupt #8"]
    IOSS_INTERRUPTS_GPIO_8 = 8,

    #[doc = "GPIO Port Interrupt #9"]
    IOSS_INTERRUPTS_GPIO_9 = 9,

    #[doc = "GPIO Port Interrupt #10"]
    IOSS_INTERRUPTS_GPIO_10 = 10,

    #[doc = "GPIO Port Interrupt #11"]
    IOSS_INTERRUPTS_GPIO_11 = 11,

    #[doc = "GPIO Port Interrupt #12"]
    IOSS_INTERRUPTS_GPIO_12 = 12,

    #[doc = "GPIO Port Interrupt #13"]
    IOSS_INTERRUPTS_GPIO_13 = 13,

    #[doc = "GPIO Port Interrupt #14"]
    IOSS_INTERRUPTS_GPIO_14 = 14,

    #[doc = "GPIO All Ports"]
    IOSS_INTERRUPT_GPIO = 15,

    #[doc = "GPIO Supply Detect Interrupt"]
    IOSS_INTERRUPT_VDD = 16,

    #[doc = "Low Power Comparator Interrupt"]
    LPCOMP_INTERRUPT = 17,

    #[doc = "Serial Communication Block #8 (DeepSleep capable)"]
    SCB_8_INTERRUPT = 18,

    #[doc = "Multi Counter Watchdog Timer interrupt"]
    SRSS_INTERRUPT_MCWDT_0 = 19,

    #[doc = "Multi Counter Watchdog Timer interrupt"]
    SRSS_INTERRUPT_MCWDT_1 = 20,

    #[doc = "Backup domain interrupt"]
    SRSS_INTERRUPT_BACKUP = 21,

    #[doc = "Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)"]
    SRSS_INTERRUPT = 22,

    #[doc = "CTBm Interrupt (all CTBms)"]
    PASS_INTERRUPT_CTBS = 23,

    #[doc = "Bluetooth Radio interrupt"]
    BLESS_INTERRUPT = 24,

    #[doc = "CPUSS Inter Process Communication Interrupt #0"]
    CPUSS_INTERRUPTS_IPC_0 = 25,

    #[doc = "CPUSS Inter Process Communication Interrupt #1"]
    CPUSS_INTERRUPTS_IPC_1 = 26,

    #[doc = "CPUSS Inter Process Communication Interrupt #2"]
    CPUSS_INTERRUPTS_IPC_2 = 27,

    #[doc = "CPUSS Inter Process Communication Interrupt #3"]
    CPUSS_INTERRUPTS_IPC_3 = 28,

    #[doc = "CPUSS Inter Process Communication Interrupt #4"]
    CPUSS_INTERRUPTS_IPC_4 = 29,

    #[doc = "CPUSS Inter Process Communication Interrupt #5"]
    CPUSS_INTERRUPTS_IPC_5 = 30,

    #[doc = "CPUSS Inter Process Communication Interrupt #6"]
    CPUSS_INTERRUPTS_IPC_6 = 31,

    #[doc = "CPUSS Inter Process Communication Interrupt #7"]
    CPUSS_INTERRUPTS_IPC_7 = 32,

    #[doc = "CPUSS Inter Process Communication Interrupt #8"]
    CPUSS_INTERRUPTS_IPC_8 = 33,

    #[doc = "CPUSS Inter Process Communication Interrupt #9"]
    CPUSS_INTERRUPTS_IPC_9 = 34,

    #[doc = "CPUSS Inter Process Communication Interrupt #10"]
    CPUSS_INTERRUPTS_IPC_10 = 35,

    #[doc = "CPUSS Inter Process Communication Interrupt #11"]
    CPUSS_INTERRUPTS_IPC_11 = 36,

    #[doc = "CPUSS Inter Process Communication Interrupt #12"]
    CPUSS_INTERRUPTS_IPC_12 = 37,

    #[doc = "CPUSS Inter Process Communication Interrupt #13"]
    CPUSS_INTERRUPTS_IPC_13 = 38,

    #[doc = "CPUSS Inter Process Communication Interrupt #14"]
    CPUSS_INTERRUPTS_IPC_14 = 39,

    #[doc = "CPUSS Inter Process Communication Interrupt #15"]
    CPUSS_INTERRUPTS_IPC_15 = 40,

    #[doc = "Serial Communication Block #0"]
    SCB_0_INTERRUPT = 41,

    #[doc = "Serial Communication Block #1"]
    SCB_1_INTERRUPT = 42,

    #[doc = "Serial Communication Block #2"]
    SCB_2_INTERRUPT = 43,

    #[doc = "Serial Communication Block #3"]
    SCB_3_INTERRUPT = 44,

    #[doc = "Serial Communication Block #4"]
    SCB_4_INTERRUPT = 45,

    #[doc = "Serial Communication Block #5"]
    SCB_5_INTERRUPT = 46,

    #[doc = "Serial Communication Block #6"]
    SCB_6_INTERRUPT = 47,

    #[doc = "Serial Communication Block #7"]
    SCB_7_INTERRUPT = 48,

    #[doc = "CSD (Capsense) interrupt"]
    CSD_INTERRUPT = 49,

    #[doc = "CPUSS DataWire #0, Channel #0"]
    CPUSS_INTERRUPTS_DW0_0 = 50,

    #[doc = "CPUSS DataWire #0, Channel #1"]
    CPUSS_INTERRUPTS_DW0_1 = 51,

    #[doc = "CPUSS DataWire #0, Channel #2"]
    CPUSS_INTERRUPTS_DW0_2 = 52,

    #[doc = "CPUSS DataWire #0, Channel #3"]
    CPUSS_INTERRUPTS_DW0_3 = 53,

    #[doc = "CPUSS DataWire #0, Channel #4"]
    CPUSS_INTERRUPTS_DW0_4 = 54,

    #[doc = "CPUSS DataWire #0, Channel #5"]
    CPUSS_INTERRUPTS_DW0_5 = 55,

    #[doc = "CPUSS DataWire #0, Channel #6"]
    CPUSS_INTERRUPTS_DW0_6 = 56,

    #[doc = "CPUSS DataWire #0, Channel #7"]
    CPUSS_INTERRUPTS_DW0_7 = 57,

    #[doc = "CPUSS DataWire #0, Channel #8"]
    CPUSS_INTERRUPTS_DW0_8 = 58,

    #[doc = "CPUSS DataWire #0, Channel #9"]
    CPUSS_INTERRUPTS_DW0_9 = 59,

    #[doc = "CPUSS DataWire #0, Channel #10"]
    CPUSS_INTERRUPTS_DW0_10 = 60,

    #[doc = "CPUSS DataWire #0, Channel #11"]
    CPUSS_INTERRUPTS_DW0_11 = 61,

    #[doc = "CPUSS DataWire #0, Channel #12"]
    CPUSS_INTERRUPTS_DW0_12 = 62,

    #[doc = "CPUSS DataWire #0, Channel #13"]
    CPUSS_INTERRUPTS_DW0_13 = 63,

    #[doc = "CPUSS DataWire #0, Channel #14"]
    CPUSS_INTERRUPTS_DW0_14 = 64,

    #[doc = "CPUSS DataWire #0, Channel #15"]
    CPUSS_INTERRUPTS_DW0_15 = 65,

    #[doc = "CPUSS DataWire #1, Channel #0"]
    CPUSS_INTERRUPTS_DW1_0 = 66,

    #[doc = "CPUSS DataWire #1, Channel #1"]
    CPUSS_INTERRUPTS_DW1_1 = 67,

    #[doc = "CPUSS DataWire #1, Channel #2"]
    CPUSS_INTERRUPTS_DW1_2 = 68,

    #[doc = "CPUSS DataWire #1, Channel #3"]
    CPUSS_INTERRUPTS_DW1_3 = 69,

    #[doc = "CPUSS DataWire #1, Channel #4"]
    CPUSS_INTERRUPTS_DW1_4 = 70,

    #[doc = "CPUSS DataWire #1, Channel #5"]
    CPUSS_INTERRUPTS_DW1_5 = 71,

    #[doc = "CPUSS DataWire #1, Channel #6"]
    CPUSS_INTERRUPTS_DW1_6 = 72,

    #[doc = "CPUSS DataWire #1, Channel #7"]
    CPUSS_INTERRUPTS_DW1_7 = 73,

    #[doc = "CPUSS DataWire #1, Channel #8"]
    CPUSS_INTERRUPTS_DW1_8 = 74,

    #[doc = "CPUSS DataWire #1, Channel #9"]
    CPUSS_INTERRUPTS_DW1_9 = 75,

    #[doc = "CPUSS DataWire #1, Channel #10"]
    CPUSS_INTERRUPTS_DW1_10 = 76,

    #[doc = "CPUSS DataWire #1, Channel #11"]
    CPUSS_INTERRUPTS_DW1_11 = 77,

    #[doc = "CPUSS DataWire #1, Channel #12"]
    CPUSS_INTERRUPTS_DW1_12 = 78,

    #[doc = "CPUSS DataWire #1, Channel #13"]
    CPUSS_INTERRUPTS_DW1_13 = 79,

    #[doc = "CPUSS DataWire #1, Channel #14"]
    CPUSS_INTERRUPTS_DW1_14 = 80,

    #[doc = "CPUSS DataWire #1, Channel #15"]
    CPUSS_INTERRUPTS_DW1_15 = 81,

    #[doc = "CPUSS Fault Structure Interrupt #0"]
    CPUSS_INTERRUPTS_FAULT_0 = 82,

    #[doc = "CPUSS Fault Structure Interrupt #1"]
    CPUSS_INTERRUPTS_FAULT_1 = 83,

    #[doc = "CRYPTO Accelerator Interrupt"]
    CPUSS_INTERRUPT_CRYPTO = 84,

    #[doc = "FLASH Macro Interrupt"]
    CPUSS_INTERRUPT_FM = 85,

    #[doc = "CM0+ CTI #0"]
    CPUSS_INTERRUPTS_CM0_CTI_0 = 86,

    #[doc = "CM0+ CTI #1"]
    CPUSS_INTERRUPTS_CM0_CTI_1 = 87,

    #[doc = "CM4 CTI #0"]
    CPUSS_INTERRUPTS_CM4_CTI_0 = 88,

    #[doc = "CM4 CTI #1"]
    CPUSS_INTERRUPTS_CM4_CTI_1 = 89,

    #[doc = "TCPWM #0, Counter #0"]
    TCPWM_0_INTERRUPTS_0 = 90,

    #[doc = "TCPWM #0, Counter #1"]
    TCPWM_0_INTERRUPTS_1 = 91,

    #[doc = "TCPWM #0, Counter #2"]
    TCPWM_0_INTERRUPTS_2 = 92,

    #[doc = "TCPWM #0, Counter #3"]
    TCPWM_0_INTERRUPTS_3 = 93,

    #[doc = "TCPWM #0, Counter #4"]
    TCPWM_0_INTERRUPTS_4 = 94,

    #[doc = "TCPWM #0, Counter #5"]
    TCPWM_0_INTERRUPTS_5 = 95,

    #[doc = "TCPWM #0, Counter #6"]
    TCPWM_0_INTERRUPTS_6 = 96,

    #[doc = "TCPWM #0, Counter #7"]
    TCPWM_0_INTERRUPTS_7 = 97,

    #[doc = "TCPWM #1, Counter #0"]
    TCPWM_1_INTERRUPTS_0 = 98,

    #[doc = "TCPWM #1, Counter #1"]
    TCPWM_1_INTERRUPTS_1 = 99,

    #[doc = "TCPWM #1, Counter #2"]
    TCPWM_1_INTERRUPTS_2 = 100,

    #[doc = "TCPWM #1, Counter #3"]
    TCPWM_1_INTERRUPTS_3 = 101,

    #[doc = "TCPWM #1, Counter #4"]
    TCPWM_1_INTERRUPTS_4 = 102,

    #[doc = "TCPWM #1, Counter #5"]
    TCPWM_1_INTERRUPTS_5 = 103,

    #[doc = "TCPWM #1, Counter #6"]
    TCPWM_1_INTERRUPTS_6 = 104,

    #[doc = "TCPWM #1, Counter #7"]
    TCPWM_1_INTERRUPTS_7 = 105,

    #[doc = "TCPWM #1, Counter #8"]
    TCPWM_1_INTERRUPTS_8 = 106,

    #[doc = "TCPWM #1, Counter #9"]
    TCPWM_1_INTERRUPTS_9 = 107,

    #[doc = "TCPWM #1, Counter #10"]
    TCPWM_1_INTERRUPTS_10 = 108,

    #[doc = "TCPWM #1, Counter #11"]
    TCPWM_1_INTERRUPTS_11 = 109,

    #[doc = "TCPWM #1, Counter #12"]
    TCPWM_1_INTERRUPTS_12 = 110,

    #[doc = "TCPWM #1, Counter #13"]
    TCPWM_1_INTERRUPTS_13 = 111,

    #[doc = "TCPWM #1, Counter #14"]
    TCPWM_1_INTERRUPTS_14 = 112,

    #[doc = "TCPWM #1, Counter #15"]
    TCPWM_1_INTERRUPTS_15 = 113,

    #[doc = "TCPWM #1, Counter #16"]
    TCPWM_1_INTERRUPTS_16 = 114,

    #[doc = "TCPWM #1, Counter #17"]
    TCPWM_1_INTERRUPTS_17 = 115,

    #[doc = "TCPWM #1, Counter #18"]
    TCPWM_1_INTERRUPTS_18 = 116,

    #[doc = "TCPWM #1, Counter #19"]
    TCPWM_1_INTERRUPTS_19 = 117,

    #[doc = "TCPWM #1, Counter #20"]
    TCPWM_1_INTERRUPTS_20 = 118,

    #[doc = "TCPWM #1, Counter #21"]
    TCPWM_1_INTERRUPTS_21 = 119,

    #[doc = "TCPWM #1, Counter #22"]
    TCPWM_1_INTERRUPTS_22 = 120,

    #[doc = "TCPWM #1, Counter #23"]
    TCPWM_1_INTERRUPTS_23 = 121,

    #[doc = "UDB Interrupt #0"]
    UDB_INTERRUPTS_0 = 122,

    #[doc = "UDB Interrupt #1"]
    UDB_INTERRUPTS_1 = 123,

    #[doc = "UDB Interrupt #2"]
    UDB_INTERRUPTS_2 = 124,

    #[doc = "UDB Interrupt #3"]
    UDB_INTERRUPTS_3 = 125,

    #[doc = "UDB Interrupt #4"]
    UDB_INTERRUPTS_4 = 126,

    #[doc = "UDB Interrupt #5"]
    UDB_INTERRUPTS_5 = 127,

    #[doc = "UDB Interrupt #6"]
    UDB_INTERRUPTS_6 = 128,

    #[doc = "UDB Interrupt #7"]
    UDB_INTERRUPTS_7 = 129,

    #[doc = "UDB Interrupt #8"]
    UDB_INTERRUPTS_8 = 130,

    #[doc = "UDB Interrupt #9"]
    UDB_INTERRUPTS_9 = 131,

    #[doc = "UDB Interrupt #10"]
    UDB_INTERRUPTS_10 = 132,

    #[doc = "UDB Interrupt #11"]
    UDB_INTERRUPTS_11 = 133,

    #[doc = "UDB Interrupt #12"]
    UDB_INTERRUPTS_12 = 134,

    #[doc = "UDB Interrupt #13"]
    UDB_INTERRUPTS_13 = 135,

    #[doc = "UDB Interrupt #14"]
    UDB_INTERRUPTS_14 = 136,

    #[doc = "UDB Interrupt #15"]
    UDB_INTERRUPTS_15 = 137,

    #[doc = "SAR ADC interrupt"]
    PASS_INTERRUPT_SAR = 138,

    #[doc = "I2S Audio interrupt"]
    AUDIOSS_INTERRUPT_I2S = 139,

    #[doc = "PDM/PCM Audio interrupt"]
    AUDIOSS_INTERRUPT_PDM = 140,

    #[doc = "Energy Profiler interrupt"]
    PROFILE_INTERRUPT = 141,

    #[doc = "Serial Memory Interface interrupt"]
    SMIF_INTERRUPT = 142,

    #[doc = "USB Interrupt"]
    USB_INTERRUPT_HI = 143,

    #[doc = "USB Interrupt"]
    USB_INTERRUPT_MED = 144,

    #[doc = "USB Interrupt"]
    USB_INTERRUPT_LO = 145,

    #[doc = "Consolidated interrrupt for all DACs"]
    PASS_INTERRUPT_DACS = 146,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
    #[inline(always)]
    fn number(self) -> u16 {
        self as u16
    }
}
#[allow(non_snake_case)]
/// Required for compatibility with RTIC and other frameworks
pub struct Peripherals {
    #[cfg(feature = "peri")]
    pub PERI: self::Peri,
    #[cfg(feature = "crypto")]
    pub CRYPTO: self::Crypto,
    #[cfg(feature = "cpuss")]
    pub CPUSS: self::Cpuss,
    #[cfg(feature = "fault")]
    pub FAULT: self::Fault,
    #[cfg(feature = "ipc")]
    pub IPC: self::Ipc,
    #[cfg(feature = "prot")]
    pub PROT: self::Prot,
    #[cfg(feature = "flashc")]
    pub FLASHC: self::Flashc,
    #[cfg(feature = "srss")]
    pub SRSS: self::Srss,
    #[cfg(feature = "backup")]
    pub BACKUP: self::Backup,
    #[cfg(feature = "dw0")]
    pub DW0: self::Dw,
    #[cfg(feature = "dw1")]
    pub DW1: self::Dw,
    #[cfg(feature = "efuse")]
    pub EFUSE: self::Efuse,
    #[cfg(feature = "profile")]
    pub PROFILE: self::Profile,
    #[cfg(feature = "hsiom")]
    pub HSIOM: self::Hsiom,
    #[cfg(feature = "gpio")]
    pub GPIO: self::Gpio,
    #[cfg(feature = "smartio")]
    pub SMARTIO: self::Smartio,
    #[cfg(feature = "lpcomp")]
    pub LPCOMP: self::Lpcomp,
    #[cfg(feature = "csd0")]
    pub CSD0: self::Csd,
    #[cfg(feature = "tcpwm0")]
    pub TCPWM0: self::Tcpwm,
    #[cfg(feature = "tcpwm1")]
    pub TCPWM1: self::Tcpwm,
    #[cfg(feature = "lcd0")]
    pub LCD0: self::Lcd,
    #[cfg(feature = "ble")]
    pub BLE: self::Ble,
    #[cfg(feature = "usbfs0")]
    pub USBFS0: self::Usbfs,
    #[cfg(feature = "smif0")]
    pub SMIF0: self::Smif,
    #[cfg(feature = "scb0")]
    pub SCB0: self::Scb,
    #[cfg(feature = "scb1")]
    pub SCB1: self::Scb,
    #[cfg(feature = "scb2")]
    pub SCB2: self::Scb,
    #[cfg(feature = "scb3")]
    pub SCB3: self::Scb,
    #[cfg(feature = "scb4")]
    pub SCB4: self::Scb,
    #[cfg(feature = "scb5")]
    pub SCB5: self::Scb,
    #[cfg(feature = "scb6")]
    pub SCB6: self::Scb,
    #[cfg(feature = "scb7")]
    pub SCB7: self::Scb,
    #[cfg(feature = "scb8")]
    pub SCB8: self::Scb,
    #[cfg(feature = "ctbm0")]
    pub CTBM0: self::Ctbm,
    #[cfg(feature = "ctdac0")]
    pub CTDAC0: self::Ctdac,
    #[cfg(feature = "sar")]
    pub SAR: self::Sar,
    #[cfg(feature = "pass")]
    pub PASS: self::Pass,
    #[cfg(feature = "i2s0")]
    pub I2S0: self::I2S,
    #[cfg(feature = "pdm0")]
    pub PDM0: self::Pdm,
}

impl Peripherals {
    /// Returns Peripheral struct multiple times
    /// Required for compatibility with RTIC and other frameworks
    #[inline]
    pub fn take() -> Option<Self> {
        Some(Self::steal())
    }

    /// Returns Peripheral struct multiple times
    /// Required for compatibility with RTIC and other frameworks
    #[inline]
    pub fn steal() -> Self {
        Peripherals {
            #[cfg(feature = "peri")]
            PERI: crate::PERI,
            #[cfg(feature = "crypto")]
            CRYPTO: crate::CRYPTO,
            #[cfg(feature = "cpuss")]
            CPUSS: crate::CPUSS,
            #[cfg(feature = "fault")]
            FAULT: crate::FAULT,
            #[cfg(feature = "ipc")]
            IPC: crate::IPC,
            #[cfg(feature = "prot")]
            PROT: crate::PROT,
            #[cfg(feature = "flashc")]
            FLASHC: crate::FLASHC,
            #[cfg(feature = "srss")]
            SRSS: crate::SRSS,
            #[cfg(feature = "backup")]
            BACKUP: crate::BACKUP,
            #[cfg(feature = "dw0")]
            DW0: crate::DW0,
            #[cfg(feature = "dw1")]
            DW1: crate::DW1,
            #[cfg(feature = "efuse")]
            EFUSE: crate::EFUSE,
            #[cfg(feature = "profile")]
            PROFILE: crate::PROFILE,
            #[cfg(feature = "hsiom")]
            HSIOM: crate::HSIOM,
            #[cfg(feature = "gpio")]
            GPIO: crate::GPIO,
            #[cfg(feature = "smartio")]
            SMARTIO: crate::SMARTIO,
            #[cfg(feature = "lpcomp")]
            LPCOMP: crate::LPCOMP,
            #[cfg(feature = "csd0")]
            CSD0: crate::CSD0,
            #[cfg(feature = "tcpwm0")]
            TCPWM0: crate::TCPWM0,
            #[cfg(feature = "tcpwm1")]
            TCPWM1: crate::TCPWM1,
            #[cfg(feature = "lcd0")]
            LCD0: crate::LCD0,
            #[cfg(feature = "ble")]
            BLE: crate::BLE,
            #[cfg(feature = "usbfs0")]
            USBFS0: crate::USBFS0,
            #[cfg(feature = "smif0")]
            SMIF0: crate::SMIF0,
            #[cfg(feature = "scb0")]
            SCB0: crate::SCB0,
            #[cfg(feature = "scb1")]
            SCB1: crate::SCB1,
            #[cfg(feature = "scb2")]
            SCB2: crate::SCB2,
            #[cfg(feature = "scb3")]
            SCB3: crate::SCB3,
            #[cfg(feature = "scb4")]
            SCB4: crate::SCB4,
            #[cfg(feature = "scb5")]
            SCB5: crate::SCB5,
            #[cfg(feature = "scb6")]
            SCB6: crate::SCB6,
            #[cfg(feature = "scb7")]
            SCB7: crate::SCB7,
            #[cfg(feature = "scb8")]
            SCB8: crate::SCB8,
            #[cfg(feature = "ctbm0")]
            CTBM0: crate::CTBM0,
            #[cfg(feature = "ctdac0")]
            CTDAC0: crate::CTDAC0,
            #[cfg(feature = "sar")]
            SAR: crate::SAR,
            #[cfg(feature = "pass")]
            PASS: crate::PASS,
            #[cfg(feature = "i2s0")]
            I2S0: crate::I2S0,
            #[cfg(feature = "pdm0")]
            PDM0: crate::PDM0,
        }
    }
}