/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"Serial Communications Block (SPI/UART/I2C)"]
unsafe impl ::core::marker::Send for super::Scb {}
unsafe impl ::core::marker::Sync for super::Scb {}
impl super::Scb {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "Generic control"]
#[inline(always)]
pub const fn ctrl(&self) -> &'static crate::common::Reg<self::Ctrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Ctrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Generic status"]
#[inline(always)]
pub const fn status(&self) -> &'static crate::common::Reg<self::Status_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::Status_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "Command/response control"]
#[inline(always)]
pub const fn cmd_resp_ctrl(
&self,
) -> &'static crate::common::Reg<self::CmdRespCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CmdRespCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(8usize),
)
}
}
#[doc = "Command/response status"]
#[inline(always)]
pub const fn cmd_resp_status(
&self,
) -> &'static crate::common::Reg<self::CmdRespStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::CmdRespStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(12usize),
)
}
}
#[doc = "SPI control"]
#[inline(always)]
pub const fn spi_ctrl(
&self,
) -> &'static crate::common::Reg<self::SpiCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SpiCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "SPI status"]
#[inline(always)]
pub const fn spi_status(
&self,
) -> &'static crate::common::Reg<self::SpiStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::SpiStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
#[doc = "UART control"]
#[inline(always)]
pub const fn uart_ctrl(
&self,
) -> &'static crate::common::Reg<self::UartCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::UartCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(64usize),
)
}
}
#[doc = "UART transmitter control"]
#[inline(always)]
pub const fn uart_tx_ctrl(
&self,
) -> &'static crate::common::Reg<self::UartTxCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::UartTxCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(68usize),
)
}
}
#[doc = "UART receiver control"]
#[inline(always)]
pub const fn uart_rx_ctrl(
&self,
) -> &'static crate::common::Reg<self::UartRxCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::UartRxCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(72usize),
)
}
}
#[doc = "UART receiver status"]
#[inline(always)]
pub const fn uart_rx_status(
&self,
) -> &'static crate::common::Reg<self::UartRxStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::UartRxStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(76usize),
)
}
}
#[doc = "UART flow control"]
#[inline(always)]
pub const fn uart_flow_ctrl(
&self,
) -> &'static crate::common::Reg<self::UartFlowCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::UartFlowCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(80usize),
)
}
}
#[doc = "I2C control"]
#[inline(always)]
pub const fn i2c_ctrl(
&self,
) -> &'static crate::common::Reg<self::I2CCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::I2CCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(96usize),
)
}
}
#[doc = "I2C status"]
#[inline(always)]
pub const fn i2c_status(
&self,
) -> &'static crate::common::Reg<self::I2CStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::I2CStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(100usize),
)
}
}
#[doc = "I2C master command"]
#[inline(always)]
pub const fn i2c_m_cmd(
&self,
) -> &'static crate::common::Reg<self::I2CMCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::I2CMCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(104usize),
)
}
}
#[doc = "I2C slave command"]
#[inline(always)]
pub const fn i2c_s_cmd(
&self,
) -> &'static crate::common::Reg<self::I2CSCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::I2CSCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(108usize),
)
}
}
#[doc = "I2C configuration"]
#[inline(always)]
pub const fn i2c_cfg(
&self,
) -> &'static crate::common::Reg<self::I2CCfg_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::I2CCfg_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(112usize),
)
}
}
#[doc = "Transmitter control"]
#[inline(always)]
pub const fn tx_ctrl(
&self,
) -> &'static crate::common::Reg<self::TxCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TxCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(512usize),
)
}
}
#[doc = "Transmitter FIFO control"]
#[inline(always)]
pub const fn tx_fifo_ctrl(
&self,
) -> &'static crate::common::Reg<self::TxFifoCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TxFifoCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(516usize),
)
}
}
#[doc = "Transmitter FIFO status"]
#[inline(always)]
pub const fn tx_fifo_status(
&self,
) -> &'static crate::common::Reg<self::TxFifoStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::TxFifoStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(520usize),
)
}
}
#[doc = "Transmitter FIFO write"]
#[inline(always)]
pub const fn tx_fifo_wr(
&self,
) -> &'static crate::common::Reg<self::TxFifoWr_SPEC, crate::common::W> {
unsafe {
crate::common::Reg::<self::TxFifoWr_SPEC, crate::common::W>::from_ptr(
self._svd2pac_as_ptr().add(576usize),
)
}
}
#[doc = "Receiver control"]
#[inline(always)]
pub const fn rx_ctrl(
&self,
) -> &'static crate::common::Reg<self::RxCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::RxCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(768usize),
)
}
}
#[doc = "Receiver FIFO control"]
#[inline(always)]
pub const fn rx_fifo_ctrl(
&self,
) -> &'static crate::common::Reg<self::RxFifoCtrl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::RxFifoCtrl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(772usize),
)
}
}
#[doc = "Receiver FIFO status"]
#[inline(always)]
pub const fn rx_fifo_status(
&self,
) -> &'static crate::common::Reg<self::RxFifoStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::RxFifoStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(776usize),
)
}
}
#[doc = "Slave address and mask"]
#[inline(always)]
pub const fn rx_match(
&self,
) -> &'static crate::common::Reg<self::RxMatch_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::RxMatch_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(784usize),
)
}
}
#[doc = "Receiver FIFO read"]
#[inline(always)]
pub const fn rx_fifo_rd(
&self,
) -> &'static crate::common::Reg<self::RxFifoRd_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::RxFifoRd_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(832usize),
)
}
}
#[doc = "Receiver FIFO read silent"]
#[inline(always)]
pub const fn rx_fifo_rd_silent(
&self,
) -> &'static crate::common::Reg<self::RxFifoRdSilent_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::RxFifoRdSilent_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(836usize),
)
}
}
#[doc = "Active clocked interrupt signal"]
#[inline(always)]
pub const fn intr_cause(
&self,
) -> &'static crate::common::Reg<self::IntrCause_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrCause_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(3584usize),
)
}
}
#[doc = "Externally clocked I2C interrupt request"]
#[inline(always)]
pub const fn intr_i2c_ec(
&self,
) -> &'static crate::common::Reg<self::IntrI2CEc_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrI2CEc_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3712usize),
)
}
}
#[doc = "Externally clocked I2C interrupt mask"]
#[inline(always)]
pub const fn intr_i2c_ec_mask(
&self,
) -> &'static crate::common::Reg<self::IntrI2CEcMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrI2CEcMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3720usize),
)
}
}
#[doc = "Externally clocked I2C interrupt masked"]
#[inline(always)]
pub const fn intr_i2c_ec_masked(
&self,
) -> &'static crate::common::Reg<self::IntrI2CEcMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrI2CEcMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(3724usize),
)
}
}
#[doc = "Externally clocked SPI interrupt request"]
#[inline(always)]
pub const fn intr_spi_ec(
&self,
) -> &'static crate::common::Reg<self::IntrSpiEc_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrSpiEc_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3776usize),
)
}
}
#[doc = "Externally clocked SPI interrupt mask"]
#[inline(always)]
pub const fn intr_spi_ec_mask(
&self,
) -> &'static crate::common::Reg<self::IntrSpiEcMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrSpiEcMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3784usize),
)
}
}
#[doc = "Externally clocked SPI interrupt masked"]
#[inline(always)]
pub const fn intr_spi_ec_masked(
&self,
) -> &'static crate::common::Reg<self::IntrSpiEcMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrSpiEcMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(3788usize),
)
}
}
#[doc = "Master interrupt request"]
#[inline(always)]
pub const fn intr_m(&self) -> &'static crate::common::Reg<self::IntrM_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrM_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3840usize),
)
}
}
#[doc = "Master interrupt set request"]
#[inline(always)]
pub const fn intr_m_set(
&self,
) -> &'static crate::common::Reg<self::IntrMSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrMSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3844usize),
)
}
}
#[doc = "Master interrupt mask"]
#[inline(always)]
pub const fn intr_m_mask(
&self,
) -> &'static crate::common::Reg<self::IntrMMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrMMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3848usize),
)
}
}
#[doc = "Master interrupt masked request"]
#[inline(always)]
pub const fn intr_m_masked(
&self,
) -> &'static crate::common::Reg<self::IntrMMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrMMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(3852usize),
)
}
}
#[doc = "Slave interrupt request"]
#[inline(always)]
pub const fn intr_s(&self) -> &'static crate::common::Reg<self::IntrS_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrS_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3904usize),
)
}
}
#[doc = "Slave interrupt set request"]
#[inline(always)]
pub const fn intr_s_set(
&self,
) -> &'static crate::common::Reg<self::IntrSSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrSSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3908usize),
)
}
}
#[doc = "Slave interrupt mask"]
#[inline(always)]
pub const fn intr_s_mask(
&self,
) -> &'static crate::common::Reg<self::IntrSMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrSMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3912usize),
)
}
}
#[doc = "Slave interrupt masked request"]
#[inline(always)]
pub const fn intr_s_masked(
&self,
) -> &'static crate::common::Reg<self::IntrSMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrSMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(3916usize),
)
}
}
#[doc = "Transmitter interrupt request"]
#[inline(always)]
pub const fn intr_tx(
&self,
) -> &'static crate::common::Reg<self::IntrTx_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrTx_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3968usize),
)
}
}
#[doc = "Transmitter interrupt set request"]
#[inline(always)]
pub const fn intr_tx_set(
&self,
) -> &'static crate::common::Reg<self::IntrTxSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrTxSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3972usize),
)
}
}
#[doc = "Transmitter interrupt mask"]
#[inline(always)]
pub const fn intr_tx_mask(
&self,
) -> &'static crate::common::Reg<self::IntrTxMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrTxMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3976usize),
)
}
}
#[doc = "Transmitter interrupt masked request"]
#[inline(always)]
pub const fn intr_tx_masked(
&self,
) -> &'static crate::common::Reg<self::IntrTxMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrTxMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(3980usize),
)
}
}
#[doc = "Receiver interrupt request"]
#[inline(always)]
pub const fn intr_rx(
&self,
) -> &'static crate::common::Reg<self::IntrRx_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrRx_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4032usize),
)
}
}
#[doc = "Receiver interrupt set request"]
#[inline(always)]
pub const fn intr_rx_set(
&self,
) -> &'static crate::common::Reg<self::IntrRxSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrRxSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4036usize),
)
}
}
#[doc = "Receiver interrupt mask"]
#[inline(always)]
pub const fn intr_rx_mask(
&self,
) -> &'static crate::common::Reg<self::IntrRxMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrRxMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4040usize),
)
}
}
#[doc = "Receiver interrupt masked request"]
#[inline(always)]
pub const fn intr_rx_masked(
&self,
) -> &'static crate::common::Reg<self::IntrRxMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrRxMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(4044usize),
)
}
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctrl_SPEC;
impl crate::sealed::RegSpec for Ctrl_SPEC {
type DataType = u32;
}
#[doc = "Generic control"]
pub type Ctrl = crate::RegValueT<Ctrl_SPEC>;
impl Ctrl {
#[doc = "N/A"]
#[inline(always)]
pub fn ovs(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0xf,1,0,u8,u8,Ctrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave)\n\'0\': Internally clocked mode \n\'1\': Externally clocked mode \n\nIn internally clocked mode the address detection(and slave selection detection) is done by clk_scb, and thus won\'t be done in deep sleep power mode as clk_scb isn\'t active. \nIn externally clocked mode the address detection is done by the I2C/SPI interface clock. This allows for the device to be awoken on I2C salve address match and SPI slave select assertion.\n\nThe clocking for the rest of the logic is determined by CTRL.EC_OP_MODE.\n\nExternally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported.\n\nIn UART mode this field must be \'0\'."]
#[inline(always)]
pub fn ec_am_mode(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "This field specifies the clocking for the SCB block after the address phase\n\'0\': Internally clocked mode \n\'1\': externally clocked mode\n\nIn internally clocked mode, the serial interface protocols run off the clk_scb. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. \n\nExternally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. \n\nIn UART mode this field must be \'0\'."]
#[inline(always)]
pub fn ec_op_mode(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "This field determines if EZ mode is enabled or disabled for the SCB block\n\'0\': EZ Mode Disabled\n\'1\': EZ Mode Enabled\n\nIn EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. \n\nEZ mode can only be used for synchronous serial interface protocols (SPI and I2C) in slave mode. \n\nIn SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The external master should use continuous data frames; i.e. data frames not seperated by slave deselection. \n\nIn EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first.\n\nIn UART mode this field must be \'0\'."]
#[inline(always)]
pub fn ez_mode(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn byte_mode(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Determines CMD_RESP mode of operation:\n\'0\': CMD_RESP mode disabled.\n\'1\': CMD_RESP mode enabled (also requires EC_AM_MODE and EC_OP_MODE to be set to \'1\').\n\nIn CMD_RESP mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a write memory data element or a read memory data element. The difference from EZ mode is that the address is written by the CPU, not the interface master.\n\nCMD_RESP mode can only be used for synchronous serial interface protocols (SPI and I2C) in slave mode. \n\nIn SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The external master should use continuous data frames; i.e. data frames not seperated by slave deselection. \n\nIn CMD_RESP mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first.\n\nIn UART mode this field must be \'0\'."]
#[inline(always)]
pub fn cmd_resp_mode(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Determines whether a received matching address is accepted in the RX FIFO:.\n\'0\': Matching address does not go in RX FIFO\n\'1\': Match address does go in RX FIFO\n\nIn I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when this bit is \'1\' for both I2C read and write transfers.\n\nIn multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. \n\nNote: non-matching addresses are never put in the RX FIFO. \n\nIn SPI mode this field must be \'0\'"]
#[inline(always)]
pub fn addr_accept(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states \n\'0\': Do not block, but ingore a write and return 0xffff:ffff for a read\n\'1\': Block, resulting in CPU wait states. \n\nIf BLOCK is \'0\' and the accesses collide, CPU read operations return 0xffff:ffff and CPU write operations are ignored. Colliding accesses are registered as interrupt causes: field BLOCKED of the INTR_TX and INTR_RX registers."]
#[inline(always)]
pub fn block(self) -> crate::common::RegisterFieldBool<17, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mode(
self,
) -> crate::common::RegisterField<
24,
0x3,
1,
0,
ctrl::Mode,
ctrl::Mode,
Ctrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
24,
0x3,
1,
0,
ctrl::Mode,
ctrl::Mode,
Ctrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "0\': Block Disabled\n\'1\': Block Enabled\n\nThe proper order in which to initialize the SCB is as follows:\n- Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable.\n- Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality.\n- Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information.\n- Program CTRL to enable SCB, select the specific operation mode and oversampling factor.\nWhen the SCB is enabled, no control information should be changed. Changes must be made AFTER disabling the SCB, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the SCB is re-enabled. Note that disabling the SCB will cause re-initialization of the design and associated state is lost (e.g. FIFO content)."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Ctrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31, 1, 0, Ctrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Ctrl {
#[inline(always)]
fn default() -> Ctrl {
<crate::RegValueT<Ctrl_SPEC> as RegisterValue<_>>::new(50331663)
}
}
pub mod ctrl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Mode_SPEC;
pub type Mode = crate::EnumBitfieldStruct<u8, Mode_SPEC>;
impl Mode {
#[doc = "Inter-Integrated Circuits (I2C) mode."]
pub const I_2_C: Self = Self::new(0);
#[doc = "Serial Peripheral Interface (SPI) mode."]
pub const SPI: Self = Self::new(1);
#[doc = "Universal Asynchronous Receiver/Transmitter (UART) mode."]
pub const UART: Self = Self::new(2);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Status_SPEC;
impl crate::sealed::RegSpec for Status_SPEC {
type DataType = u32;
}
#[doc = "Generic status"]
pub type Status = crate::RegValueT<Status_SPEC>;
impl Status {
#[doc = "Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus wait states (a blocked CPU access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether CPU access was actually blocked by externally clocked logic."]
#[inline(always)]
pub fn ec_busy(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Status {
#[inline(always)]
fn default() -> Status {
<crate::RegValueT<Status_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CmdRespCtrl_SPEC;
impl crate::sealed::RegSpec for CmdRespCtrl_SPEC {
type DataType = u32;
}
#[doc = "Command/response control"]
pub type CmdRespCtrl = crate::RegValueT<CmdRespCtrl_SPEC>;
impl CmdRespCtrl {
#[doc = "I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."]
#[inline(always)]
pub fn base_rd_addr(
self,
) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, CmdRespCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,CmdRespCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."]
#[inline(always)]
pub fn base_wr_addr(
self,
) -> crate::common::RegisterField<16, 0x1ff, 1, 0, u16, u16, CmdRespCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x1ff,1,0,u16,u16,CmdRespCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CmdRespCtrl {
#[inline(always)]
fn default() -> CmdRespCtrl {
<crate::RegValueT<CmdRespCtrl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CmdRespStatus_SPEC;
impl crate::sealed::RegSpec for CmdRespStatus_SPEC {
type DataType = u32;
}
#[doc = "Command/response status"]
pub type CmdRespStatus = crate::RegValueT<CmdRespStatus_SPEC>;
impl CmdRespStatus {
#[doc = "I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximim memory buffer address). \n\nThe field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR). \n\nThis field is reliable when there is no bus transfer. This field is potentially unreliable when there is a ongoing bus transfer, i.e. when CMD_RESP_EC_BUSY is \'0\', the field is reliable."]
#[inline(always)]
pub fn curr_rd_addr(
self,
) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, CmdRespStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,CmdRespStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximim memory buffer address).\n\nThe field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR).\n\nThis field is reliable when there is no bus transfer. This field is potentially unreliable when there is a ongoing bus transfer, i.e when CMD_RESP_EC_BUSY is \'0\', the field is reliable."]
#[inline(always)]
pub fn curr_wr_addr(
self,
) -> crate::common::RegisterField<16, 0x1ff, 1, 0, u16, u16, CmdRespStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<
16,
0x1ff,
1,
0,
u16,
u16,
CmdRespStatus_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "Indicates whether there is an ongoing bus transfer to the SCB.\n\'0\': no ongoing bus transfer.\n\'1\': ongoing bus transfer.\n\nFor SPI, the field is \'1\' when slave mode is selected.\n\nFor I2C, the field is set to \'1\' at a I2C START/RESTART. In case of an address match, the field is set to \'0\' on a I2C STOP. In case of NO address match, the field is set to \'0\' after the failing address match."]
#[inline(always)]
pub fn cmd_resp_ec_bus_busy(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, CmdRespStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<30,1,0,CmdRespStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn cmd_resp_ec_busy(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, CmdRespStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<31,1,0,CmdRespStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for CmdRespStatus {
#[inline(always)]
fn default() -> CmdRespStatus {
<crate::RegValueT<CmdRespStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SpiCtrl_SPEC;
impl crate::sealed::RegSpec for SpiCtrl_SPEC {
type DataType = u32;
}
#[doc = "SPI control"]
pub type SpiCtrl = crate::RegValueT<SpiCtrl_SPEC>;
impl SpiCtrl {
#[doc = "Continuous SPI data transfers enabled (\'1\') or not (\'0\'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field.\n\nWhen continuous transfers are enabled indiviual data transfers are NOT seperated by slave select deselection as long as there is data in the TX FIFO. If the TX FIFO becomes empty then the slave select will be deselected. \n\nWhen continuous transfers are not enabled individual data frame transfers are always seperated by slave select deselection: independent of the availability of TX FIFO data frames."]
#[inline(always)]
pub fn ssel_continuous(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, SpiCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, SpiCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Only used in SPI Texas Instruments\' submode.\n\nWhen \'1\', the data frame start indication is a pulse on the Slave SELECT line that precedes the transfer of the first data frame bit.\n\nWhen \'0\', the data frame start indication is a pulse on the Slave SELECT line that coincides with the transfer of the first data frame bit."]
#[inline(always)]
pub fn select_precede(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, SpiCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, SpiCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn cpha(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, SpiCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, SpiCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn cpol(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, SpiCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, SpiCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Changes the SCLK edge on which MISO is captured. Only used in master mode.\n\nWhen \'0\', the default applies (\nfor Motorola as determined by CPOL and CPHA, \nfor Texas Instruments on the falling edge of SCLK and \nfor National Semiconductors on the rising edge of SCLK). \n\nWhen \'1\', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master."]
#[inline(always)]
pub fn late_miso_sample(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, SpiCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, SpiCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn sclk_continuous(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, SpiCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, SpiCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn ssel_polarity0(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, SpiCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, SpiCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn ssel_polarity1(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, SpiCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9, 1, 0, SpiCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn ssel_polarity2(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, SpiCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10, 1, 0, SpiCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn ssel_polarity3(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, SpiCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11, 1, 0, SpiCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode.\n\'0\': No local loopback\n\'1\': the SPI master MISO line is connected to the SPI master MOSI line. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI."]
#[inline(always)]
pub fn loopback(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, SpiCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16, 1, 0, SpiCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mode(
self,
) -> crate::common::RegisterField<
24,
0x3,
1,
0,
spi_ctrl::Mode,
spi_ctrl::Mode,
SpiCtrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
24,
0x3,
1,
0,
spi_ctrl::Mode,
spi_ctrl::Mode,
SpiCtrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Selects one of the four incoming/outgoing SPI slave select signals:\n- 0: Slave 0, SSEL\\[0\\].\n- 1: Slave 1, SSEL\\[1\\].\n- 2: Slave 2, SSEL\\[2\\].\n- 3: Slave 3, SSEL\\[3\\].\nThe SCB should be disabled when changes are made to this field."]
#[inline(always)]
pub fn ssel(
self,
) -> crate::common::RegisterField<26, 0x3, 1, 0, u8, u8, SpiCtrl_SPEC, crate::common::RW> {
crate::common::RegisterField::<26,0x3,1,0,u8,u8,SpiCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn master_mode(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, SpiCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31, 1, 0, SpiCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for SpiCtrl {
#[inline(always)]
fn default() -> SpiCtrl {
<crate::RegValueT<SpiCtrl_SPEC> as RegisterValue<_>>::new(50331648)
}
}
pub mod spi_ctrl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Mode_SPEC;
pub type Mode = crate::EnumBitfieldStruct<u8, Mode_SPEC>;
impl Mode {
#[doc = "SPI Motorola submode. In master mode, when not transmitting data (SELECT is inactive), SCLK is stable at CPOL. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive."]
pub const SPI_MOTOROLA: Self = Self::new(0);
#[doc = "SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is stable at \'0\'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive; i.e. no pulse is generated."]
pub const SPI_TI: Self = Self::new(1);
#[doc = "SPI National Semiconductors submode. In master mode, when not transmitting data, SCLK is stable at \'0\'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive."]
pub const SPI_NS: Self = Self::new(2);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SpiStatus_SPEC;
impl crate::sealed::RegSpec for SpiStatus_SPEC {
type DataType = u32;
}
#[doc = "SPI status"]
pub type SpiStatus = crate::RegValueT<SpiStatus_SPEC>;
impl SpiStatus {
#[doc = "N/A"]
#[inline(always)]
pub fn bus_busy(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, SpiStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, SpiStatus_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and CURR_ADDR are reliable."]
#[inline(always)]
pub fn spi_ec_busy(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, SpiStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1, 1, 0, SpiStatus_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is \'1\')."]
#[inline(always)]
pub fn curr_ez_addr(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, SpiStatus_SPEC, crate::common::R> {
crate::common::RegisterField::<8,0xff,1,0,u8,u8,SpiStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."]
#[inline(always)]
pub fn base_ez_addr(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, SpiStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,SpiStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for SpiStatus {
#[inline(always)]
fn default() -> SpiStatus {
<crate::RegValueT<SpiStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UartCtrl_SPEC;
impl crate::sealed::RegSpec for UartCtrl_SPEC {
type DataType = u32;
}
#[doc = "UART control"]
pub type UartCtrl = crate::RegValueT<UartCtrl_SPEC>;
impl UartCtrl {
#[doc = "Local loopback control (does NOT affect the information on the pins). \n0: Loopback is not enabled\n1: UART_TX is connected to UART_RX. UART_RTS is connected to UART_CTS.\nThis allows a SCB UART transmitter to communicate with its receiver counterpart."]
#[inline(always)]
pub fn loopback(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, UartCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,UartCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mode(
self,
) -> crate::common::RegisterField<
24,
0x3,
1,
0,
uart_ctrl::Mode,
uart_ctrl::Mode,
UartCtrl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
24,
0x3,
1,
0,
uart_ctrl::Mode,
uart_ctrl::Mode,
UartCtrl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for UartCtrl {
#[inline(always)]
fn default() -> UartCtrl {
<crate::RegValueT<UartCtrl_SPEC> as RegisterValue<_>>::new(50331648)
}
}
pub mod uart_ctrl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Mode_SPEC;
pub type Mode = crate::EnumBitfieldStruct<u8, Mode_SPEC>;
impl Mode {
#[doc = "Standard UART submode."]
pub const UART_STD: Self = Self::new(0);
#[doc = "SmartCard (ISO7816) submode. Support for negative acknowledgement (NACK) on the receiver side and retransmission on the transmitter side."]
pub const UART_SMARTCARD: Self = Self::new(1);
#[doc = "Infrared Data Association (IrDA) submode. Return to Zero modulation scheme."]
pub const UART_IRDA: Self = Self::new(2);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UartTxCtrl_SPEC;
impl crate::sealed::RegSpec for UartTxCtrl_SPEC {
type DataType = u32;
}
#[doc = "UART transmitter control"]
pub type UartTxCtrl = crate::RegValueT<UartTxCtrl_SPEC>;
impl UartTxCtrl {
#[doc = "Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is \\[1, 7\\]; i.e. a stop period should last at least one bit period."]
#[inline(always)]
pub fn stop_bits(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, UartTxCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,UartTxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn parity(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, UartTxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,UartTxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn parity_enabled(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, UartTxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,UartTxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn retry_on_nack(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, UartTxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,UartTxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for UartTxCtrl {
#[inline(always)]
fn default() -> UartTxCtrl {
<crate::RegValueT<UartTxCtrl_SPEC> as RegisterValue<_>>::new(2)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UartRxCtrl_SPEC;
impl crate::sealed::RegSpec for UartRxCtrl_SPEC {
type DataType = u32;
}
#[doc = "UART receiver control"]
pub type UartRxCtrl = crate::RegValueT<UartRxCtrl_SPEC>;
impl UartRxCtrl {
#[doc = "Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is \\[1, 7\\]; i.e. a stop period should last at least one bit period. \n\nNote that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle time between data frames and the data frame value."]
#[inline(always)]
pub fn stop_bits(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, UartRxCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,UartRxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn parity(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, UartRxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,UartRxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn parity_enabled(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, UartRxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,UartRxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Inverts incoming RX line signal \'uart_rx_in\'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality."]
#[inline(always)]
pub fn polarity(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, UartRxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,UartRxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn drop_on_parity_error(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, UartRxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,UartRxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Behaviour when an error is detected in a start or stop period. When \'0\', received data is sent to the RX FIFO. When \'1\', received data is dropped and lost."]
#[inline(always)]
pub fn drop_on_frame_error(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, UartRxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,UartRxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Multi-processor mode. When \'1\', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode, the 9th received bit of a data frame seperates addresses (bit is \'1\') from data (bit is \'0\'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data is sent to the RX FIFO. In the case of NO match, subsequent received data is dropped."]
#[inline(always)]
pub fn mp_mode(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, UartRxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,UartRxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Only applicable in standard UART submode. When \'1\', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of \'0\'. BREAK_WIDTH specifies the minum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to \'1\'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to \'1\' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte."]
#[inline(always)]
pub fn lin_mode(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, UartRxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12,1,0,UartRxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Only applicable in standard UART submode. When \'1\', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a \'1\'. \n\nThis functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle (\'1\') to START (\'0\') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO. \n\nThe woken up CPU will enable the SCB\'s UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will then synchronize to a \'0\' to \'1\' transition, which indicates the first data frame bit is received (first data frame bit should be \'1\'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit."]
#[inline(always)]
pub fn skip_start(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, UartRxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<13,1,0,UartRxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is \'0\'. This feature is useful for standard UART submode and LIN submode (\'break field\' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to \'1\'. \n\nNote for LIN the break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver\'s definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive \'0\' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive \'0\' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value."]
#[inline(always)]
pub fn break_width(
self,
) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, UartRxCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xf,1,0,u8,u8,UartRxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for UartRxCtrl {
#[inline(always)]
fn default() -> UartRxCtrl {
<crate::RegValueT<UartRxCtrl_SPEC> as RegisterValue<_>>::new(655362)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UartRxStatus_SPEC;
impl crate::sealed::RegSpec for UartRxStatus_SPEC {
type DataType = u32;
}
#[doc = "UART receiver status"]
pub type UartRxStatus = crate::RegValueT<UartRxStatus_SPEC>;
impl UartRxStatus {
#[doc = "For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to \'1\'."]
#[inline(always)]
pub fn br_counter(
self,
) -> crate::common::RegisterField<0, 0xfff, 1, 0, u16, u16, UartRxStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xfff,1,0,u16,u16,UartRxStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for UartRxStatus {
#[inline(always)]
fn default() -> UartRxStatus {
<crate::RegValueT<UartRxStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UartFlowCtrl_SPEC;
impl crate::sealed::RegSpec for UartFlowCtrl_SPEC {
type DataType = u32;
}
#[doc = "UART flow control"]
pub type UartFlowCtrl = crate::RegValueT<UartFlowCtrl_SPEC>;
impl UartFlowCtrl {
#[doc = "Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal is activated. By setting this field to \'0\', flow control is disabled"]
#[inline(always)]
pub fn trigger_level(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, UartFlowCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,UartFlowCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Polarity of the RTS output signal:\n\'0\': RTS is active low; \n\'1\': RTS is active high; \n\nDuring SCB reset (Hibernate system power mode), RTS output signal is \'1\'. This represents an inactive state assuming an active low polarity."]
#[inline(always)]
pub fn rts_polarity(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, UartFlowCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,UartFlowCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Polarity of the CTS input signal\n\'0\': CTS is active low ; \n\'1\': CTS is active high;"]
#[inline(always)]
pub fn cts_polarity(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, UartFlowCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,UartFlowCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Enable use of CTS input signal by the UART transmitter:\n\'0\': Disabled. The UART transmitter ignores the CTS input signal and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register.\n\'1\': Enabled. The UART transmitter uses CTS input signal to qualify the transmission of data. It transmits when CTS input signal is active and a data frame is available for transmission in the TX FIFO or the TX shift register.\n\nIf UART_CTRL.LOOPBACK is \'1\', the CTS input signal is driven by the RTS output signal locally in SCB (both signals are subjected to signal polarity changes as indicated by RTS_POLARITY and CTS_POLARITY)."]
#[inline(always)]
pub fn cts_enabled(
self,
) -> crate::common::RegisterFieldBool<25, 1, 0, UartFlowCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<25,1,0,UartFlowCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for UartFlowCtrl {
#[inline(always)]
fn default() -> UartFlowCtrl {
<crate::RegValueT<UartFlowCtrl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct I2CCtrl_SPEC;
impl crate::sealed::RegSpec for I2CCtrl_SPEC {
type DataType = u32;
}
#[doc = "I2C control"]
pub type I2CCtrl = crate::RegValueT<I2CCtrl_SPEC>;
impl I2CCtrl {
#[doc = "Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is \\[5, 15\\] with input signal median filtering and \\[4, 15\\] without input signal median filtering.\n\nThe field is only used in master mode. In slave mode, the field is NOT used. See architecture TRM for information on slave data rate requirments."]
#[inline(always)]
pub fn high_phase_ovs(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, I2CCtrl_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0xf,1,0,u8,u8,I2CCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is \\[7, 15\\] with input signal median filtering and \\[6, 15\\] without input signal median filtering. \n\nThe field is only used in master mode. In slave mode, the field is NOT used. See architecture TRM for information on slave data rate requirments."]
#[inline(always)]
pub fn low_phase_ovs(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, I2CCtrl_SPEC, crate::common::RW> {
crate::common::RegisterField::<4,0xf,1,0,u8,u8,I2CCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When \'1\', a received data element by the master is immediately ACK\'d when the RX FIFO is not full. When \'0\' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK"]
#[inline(always)]
pub fn m_ready_data_ack(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, I2CCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, I2CCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "When \'1\', a received data element by the master is immediately NACK\'d when the RX FIFO is full. When \'0\', clock stretching is used instead (till the RX FIFO is no longer full)."]
#[inline(always)]
pub fn m_not_ready_data_nack(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, I2CCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9, 1, 0, I2CCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "When \'1\', a received general call slave address is immediately NACK\'d (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure.\nWhen \'0\' the general call address is accepted and follows S_READY_ADDR_ACK and S_NOT_READY_ADDR_NACK"]
#[inline(always)]
pub fn s_general_ignore(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, I2CCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11, 1, 0, I2CCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "When \'1\', a received (matching) slave address is immediately ACK\'d when the RX FIFO is not full. In EZ and CMD_RESP mode, this field should be set to \'1\'.\nWhen \'0\' the address must be ACK/NACK\'d by the CPU using I2C_S_CMD.S_ACK or I2C_S_CMD.S_NACK"]
#[inline(always)]
pub fn s_ready_addr_ack(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, I2CCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12, 1, 0, I2CCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "When \'1\', a received data element by the slave is immediately ACK\'d when the RX FIFO is not full. In EZ and CMD_RESP mode, this field should be set to \'1\'.\nWhen \'0\' the data must be ACK/NACK\'d by the CPU using I2C_S_CMD.S_ACK or I2C_S_CMD.S_NACK"]
#[inline(always)]
pub fn s_ready_data_ack(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, I2CCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<13, 1, 0, I2CCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Only used for FIFO mode, NOT EZ or CMD_RESP mode.\n\nFunctionality is as follows:\n- 1: In Active/Sleep mode a received (matching) slave address is immediately NACK\'d when the RX FIFO is full\nIn DeepSleep power mode when EC_AM = \'1\' and EC_OP = \'0\' clk_scb is not avaliable, so the incoming address will be NACK\'d until the clock is avaliable. Once clk_scb is avaliable the address ACK will follow S_READY_ADDR_ACK\n- 0: in Active/Sleep mode clock stretching is performed when the RX FIFO is full, the strech is released when the RX FIFO is no longer full.\nIn DeepSleep power mode when EC_AM = \'1\' and EC_OP = \'0\' clk_scb is not avaliable, so the clocked will be streched on an incoming address until clk_scb is avaliable. After clk_scb is avalaible the address ACK will follow S_READY_ADDR_ACK"]
#[inline(always)]
pub fn s_not_ready_addr_nack(
self,
) -> crate::common::RegisterFieldBool<14, 1, 0, I2CCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<14, 1, 0, I2CCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Only used for FIFO mode, NOT EZ or CMD_RESP mode.\n\nFunctionality is as follows:\n- 1: a received data element byte the slave is immediately NACK\'d when the receiver FIFO is full.\n- 0: clock stretching is performed (till the receiver FIFO is no longer full)."]
#[inline(always)]
pub fn s_not_ready_data_nack(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, I2CCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<15, 1, 0, I2CCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. \nWhen \'0\', no loopback\nWhen \'1\', loopback is enabled internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself."]
#[inline(always)]
pub fn loopback(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, I2CCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16, 1, 0, I2CCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn slave_mode(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, I2CCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30, 1, 0, I2CCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Master mode enabled (\'1\') or not (\'0\'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself."]
#[inline(always)]
pub fn master_mode(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, I2CCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31, 1, 0, I2CCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for I2CCtrl {
#[inline(always)]
fn default() -> I2CCtrl {
<crate::RegValueT<I2CCtrl_SPEC> as RegisterValue<_>>::new(64392)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct I2CStatus_SPEC;
impl crate::sealed::RegSpec for I2CStatus_SPEC {
type DataType = u32;
}
#[doc = "I2C status"]
pub type I2CStatus = crate::RegValueT<I2CStatus_SPEC>;
impl I2CStatus {
#[doc = "I2C bus is busy. The bus is considered busy (\'1\'), from the time a START is detected or from the time the SCL line is \'0\'. The bus is considered idle (\'0\'), from the time a STOP is detected. If the SCB is disabled, BUS_BUSY is \'0\'. After enabling the SCB, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period).\n\nFor single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions).\n\nFor multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions)."]
#[inline(always)]
pub fn bus_busy(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, I2CStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, I2CStatus_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_EZ_ADDR and CURR_EZ_ADDR are reliable."]
#[inline(always)]
pub fn i2c_ec_busy(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, I2CStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1, 1, 0, I2CStatus_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn s_read(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, I2CStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4, 1, 0, I2CStatus_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn m_read(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, I2CStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5, 1, 0, I2CStatus_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is \'1\')."]
#[inline(always)]
pub fn curr_ez_addr(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, I2CStatus_SPEC, crate::common::R> {
crate::common::RegisterField::<8,0xff,1,0,u8,u8,I2CStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable."]
#[inline(always)]
pub fn base_ez_addr(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, I2CStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,I2CStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for I2CStatus {
#[inline(always)]
fn default() -> I2CStatus {
<crate::RegValueT<I2CStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct I2CMCmd_SPEC;
impl crate::sealed::RegSpec for I2CMCmd_SPEC {
type DataType = u32;
}
#[doc = "I2C master command"]
pub type I2CMCmd = crate::RegValueT<I2CMCmd_SPEC>;
impl I2CMCmd {
#[doc = "When \'1\', transmit a START or REPEATED START. \n\nWhether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to \'0\'."]
#[inline(always)]
pub fn m_start(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, I2CMCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, I2CMCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "When \'1\', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is \'0\', note that BUSY has a default value of \'0\'). \n\nFor bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is \'0\') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to \'0\'."]
#[inline(always)]
pub fn m_start_on_idle(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, I2CMCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, I2CMCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn m_ack(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, I2CMCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, I2CMCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn m_nack(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, I2CMCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, I2CMCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn m_stop(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, I2CMCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, I2CMCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for I2CMCmd {
#[inline(always)]
fn default() -> I2CMCmd {
<crate::RegValueT<I2CMCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct I2CSCmd_SPEC;
impl crate::sealed::RegSpec for I2CSCmd_SPEC {
type DataType = u32;
}
#[doc = "I2C slave command"]
pub type I2CSCmd = crate::RegValueT<I2CSCmd_SPEC>;
impl I2CSCmd {
#[doc = "When \'1\', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to \'0\'. In EZ and CMD_RESP mode, this field should be set to \'0\' (it is only to be used in FIFO mode)."]
#[inline(always)]
pub fn s_ack(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, I2CSCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, I2CSCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "When \'1\', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to \'0\'. In EZ and CMD_RESP mode, this field should be set to \'0\' (it is only to be used in FIFO mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK."]
#[inline(always)]
pub fn s_nack(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, I2CSCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, I2CSCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for I2CSCmd {
#[inline(always)]
fn default() -> I2CSCmd {
<crate::RegValueT<I2CSCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct I2CCfg_SPEC;
impl crate::sealed::RegSpec for I2CCfg_SPEC {
type DataType = u32;
}
#[doc = "I2C configuration"]
pub type I2CCfg = crate::RegValueT<I2CCfg_SPEC>;
impl I2CCfg {
#[doc = "Trim bits for \'i2c_sda_in\' 50 ns filter. \n\nSDA_IN_FILT_TRIM\\[1\\] is used to enable I2CS_EC or SPIS_EC access to internal EZ memory.\n1: enable clk_scb\n0: disable clk_scb\n\nBefore going to deepsleep this field should be set to 0. It should be re-enabled once the device is awoken and clk_hf\\[0\\] is at the desired frequency."]
#[inline(always)]
pub fn sda_in_filt_trim(
self,
) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, I2CCfg_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0x3,1,0,u8,u8,I2CCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn sda_in_filt_sel(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, I2CCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, I2CCfg_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Trim bits for \'i2c_scl_in\' 50 ns filter. Not to be modified by the user"]
#[inline(always)]
pub fn scl_in_filt_trim(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, I2CCfg_SPEC, crate::common::RW> {
crate::common::RegisterField::<8,0x3,1,0,u8,u8,I2CCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn scl_in_filt_sel(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, I2CCfg_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12, 1, 0, I2CCfg_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Trim bits for \'i2c_sda_out\' 50 ns filter 0. Not to be modified by the user"]
#[inline(always)]
pub fn sda_out_filt0_trim(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, I2CCfg_SPEC, crate::common::RW> {
crate::common::RegisterField::<16,0x3,1,0,u8,u8,I2CCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Trim bits for \'i2c_sda_out\' 50 ns filter 1. Not to be modified by the user"]
#[inline(always)]
pub fn sda_out_filt1_trim(
self,
) -> crate::common::RegisterField<18, 0x3, 1, 0, u8, u8, I2CCfg_SPEC, crate::common::RW> {
crate::common::RegisterField::<18,0x3,1,0,u8,u8,I2CCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Trim bits for \'i2c_sda_out\' 50 ns filter 2. Not to be modified by the user"]
#[inline(always)]
pub fn sda_out_filt2_trim(
self,
) -> crate::common::RegisterField<20, 0x3, 1, 0, u8, u8, I2CCfg_SPEC, crate::common::RW> {
crate::common::RegisterField::<20,0x3,1,0,u8,u8,I2CCfg_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn sda_out_filt_sel(
self,
) -> crate::common::RegisterField<28, 0x3, 1, 0, u8, u8, I2CCfg_SPEC, crate::common::RW> {
crate::common::RegisterField::<28,0x3,1,0,u8,u8,I2CCfg_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for I2CCfg {
#[inline(always)]
fn default() -> I2CCfg {
<crate::RegValueT<I2CCfg_SPEC> as RegisterValue<_>>::new(2756627)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxCtrl_SPEC;
impl crate::sealed::RegSpec for TxCtrl_SPEC {
type DataType = u32;
}
#[doc = "Transmitter control"]
pub type TxCtrl = crate::RegValueT<TxCtrl_SPEC>;
impl TxCtrl {
#[doc = "Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is \\[3, 8\\]. For SPI, the valid range is \\[3, 15\\]. For I2C the only valid value is 7. In EZ and CMD_RESP mode (for both SPI and I2C), the only valid value is 7."]
#[inline(always)]
pub fn data_width(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, TxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0xf,1,0,u8,u8,TxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Least significant bit first (\'0\') or most significant bit first (\'1\'). For I2C, this field should be \'1\'. For EZ and CMD_RESP this field must be set to \'1\'"]
#[inline(always)]
pub fn msb_first(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, TxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, TxCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Each IO cell \'xxx\' has two associated SCB output signals \'xxx_out_en\' and \'xxx_out\'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave when connected to SCBs.\n\n\'0\': Normal operation mode. In this operation mode \'xxx_out_en\' output enable signal is typically constant \'1\' the \'xxx_out\' output is the outputted value. In other words, in normal operation mode, the \'xxx_out\' output is used to control the IO cell output value: \'xxx_out\' is \'0\' to drive an IO cell output value of \'0\' and \'xxx_out\' is \'1\' to drive an IO cell output value of \'1\'.\n\n\'1\': Open drain operation mode. In this operation mode \'xxx_out_en\' output controls the outputted value. Typically the \'xxx_out\' signal is a constant \'0\'. Thus when \'xxx_out_en\' is \'1\' the line is driven low, but when \'xxx_out_en\' is \'0\' the output is not driven. This requires that the line is driven high by an external device or pull-up resistor\n\nThe open drain mode is supported for:\n- I2C mode this field must be set.\n- UART mode use this mode when a pull-up resistor is used on the TX line. \n- SPI mode this field must be set if there are multiple slaves driving MISO."]
#[inline(always)]
pub fn open_drain(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, TxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16, 1, 0, TxCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for TxCtrl {
#[inline(always)]
fn default() -> TxCtrl {
<crate::RegValueT<TxCtrl_SPEC> as RegisterValue<_>>::new(263)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxFifoCtrl_SPEC;
impl crate::sealed::RegSpec for TxFifoCtrl_SPEC {
type DataType = u32;
}
#[doc = "Transmitter FIFO control"]
pub type TxFifoCtrl = crate::RegValueT<TxFifoCtrl_SPEC>;
impl TxFifoCtrl {
#[doc = "N/A"]
#[inline(always)]
pub fn trigger_level(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, TxFifoCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,TxFifoCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn clear(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, TxFifoCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,TxFifoCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn freeze(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, TxFifoCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,TxFifoCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TxFifoCtrl {
#[inline(always)]
fn default() -> TxFifoCtrl {
<crate::RegValueT<TxFifoCtrl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxFifoStatus_SPEC;
impl crate::sealed::RegSpec for TxFifoStatus_SPEC {
type DataType = u32;
}
#[doc = "Transmitter FIFO status"]
pub type TxFifoStatus = crate::RegValueT<TxFifoStatus_SPEC>;
impl TxFifoStatus {
#[doc = "N/A"]
#[inline(always)]
pub fn used(
self,
) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, TxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,TxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn sr_valid(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, TxFifoStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<15,1,0,TxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rd_ptr(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, TxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,TxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn wr_ptr(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, TxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,TxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for TxFifoStatus {
#[inline(always)]
fn default() -> TxFifoStatus {
<crate::RegValueT<TxFifoStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxFifoWr_SPEC;
impl crate::sealed::RegSpec for TxFifoWr_SPEC {
type DataType = u32;
}
#[doc = "Transmitter FIFO write"]
pub type TxFifoWr = crate::RegValueT<TxFifoWr_SPEC>;
impl TxFifoWr {
#[doc = "N/A"]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, TxFifoWr_SPEC, crate::common::W>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,TxFifoWr_SPEC,crate::common::W>::from_register(self,0)
}
}
impl ::core::default::Default for TxFifoWr {
#[inline(always)]
fn default() -> TxFifoWr {
<crate::RegValueT<TxFifoWr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxCtrl_SPEC;
impl crate::sealed::RegSpec for RxCtrl_SPEC {
type DataType = u32;
}
#[doc = "Receiver control"]
pub type RxCtrl = crate::RegValueT<RxCtrl_SPEC>;
impl RxCtrl {
#[doc = "N/A"]
#[inline(always)]
pub fn data_width(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, RxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0xf,1,0,u8,u8,RxCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Least significant bit first (\'0\') or most significant bit first (\'1\'). For I2C, this field should be \'1\'. For EZ and CMD_RESP this field must be set to \'1\'"]
#[inline(always)]
pub fn msb_first(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, RxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, RxCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn median(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, RxCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9, 1, 0, RxCtrl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for RxCtrl {
#[inline(always)]
fn default() -> RxCtrl {
<crate::RegValueT<RxCtrl_SPEC> as RegisterValue<_>>::new(263)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxFifoCtrl_SPEC;
impl crate::sealed::RegSpec for RxFifoCtrl_SPEC {
type DataType = u32;
}
#[doc = "Receiver FIFO control"]
pub type RxFifoCtrl = crate::RegValueT<RxFifoCtrl_SPEC>;
impl RxFifoCtrl {
#[doc = "N/A"]
#[inline(always)]
pub fn trigger_level(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, RxFifoCtrl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,RxFifoCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn clear(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, RxFifoCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,RxFifoCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn freeze(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, RxFifoCtrl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,RxFifoCtrl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RxFifoCtrl {
#[inline(always)]
fn default() -> RxFifoCtrl {
<crate::RegValueT<RxFifoCtrl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxFifoStatus_SPEC;
impl crate::sealed::RegSpec for RxFifoStatus_SPEC {
type DataType = u32;
}
#[doc = "Receiver FIFO status"]
pub type RxFifoStatus = crate::RegValueT<RxFifoStatus_SPEC>;
impl RxFifoStatus {
#[doc = "N/A"]
#[inline(always)]
pub fn used(
self,
) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, RxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,RxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn sr_valid(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, RxFifoStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<15,1,0,RxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn rd_ptr(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, RxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,RxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn wr_ptr(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, RxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,RxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for RxFifoStatus {
#[inline(always)]
fn default() -> RxFifoStatus {
<crate::RegValueT<RxFifoStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxMatch_SPEC;
impl crate::sealed::RegSpec for RxMatch_SPEC {
type DataType = u32;
}
#[doc = "Slave address and mask"]
pub type RxMatch = crate::RegValueT<RxMatch_SPEC>;
impl RxMatch {
#[doc = "N/A"]
#[inline(always)]
pub fn addr(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, RxMatch_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0xff,1,0,u8,u8,RxMatch_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn mask(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, RxMatch_SPEC, crate::common::RW> {
crate::common::RegisterField::<16,0xff,1,0,u8,u8,RxMatch_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RxMatch {
#[inline(always)]
fn default() -> RxMatch {
<crate::RegValueT<RxMatch_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxFifoRd_SPEC;
impl crate::sealed::RegSpec for RxFifoRd_SPEC {
type DataType = u32;
}
#[doc = "Receiver FIFO read"]
pub type RxFifoRd = crate::RegValueT<RxFifoRd_SPEC>;
impl RxFifoRd {
#[doc = "Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is \'1\', only DATA\\[7:0\\] are used.\n\nWhen in debug mode a read from this register behaves as a read from the SCB_RX_FIFO_RD_SILENT register. That is data will not be removed from the FIFO\n\nA read from an empty RX FIFO sets INTR_RX.UNDERFLOW to \'1\'."]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, RxFifoRd_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,RxFifoRd_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for RxFifoRd {
#[inline(always)]
fn default() -> RxFifoRd {
<crate::RegValueT<RxFifoRd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxFifoRdSilent_SPEC;
impl crate::sealed::RegSpec for RxFifoRdSilent_SPEC {
type DataType = u32;
}
#[doc = "Receiver FIFO read silent"]
pub type RxFifoRdSilent = crate::RegValueT<RxFifoRdSilent_SPEC>;
impl RxFifoRdSilent {
#[doc = "N/A"]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
RxFifoRdSilent_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
RxFifoRdSilent_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RxFifoRdSilent {
#[inline(always)]
fn default() -> RxFifoRdSilent {
<crate::RegValueT<RxFifoRdSilent_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrCause_SPEC;
impl crate::sealed::RegSpec for IntrCause_SPEC {
type DataType = u32;
}
#[doc = "Active clocked interrupt signal"]
pub type IntrCause = crate::RegValueT<IntrCause_SPEC>;
impl IntrCause {
#[doc = "Master interrupt active (\'interrupt_master\'): INTR_M_MASKED != 0."]
#[inline(always)]
pub fn m(self) -> crate::common::RegisterFieldBool<0, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Slave interrupt active (\'interrupt_slave\'): INTR_S_MASKED != 0."]
#[inline(always)]
pub fn s(self) -> crate::common::RegisterFieldBool<1, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Transmitter interrupt active (\'interrupt_tx\'): INTR_TX_MASKED != 0."]
#[inline(always)]
pub fn tx(self) -> crate::common::RegisterFieldBool<2, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Receiver interrupt active (\'interrupt_rx\'): INTR_RX_MASKED != 0."]
#[inline(always)]
pub fn rx(self) -> crate::common::RegisterFieldBool<3, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Externally clock I2C interrupt active (\'interrupt_i2c_ec\'): INTR_I2C_EC_MASKED != 0."]
#[inline(always)]
pub fn i2c_ec(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Externally clocked SPI interrupt active (\'interrupt_spi_ec\'): INTR_SPI_EC_MASKED != 0."]
#[inline(always)]
pub fn spi_ec(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrCause_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5, 1, 0, IntrCause_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for IntrCause {
#[inline(always)]
fn default() -> IntrCause {
<crate::RegValueT<IntrCause_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrI2CEc_SPEC;
impl crate::sealed::RegSpec for IntrI2CEc_SPEC {
type DataType = u32;
}
#[doc = "Externally clocked I2C interrupt request"]
pub type IntrI2CEc = crate::RegValueT<IntrI2CEc_SPEC>;
impl IntrI2CEc {
#[doc = "Wake up request. Active on incoming slave request (with address match).\n\nOnly set when EC_AM is \'1\'."]
#[inline(always)]
pub fn wake_up(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrI2CEc_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrI2CEc_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "STOP detection. Activated on the end of a every transfer (I2C STOP).\n\nOnly set for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is \'1\'."]
#[inline(always)]
pub fn ez_stop(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrI2CEc_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,IntrI2CEc_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. \n\nOnly set for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is \'1\'."]
#[inline(always)]
pub fn ez_write_stop(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrI2CEc_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,IntrI2CEc_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from.\n\nOnly set for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is \'1\'."]
#[inline(always)]
pub fn ez_read_stop(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrI2CEc_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,IntrI2CEc_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrI2CEc {
#[inline(always)]
fn default() -> IntrI2CEc {
<crate::RegValueT<IntrI2CEc_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrI2CEcMask_SPEC;
impl crate::sealed::RegSpec for IntrI2CEcMask_SPEC {
type DataType = u32;
}
#[doc = "Externally clocked I2C interrupt mask"]
pub type IntrI2CEcMask = crate::RegValueT<IntrI2CEcMask_SPEC>;
impl IntrI2CEcMask {
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn wake_up(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrI2CEcMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrI2CEcMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn ez_stop(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrI2CEcMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,IntrI2CEcMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn ez_write_stop(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrI2CEcMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,IntrI2CEcMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn ez_read_stop(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrI2CEcMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,IntrI2CEcMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrI2CEcMask {
#[inline(always)]
fn default() -> IntrI2CEcMask {
<crate::RegValueT<IntrI2CEcMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrI2CEcMasked_SPEC;
impl crate::sealed::RegSpec for IntrI2CEcMasked_SPEC {
type DataType = u32;
}
#[doc = "Externally clocked I2C interrupt masked"]
pub type IntrI2CEcMasked = crate::RegValueT<IntrI2CEcMasked_SPEC>;
impl IntrI2CEcMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn wake_up(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrI2CEcMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,IntrI2CEcMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn ez_stop(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrI2CEcMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,IntrI2CEcMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn ez_write_stop(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrI2CEcMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,IntrI2CEcMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn ez_read_stop(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrI2CEcMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3,1,0,IntrI2CEcMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrI2CEcMasked {
#[inline(always)]
fn default() -> IntrI2CEcMasked {
<crate::RegValueT<IntrI2CEcMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSpiEc_SPEC;
impl crate::sealed::RegSpec for IntrSpiEc_SPEC {
type DataType = u32;
}
#[doc = "Externally clocked SPI interrupt request"]
pub type IntrSpiEc = crate::RegValueT<IntrSpiEc_SPEC>;
impl IntrSpiEc {
#[doc = "Wake up request. Active on incoming slave request.\n\nOnly set when EC_AM is \'1\'."]
#[inline(always)]
pub fn wake_up(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSpiEc_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrSpiEc_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "STOP detection. Activated on the end of a every transfer (SPI deselection).\n\nOnly set in EZ and CMD_RESP mode and when EC_OP is \'1\'."]
#[inline(always)]
pub fn ez_stop(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSpiEc_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,IntrSpiEc_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. \n\nOnly set in EZ and CMD_RESP modes and when EC_OP is \'1\'."]
#[inline(always)]
pub fn ez_write_stop(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrSpiEc_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,IntrSpiEc_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from.\n\nOnly set in EZ and CMD_RESP modes and when EC_OP is \'1\'."]
#[inline(always)]
pub fn ez_read_stop(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrSpiEc_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,IntrSpiEc_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrSpiEc {
#[inline(always)]
fn default() -> IntrSpiEc {
<crate::RegValueT<IntrSpiEc_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSpiEcMask_SPEC;
impl crate::sealed::RegSpec for IntrSpiEcMask_SPEC {
type DataType = u32;
}
#[doc = "Externally clocked SPI interrupt mask"]
pub type IntrSpiEcMask = crate::RegValueT<IntrSpiEcMask_SPEC>;
impl IntrSpiEcMask {
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn wake_up(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSpiEcMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrSpiEcMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn ez_stop(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSpiEcMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,IntrSpiEcMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn ez_write_stop(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrSpiEcMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,IntrSpiEcMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn ez_read_stop(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrSpiEcMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,IntrSpiEcMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrSpiEcMask {
#[inline(always)]
fn default() -> IntrSpiEcMask {
<crate::RegValueT<IntrSpiEcMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSpiEcMasked_SPEC;
impl crate::sealed::RegSpec for IntrSpiEcMasked_SPEC {
type DataType = u32;
}
#[doc = "Externally clocked SPI interrupt masked"]
pub type IntrSpiEcMasked = crate::RegValueT<IntrSpiEcMasked_SPEC>;
impl IntrSpiEcMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn wake_up(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSpiEcMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,IntrSpiEcMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn ez_stop(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSpiEcMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,IntrSpiEcMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn ez_write_stop(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrSpiEcMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,IntrSpiEcMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn ez_read_stop(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrSpiEcMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3,1,0,IntrSpiEcMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrSpiEcMasked {
#[inline(always)]
fn default() -> IntrSpiEcMasked {
<crate::RegValueT<IntrSpiEcMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrM_SPEC;
impl crate::sealed::RegSpec for IntrM_SPEC {
type DataType = u32;
}
#[doc = "Master interrupt request"]
pub type IntrM = crate::RegValueT<IntrM_SPEC>;
impl IntrM {
#[doc = "N/A"]
#[inline(always)]
pub fn i2c_arb_lost(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrM_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrM_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn i2c_nack(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrM_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrM_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn i2c_ack(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrM_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, IntrM_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn i2c_stop(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrM_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, IntrM_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn i2c_bus_error(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrM_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, IntrM_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn spi_done(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrM_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9, 1, 0, IntrM_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for IntrM {
#[inline(always)]
fn default() -> IntrM {
<crate::RegValueT<IntrM_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMSet_SPEC;
impl crate::sealed::RegSpec for IntrMSet_SPEC {
type DataType = u32;
}
#[doc = "Master interrupt set request"]
pub type IntrMSet = crate::RegValueT<IntrMSet_SPEC>;
impl IntrMSet {
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_arb_lost(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrMSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_nack(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrMSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_ack(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrMSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, IntrMSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_stop(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrMSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, IntrMSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_bus_error(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrMSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, IntrMSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn spi_done(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrMSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9, 1, 0, IntrMSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for IntrMSet {
#[inline(always)]
fn default() -> IntrMSet {
<crate::RegValueT<IntrMSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMMask_SPEC;
impl crate::sealed::RegSpec for IntrMMask_SPEC {
type DataType = u32;
}
#[doc = "Master interrupt mask"]
pub type IntrMMask = crate::RegValueT<IntrMMask_SPEC>;
impl IntrMMask {
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_arb_lost(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrMMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_nack(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,IntrMMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_ack(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrMMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,IntrMMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_stop(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrMMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,IntrMMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_bus_error(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrMMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,IntrMMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn spi_done(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrMMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,IntrMMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMMask {
#[inline(always)]
fn default() -> IntrMMask {
<crate::RegValueT<IntrMMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMMasked_SPEC;
impl crate::sealed::RegSpec for IntrMMasked_SPEC {
type DataType = u32;
}
#[doc = "Master interrupt masked request"]
pub type IntrMMasked = crate::RegValueT<IntrMMasked_SPEC>;
impl IntrMMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn i2c_arb_lost(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,IntrMMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn i2c_nack(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,IntrMMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn i2c_ack(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrMMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,IntrMMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn i2c_stop(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrMMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4,1,0,IntrMMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn i2c_bus_error(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrMMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8,1,0,IntrMMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn spi_done(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrMMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<9,1,0,IntrMMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMMasked {
#[inline(always)]
fn default() -> IntrMMasked {
<crate::RegValueT<IntrMMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrS_SPEC;
impl crate::sealed::RegSpec for IntrS_SPEC {
type DataType = u32;
}
#[doc = "Slave interrupt request"]
pub type IntrS = crate::RegValueT<IntrS_SPEC>;
impl IntrS {
#[doc = "I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is \'1\'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine aborts the ongoing transfer. SW may decide to clear the TX and RX FIFOs in case of this error."]
#[inline(always)]
pub fn i2c_arb_lost(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrS_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrS_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn i2c_nack(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrS_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrS_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn i2c_ack(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrS_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, IntrS_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to \'1\', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address.\n\nNote that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK\'d or NACK\'d.\n\nIn EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ base address, will not result in this event being detected)."]
#[inline(always)]
pub fn i2c_write_stop(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrS_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, IntrS_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn i2c_stop(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrS_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, IntrS_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "I2C slave START received. Set to \'1\', when START or REPEATED START event is detected.\n\nIn the case of externally clocked address matching (CTRL.EC_AM_MODE is \'1\') AND clock stretching is performed (till the internally clocked logic takes over) (I2C_CTRL.S_NOT_READY_ADDR_NACK is \'0\'), this field is NOT set. Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL."]
#[inline(always)]
pub fn i2c_start(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrS_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, IntrS_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn i2c_addr_match(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrS_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, IntrS_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO. \n\nIn the case of externally clocked address matching (CTRL.EC_AM_MODE is \'1\') and internally clocked operation (CTRL.EC_OP_MODE is \'0\'), this field is set when the event is detected."]
#[inline(always)]
pub fn i2c_general(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrS_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7, 1, 0, IntrS_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error."]
#[inline(always)]
pub fn i2c_bus_error(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrS_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, IntrS_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn spi_ez_write_stop(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrS_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9, 1, 0, IntrS_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn spi_ez_stop(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrS_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10, 1, 0, IntrS_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error."]
#[inline(always)]
pub fn spi_bus_error(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, IntrS_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11, 1, 0, IntrS_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for IntrS {
#[inline(always)]
fn default() -> IntrS {
<crate::RegValueT<IntrS_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSSet_SPEC;
impl crate::sealed::RegSpec for IntrSSet_SPEC {
type DataType = u32;
}
#[doc = "Slave interrupt set request"]
pub type IntrSSet = crate::RegValueT<IntrSSet_SPEC>;
impl IntrSSet {
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_arb_lost(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrSSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_nack(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrSSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_ack(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrSSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, IntrSSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_write_stop(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrSSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, IntrSSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_stop(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrSSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, IntrSSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_start(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrSSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, IntrSSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_addr_match(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrSSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, IntrSSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_general(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrSSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7, 1, 0, IntrSSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_bus_error(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrSSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, IntrSSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn spi_ez_write_stop(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrSSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9, 1, 0, IntrSSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn spi_ez_stop(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrSSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,IntrSSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn spi_bus_error(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, IntrSSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,IntrSSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrSSet {
#[inline(always)]
fn default() -> IntrSSet {
<crate::RegValueT<IntrSSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSMask_SPEC;
impl crate::sealed::RegSpec for IntrSMask_SPEC {
type DataType = u32;
}
#[doc = "Slave interrupt mask"]
pub type IntrSMask = crate::RegValueT<IntrSMask_SPEC>;
impl IntrSMask {
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_arb_lost(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrSMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_nack(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,IntrSMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_ack(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrSMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,IntrSMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_write_stop(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrSMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,IntrSMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_stop(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrSMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,IntrSMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_start(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrSMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,IntrSMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_addr_match(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrSMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,IntrSMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_general(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrSMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,IntrSMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn i2c_bus_error(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrSMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,IntrSMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn spi_ez_write_stop(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrSMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,IntrSMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn spi_ez_stop(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrSMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,IntrSMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn spi_bus_error(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, IntrSMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,IntrSMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrSMask {
#[inline(always)]
fn default() -> IntrSMask {
<crate::RegValueT<IntrSMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSMasked_SPEC;
impl crate::sealed::RegSpec for IntrSMasked_SPEC {
type DataType = u32;
}
#[doc = "Slave interrupt masked request"]
pub type IntrSMasked = crate::RegValueT<IntrSMasked_SPEC>;
impl IntrSMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn i2c_arb_lost(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,IntrSMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn i2c_nack(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,IntrSMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn i2c_ack(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrSMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,IntrSMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn i2c_write_stop(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrSMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3,1,0,IntrSMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn i2c_stop(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrSMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4,1,0,IntrSMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn i2c_start(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrSMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5,1,0,IntrSMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn i2c_addr_match(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrSMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<6,1,0,IntrSMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn i2c_general(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrSMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<7,1,0,IntrSMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn i2c_bus_error(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrSMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8,1,0,IntrSMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn spi_ez_write_stop(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrSMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<9,1,0,IntrSMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn spi_ez_stop(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrSMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<10,1,0,IntrSMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn spi_bus_error(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, IntrSMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<11,1,0,IntrSMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrSMasked {
#[inline(always)]
fn default() -> IntrSMasked {
<crate::RegValueT<IntrSMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrTx_SPEC;
impl crate::sealed::RegSpec for IntrTx_SPEC {
type DataType = u32;
}
#[doc = "Transmitter interrupt request"]
pub type IntrTx = crate::RegValueT<IntrTx_SPEC>;
impl IntrTx {
#[doc = "N/A"]
#[inline(always)]
pub fn trigger(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrTx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrTx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn not_full(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrTx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrTx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn empty(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrTx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, IntrTx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn overflow(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrTx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, IntrTx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is \'1\'.\n\nOnly used in FIFO mode."]
#[inline(always)]
pub fn underflow(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrTx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, IntrTx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "CPU write can not get access to the EZ memory (EZ data access), due to an externally clocked EZ access."]
#[inline(always)]
pub fn blocked(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrTx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7, 1, 0, IntrTx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn uart_nack(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrTx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, IntrTx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO, and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty)."]
#[inline(always)]
pub fn uart_done(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrTx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9, 1, 0, IntrTx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes."]
#[inline(always)]
pub fn uart_arb_lost(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrTx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10, 1, 0, IntrTx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for IntrTx {
#[inline(always)]
fn default() -> IntrTx {
<crate::RegValueT<IntrTx_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrTxSet_SPEC;
impl crate::sealed::RegSpec for IntrTxSet_SPEC {
type DataType = u32;
}
#[doc = "Transmitter interrupt set request"]
pub type IntrTxSet = crate::RegValueT<IntrTxSet_SPEC>;
impl IntrTxSet {
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn trigger(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrTxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrTxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn not_full(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrTxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,IntrTxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn empty(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrTxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,IntrTxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn overflow(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrTxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,IntrTxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn underflow(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrTxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,IntrTxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn blocked(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrTxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,IntrTxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn uart_nack(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrTxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,IntrTxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn uart_done(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrTxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,IntrTxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn uart_arb_lost(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrTxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,IntrTxSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrTxSet {
#[inline(always)]
fn default() -> IntrTxSet {
<crate::RegValueT<IntrTxSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrTxMask_SPEC;
impl crate::sealed::RegSpec for IntrTxMask_SPEC {
type DataType = u32;
}
#[doc = "Transmitter interrupt mask"]
pub type IntrTxMask = crate::RegValueT<IntrTxMask_SPEC>;
impl IntrTxMask {
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn trigger(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrTxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrTxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn not_full(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrTxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,IntrTxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn empty(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrTxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,IntrTxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn overflow(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrTxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,IntrTxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn underflow(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrTxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,IntrTxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn blocked(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrTxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,IntrTxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn uart_nack(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrTxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,IntrTxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn uart_done(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrTxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,IntrTxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn uart_arb_lost(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrTxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,IntrTxMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrTxMask {
#[inline(always)]
fn default() -> IntrTxMask {
<crate::RegValueT<IntrTxMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrTxMasked_SPEC;
impl crate::sealed::RegSpec for IntrTxMasked_SPEC {
type DataType = u32;
}
#[doc = "Transmitter interrupt masked request"]
pub type IntrTxMasked = crate::RegValueT<IntrTxMasked_SPEC>;
impl IntrTxMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn trigger(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrTxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,IntrTxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn not_full(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrTxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,IntrTxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn empty(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrTxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4,1,0,IntrTxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn overflow(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrTxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5,1,0,IntrTxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn underflow(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrTxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<6,1,0,IntrTxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn blocked(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrTxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<7,1,0,IntrTxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn uart_nack(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrTxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8,1,0,IntrTxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn uart_done(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrTxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<9,1,0,IntrTxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn uart_arb_lost(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrTxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<10,1,0,IntrTxMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrTxMasked {
#[inline(always)]
fn default() -> IntrTxMasked {
<crate::RegValueT<IntrTxMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrRx_SPEC;
impl crate::sealed::RegSpec for IntrRx_SPEC {
type DataType = u32;
}
#[doc = "Receiver interrupt request"]
pub type IntrRx = crate::RegValueT<IntrRx_SPEC>;
impl IntrRx {
#[doc = "N/A"]
#[inline(always)]
pub fn trigger(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrRx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrRx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn not_empty(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrRx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, IntrRx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn full(self) -> crate::common::RegisterFieldBool<3, 1, 0, IntrRx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, IntrRx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn overflow(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrRx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, IntrRx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn underflow(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrRx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, IntrRx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "CPU read transfer can not get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access."]
#[inline(always)]
pub fn blocked(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrRx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7, 1, 0, IntrRx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "UART Frame error in received data frame. \nThis can be either a start or stop bit(s) error:\nStart bit error: after the detection of the beginning of a start bit period (RX line changes from \'1\' to \'0\'), the middle of the start bit period is sampled erroneously (RX line is \'1\'). Note: a start bit error is detected BEFORE a data frame is received.\nStop bit error: the RX line is sampled as \'0\', but a \'1\' was expected. Note: a stop bit error may result in failure to receive successive data frame(s). Note: a stop bit error is detected AFTER a data frame is received.\n\nA stop bit error is detected after a data frame is received, and the UART_RX_CTL.DROP_ON_FRAME_ERROR field specifies whether the received frame is dropped or send to the RX FIFO. If UART_RX_CTL.DROP_ON_FRAME_ERROR is \'1\', the received data frame is dropped. If UART_RX_CTL.DROP_ON_FRAME_ERROR is \'0\', the received data frame is send to the RX FIFO. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO; i.e. the RX FIFO does not have error flags to tag erroneous data frames."]
#[inline(always)]
pub fn frame_error(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrRx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, IntrRx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is \'1\', the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is \'0\', the received frame is send to the RX FIFO. In SmartCard submode, negatively acknowledged data frames generate a parity error. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO."]
#[inline(always)]
pub fn parity_error(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrRx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9, 1, 0, IntrRx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte."]
#[inline(always)]
pub fn baud_detect(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrRx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10, 1, 0, IntrRx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Break detection is successful: the line is \'0\' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. \'break-in-data\' is supported. This feature is supported for the UART standard and LIN submodes. For the UART standard submodes, ongoing receipt of data frames is NOT affected; i.e. Firmware is expected to take the proper action. For the LIN submode, possible ongoing receipt of a data frame is stopped and the (partially) received data frame is dropped and baud rate detection is started. Set to \'1\', when event is detected. Write with \'1\' to clear bit."]
#[inline(always)]
pub fn break_detect(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, IntrRx_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11, 1, 0, IntrRx_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for IntrRx {
#[inline(always)]
fn default() -> IntrRx {
<crate::RegValueT<IntrRx_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrRxSet_SPEC;
impl crate::sealed::RegSpec for IntrRxSet_SPEC {
type DataType = u32;
}
#[doc = "Receiver interrupt set request"]
pub type IntrRxSet = crate::RegValueT<IntrRxSet_SPEC>;
impl IntrRxSet {
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn trigger(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrRxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrRxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt status register."]
#[inline(always)]
pub fn not_empty(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrRxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,IntrRxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt status register."]
#[inline(always)]
pub fn full(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrRxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,IntrRxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt status register."]
#[inline(always)]
pub fn overflow(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrRxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,IntrRxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt status register."]
#[inline(always)]
pub fn underflow(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrRxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,IntrRxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt status register."]
#[inline(always)]
pub fn blocked(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrRxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,IntrRxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt status register."]
#[inline(always)]
pub fn frame_error(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrRxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,IntrRxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt status register."]
#[inline(always)]
pub fn parity_error(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrRxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,IntrRxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt status register."]
#[inline(always)]
pub fn baud_detect(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrRxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,IntrRxSet_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt status register."]
#[inline(always)]
pub fn break_detect(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, IntrRxSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,IntrRxSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrRxSet {
#[inline(always)]
fn default() -> IntrRxSet {
<crate::RegValueT<IntrRxSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrRxMask_SPEC;
impl crate::sealed::RegSpec for IntrRxMask_SPEC {
type DataType = u32;
}
#[doc = "Receiver interrupt mask"]
pub type IntrRxMask = crate::RegValueT<IntrRxMask_SPEC>;
impl IntrRxMask {
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn trigger(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrRxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrRxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn not_empty(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrRxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,IntrRxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn full(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrRxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,IntrRxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn overflow(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrRxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,IntrRxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn underflow(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrRxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,IntrRxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn blocked(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrRxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,IntrRxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn frame_error(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrRxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,IntrRxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn parity_error(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrRxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,IntrRxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn baud_detect(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrRxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,IntrRxMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn break_detect(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, IntrRxMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,IntrRxMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrRxMask {
#[inline(always)]
fn default() -> IntrRxMask {
<crate::RegValueT<IntrRxMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrRxMasked_SPEC;
impl crate::sealed::RegSpec for IntrRxMasked_SPEC {
type DataType = u32;
}
#[doc = "Receiver interrupt masked request"]
pub type IntrRxMasked = crate::RegValueT<IntrRxMasked_SPEC>;
impl IntrRxMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn trigger(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrRxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,IntrRxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn not_empty(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, IntrRxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,IntrRxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn full(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, IntrRxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3,1,0,IntrRxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn overflow(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrRxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5,1,0,IntrRxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn underflow(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrRxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<6,1,0,IntrRxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn blocked(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, IntrRxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<7,1,0,IntrRxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn frame_error(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrRxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8,1,0,IntrRxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn parity_error(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, IntrRxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<9,1,0,IntrRxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn baud_detect(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, IntrRxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<10,1,0,IntrRxMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn break_detect(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, IntrRxMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<11,1,0,IntrRxMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrRxMasked {
#[inline(always)]
fn default() -> IntrRxMasked {
<crate::RegValueT<IntrRxMasked_SPEC> as RegisterValue<_>>::new(0)
}
}