/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"Flash controller"]
unsafe impl ::core::marker::Send for super::Flashc {}
unsafe impl ::core::marker::Sync for super::Flashc {}
impl super::Flashc {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "Control"]
#[inline(always)]
pub const fn flash_ctl(
&self,
) -> &'static crate::common::Reg<self::FlashCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::FlashCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Flash power control"]
#[inline(always)]
pub const fn flash_pwr_ctl(
&self,
) -> &'static crate::common::Reg<self::FlashPwrCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::FlashPwrCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "Command"]
#[inline(always)]
pub const fn flash_cmd(
&self,
) -> &'static crate::common::Reg<self::FlashCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::FlashCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(8usize),
)
}
}
#[doc = "BIST control"]
#[inline(always)]
pub const fn bist_ctl(
&self,
) -> &'static crate::common::Reg<self::BistCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::BistCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(256usize),
)
}
}
#[doc = "BIST command"]
#[inline(always)]
pub const fn bist_cmd(
&self,
) -> &'static crate::common::Reg<self::BistCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::BistCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(260usize),
)
}
}
#[doc = "BIST address start register"]
#[inline(always)]
pub const fn bist_addr_start(
&self,
) -> &'static crate::common::Reg<self::BistAddrStart_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::BistAddrStart_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(264usize),
)
}
}
#[doc = "BIST data register(s)"]
#[inline(always)]
pub const fn bist_data(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::BistData_SPEC, crate::common::RW>,
8,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x10cusize))
}
}
#[doc = "BIST data actual register(s)"]
#[inline(always)]
pub const fn bist_data_act(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::BistDataAct_SPEC, crate::common::R>,
8,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x12cusize))
}
}
#[doc = "BIST data expected register(s)"]
#[inline(always)]
pub const fn bist_data_exp(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::BistDataExp_SPEC, crate::common::R>,
8,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x14cusize))
}
}
#[doc = "BIST address register"]
#[inline(always)]
pub const fn bist_addr(
&self,
) -> &'static crate::common::Reg<self::BistAddr_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::BistAddr_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(364usize),
)
}
}
#[doc = "BIST status register"]
#[inline(always)]
pub const fn bist_status(
&self,
) -> &'static crate::common::Reg<self::BistStatus_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::BistStatus_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(368usize),
)
}
}
#[doc = "CM0+ cache control"]
#[inline(always)]
pub const fn cm0_ca_ctl0(
&self,
) -> &'static crate::common::Reg<self::Cm0CaCtl0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0CaCtl0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1024usize),
)
}
}
#[doc = "CM0+ cache control"]
#[inline(always)]
pub const fn cm0_ca_ctl1(
&self,
) -> &'static crate::common::Reg<self::Cm0CaCtl1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0CaCtl1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1028usize),
)
}
}
#[doc = "CM0+ cache control"]
#[inline(always)]
pub const fn cm0_ca_ctl2(
&self,
) -> &'static crate::common::Reg<self::Cm0CaCtl2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0CaCtl2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1032usize),
)
}
}
#[doc = "CM0+ cache command"]
#[inline(always)]
pub const fn cm0_ca_cmd(
&self,
) -> &'static crate::common::Reg<self::Cm0CaCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0CaCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1036usize),
)
}
}
#[doc = "CM0+ cache status 0"]
#[inline(always)]
pub const fn cm0_ca_status0(
&self,
) -> &'static crate::common::Reg<self::Cm0CaStatus0_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::Cm0CaStatus0_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1088usize),
)
}
}
#[doc = "CM0+ cache status 1"]
#[inline(always)]
pub const fn cm0_ca_status1(
&self,
) -> &'static crate::common::Reg<self::Cm0CaStatus1_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::Cm0CaStatus1_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1092usize),
)
}
}
#[doc = "CM0+ cache status 2"]
#[inline(always)]
pub const fn cm0_ca_status2(
&self,
) -> &'static crate::common::Reg<self::Cm0CaStatus2_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::Cm0CaStatus2_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1096usize),
)
}
}
#[doc = "CM4 cache control"]
#[inline(always)]
pub const fn cm4_ca_ctl0(
&self,
) -> &'static crate::common::Reg<self::Cm4CaCtl0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm4CaCtl0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1152usize),
)
}
}
#[doc = "CM4 cache control"]
#[inline(always)]
pub const fn cm4_ca_ctl1(
&self,
) -> &'static crate::common::Reg<self::Cm4CaCtl1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm4CaCtl1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1156usize),
)
}
}
#[doc = "CM4 cache control"]
#[inline(always)]
pub const fn cm4_ca_ctl2(
&self,
) -> &'static crate::common::Reg<self::Cm4CaCtl2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm4CaCtl2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1160usize),
)
}
}
#[doc = "CM4 cache command"]
#[inline(always)]
pub const fn cm4_ca_cmd(
&self,
) -> &'static crate::common::Reg<self::Cm4CaCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm4CaCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1164usize),
)
}
}
#[doc = "CM4 cache status 0"]
#[inline(always)]
pub const fn cm4_ca_status0(
&self,
) -> &'static crate::common::Reg<self::Cm4CaStatus0_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::Cm4CaStatus0_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1216usize),
)
}
}
#[doc = "CM4 cache status 1"]
#[inline(always)]
pub const fn cm4_ca_status1(
&self,
) -> &'static crate::common::Reg<self::Cm4CaStatus1_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::Cm4CaStatus1_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1220usize),
)
}
}
#[doc = "CM4 cache status 2"]
#[inline(always)]
pub const fn cm4_ca_status2(
&self,
) -> &'static crate::common::Reg<self::Cm4CaStatus2_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::Cm4CaStatus2_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1224usize),
)
}
}
#[doc = "Cryptography buffer control"]
#[inline(always)]
pub const fn crypto_buff_ctl(
&self,
) -> &'static crate::common::Reg<self::CryptoBuffCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CryptoBuffCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1280usize),
)
}
}
#[doc = "Cryptography buffer command"]
#[inline(always)]
pub const fn crypto_buff_cmd(
&self,
) -> &'static crate::common::Reg<self::CryptoBuffCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::CryptoBuffCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1288usize),
)
}
}
#[doc = "Datawire 0 buffer control"]
#[inline(always)]
pub const fn dw0_buff_ctl(
&self,
) -> &'static crate::common::Reg<self::Dw0BuffCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Dw0BuffCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1408usize),
)
}
}
#[doc = "Datawire 0 buffer command"]
#[inline(always)]
pub const fn dw0_buff_cmd(
&self,
) -> &'static crate::common::Reg<self::Dw0BuffCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Dw0BuffCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1416usize),
)
}
}
#[doc = "Datawire 1 buffer control"]
#[inline(always)]
pub const fn dw1_buff_ctl(
&self,
) -> &'static crate::common::Reg<self::Dw1BuffCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Dw1BuffCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1536usize),
)
}
}
#[doc = "Datawire 1 buffer command"]
#[inline(always)]
pub const fn dw1_buff_cmd(
&self,
) -> &'static crate::common::Reg<self::Dw1BuffCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Dw1BuffCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1544usize),
)
}
}
#[doc = "Debug access port buffer control"]
#[inline(always)]
pub const fn dap_buff_ctl(
&self,
) -> &'static crate::common::Reg<self::DapBuffCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::DapBuffCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1664usize),
)
}
}
#[doc = "Debug access port buffer command"]
#[inline(always)]
pub const fn dap_buff_cmd(
&self,
) -> &'static crate::common::Reg<self::DapBuffCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::DapBuffCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1672usize),
)
}
}
#[doc = "External master 0 buffer control"]
#[inline(always)]
pub const fn ext_ms0_buff_ctl(
&self,
) -> &'static crate::common::Reg<self::ExtMs0BuffCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ExtMs0BuffCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1792usize),
)
}
}
#[doc = "External master 0 buffer command"]
#[inline(always)]
pub const fn ext_ms0_buff_cmd(
&self,
) -> &'static crate::common::Reg<self::ExtMs0BuffCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ExtMs0BuffCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1800usize),
)
}
}
#[doc = "External master 1 buffer control"]
#[inline(always)]
pub const fn ext_ms1_buff_ctl(
&self,
) -> &'static crate::common::Reg<self::ExtMs1BuffCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ExtMs1BuffCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1920usize),
)
}
}
#[doc = "External master 1 buffer command"]
#[inline(always)]
pub const fn ext_ms1_buff_cmd(
&self,
) -> &'static crate::common::Reg<self::ExtMs1BuffCmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ExtMs1BuffCmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1928usize),
)
}
}
#[doc = "Flash Macro Registers"]
#[inline(always)]
pub const fn fm_ctl(self) -> crate::flashc::FmCtl {
unsafe { crate::flashc::_FmCtl::_svd2pac_from_ptr(self._svd2pac_as_ptr().add(61440usize)) }
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct FlashCtl_SPEC;
impl crate::sealed::RegSpec for FlashCtl_SPEC {
type DataType = u32;
}
#[doc = "Control"]
pub type FlashCtl = crate::RegValueT<FlashCtl_SPEC>;
impl FlashCtl {
#[doc = "FLASH macro main interface wait states:\n0: 0 wait states.\n...\n15: 15 wait states"]
#[inline(always)]
pub fn main_ws(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, FlashCtl_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0xf,1,0,u8,u8,FlashCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies remapping of FLASH macro main region.\n0: No remapping.\n1: Remapping. The highest address bit of the FLASH main region is inverted. This effectively remaps the location of FLASH main region physical sectors in the logical address space. In other words, the higher half physical sectors are swapped with the lower half physical sectors.\n\nNote: remapping only affects reading of the FLASH main region (over the R interface). It does NOT affect programming/erasing of the FLASH memory region (over the C interface).\n\nE.g., for a 512 KB / 4 Mb main region, the logical address space ranges from \\[0x1000:0000, 0x1007:ffff\\] (the highest bit if the FLASH main region is bit 18). The memory has four physical sectors: sectors 0, 1, 2 and 3. If REMAP is \'0\', the physical regions logical addresses are as follows:\n- The physical region 0: \\[0x1000:0000, 0x1001:ffff\\].\n- The physical region 1: \\[0x1002:0000, 0x1003:ffff\\].\n- The physical region 2: \\[0x1004:0000, 0x1005:ffff\\].\n- The physical region 3: \\[0x1006:0000, 0x1007:ffff\\].\nIf REMAP is \'1\', the physical regions logical addresses are as follows:\n- The physical region 0: \\[0x1004:0000, 0x1005:ffff\\].\n- The physical region 1: \\[0x1006:0000, 0x1007:ffff\\].\n- The physical region 2: \\[0x1000:0000, 0x1001:ffff\\].\n- The physical region 3: \\[0x1002:0000, 0x1003:ffff\\].\n\nNote: when the REMAP is changed, SW should invalidate the caches and buffers."]
#[inline(always)]
pub fn remap(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, FlashCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, FlashCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for FlashCtl {
#[inline(always)]
fn default() -> FlashCtl {
<crate::RegValueT<FlashCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct FlashPwrCtl_SPEC;
impl crate::sealed::RegSpec for FlashPwrCtl_SPEC {
type DataType = u32;
}
#[doc = "Flash power control"]
pub type FlashPwrCtl = crate::RegValueT<FlashPwrCtl_SPEC>;
impl FlashPwrCtl {
#[doc = "Controls \'enable\' pin of the Flash memory."]
#[inline(always)]
pub fn enable(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, FlashPwrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,FlashPwrCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Controls \'enable_hv\' pin of the Flash memory."]
#[inline(always)]
pub fn enable_hv(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, FlashPwrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,FlashPwrCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for FlashPwrCtl {
#[inline(always)]
fn default() -> FlashPwrCtl {
<crate::RegValueT<FlashPwrCtl_SPEC> as RegisterValue<_>>::new(3)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct FlashCmd_SPEC;
impl crate::sealed::RegSpec for FlashCmd_SPEC {
type DataType = u32;
}
#[doc = "Command"]
pub type FlashCmd = crate::RegValueT<FlashCmd_SPEC>;
impl FlashCmd {
#[doc = "FLASH cache and buffer invalidation for ALL cache and buffers. SW writes a \'1\' to clear the cache and buffers. HW sets this field to \'0\' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches\' LRU structures are also reset to their default state."]
#[inline(always)]
pub fn inv(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, FlashCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, FlashCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for FlashCmd {
#[inline(always)]
fn default() -> FlashCmd {
<crate::RegValueT<FlashCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct BistCtl_SPEC;
impl crate::sealed::RegSpec for BistCtl_SPEC {
type DataType = u32;
}
#[doc = "BIST control"]
pub type BistCtl = crate::RegValueT<BistCtl_SPEC>;
impl BistCtl {
#[doc = "This field specifies how the data check should be performed after reading the data from Flash memory.\n0: Read the Flash and compare the output to BIST_DATA (R0).\n1: Read the Flash and compare the output to the binary complement of BIST_DATA (R1).\n3: Read the Flash and compare with BIST_DATA\\[\\] and compliment of BIST_DATA alternately (R01). The expected data of the first read is BIST_DATA, expected data of the second read is binary compliment of BIST_DATA, third read expected data is BIST_DATA, fourth read expected data is binary compliment of BIST_DATA and so on."]
#[inline(always)]
pub fn opcode(
self,
) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, BistCtl_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0x3,1,0,u8,u8,BistCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies direction in which Flash BIST steps through addresses:\n0: BIST steps through the Flash from the maximum row and column addresses (as specified by a design time configuration parameter when ADDR_START_ENABLED is \'0\' and as specified by BIST_ADDR_START when ADDR_START_ENABLED is \'1\') to the minimum row and column addresses. \n1: BIST steps through the Flash from the minimum row and column addresses (\'0\' when ADDR_START_ENABLED is \'0\' and as specified by BIST_ADDR_START when ADDR_START_ENABLED is \'1\'\' to the maximum row and column addresses."]
#[inline(always)]
pub fn up(self) -> crate::common::RegisterFieldBool<2, 1, 0, BistCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, BistCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Specifies how the Flash BIST addresses are generated:\n\'0\': Column address is incremented/decremented till it reaches its maximum/minimum value. Once it reach its maximum/minimum value, it is set to its minimum/maximum value and only then is the row address incremented/decremented.\n\'1\': Row address is incremented/decremented till it reaches its maximum/minimum value. Once it reach its maximum/minimum value, it is set to its minimum/maximum value and only then is the column address incremented/decremented."]
#[inline(always)]
pub fn row_first(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, BistCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3, 1, 0, BistCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Specifies Flash BIST start addresses:\n\'0\': Row and column addresses start with their maximum/minimum values.\n\'1\': Row and column addresses start with their values as specified by BIST_ADDR_START.\n\nThis feature is supported only for simple increment/decrement patterns. It is not supported with address compliment pattern (BIST_CTL.ADDR_COMPLIMENT_ENABLED) or address pattern which increments/decrements both row address and column address (BIST_CTL.INCR_DECR_BOTH) for every read."]
#[inline(always)]
pub fn addr_start_enabled(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, BistCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, BistCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Specifies to generate address compliment patterns.\n0: Generate normal increment/decrement patterns.\n1: Generate address patterns which interleaves compliment of previous address in between.\nExample: The following is an example pattern, With UP=1 and ROW_FIRST =0\n00_00\n11_11\n00_01\n11_10\n00_10\n11_01\n..."]
#[inline(always)]
pub fn addr_compliment_enabled(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, BistCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, BistCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Specifies to generate patterns where both column address and row address are incremented/decremented simultaneously.\n0: Generate normal increment/decrement patterns.\n1: Generate address patterns with both row and column address changing.\nExample: With UP = 1 and ROW_FIRST = 0\n00_00\n01_01\n10_10\n11_11\n00_01\n01_10\n10_11\n11_00\n00_10\n..."]
#[inline(always)]
pub fn incr_decr_both(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, BistCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, BistCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Specifies the BIST to continue indefinitely, regardless of occurrence of errors or not.\n0: BIST controller doesn\'t stop on the data failures, it continues regardless of the errors.\n1: BIST controller stops on when the first data failure is encountered."]
#[inline(always)]
pub fn stop_on_error(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, BistCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7, 1, 0, BistCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for BistCtl {
#[inline(always)]
fn default() -> BistCtl {
<crate::RegValueT<BistCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct BistCmd_SPEC;
impl crate::sealed::RegSpec for BistCmd_SPEC {
type DataType = u32;
}
#[doc = "BIST command"]
pub type BistCmd = crate::RegValueT<BistCmd_SPEC>;
impl BistCmd {
#[doc = "1: Start FLASH BIST. Hardware set this field to \'0\' when BIST is completed."]
#[inline(always)]
pub fn start(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, BistCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, BistCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for BistCmd {
#[inline(always)]
fn default() -> BistCmd {
<crate::RegValueT<BistCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct BistAddrStart_SPEC;
impl crate::sealed::RegSpec for BistAddrStart_SPEC {
type DataType = u32;
}
#[doc = "BIST address start register"]
pub type BistAddrStart = crate::RegValueT<BistAddrStart_SPEC>;
impl BistAddrStart {
#[doc = "Column start address. Useful to apply BIST to a part of an Flash. The value of this field should be in a legal range (a value outside of the legal range has an undefined result, and may lock up the BIST state machine). This legal range is dependent on the number of columns of the SRAM the BIST is applied to (as specified by BIST_CTL.SRAMS_ENABLED). E.g. for a Flash with n columns, the legal range is \\[0, n-1\\]."]
#[inline(always)]
pub fn col_addr_start(
self,
) -> crate::common::RegisterField<
0,
0xffff,
1,
0,
u16,
u16,
BistAddrStart_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
BistAddrStart_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Row start address. Useful to apply BIST to a part of an Flash. The value of this field should be in a legal range (a value outside of the legal range has an undefined result, and may lock up the BIST state machine). This legal range is dependent on the number of rows of the SRAM the BIST is applied to (as specified by BIST_CTL.SRAMS_ENABLED). E.g. for a Flash with m columns, the legal range is \\[0, m-1\\]."]
#[inline(always)]
pub fn row_addr_start(
self,
) -> crate::common::RegisterField<
16,
0xffff,
1,
0,
u16,
u16,
BistAddrStart_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0xffff,
1,
0,
u16,
u16,
BistAddrStart_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for BistAddrStart {
#[inline(always)]
fn default() -> BistAddrStart {
<crate::RegValueT<BistAddrStart_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct BistData_SPEC;
impl crate::sealed::RegSpec for BistData_SPEC {
type DataType = u32;
}
#[doc = "BIST data register(s)"]
pub type BistData = crate::RegValueT<BistData_SPEC>;
impl BistData {
#[doc = "BIST data register to store the expected value for data comparison.\nFor a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value."]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, BistData_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
BistData_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for BistData {
#[inline(always)]
fn default() -> BistData {
<crate::RegValueT<BistData_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct BistDataAct_SPEC;
impl crate::sealed::RegSpec for BistDataAct_SPEC {
type DataType = u32;
}
#[doc = "BIST data actual register(s)"]
pub type BistDataAct = crate::RegValueT<BistDataAct_SPEC>;
impl BistDataAct {
#[doc = "This field specified the actual Flash data output that caused the BIST failure."]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
BistDataAct_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
BistDataAct_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for BistDataAct {
#[inline(always)]
fn default() -> BistDataAct {
<crate::RegValueT<BistDataAct_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct BistDataExp_SPEC;
impl crate::sealed::RegSpec for BistDataExp_SPEC {
type DataType = u32;
}
#[doc = "BIST data expected register(s)"]
pub type BistDataExp = crate::RegValueT<BistDataExp_SPEC>;
impl BistDataExp {
#[doc = "This field specified the expected Flash data output."]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
BistDataExp_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
BistDataExp_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for BistDataExp {
#[inline(always)]
fn default() -> BistDataExp {
<crate::RegValueT<BistDataExp_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct BistAddr_SPEC;
impl crate::sealed::RegSpec for BistAddr_SPEC {
type DataType = u32;
}
#[doc = "BIST address register"]
pub type BistAddr = crate::RegValueT<BistAddr_SPEC>;
impl BistAddr {
#[doc = "Current column address."]
#[inline(always)]
pub fn col_addr(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, BistAddr_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,BistAddr_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Current row address."]
#[inline(always)]
pub fn row_addr(
self,
) -> crate::common::RegisterField<16, 0xffff, 1, 0, u16, u16, BistAddr_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xffff,1,0,u16,u16,BistAddr_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for BistAddr {
#[inline(always)]
fn default() -> BistAddr {
<crate::RegValueT<BistAddr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct BistStatus_SPEC;
impl crate::sealed::RegSpec for BistStatus_SPEC {
type DataType = u32;
}
#[doc = "BIST status register"]
pub type BistStatus = crate::RegValueT<BistStatus_SPEC>;
impl BistStatus {
#[doc = "0: BIST passed.\n1: BIST failed."]
#[inline(always)]
pub fn fail(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, BistStatus_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,BistStatus_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for BistStatus {
#[inline(always)]
fn default() -> BistStatus {
<crate::RegValueT<BistStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0CaCtl0_SPEC;
impl crate::sealed::RegSpec for Cm0CaCtl0_SPEC {
type DataType = u32;
}
#[doc = "CM0+ cache control"]
pub type Cm0CaCtl0 = crate::RegValueT<Cm0CaCtl0_SPEC>;
impl Cm0CaCtl0 {
#[doc = "Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2."]
#[inline(always)]
pub fn way(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, Cm0CaCtl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3,1,0,u8,u8,Cm0CaCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2."]
#[inline(always)]
pub fn set_addr(
self,
) -> crate::common::RegisterField<24, 0x7, 1, 0, u8, u8, Cm0CaCtl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0x7,1,0,u8,u8,Cm0CaCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Prefetch enable:\n0: Disabled.\n1: Enabled.\n\nPrefetching requires the cache to be enabled; i.e. ENABLED is \'1\'."]
#[inline(always)]
pub fn pref_en(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, Cm0CaCtl0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,Cm0CaCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Cache enable:\n0: Disabled. The cache tag valid bits are reset to \'0\'s and the cache LRU information is set to \'1\'s (making way 0 the LRU way and way 3 the MRU way).\n1: Enabled."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Cm0CaCtl0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,Cm0CaCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cm0CaCtl0 {
#[inline(always)]
fn default() -> Cm0CaCtl0 {
<crate::RegValueT<Cm0CaCtl0_SPEC> as RegisterValue<_>>::new(3221225472)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0CaCtl1_SPEC;
impl crate::sealed::RegSpec for Cm0CaCtl1_SPEC {
type DataType = u32;
}
#[doc = "CM0+ cache control"]
pub type Cm0CaCtl1 = crate::RegValueT<Cm0CaCtl1_SPEC>;
impl Cm0CaCtl1 {
#[doc = "Set Power mode for CM0 cache"]
#[inline(always)]
pub fn pwr_mode(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
cm0_ca_ctl1::PwrMode,
cm0_ca_ctl1::PwrMode,
Cm0CaCtl1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
cm0_ca_ctl1::PwrMode,
cm0_ca_ctl1::PwrMode,
Cm0CaCtl1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Register key (to prevent accidental writes).\n- Should be written with a 0x05fa key value for the write to take effect.\n- Always reads as 0xfa05."]
#[inline(always)]
pub fn vectkeystat(
self,
) -> crate::common::RegisterField<16, 0xffff, 1, 0, u16, u16, Cm0CaCtl1_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xffff,1,0,u16,u16,Cm0CaCtl1_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Cm0CaCtl1 {
#[inline(always)]
fn default() -> Cm0CaCtl1 {
<crate::RegValueT<Cm0CaCtl1_SPEC> as RegisterValue<_>>::new(4194631683)
}
}
pub mod cm0_ca_ctl1 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PwrMode_SPEC;
pub type PwrMode = crate::EnumBitfieldStruct<u8, PwrMode_SPEC>;
impl PwrMode {
#[doc = "See CM4_PWR_CTL"]
pub const OFF: Self = Self::new(0);
#[doc = "undefined"]
pub const RSVD: Self = Self::new(1);
#[doc = "See CM4_PWR_CTL"]
pub const RETAINED: Self = Self::new(2);
#[doc = "See CM4_PWR_CTL"]
pub const ENABLED: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0CaCtl2_SPEC;
impl crate::sealed::RegSpec for Cm0CaCtl2_SPEC {
type DataType = u32;
}
#[doc = "CM0+ cache control"]
pub type Cm0CaCtl2 = crate::RegValueT<Cm0CaCtl2_SPEC>;
impl Cm0CaCtl2 {
#[doc = "Number clock cycles delay needed after power domain power up"]
#[inline(always)]
pub fn pwrup_delay(
self,
) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, Cm0CaCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x3ff,1,0,u16,u16,Cm0CaCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cm0CaCtl2 {
#[inline(always)]
fn default() -> Cm0CaCtl2 {
<crate::RegValueT<Cm0CaCtl2_SPEC> as RegisterValue<_>>::new(300)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0CaCmd_SPEC;
impl crate::sealed::RegSpec for Cm0CaCmd_SPEC {
type DataType = u32;
}
#[doc = "CM0+ cache command"]
pub type Cm0CaCmd = crate::RegValueT<Cm0CaCmd_SPEC>;
impl Cm0CaCmd {
#[doc = "FLASH cache invalidation. SW writes a \'1\' to clear the cache. W sets this field to \'0\' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The cache\'s LRU structure is also reset to its default state."]
#[inline(always)]
pub fn inv(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Cm0CaCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Cm0CaCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Cm0CaCmd {
#[inline(always)]
fn default() -> Cm0CaCmd {
<crate::RegValueT<Cm0CaCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0CaStatus0_SPEC;
impl crate::sealed::RegSpec for Cm0CaStatus0_SPEC {
type DataType = u32;
}
#[doc = "CM0+ cache status 0"]
pub type Cm0CaStatus0 = crate::RegValueT<Cm0CaStatus0_SPEC>;
impl Cm0CaStatus0 {
#[doc = "Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR."]
#[inline(always)]
pub fn valid16(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Cm0CaStatus0_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Cm0CaStatus0_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Cm0CaStatus0 {
#[inline(always)]
fn default() -> Cm0CaStatus0 {
<crate::RegValueT<Cm0CaStatus0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0CaStatus1_SPEC;
impl crate::sealed::RegSpec for Cm0CaStatus1_SPEC {
type DataType = u32;
}
#[doc = "CM0+ cache status 1"]
pub type Cm0CaStatus1 = crate::RegValueT<Cm0CaStatus1_SPEC>;
impl Cm0CaStatus1 {
#[doc = "Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR."]
#[inline(always)]
pub fn tag(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
Cm0CaStatus1_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
Cm0CaStatus1_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Cm0CaStatus1 {
#[inline(always)]
fn default() -> Cm0CaStatus1 {
<crate::RegValueT<Cm0CaStatus1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0CaStatus2_SPEC;
impl crate::sealed::RegSpec for Cm0CaStatus2_SPEC {
type DataType = u32;
}
#[doc = "CM0+ cache status 2"]
pub type Cm0CaStatus2 = crate::RegValueT<Cm0CaStatus2_SPEC>;
impl Cm0CaStatus2 {
#[doc = "Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows (\'X_LRU_Y\' indicates that way X is Less Recently Used than way Y):\nBit 5: 0_LRU_1: way 0 less recently used than way 1.\nBit 4: 0_LRU_2.\nBit 3: 0_LRU_3.\nBit 2: 1_LRU_2.\nBit 1: 1_LRU_3.\nBit 0: 2_LRU_3."]
#[inline(always)]
pub fn lru(
self,
) -> crate::common::RegisterField<0, 0x3f, 1, 0, u8, u8, Cm0CaStatus2_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x3f,1,0,u8,u8,Cm0CaStatus2_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Cm0CaStatus2 {
#[inline(always)]
fn default() -> Cm0CaStatus2 {
<crate::RegValueT<Cm0CaStatus2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm4CaCtl0_SPEC;
impl crate::sealed::RegSpec for Cm4CaCtl0_SPEC {
type DataType = u32;
}
#[doc = "CM4 cache control"]
pub type Cm4CaCtl0 = crate::RegValueT<Cm4CaCtl0_SPEC>;
impl Cm4CaCtl0 {
#[doc = "See CM0_CA_CTL."]
#[inline(always)]
pub fn way(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, Cm4CaCtl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3,1,0,u8,u8,Cm4CaCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See CM0_CA_CTL."]
#[inline(always)]
pub fn set_addr(
self,
) -> crate::common::RegisterField<24, 0x7, 1, 0, u8, u8, Cm4CaCtl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0x7,1,0,u8,u8,Cm4CaCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See CM0_CA_CTL."]
#[inline(always)]
pub fn pref_en(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, Cm4CaCtl0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,Cm4CaCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See CM0_CA_CTL."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Cm4CaCtl0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,Cm4CaCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cm4CaCtl0 {
#[inline(always)]
fn default() -> Cm4CaCtl0 {
<crate::RegValueT<Cm4CaCtl0_SPEC> as RegisterValue<_>>::new(3221225472)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm4CaCtl1_SPEC;
impl crate::sealed::RegSpec for Cm4CaCtl1_SPEC {
type DataType = u32;
}
#[doc = "CM4 cache control"]
pub type Cm4CaCtl1 = crate::RegValueT<Cm4CaCtl1_SPEC>;
impl Cm4CaCtl1 {
#[doc = "Set Power mode for CM4 cache"]
#[inline(always)]
pub fn pwr_mode(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
cm4_ca_ctl1::PwrMode,
cm4_ca_ctl1::PwrMode,
Cm4CaCtl1_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
cm4_ca_ctl1::PwrMode,
cm4_ca_ctl1::PwrMode,
Cm4CaCtl1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Register key (to prevent accidental writes).\n- Should be written with a 0x05fa key value for the write to take effect.\n- Always reads as 0xfa05."]
#[inline(always)]
pub fn vectkeystat(
self,
) -> crate::common::RegisterField<16, 0xffff, 1, 0, u16, u16, Cm4CaCtl1_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xffff,1,0,u16,u16,Cm4CaCtl1_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Cm4CaCtl1 {
#[inline(always)]
fn default() -> Cm4CaCtl1 {
<crate::RegValueT<Cm4CaCtl1_SPEC> as RegisterValue<_>>::new(4194631683)
}
}
pub mod cm4_ca_ctl1 {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PwrMode_SPEC;
pub type PwrMode = crate::EnumBitfieldStruct<u8, PwrMode_SPEC>;
impl PwrMode {
#[doc = "See CM4_PWR_CTL"]
pub const OFF: Self = Self::new(0);
#[doc = "undefined"]
pub const RSVD: Self = Self::new(1);
#[doc = "See CM4_PWR_CTL"]
pub const RETAINED: Self = Self::new(2);
#[doc = "See CM4_PWR_CTL"]
pub const ENABLED: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm4CaCtl2_SPEC;
impl crate::sealed::RegSpec for Cm4CaCtl2_SPEC {
type DataType = u32;
}
#[doc = "CM4 cache control"]
pub type Cm4CaCtl2 = crate::RegValueT<Cm4CaCtl2_SPEC>;
impl Cm4CaCtl2 {
#[doc = "Number clock cycles delay needed after power domain power up"]
#[inline(always)]
pub fn pwrup_delay(
self,
) -> crate::common::RegisterField<0, 0x3ff, 1, 0, u16, u16, Cm4CaCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x3ff,1,0,u16,u16,Cm4CaCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cm4CaCtl2 {
#[inline(always)]
fn default() -> Cm4CaCtl2 {
<crate::RegValueT<Cm4CaCtl2_SPEC> as RegisterValue<_>>::new(300)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm4CaCmd_SPEC;
impl crate::sealed::RegSpec for Cm4CaCmd_SPEC {
type DataType = u32;
}
#[doc = "CM4 cache command"]
pub type Cm4CaCmd = crate::RegValueT<Cm4CaCmd_SPEC>;
impl Cm4CaCmd {
#[doc = "See CM0_CA_CMD."]
#[inline(always)]
pub fn inv(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Cm4CaCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Cm4CaCmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Cm4CaCmd {
#[inline(always)]
fn default() -> Cm4CaCmd {
<crate::RegValueT<Cm4CaCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm4CaStatus0_SPEC;
impl crate::sealed::RegSpec for Cm4CaStatus0_SPEC {
type DataType = u32;
}
#[doc = "CM4 cache status 0"]
pub type Cm4CaStatus0 = crate::RegValueT<Cm4CaStatus0_SPEC>;
impl Cm4CaStatus0 {
#[doc = "See CM0_CA_STATUS0."]
#[inline(always)]
pub fn valid16(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Cm4CaStatus0_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Cm4CaStatus0_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Cm4CaStatus0 {
#[inline(always)]
fn default() -> Cm4CaStatus0 {
<crate::RegValueT<Cm4CaStatus0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm4CaStatus1_SPEC;
impl crate::sealed::RegSpec for Cm4CaStatus1_SPEC {
type DataType = u32;
}
#[doc = "CM4 cache status 1"]
pub type Cm4CaStatus1 = crate::RegValueT<Cm4CaStatus1_SPEC>;
impl Cm4CaStatus1 {
#[doc = "See CM0_CA_STATUS1."]
#[inline(always)]
pub fn tag(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
Cm4CaStatus1_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
Cm4CaStatus1_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Cm4CaStatus1 {
#[inline(always)]
fn default() -> Cm4CaStatus1 {
<crate::RegValueT<Cm4CaStatus1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm4CaStatus2_SPEC;
impl crate::sealed::RegSpec for Cm4CaStatus2_SPEC {
type DataType = u32;
}
#[doc = "CM4 cache status 2"]
pub type Cm4CaStatus2 = crate::RegValueT<Cm4CaStatus2_SPEC>;
impl Cm4CaStatus2 {
#[doc = "See CM0_CA_STATUS2."]
#[inline(always)]
pub fn lru(
self,
) -> crate::common::RegisterField<0, 0x3f, 1, 0, u8, u8, Cm4CaStatus2_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x3f,1,0,u8,u8,Cm4CaStatus2_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Cm4CaStatus2 {
#[inline(always)]
fn default() -> Cm4CaStatus2 {
<crate::RegValueT<Cm4CaStatus2_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CryptoBuffCtl_SPEC;
impl crate::sealed::RegSpec for CryptoBuffCtl_SPEC {
type DataType = u32;
}
#[doc = "Cryptography buffer control"]
pub type CryptoBuffCtl = crate::RegValueT<CryptoBuffCtl_SPEC>;
impl CryptoBuffCtl {
#[doc = "Prefetch enable:\n0: Disabled.\n1: Enabled.\n\nPrefetching requires the buffer to be enabled; i.e. ENABLED is \'1\'."]
#[inline(always)]
pub fn pref_en(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, CryptoBuffCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,CryptoBuffCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Cache enable:\n0: Disabled.\n1: Enabled."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, CryptoBuffCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,CryptoBuffCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CryptoBuffCtl {
#[inline(always)]
fn default() -> CryptoBuffCtl {
<crate::RegValueT<CryptoBuffCtl_SPEC> as RegisterValue<_>>::new(3221225472)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CryptoBuffCmd_SPEC;
impl crate::sealed::RegSpec for CryptoBuffCmd_SPEC {
type DataType = u32;
}
#[doc = "Cryptography buffer command"]
pub type CryptoBuffCmd = crate::RegValueT<CryptoBuffCmd_SPEC>;
impl CryptoBuffCmd {
#[doc = "FLASH buffer invalidation. SW writes a \'1\' to clear the buffer. HW sets this field to \'0\' when the operation is completed."]
#[inline(always)]
pub fn inv(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, CryptoBuffCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,CryptoBuffCmd_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CryptoBuffCmd {
#[inline(always)]
fn default() -> CryptoBuffCmd {
<crate::RegValueT<CryptoBuffCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Dw0BuffCtl_SPEC;
impl crate::sealed::RegSpec for Dw0BuffCtl_SPEC {
type DataType = u32;
}
#[doc = "Datawire 0 buffer control"]
pub type Dw0BuffCtl = crate::RegValueT<Dw0BuffCtl_SPEC>;
impl Dw0BuffCtl {
#[doc = "See CRYPTO_BUFF_CTL."]
#[inline(always)]
pub fn pref_en(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, Dw0BuffCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,Dw0BuffCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See CRYPTO_BUFF_CTL."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Dw0BuffCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,Dw0BuffCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Dw0BuffCtl {
#[inline(always)]
fn default() -> Dw0BuffCtl {
<crate::RegValueT<Dw0BuffCtl_SPEC> as RegisterValue<_>>::new(3221225472)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Dw0BuffCmd_SPEC;
impl crate::sealed::RegSpec for Dw0BuffCmd_SPEC {
type DataType = u32;
}
#[doc = "Datawire 0 buffer command"]
pub type Dw0BuffCmd = crate::RegValueT<Dw0BuffCmd_SPEC>;
impl Dw0BuffCmd {
#[doc = "See CRYPTO_BUFF_CMD."]
#[inline(always)]
pub fn inv(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Dw0BuffCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Dw0BuffCmd_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Dw0BuffCmd {
#[inline(always)]
fn default() -> Dw0BuffCmd {
<crate::RegValueT<Dw0BuffCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Dw1BuffCtl_SPEC;
impl crate::sealed::RegSpec for Dw1BuffCtl_SPEC {
type DataType = u32;
}
#[doc = "Datawire 1 buffer control"]
pub type Dw1BuffCtl = crate::RegValueT<Dw1BuffCtl_SPEC>;
impl Dw1BuffCtl {
#[doc = "See CRYPTO_BUFF_CTL."]
#[inline(always)]
pub fn pref_en(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, Dw1BuffCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,Dw1BuffCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See CRYPTO_BUFF_CTL."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Dw1BuffCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,Dw1BuffCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Dw1BuffCtl {
#[inline(always)]
fn default() -> Dw1BuffCtl {
<crate::RegValueT<Dw1BuffCtl_SPEC> as RegisterValue<_>>::new(3221225472)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Dw1BuffCmd_SPEC;
impl crate::sealed::RegSpec for Dw1BuffCmd_SPEC {
type DataType = u32;
}
#[doc = "Datawire 1 buffer command"]
pub type Dw1BuffCmd = crate::RegValueT<Dw1BuffCmd_SPEC>;
impl Dw1BuffCmd {
#[doc = "See CRYPTO_BUFF_CMD."]
#[inline(always)]
pub fn inv(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Dw1BuffCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Dw1BuffCmd_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Dw1BuffCmd {
#[inline(always)]
fn default() -> Dw1BuffCmd {
<crate::RegValueT<Dw1BuffCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DapBuffCtl_SPEC;
impl crate::sealed::RegSpec for DapBuffCtl_SPEC {
type DataType = u32;
}
#[doc = "Debug access port buffer control"]
pub type DapBuffCtl = crate::RegValueT<DapBuffCtl_SPEC>;
impl DapBuffCtl {
#[doc = "See CRYPTO_BUFF_CTL."]
#[inline(always)]
pub fn pref_en(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, DapBuffCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,DapBuffCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See CRYPTO_BUFF_CTL."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, DapBuffCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,DapBuffCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for DapBuffCtl {
#[inline(always)]
fn default() -> DapBuffCtl {
<crate::RegValueT<DapBuffCtl_SPEC> as RegisterValue<_>>::new(3221225472)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DapBuffCmd_SPEC;
impl crate::sealed::RegSpec for DapBuffCmd_SPEC {
type DataType = u32;
}
#[doc = "Debug access port buffer command"]
pub type DapBuffCmd = crate::RegValueT<DapBuffCmd_SPEC>;
impl DapBuffCmd {
#[doc = "See CRYPTO_BUFF_CMD."]
#[inline(always)]
pub fn inv(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, DapBuffCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,DapBuffCmd_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for DapBuffCmd {
#[inline(always)]
fn default() -> DapBuffCmd {
<crate::RegValueT<DapBuffCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ExtMs0BuffCtl_SPEC;
impl crate::sealed::RegSpec for ExtMs0BuffCtl_SPEC {
type DataType = u32;
}
#[doc = "External master 0 buffer control"]
pub type ExtMs0BuffCtl = crate::RegValueT<ExtMs0BuffCtl_SPEC>;
impl ExtMs0BuffCtl {
#[doc = "See CRYPTO_BUFF_CTL."]
#[inline(always)]
pub fn pref_en(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, ExtMs0BuffCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,ExtMs0BuffCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See CRYPTO_BUFF_CTL."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ExtMs0BuffCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,ExtMs0BuffCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ExtMs0BuffCtl {
#[inline(always)]
fn default() -> ExtMs0BuffCtl {
<crate::RegValueT<ExtMs0BuffCtl_SPEC> as RegisterValue<_>>::new(3221225472)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ExtMs0BuffCmd_SPEC;
impl crate::sealed::RegSpec for ExtMs0BuffCmd_SPEC {
type DataType = u32;
}
#[doc = "External master 0 buffer command"]
pub type ExtMs0BuffCmd = crate::RegValueT<ExtMs0BuffCmd_SPEC>;
impl ExtMs0BuffCmd {
#[doc = "See CRYPTO_BUFF_CMD."]
#[inline(always)]
pub fn inv(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ExtMs0BuffCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ExtMs0BuffCmd_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ExtMs0BuffCmd {
#[inline(always)]
fn default() -> ExtMs0BuffCmd {
<crate::RegValueT<ExtMs0BuffCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ExtMs1BuffCtl_SPEC;
impl crate::sealed::RegSpec for ExtMs1BuffCtl_SPEC {
type DataType = u32;
}
#[doc = "External master 1 buffer control"]
pub type ExtMs1BuffCtl = crate::RegValueT<ExtMs1BuffCtl_SPEC>;
impl ExtMs1BuffCtl {
#[doc = "See CRYPTO_BUFF_CTL."]
#[inline(always)]
pub fn pref_en(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, ExtMs1BuffCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,ExtMs1BuffCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See CRYPTO_BUFF_CTL."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, ExtMs1BuffCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,ExtMs1BuffCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ExtMs1BuffCtl {
#[inline(always)]
fn default() -> ExtMs1BuffCtl {
<crate::RegValueT<ExtMs1BuffCtl_SPEC> as RegisterValue<_>>::new(3221225472)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ExtMs1BuffCmd_SPEC;
impl crate::sealed::RegSpec for ExtMs1BuffCmd_SPEC {
type DataType = u32;
}
#[doc = "External master 1 buffer command"]
pub type ExtMs1BuffCmd = crate::RegValueT<ExtMs1BuffCmd_SPEC>;
impl ExtMs1BuffCmd {
#[doc = "See CRYPTO_BUFF_CMD."]
#[inline(always)]
pub fn inv(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ExtMs1BuffCmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,ExtMs1BuffCmd_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for ExtMs1BuffCmd {
#[inline(always)]
fn default() -> ExtMs1BuffCmd {
<crate::RegValueT<ExtMs1BuffCmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc = "Flash Macro Registers"]
#[non_exhaustive]
pub struct _FmCtl;
#[doc = "Flash Macro Registers"]
pub type FmCtl = &'static _FmCtl;
unsafe impl ::core::marker::Sync for _FmCtl {}
impl _FmCtl {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "Flash macro control"]
#[inline(always)]
pub const fn fm_ctl(
&self,
) -> &'static crate::common::Reg<fm_ctl::FmCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::FmCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Status"]
#[inline(always)]
pub const fn status(
&self,
) -> &'static crate::common::Reg<fm_ctl::Status_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<fm_ctl::Status_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "Flash macro address"]
#[inline(always)]
pub const fn fm_addr(
&self,
) -> &'static crate::common::Reg<fm_ctl::FmAddr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::FmAddr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(8usize),
)
}
}
#[doc = "Regular flash geometry"]
#[inline(always)]
pub const fn geometry(
&self,
) -> &'static crate::common::Reg<fm_ctl::Geometry_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<fm_ctl::Geometry_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(12usize),
)
}
}
#[doc = "Supervisory flash geometry"]
#[inline(always)]
pub const fn geometry_supervisory(
&self,
) -> &'static crate::common::Reg<fm_ctl::GeometrySupervisory_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<fm_ctl::GeometrySupervisory_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(16usize),
)
}
}
#[doc = "Timer control"]
#[inline(always)]
pub const fn timer_ctl(
&self,
) -> &'static crate::common::Reg<fm_ctl::TimerCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::TimerCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(20usize),
)
}
}
#[doc = "Analog control 0"]
#[inline(always)]
pub const fn ana_ctl0(
&self,
) -> &'static crate::common::Reg<fm_ctl::AnaCtl0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::AnaCtl0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(24usize),
)
}
}
#[doc = "Analog control 1"]
#[inline(always)]
pub const fn ana_ctl1(
&self,
) -> &'static crate::common::Reg<fm_ctl::AnaCtl1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::AnaCtl1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(28usize),
)
}
}
#[doc = "N/A, DNU"]
#[inline(always)]
pub const fn geometry_gen(
&self,
) -> &'static crate::common::Reg<fm_ctl::GeometryGen_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<fm_ctl::GeometryGen_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "Test mode control"]
#[inline(always)]
pub const fn test_ctl(
&self,
) -> &'static crate::common::Reg<fm_ctl::TestCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::TestCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
#[doc = "Wiat State control"]
#[inline(always)]
pub const fn wait_ctl(
&self,
) -> &'static crate::common::Reg<fm_ctl::WaitCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::WaitCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(40usize),
)
}
}
#[doc = "Monitor Status"]
#[inline(always)]
pub const fn monitor_status(
&self,
) -> &'static crate::common::Reg<fm_ctl::MonitorStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<fm_ctl::MonitorStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(44usize),
)
}
}
#[doc = "Scratch Control"]
#[inline(always)]
pub const fn scratch_ctl(
&self,
) -> &'static crate::common::Reg<fm_ctl::ScratchCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::ScratchCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(48usize),
)
}
}
#[doc = "High voltage control"]
#[inline(always)]
pub const fn hv_ctl(
&self,
) -> &'static crate::common::Reg<fm_ctl::HvCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::HvCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(52usize),
)
}
}
#[doc = "Aclk control"]
#[inline(always)]
pub const fn aclk_ctl(
&self,
) -> &'static crate::common::Reg<fm_ctl::AclkCtl_SPEC, crate::common::W> {
unsafe {
crate::common::Reg::<fm_ctl::AclkCtl_SPEC, crate::common::W>::from_ptr(
self._svd2pac_as_ptr().add(56usize),
)
}
}
#[doc = "Interrupt"]
#[inline(always)]
pub const fn intr(&self) -> &'static crate::common::Reg<fm_ctl::Intr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::Intr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(60usize),
)
}
}
#[doc = "Interrupt set"]
#[inline(always)]
pub const fn intr_set(
&self,
) -> &'static crate::common::Reg<fm_ctl::IntrSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::IntrSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(64usize),
)
}
}
#[doc = "Interrupt mask"]
#[inline(always)]
pub const fn intr_mask(
&self,
) -> &'static crate::common::Reg<fm_ctl::IntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::IntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(68usize),
)
}
}
#[doc = "Interrupt masked"]
#[inline(always)]
pub const fn intr_masked(
&self,
) -> &'static crate::common::Reg<fm_ctl::IntrMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<fm_ctl::IntrMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(72usize),
)
}
}
#[doc = "Flash macro high Voltage page latches data (for all page latches)"]
#[inline(always)]
pub const fn fm_hv_data_all(
&self,
) -> &'static crate::common::Reg<fm_ctl::FmHvDataAll_SPEC, crate::common::W> {
unsafe {
crate::common::Reg::<fm_ctl::FmHvDataAll_SPEC, crate::common::W>::from_ptr(
self._svd2pac_as_ptr().add(76usize),
)
}
}
#[doc = "Cal control BG LO trim bits"]
#[inline(always)]
pub const fn cal_ctl0(
&self,
) -> &'static crate::common::Reg<fm_ctl::CalCtl0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::CalCtl0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(80usize),
)
}
}
#[doc = "Cal control BG HI trim bits"]
#[inline(always)]
pub const fn cal_ctl1(
&self,
) -> &'static crate::common::Reg<fm_ctl::CalCtl1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::CalCtl1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(84usize),
)
}
}
#[doc = "Cal control BG LO&HI ipref trim, ref sel, fm_active, turbo_ext"]
#[inline(always)]
pub const fn cal_ctl2(
&self,
) -> &'static crate::common::Reg<fm_ctl::CalCtl2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::CalCtl2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(88usize),
)
}
}
#[doc = "Cal control osc trim bits, idac, sdac, itim, bdac."]
#[inline(always)]
pub const fn cal_ctl3(
&self,
) -> &'static crate::common::Reg<fm_ctl::CalCtl3_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::CalCtl3_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(92usize),
)
}
}
#[doc = "Bookmark register - keeps the current FW HV seq"]
#[inline(always)]
pub const fn bookmark(
&self,
) -> &'static crate::common::Reg<fm_ctl::Bookmark_SPEC, crate::common::W> {
unsafe {
crate::common::Reg::<fm_ctl::Bookmark_SPEC, crate::common::W>::from_ptr(
self._svd2pac_as_ptr().add(96usize),
)
}
}
#[doc = "Redundancy Control normal sectors 0,1"]
#[inline(always)]
pub const fn red_ctl01(
&self,
) -> &'static crate::common::Reg<fm_ctl::RedCtl01_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::RedCtl01_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(128usize),
)
}
}
#[doc = "Redundancy Controll normal sectors 2,3"]
#[inline(always)]
pub const fn red_ctl23(
&self,
) -> &'static crate::common::Reg<fm_ctl::RedCtl23_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::RedCtl23_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(132usize),
)
}
}
#[doc = "Redundancy Controll normal sectors 4,5"]
#[inline(always)]
pub const fn red_ctl45(
&self,
) -> &'static crate::common::Reg<fm_ctl::RedCtl45_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::RedCtl45_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(136usize),
)
}
}
#[doc = "Redundancy Controll normal sectors 6,7"]
#[inline(always)]
pub const fn red_ctl67(
&self,
) -> &'static crate::common::Reg<fm_ctl::RedCtl67_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::RedCtl67_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(140usize),
)
}
}
#[doc = "Redundancy Controll special sectors 0,1"]
#[inline(always)]
pub const fn red_ctl_sm01(
&self,
) -> &'static crate::common::Reg<fm_ctl::RedCtlSm01_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<fm_ctl::RedCtlSm01_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(144usize),
)
}
}
#[doc = "Do Not Use"]
#[inline(always)]
pub const fn tm_cmpr(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<fm_ctl::TmCmpr_SPEC, crate::common::R>,
32,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x100usize))
}
}
#[doc = "Flash macro high Voltage page latches data"]
#[inline(always)]
pub const fn fm_hv_data(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<fm_ctl::FmHvData_SPEC, crate::common::RW>,
256,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x800usize))
}
}
#[doc = "Flash macro memory sense amplifier and column decoder data"]
#[inline(always)]
pub const fn fm_mem_data(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<fm_ctl::FmMemData_SPEC, crate::common::R>,
256,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xc00usize))
}
}
}
pub mod fm_ctl {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct FmCtl_SPEC;
impl crate::sealed::RegSpec for FmCtl_SPEC {
type DataType = u32;
}
#[doc = "Flash macro control"]
pub type FmCtl = crate::RegValueT<FmCtl_SPEC>;
impl FmCtl {
#[doc = "Flash macro mode selection:\n\'0\': Normal functional mode.\n\'1\': Sets \'pre-program control bit\' for soft pre-program operation of all selected SONOS cells. the control bit is cleared by the HW after any program operation.\n\'2\': Sets\n...\n\'15\': TBD"]
#[inline(always)]
pub fn fm_mode(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, FmCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,FmCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Flash macro sequence select:\n\'0\': TBD\n\'1\': TBD\n\'2\': TBD\n\'3\': TBD"]
#[inline(always)]
pub fn fm_seq(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, FmCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,FmCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Direct memory cell access address."]
#[inline(always)]
pub fn daa_mux_sel(
self,
) -> crate::common::RegisterField<16, 0x7f, 1, 0, u8, u8, FmCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x7f,1,0,u8,u8,FmCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Interface selection. Specifies the interface that is used for flash memory read operations:\n\'0\': R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface.\n\'1\': C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure."]
#[inline(always)]
pub fn if_sel(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, FmCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,FmCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "\'0\': normal mode\n\'1\': Fm Write Enable"]
#[inline(always)]
pub fn wr_en(
self,
) -> crate::common::RegisterFieldBool<25, 1, 0, FmCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<25,1,0,FmCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for FmCtl {
#[inline(always)]
fn default() -> FmCtl {
<crate::RegValueT<FmCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Status_SPEC;
impl crate::sealed::RegSpec for Status_SPEC {
type DataType = u32;
}
#[doc = "Status"]
pub type Status = crate::RegValueT<Status_SPEC>;
impl Status {
#[doc = "Indicates if the high voltage timer is running:\n\'0\': not running\n\'1\': running"]
#[inline(always)]
pub fn hv_timer_running(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,Status_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Indicates the isolation status at HV trim and redundancy registers inputs\n\'0\' - Not isolated, writing permitted\n\'1\' - isolated writing disabled"]
#[inline(always)]
pub fn hv_regs_isolated(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,Status_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Indicates a bulk, sector erase, program has been requested when axa=1\n\'0\' - no error\n\'1\' - illegal HV operation error"]
#[inline(always)]
pub fn illegal_hvop(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,Status_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.. \nUsed in the testchip boot only as an \'FM READY\' flag. \n\'0\' - turbo mode \n\'1\' - normal mode"]
#[inline(always)]
pub fn turbo_n(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3,1,0,Status_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "FM_CTL.WR_EN bit after being synchronized in clk_r domain"]
#[inline(always)]
pub fn wr_en_mon(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4,1,0,Status_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "FM_CTL.IF_SEL bit after being synchronized in clk_r domain"]
#[inline(always)]
pub fn if_sel_mon(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5,1,0,Status_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Status {
#[inline(always)]
fn default() -> Status {
<crate::RegValueT<Status_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct FmAddr_SPEC;
impl crate::sealed::RegSpec for FmAddr_SPEC {
type DataType = u32;
}
#[doc = "Flash macro address"]
pub type FmAddr = crate::RegValueT<FmAddr_SPEC>;
impl FmAddr {
#[doc = "Row address."]
#[inline(always)]
pub fn ra(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, FmAddr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xffff,1,0,u16,u16,FmAddr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Bank address."]
#[inline(always)]
pub fn ba(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, FmAddr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,FmAddr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Auxiliary address field:\n\'0\': regular flash memory.\n\'1\': supervisory flash memory."]
#[inline(always)]
pub fn axa(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, FmAddr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,FmAddr_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for FmAddr {
#[inline(always)]
fn default() -> FmAddr {
<crate::RegValueT<FmAddr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Geometry_SPEC;
impl crate::sealed::RegSpec for Geometry_SPEC {
type DataType = u32;
}
#[doc = "Regular flash geometry"]
pub type Geometry = crate::RegValueT<Geometry_SPEC>;
impl Geometry {
#[doc = "Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access:\n\'0\': 1 Byte\n\'1\': 2 Bytes\n\'2\': 4 Bytes\n...\n\'7\': 128 Bytes\n\nThe currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively."]
#[inline(always)]
pub fn word_size_log2(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, Geometry_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,Geometry_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Number of Bytes per page (log 2):\n\'0\': 1 Byte\n\'1\': 2 Bytes\n\'2\': 4 Bytes\n...\n\'15\': 32768 Bytes\n\nThe currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively."]
#[inline(always)]
pub fn page_size_log2(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, Geometry_SPEC, crate::common::R>
{
crate::common::RegisterField::<4,0xf,1,0,u8,u8,Geometry_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Number of rows (minus 1):\n\'0\': 1 row\n\'1\': 2 rows\n\'2\': 3 rows\n...\n\'65535\': 65536 rows"]
#[inline(always)]
pub fn row_count(
self,
) -> crate::common::RegisterField<8, 0xffff, 1, 0, u16, u16, Geometry_SPEC, crate::common::R>
{
crate::common::RegisterField::<8,0xffff,1,0,u16,u16,Geometry_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Number of banks (minus 1):\n\'0\': 1 bank\n\'1\': 2 banks\n...\n\'255\': 256 banks"]
#[inline(always)]
pub fn bank_count(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, Geometry_SPEC, crate::common::R>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,Geometry_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Geometry {
#[inline(always)]
fn default() -> Geometry {
<crate::RegValueT<Geometry_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct GeometrySupervisory_SPEC;
impl crate::sealed::RegSpec for GeometrySupervisory_SPEC {
type DataType = u32;
}
#[doc = "Supervisory flash geometry"]
pub type GeometrySupervisory = crate::RegValueT<GeometrySupervisory_SPEC>;
impl GeometrySupervisory {
#[doc = "Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2."]
#[inline(always)]
pub fn word_size_log2(
self,
) -> crate::common::RegisterField<
0,
0xf,
1,
0,
u8,
u8,
GeometrySupervisory_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xf,
1,
0,
u8,
u8,
GeometrySupervisory_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2."]
#[inline(always)]
pub fn page_size_log2(
self,
) -> crate::common::RegisterField<
4,
0xf,
1,
0,
u8,
u8,
GeometrySupervisory_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
4,
0xf,
1,
0,
u8,
u8,
GeometrySupervisory_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT"]
#[inline(always)]
pub fn row_count(
self,
) -> crate::common::RegisterField<
8,
0xffff,
1,
0,
u16,
u16,
GeometrySupervisory_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
8,
0xffff,
1,
0,
u16,
u16,
GeometrySupervisory_SPEC,
crate::common::R,
>::from_register(self, 0)
}
#[doc = "Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT."]
#[inline(always)]
pub fn bank_count(
self,
) -> crate::common::RegisterField<
24,
0xff,
1,
0,
u8,
u8,
GeometrySupervisory_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
24,
0xff,
1,
0,
u8,
u8,
GeometrySupervisory_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for GeometrySupervisory {
#[inline(always)]
fn default() -> GeometrySupervisory {
<crate::RegValueT<GeometrySupervisory_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TimerCtl_SPEC;
impl crate::sealed::RegSpec for TimerCtl_SPEC {
type DataType = u32;
}
#[doc = "Timer control"]
pub type TimerCtl = crate::RegValueT<TimerCtl_SPEC>;
impl TimerCtl {
#[doc = "Timer period in either microseconds (SCALE is \'0\') or 100\'s of microseconds (SCALE is \'1\') multiples."]
#[inline(always)]
pub fn period(
self,
) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, TimerCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xffff,
1,
0,
u16,
u16,
TimerCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Timer tick scale:\n\'0\': 1 microsecond.\n\'1\': 100 microseconds."]
#[inline(always)]
pub fn scale(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, TimerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,TimerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Pump clock select:\n\'0\': internal clock.\n\'1\': external clock."]
#[inline(always)]
pub fn pump_clock_sel(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, TimerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,TimerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "\'1\' during pre-program operation"]
#[inline(always)]
pub fn pre_prog(
self,
) -> crate::common::RegisterFieldBool<25, 1, 0, TimerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<25,1,0,TimerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "\'0\' CSL lines driven by CSL_DAC\n\'1\' CSL lines driven by VNEG_G"]
#[inline(always)]
pub fn pre_prog_csl(
self,
) -> crate::common::RegisterFieldBool<26, 1, 0, TimerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<26,1,0,TimerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Pump enable:\n\'0\': disabled\n\'1\': enabled (also requires FM_CTL.IF_SEL to be \'1\', this additional restriction is required to prevent non intentional clearing of the FM).\nSW sets this field to \'1\' to generate a single PE pulse. \nHW clears this field when timer is expired."]
#[inline(always)]
pub fn pump_en(
self,
) -> crate::common::RegisterFieldBool<29, 1, 0, TimerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<29,1,0,TimerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "ACLK enable (generates a single cycle pulse for the FM):\n\'0\': disabled\n\'1\': enabled. SW set this field to \'1\' to generate a single cycle pulse. HW sets this field to \'0\' when the pulse is generated."]
#[inline(always)]
pub fn aclk_en(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, TimerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,TimerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Timer enable:\n\'0\': disabled\n\'1\': enabled. SW sets this field to \'1\' to start the timer. HW sets this field to \'0\' when the timer is expired."]
#[inline(always)]
pub fn timer_en(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, TimerCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,TimerCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TimerCtl {
#[inline(always)]
fn default() -> TimerCtl {
<crate::RegValueT<TimerCtl_SPEC> as RegisterValue<_>>::new(67108864)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AnaCtl0_SPEC;
impl crate::sealed::RegSpec for AnaCtl0_SPEC {
type DataType = u32;
}
#[doc = "Analog control 0"]
pub type AnaCtl0 = crate::RegValueT<AnaCtl0_SPEC>;
impl AnaCtl0 {
#[doc = "Trimming of common source line DAC."]
#[inline(always)]
pub fn csldac(
self,
) -> crate::common::RegisterField<8, 0x7, 1, 0, u8, u8, AnaCtl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x7,1,0,u8,u8,AnaCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Vcc select:\n\'0\': 1.2 V : LP reset value\n\'1\': 0.95 V: ULP reset value\nNote: the flash macro compiler has a configuration option that specifies the default/reset value of this field."]
#[inline(always)]
pub fn vcc_sel(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, AnaCtl0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,AnaCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Flips amuxbusa and amuxbusb \n\'0\': amuxbusa, amuxbusb\n\'1\': amuxbusb, amuxbusb"]
#[inline(always)]
pub fn flip_amuxbus_ab(
self,
) -> crate::common::RegisterFieldBool<27, 1, 0, AnaCtl0_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<27,1,0,AnaCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for AnaCtl0 {
#[inline(always)]
fn default() -> AnaCtl0 {
<crate::RegValueT<AnaCtl0_SPEC> as RegisterValue<_>>::new(1024)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AnaCtl1_SPEC;
impl crate::sealed::RegSpec for AnaCtl1_SPEC {
type DataType = u32;
}
#[doc = "Analog control 1"]
pub type AnaCtl1 = crate::RegValueT<AnaCtl1_SPEC>;
impl AnaCtl1 {
#[doc = "Trimming of the output margin Voltage as a function of Vpos and Vneg."]
#[inline(always)]
pub fn mdac(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, AnaCtl1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,AnaCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Trimming of positive pump output Voltage:"]
#[inline(always)]
pub fn pdac(
self,
) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, AnaCtl1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xf,1,0,u8,u8,AnaCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Trimming of negative pump output Voltage:"]
#[inline(always)]
pub fn ndac(
self,
) -> crate::common::RegisterField<24, 0xf, 1, 0, u8, u8, AnaCtl1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0xf,1,0,u8,u8,AnaCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "\'0\': vprot = BG.vprot.\n \'1\': vprot = vcc"]
#[inline(always)]
pub fn vprot_override(
self,
) -> crate::common::RegisterFieldBool<28, 1, 0, AnaCtl1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<28,1,0,AnaCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "r_grant control:\n\'0\': r_grant normal functionality\n\'1\': forces r_grant LO synchronized on clk_r"]
#[inline(always)]
pub fn r_grant_ctl(
self,
) -> crate::common::RegisterFieldBool<29, 1, 0, AnaCtl1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<29,1,0,AnaCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "\'1\': Page Latches Soft Reset"]
#[inline(always)]
pub fn rst_sft_hvpl(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, AnaCtl1_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,AnaCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for AnaCtl1 {
#[inline(always)]
fn default() -> AnaCtl1 {
<crate::RegValueT<AnaCtl1_SPEC> as RegisterValue<_>>::new(101056512)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct GeometryGen_SPEC;
impl crate::sealed::RegSpec for GeometryGen_SPEC {
type DataType = u32;
}
#[doc = "N/A, DNU"]
pub type GeometryGen = crate::RegValueT<GeometryGen_SPEC>;
impl GeometryGen {
#[doc = "N/A"]
#[inline(always)]
pub fn dnu_0x20_1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, GeometryGen_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,GeometryGen_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn dnu_0x20_2(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, GeometryGen_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2,1,0,GeometryGen_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn dnu_0x20_3(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, GeometryGen_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<3,1,0,GeometryGen_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for GeometryGen {
#[inline(always)]
fn default() -> GeometryGen {
<crate::RegValueT<GeometryGen_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TestCtl_SPEC;
impl crate::sealed::RegSpec for TestCtl_SPEC {
type DataType = u32;
}
#[doc = "Test mode control"]
pub type TestCtl = crate::RegValueT<TestCtl_SPEC>;
impl TestCtl {
#[doc = "Test mode control:\n\'0\'-\'31\': TBD"]
#[inline(always)]
pub fn test_mode(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, TestCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,TestCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Positive/negative margin mode control:\n\'0\': negative margin control\n\'1\': positive margin control"]
#[inline(always)]
pub fn pn_ctl(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, TestCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,TestCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "PUMP_EN override: Pump Enable =PUMP_EN | PE_TM"]
#[inline(always)]
pub fn tm_pe(
self,
) -> crate::common::RegisterFieldBool<9, 1, 0, TestCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<9,1,0,TestCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Test mode positive pump disable"]
#[inline(always)]
pub fn tm_dispos(
self,
) -> crate::common::RegisterFieldBool<10, 1, 0, TestCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<10,1,0,TestCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Test mode negative pump disable"]
#[inline(always)]
pub fn tm_disneg(
self,
) -> crate::common::RegisterFieldBool<11, 1, 0, TestCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<11,1,0,TestCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "1: enables the oscillator output monitor"]
#[inline(always)]
pub fn en_clk_mon(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, TestCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,TestCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Engineering Debug Register"]
#[inline(always)]
pub fn csl_debug(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, TestCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,TestCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "0\': the oscillator enable logic has control over the internal oscillator\n\'1\': forces oscillator enable HI"]
#[inline(always)]
pub fn enable_osc(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, TestCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,TestCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See BSN-242 memo\n\'0\': normal\n\'1\': disables the Word Address scrambling"]
#[inline(always)]
pub fn unscramble_wa(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, TestCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,TestCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TestCtl {
#[inline(always)]
fn default() -> TestCtl {
<crate::RegValueT<TestCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct WaitCtl_SPEC;
impl crate::sealed::RegSpec for WaitCtl_SPEC {
type DataType = u32;
}
#[doc = "Wiat State control"]
pub type WaitCtl = crate::RegValueT<WaitCtl_SPEC>;
impl WaitCtl {
#[doc = "Number of C interface wait cycles (on \'clk_c\') for a read from the memory"]
#[inline(always)]
pub fn wait_fm_mem_rd(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, WaitCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,WaitCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Number of C interface wait cycles (on \'clk_c\') for a read from the high Voltage page latches.\nCommon for reading HV Page Latches and the DATA_COMP_RESULT bit"]
#[inline(always)]
pub fn wait_fm_hv_rd(
self,
) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, WaitCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xf,1,0,u8,u8,WaitCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Number of C interface wait cycles (on \'clk_c\') for a write to the high Voltage page latches."]
#[inline(always)]
pub fn wait_fm_hv_wr(
self,
) -> crate::common::RegisterField<16, 0x7, 1, 0, u8, u8, WaitCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x7,1,0,u8,u8,WaitCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for WaitCtl {
#[inline(always)]
fn default() -> WaitCtl {
<crate::RegValueT<WaitCtl_SPEC> as RegisterValue<_>>::new(199433)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MonitorStatus_SPEC;
impl crate::sealed::RegSpec for MonitorStatus_SPEC {
type DataType = u32;
}
#[doc = "Monitor Status"]
pub type MonitorStatus = crate::RegValueT<MonitorStatus_SPEC>;
impl MonitorStatus {
#[doc = "POS pump VLO"]
#[inline(always)]
pub fn pos_pump_vlo(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, MonitorStatus_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<1,1,0,MonitorStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "NEG pump VHI"]
#[inline(always)]
pub fn neg_pump_vhi(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, MonitorStatus_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<2,1,0,MonitorStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for MonitorStatus {
#[inline(always)]
fn default() -> MonitorStatus {
<crate::RegValueT<MonitorStatus_SPEC> as RegisterValue<_>>::new(4)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ScratchCtl_SPEC;
impl crate::sealed::RegSpec for ScratchCtl_SPEC {
type DataType = u32;
}
#[doc = "Scratch Control"]
pub type ScratchCtl = crate::RegValueT<ScratchCtl_SPEC>;
impl ScratchCtl {
#[doc = "Scratchpad register fields. Provided for test purposes."]
#[inline(always)]
pub fn dummy32(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
ScratchCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
ScratchCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for ScratchCtl {
#[inline(always)]
fn default() -> ScratchCtl {
<crate::RegValueT<ScratchCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct HvCtl_SPEC;
impl crate::sealed::RegSpec for HvCtl_SPEC {
type DataType = u32;
}
#[doc = "High voltage control"]
pub type HvCtl = crate::RegValueT<HvCtl_SPEC>;
impl HvCtl {
#[doc = "Specifies the frequency in MHz of the timer clock \'clk_t\' as provide to the flash macro. E.g., if \'4\', the timer clock \'clk_t\' has a frequency of 4 MHz."]
#[inline(always)]
pub fn timer_clock_freq(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, HvCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,HvCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for HvCtl {
#[inline(always)]
fn default() -> HvCtl {
<crate::RegValueT<HvCtl_SPEC> as RegisterValue<_>>::new(50)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct AclkCtl_SPEC;
impl crate::sealed::RegSpec for AclkCtl_SPEC {
type DataType = u32;
}
#[doc = "Aclk control"]
pub type AclkCtl = crate::RegValueT<AclkCtl_SPEC>;
impl AclkCtl {
#[doc = "A write to this register generates a ACLK pulse for the flash macro (also requires FM_CTL.IF_SEL to be \'1\')."]
#[inline(always)]
pub fn aclk_gen(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, AclkCtl_SPEC, crate::common::W> {
crate::common::RegisterFieldBool::<0,1,0,AclkCtl_SPEC,crate::common::W>::from_register(self,0)
}
}
impl ::core::default::Default for AclkCtl {
#[inline(always)]
fn default() -> AclkCtl {
<crate::RegValueT<AclkCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Intr_SPEC;
impl crate::sealed::RegSpec for Intr_SPEC {
type DataType = u32;
}
#[doc = "Interrupt"]
pub type Intr = crate::RegValueT<Intr_SPEC>;
impl Intr {
#[doc = "Set to \'1\', when event is detected. Write INTR field with \'1\', to clear bit. Write INTR_SET field with \'1\', to set bit."]
#[inline(always)]
pub fn timer_expired(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Intr {
#[inline(always)]
fn default() -> Intr {
<crate::RegValueT<Intr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSet_SPEC;
impl crate::sealed::RegSpec for IntrSet_SPEC {
type DataType = u32;
}
#[doc = "Interrupt set"]
pub type IntrSet = crate::RegValueT<IntrSet_SPEC>;
impl IntrSet {
#[doc = "Write INTR_SET field with \'1\' to set corresponding INTR field (a write of \'0\' has no effect)."]
#[inline(always)]
pub fn timer_expired(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrSet_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrSet {
#[inline(always)]
fn default() -> IntrSet {
<crate::RegValueT<IntrSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMask_SPEC;
impl crate::sealed::RegSpec for IntrMask_SPEC {
type DataType = u32;
}
#[doc = "Interrupt mask"]
pub type IntrMask = crate::RegValueT<IntrMask_SPEC>;
impl IntrMask {
#[doc = "Mask for corresponding field in INTR register."]
#[inline(always)]
pub fn timer_expired(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMask {
#[inline(always)]
fn default() -> IntrMask {
<crate::RegValueT<IntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMasked_SPEC;
impl crate::sealed::RegSpec for IntrMasked_SPEC {
type DataType = u32;
}
#[doc = "Interrupt masked"]
pub type IntrMasked = crate::RegValueT<IntrMasked_SPEC>;
impl IntrMasked {
#[doc = "Logical and of corresponding request and mask fields."]
#[inline(always)]
pub fn timer_expired(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMasked {
#[inline(always)]
fn default() -> IntrMasked {
<crate::RegValueT<IntrMasked_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct FmHvDataAll_SPEC;
impl crate::sealed::RegSpec for FmHvDataAll_SPEC {
type DataType = u32;
}
#[doc = "Flash macro high Voltage page latches data (for all page latches)"]
pub type FmHvDataAll = crate::RegValueT<FmHvDataAll_SPEC>;
impl FmHvDataAll {
#[doc = "Write all high Voltage page latches with the same 32-bit data in a single write cycle"]
#[inline(always)]
pub fn data32(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
FmHvDataAll_SPEC,
crate::common::W,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
FmHvDataAll_SPEC,
crate::common::W,
>::from_register(self, 0)
}
}
impl ::core::default::Default for FmHvDataAll {
#[inline(always)]
fn default() -> FmHvDataAll {
<crate::RegValueT<FmHvDataAll_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CalCtl0_SPEC;
impl crate::sealed::RegSpec for CalCtl0_SPEC {
type DataType = u32;
}
#[doc = "Cal control BG LO trim bits"]
pub type CalCtl0 = crate::RegValueT<CalCtl0_SPEC>;
impl CalCtl0 {
#[doc = "LO Bandgap Voltage Temperature Compensation trim control."]
#[inline(always)]
pub fn vct_trim_lo_hv(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, CalCtl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,CalCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "LO Temperature compensated trim DAC. To control Vcstat slope for Vpos."]
#[inline(always)]
pub fn cdac_lo_hv(
self,
) -> crate::common::RegisterField<5, 0x7, 1, 0, u8, u8, CalCtl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<5,0x7,1,0,u8,u8,CalCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "LO Bandgap Voltage trim control."]
#[inline(always)]
pub fn vbg_trim_lo_hv(
self,
) -> crate::common::RegisterField<8, 0x1f, 1, 0, u8, u8, CalCtl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x1f,1,0,u8,u8,CalCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "LO Bandgap Voltage Temperature Compensation trim control"]
#[inline(always)]
pub fn vbg_tc_trim_lo_hv(
self,
) -> crate::common::RegisterField<13, 0x7, 1, 0, u8, u8, CalCtl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<13,0x7,1,0,u8,u8,CalCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "LO Bandgap IPTAT trim control."]
#[inline(always)]
pub fn ipref_trim_lo_hv(
self,
) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, CalCtl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xf,1,0,u8,u8,CalCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CalCtl0 {
#[inline(always)]
fn default() -> CalCtl0 {
<crate::RegValueT<CalCtl0_SPEC> as RegisterValue<_>>::new(561039)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CalCtl1_SPEC;
impl crate::sealed::RegSpec for CalCtl1_SPEC {
type DataType = u32;
}
#[doc = "Cal control BG HI trim bits"]
pub type CalCtl1 = crate::RegValueT<CalCtl1_SPEC>;
impl CalCtl1 {
#[doc = "HI Bandgap Voltage Temperature Compensation trim control."]
#[inline(always)]
pub fn vct_trim_hi_hv(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, CalCtl1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,CalCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "HI Temperature compensated trim DAC. To control Vcstat slope for Vpos."]
#[inline(always)]
pub fn cdac_hi_hv(
self,
) -> crate::common::RegisterField<5, 0x7, 1, 0, u8, u8, CalCtl1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<5,0x7,1,0,u8,u8,CalCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "HI Bandgap Voltage trim control."]
#[inline(always)]
pub fn vbg_trim_hi_hv(
self,
) -> crate::common::RegisterField<8, 0x1f, 1, 0, u8, u8, CalCtl1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x1f,1,0,u8,u8,CalCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "HI Bandgap Voltage Temperature Compensation trim control."]
#[inline(always)]
pub fn vbg_tc_trim_hi_hv(
self,
) -> crate::common::RegisterField<13, 0x7, 1, 0, u8, u8, CalCtl1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<13,0x7,1,0,u8,u8,CalCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "HI Bandgap IPTAT trim control."]
#[inline(always)]
pub fn ipref_trim_hi_hv(
self,
) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, CalCtl1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xf,1,0,u8,u8,CalCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CalCtl1 {
#[inline(always)]
fn default() -> CalCtl1 {
<crate::RegValueT<CalCtl1_SPEC> as RegisterValue<_>>::new(561039)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CalCtl2_SPEC;
impl crate::sealed::RegSpec for CalCtl2_SPEC {
type DataType = u32;
}
#[doc = "Cal control BG LO&HI ipref trim, ref sel, fm_active, turbo_ext"]
pub type CalCtl2 = crate::RegValueT<CalCtl2_SPEC>;
impl CalCtl2 {
#[doc = "LO Bandgap Current trim control."]
#[inline(always)]
pub fn icref_trim_lo_hv(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, CalCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,CalCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "LO Bandgap Current Temperature Compensation trim control"]
#[inline(always)]
pub fn icref_tc_trim_lo_hv(
self,
) -> crate::common::RegisterField<5, 0x7, 1, 0, u8, u8, CalCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<5,0x7,1,0,u8,u8,CalCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "HI Bandgap Current trim control."]
#[inline(always)]
pub fn icref_trim_hi_hv(
self,
) -> crate::common::RegisterField<8, 0x1f, 1, 0, u8, u8, CalCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x1f,1,0,u8,u8,CalCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "HI Bandgap Current Temperature Compensation trim control."]
#[inline(always)]
pub fn icref_tc_trim_hi_hv(
self,
) -> crate::common::RegisterField<13, 0x7, 1, 0, u8, u8, CalCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<13,0x7,1,0,u8,u8,CalCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Voltage reference:\n\'0\': internal bandgap reference\n\'1\': external voltage reference"]
#[inline(always)]
pub fn vref_sel_hv(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, CalCtl2_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,CalCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Current reference:\n\'0\': internal current reference\n\'1\': external current reference"]
#[inline(always)]
pub fn iref_sel_hv(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, CalCtl2_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,CalCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "0: No Action\n1: Forces FM SYS in active mode"]
#[inline(always)]
pub fn fm_active_hv(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, CalCtl2_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,CalCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "0: turbo signal generated internally\n1: turbo cleared by clk_pump_ext HI"]
#[inline(always)]
pub fn turbo_ext_hv(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, CalCtl2_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,CalCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CalCtl2 {
#[inline(always)]
fn default() -> CalCtl2 {
<crate::RegValueT<CalCtl2_SPEC> as RegisterValue<_>>::new(28784)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CalCtl3_SPEC;
impl crate::sealed::RegSpec for CalCtl3_SPEC {
type DataType = u32;
}
#[doc = "Cal control osc trim bits, idac, sdac, itim, bdac."]
pub type CalCtl3 = crate::RegValueT<CalCtl3_SPEC>;
impl CalCtl3 {
#[doc = "Flash macro pump clock trim control."]
#[inline(always)]
pub fn osc_trim_hv(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, CalCtl3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,CalCtl3_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "0: Oscillator High Frequency Range\n1: Oscillator Low Frequency range"]
#[inline(always)]
pub fn osc_range_trim_hv(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, CalCtl3_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,CalCtl3_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn idac_hv(
self,
) -> crate::common::RegisterField<5, 0xf, 1, 0, u8, u8, CalCtl3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<5,0xf,1,0,u8,u8,CalCtl3_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn sdac_hv(
self,
) -> crate::common::RegisterField<9, 0x3, 1, 0, u8, u8, CalCtl3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<9,0x3,1,0,u8,u8,CalCtl3_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Trimming of timing current"]
#[inline(always)]
pub fn itim_hv(
self,
) -> crate::common::RegisterField<11, 0xf, 1, 0, u8, u8, CalCtl3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<11,0xf,1,0,u8,u8,CalCtl3_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "0\': vdd<2.3V\n\'1\': vdd>=2.3V"]
#[inline(always)]
pub fn vddhi_hv(
self,
) -> crate::common::RegisterFieldBool<15, 1, 0, CalCtl3_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<15,1,0,CalCtl3_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Turbo pulse width trim"]
#[inline(always)]
pub fn turbo_pulsew_hv(
self,
) -> crate::common::RegisterField<16, 0x3, 1, 0, u8, u8, CalCtl3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0x3,1,0,u8,u8,CalCtl3_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "LO Bandgap Enable"]
#[inline(always)]
pub fn bglo_en_hv(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, CalCtl3_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,CalCtl3_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "HI Bandgap Enable"]
#[inline(always)]
pub fn bghi_en_hv(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, CalCtl3_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,CalCtl3_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for CalCtl3 {
#[inline(always)]
fn default() -> CalCtl3 {
<crate::RegValueT<CalCtl3_SPEC> as RegisterValue<_>>::new(42244)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Bookmark_SPEC;
impl crate::sealed::RegSpec for Bookmark_SPEC {
type DataType = u32;
}
#[doc = "Bookmark register - keeps the current FW HV seq"]
pub type Bookmark = crate::RegValueT<Bookmark_SPEC>;
impl Bookmark {
#[doc = "Used by FW. Keeps the Current HV cycle sequence"]
#[inline(always)]
pub fn bookmark(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
Bookmark_SPEC,
crate::common::W,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
Bookmark_SPEC,
crate::common::W,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Bookmark {
#[inline(always)]
fn default() -> Bookmark {
<crate::RegValueT<Bookmark_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RedCtl01_SPEC;
impl crate::sealed::RegSpec for RedCtl01_SPEC {
type DataType = u32;
}
#[doc = "Redundancy Control normal sectors 0,1"]
pub type RedCtl01 = crate::RegValueT<RedCtl01_SPEC>;
impl RedCtl01 {
#[doc = "Bad Row Pair Address for Sector 0"]
#[inline(always)]
pub fn red_addr_0(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, RedCtl01_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,RedCtl01_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "\'1\': Redundancy Enable for Sector 0"]
#[inline(always)]
pub fn red_en_0(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, RedCtl01_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,RedCtl01_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Bad Row Pair Address for Sector 1"]
#[inline(always)]
pub fn red_addr_1(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, RedCtl01_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,RedCtl01_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "\'1\': Redundancy Enable for Sector 1"]
#[inline(always)]
pub fn red_en_1(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, RedCtl01_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,RedCtl01_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RedCtl01 {
#[inline(always)]
fn default() -> RedCtl01 {
<crate::RegValueT<RedCtl01_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RedCtl23_SPEC;
impl crate::sealed::RegSpec for RedCtl23_SPEC {
type DataType = u32;
}
#[doc = "Redundancy Controll normal sectors 2,3"]
pub type RedCtl23 = crate::RegValueT<RedCtl23_SPEC>;
impl RedCtl23 {
#[doc = "Bad Row Pair Address for Sector 2"]
#[inline(always)]
pub fn red_addr_2(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, RedCtl23_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,RedCtl23_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "1\': Redundancy Enable for Sector 2"]
#[inline(always)]
pub fn red_en_2(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, RedCtl23_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,RedCtl23_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Bad Row Pair Address for Sector 3"]
#[inline(always)]
pub fn red_addr_3(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, RedCtl23_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,RedCtl23_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "1\': Redundancy Enable for Sector 3"]
#[inline(always)]
pub fn red_en_3(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, RedCtl23_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,RedCtl23_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RedCtl23 {
#[inline(always)]
fn default() -> RedCtl23 {
<crate::RegValueT<RedCtl23_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RedCtl45_SPEC;
impl crate::sealed::RegSpec for RedCtl45_SPEC {
type DataType = u32;
}
#[doc = "Redundancy Controll normal sectors 4,5"]
pub type RedCtl45 = crate::RegValueT<RedCtl45_SPEC>;
impl RedCtl45 {
#[doc = "Not Used"]
#[inline(always)]
pub fn dnu_45_1(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, RedCtl45_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,RedCtl45_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Forces the VBST regulator in active mode all the time"]
#[inline(always)]
pub fn reg_act_hv(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, RedCtl45_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,RedCtl45_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Not Used"]
#[inline(always)]
pub fn dnu_45_3(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, RedCtl45_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,RedCtl45_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "\'2b00\' F = 1MHz see fdiv_trim_hv<1> value as well\n\'2b01\' F = 0.5MHz\n\'2b10\' F = 2MHz\n\'2b11\' F = 4Mhz"]
#[inline(always)]
pub fn fdiv_trim_hv_0(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, RedCtl45_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,RedCtl45_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Not Used"]
#[inline(always)]
pub fn dnu_45_5(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, RedCtl45_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,RedCtl45_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "\'2b00\' F = 1MHz see fdiv_trim_hv<0> value as well\n\'2b01\' F = 0.5MHz\n\'2b10\' F = 2MHz\n\'2b11\' F = 4Mhz"]
#[inline(always)]
pub fn fdiv_trim_hv_1(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, RedCtl45_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,RedCtl45_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Not Used"]
#[inline(always)]
pub fn dnu_45_6(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, RedCtl45_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,RedCtl45_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "\'2b00\' V2 = 650mV see vlim_trim_hv<1> value as well\n\'2b01\' V2 = 600mV\n\'2b10\' V2 = 750mV\n\'2b11\' V2 = 700mV"]
#[inline(always)]
pub fn vlim_trim_hv_0(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, RedCtl45_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,RedCtl45_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Not Used"]
#[inline(always)]
pub fn dnu_45_8(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, RedCtl45_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,RedCtl45_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Not Used"]
#[inline(always)]
pub fn dnu_45_23_16(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, RedCtl45_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,RedCtl45_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RedCtl45 {
#[inline(always)]
fn default() -> RedCtl45 {
<crate::RegValueT<RedCtl45_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RedCtl67_SPEC;
impl crate::sealed::RegSpec for RedCtl67_SPEC {
type DataType = u32;
}
#[doc = "Redundancy Controll normal sectors 6,7"]
pub type RedCtl67 = crate::RegValueT<RedCtl67_SPEC>;
impl RedCtl67 {
#[doc = "\'2b00\' V2 = 650mV see vlim_trim_hv<0> value as well\n\'2b01\' V2 = 600mV\n\'2b10\' V2 = 750mV\n\'2b11\' V2 = 700mV"]
#[inline(always)]
pub fn vlim_trim_hv_1(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, RedCtl67_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,RedCtl67_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Not Used"]
#[inline(always)]
pub fn dnu_67_1(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, RedCtl67_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,RedCtl67_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Forces VPROT in active mode all the time"]
#[inline(always)]
pub fn vprot_act_hv(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, RedCtl67_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2,1,0,RedCtl67_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Not Used"]
#[inline(always)]
pub fn dnu_67_3(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, RedCtl67_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<3,1,0,RedCtl67_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Reduces the IPREF Tempco by not subtracting ICREF form IPREF - IPREF will be 1uA"]
#[inline(always)]
pub fn ipref_tc_hv(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, RedCtl67_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,RedCtl67_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Not Used"]
#[inline(always)]
pub fn dnu_67_5(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, RedCtl67_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5,1,0,RedCtl67_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Adds 200-300nA boost on IPREF_HI"]
#[inline(always)]
pub fn ipref_trima_hi_hv(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, RedCtl67_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6,1,0,RedCtl67_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Not Used"]
#[inline(always)]
pub fn dnu_67_7(
self,
) -> crate::common::RegisterFieldBool<7, 1, 0, RedCtl67_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<7,1,0,RedCtl67_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Adds 200-300nA boost on IPREF_LO"]
#[inline(always)]
pub fn ipref_trima_lo_hv(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, RedCtl67_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,RedCtl67_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Not Used"]
#[inline(always)]
pub fn dnu_67_23_16(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, RedCtl67_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,RedCtl67_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RedCtl67 {
#[inline(always)]
fn default() -> RedCtl67 {
<crate::RegValueT<RedCtl67_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RedCtlSm01_SPEC;
impl crate::sealed::RegSpec for RedCtlSm01_SPEC {
type DataType = u32;
}
#[doc = "Redundancy Controll special sectors 0,1"]
pub type RedCtlSm01 = crate::RegValueT<RedCtlSm01_SPEC>;
impl RedCtlSm01 {
#[doc = "Bad Row Pair Address for Special Sector 0"]
#[inline(always)]
pub fn red_addr_sm0(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, RedCtlSm01_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,RedCtlSm01_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Redundancy Enable for Special Sector 0"]
#[inline(always)]
pub fn red_en_sm0(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, RedCtlSm01_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8,1,0,RedCtlSm01_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Bad Row Pair Address for Special Sector 1"]
#[inline(always)]
pub fn red_addr_sm1(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, RedCtlSm01_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,RedCtlSm01_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Redundancy Enable for Special Sector 1"]
#[inline(always)]
pub fn red_en_sm1(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, RedCtlSm01_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<24,1,0,RedCtlSm01_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Sense Amp Control tracking delay"]
#[inline(always)]
pub fn trkd(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, RedCtlSm01_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<30,1,0,RedCtlSm01_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "\'0\': r_grant handshake disabled, r_grant always 1.\n \'1\': r_grand handshake enabled"]
#[inline(always)]
pub fn r_grant_en(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, RedCtlSm01_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<31,1,0,RedCtlSm01_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RedCtlSm01 {
#[inline(always)]
fn default() -> RedCtlSm01 {
<crate::RegValueT<RedCtlSm01_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TmCmpr_SPEC;
impl crate::sealed::RegSpec for TmCmpr_SPEC {
type DataType = u32;
}
#[doc = "Do Not Use"]
pub type TmCmpr = crate::RegValueT<TmCmpr_SPEC>;
impl TmCmpr {
#[doc = "The result of a comparison between the flash macro data output and the content of the high voltage page latches. \nThe comparison result for a given column \'Column_Number\' is updated in this register field on a read to address: 0x100+4*Column_Number.\nThe number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD.\n\'0\': FALSE (not equal)\n\n\'1\': TRUE (equal)"]
#[inline(always)]
pub fn data_comp_result(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, TmCmpr_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,TmCmpr_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for TmCmpr {
#[inline(always)]
fn default() -> TmCmpr {
<crate::RegValueT<TmCmpr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct FmHvData_SPEC;
impl crate::sealed::RegSpec for FmHvData_SPEC {
type DataType = u32;
}
#[doc = "Flash macro high Voltage page latches data"]
pub type FmHvData = crate::RegValueT<FmHvData_SPEC>;
impl FmHvData {
#[doc = "Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be \'1\').\n\nNote: the high Voltage page latches are readable for test mode functionality."]
#[inline(always)]
pub fn data32(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
FmHvData_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
FmHvData_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for FmHvData {
#[inline(always)]
fn default() -> FmHvData {
<crate::RegValueT<FmHvData_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct FmMemData_SPEC;
impl crate::sealed::RegSpec for FmMemData_SPEC {
type DataType = u32;
}
#[doc = "Flash macro memory sense amplifier and column decoder data"]
pub type FmMemData = crate::RegValueT<FmMemData_SPEC>;
impl FmMemData {
#[doc = "Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL:\n- IF_SEL is \'0\': data as specified by the R interface address\n- IF_SEL is \'1\': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register."]
#[inline(always)]
pub fn data32(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
FmMemData_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
FmMemData_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for FmMemData {
#[inline(always)]
fn default() -> FmMemData {
<crate::RegValueT<FmMemData_SPEC> as RegisterValue<_>>::new(0)
}
}
}