/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"I2S registers"]
unsafe impl ::core::marker::Send for super::I2S {}
unsafe impl ::core::marker::Sync for super::I2S {}
impl super::I2S {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "Control"]
#[inline(always)]
pub const fn ctl(&self) -> &'static crate::common::Reg<self::Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Clock control"]
#[inline(always)]
pub const fn clock_ctl(
&self,
) -> &'static crate::common::Reg<self::ClockCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ClockCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16usize),
)
}
}
#[doc = "Command"]
#[inline(always)]
pub const fn cmd(&self) -> &'static crate::common::Reg<self::Cmd_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cmd_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "Trigger control"]
#[inline(always)]
pub const fn tr_ctl(&self) -> &'static crate::common::Reg<self::TrCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TrCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(64usize),
)
}
}
#[doc = "Transmitter control"]
#[inline(always)]
pub const fn tx_ctl(&self) -> &'static crate::common::Reg<self::TxCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TxCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(128usize),
)
}
}
#[doc = "Transmitter watchdog"]
#[inline(always)]
pub const fn tx_watchdog(
&self,
) -> &'static crate::common::Reg<self::TxWatchdog_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TxWatchdog_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(132usize),
)
}
}
#[doc = "Receiver control"]
#[inline(always)]
pub const fn rx_ctl(&self) -> &'static crate::common::Reg<self::RxCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::RxCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(160usize),
)
}
}
#[doc = "Receiver watchdog"]
#[inline(always)]
pub const fn rx_watchdog(
&self,
) -> &'static crate::common::Reg<self::RxWatchdog_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::RxWatchdog_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(164usize),
)
}
}
#[doc = "TX FIFO control"]
#[inline(always)]
pub const fn tx_fifo_ctl(
&self,
) -> &'static crate::common::Reg<self::TxFifoCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TxFifoCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(512usize),
)
}
}
#[doc = "TX FIFO status"]
#[inline(always)]
pub const fn tx_fifo_status(
&self,
) -> &'static crate::common::Reg<self::TxFifoStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::TxFifoStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(516usize),
)
}
}
#[doc = "TX FIFO write"]
#[inline(always)]
pub const fn tx_fifo_wr(
&self,
) -> &'static crate::common::Reg<self::TxFifoWr_SPEC, crate::common::W> {
unsafe {
crate::common::Reg::<self::TxFifoWr_SPEC, crate::common::W>::from_ptr(
self._svd2pac_as_ptr().add(520usize),
)
}
}
#[doc = "RX FIFO control"]
#[inline(always)]
pub const fn rx_fifo_ctl(
&self,
) -> &'static crate::common::Reg<self::RxFifoCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::RxFifoCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(768usize),
)
}
}
#[doc = "RX FIFO status"]
#[inline(always)]
pub const fn rx_fifo_status(
&self,
) -> &'static crate::common::Reg<self::RxFifoStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::RxFifoStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(772usize),
)
}
}
#[doc = "RX FIFO read"]
#[inline(always)]
pub const fn rx_fifo_rd(
&self,
) -> &'static crate::common::Reg<self::RxFifoRd_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::RxFifoRd_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(776usize),
)
}
}
#[doc = "RX FIFO silent read"]
#[inline(always)]
pub const fn rx_fifo_rd_silent(
&self,
) -> &'static crate::common::Reg<self::RxFifoRdSilent_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::RxFifoRdSilent_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(780usize),
)
}
}
#[doc = "Interrupt register"]
#[inline(always)]
pub const fn intr(&self) -> &'static crate::common::Reg<self::Intr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Intr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3840usize),
)
}
}
#[doc = "Interrupt set register"]
#[inline(always)]
pub const fn intr_set(
&self,
) -> &'static crate::common::Reg<self::IntrSet_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrSet_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3844usize),
)
}
}
#[doc = "Interrupt mask register"]
#[inline(always)]
pub const fn intr_mask(
&self,
) -> &'static crate::common::Reg<self::IntrMask_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::IntrMask_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(3848usize),
)
}
}
#[doc = "Interrupt masked register"]
#[inline(always)]
pub const fn intr_masked(
&self,
) -> &'static crate::common::Reg<self::IntrMasked_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::IntrMasked_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(3852usize),
)
}
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctl_SPEC;
impl crate::sealed::RegSpec for Ctl_SPEC {
type DataType = u32;
}
#[doc = "Control"]
pub type Ctl = crate::RegValueT<Ctl_SPEC>;
impl Ctl {
#[doc = "Enables the I2S TX component:\n\'0\': Disabled.\n\'1\': Enabled."]
#[inline(always)]
pub fn tx_enabled(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30, 1, 0, Ctl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Enables the I2S RX component:\n\'0\': Disabled.\n\'1\': Enabled."]
#[inline(always)]
pub fn rx_enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31, 1, 0, Ctl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Ctl {
#[inline(always)]
fn default() -> Ctl {
<crate::RegValueT<Ctl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ClockCtl_SPEC;
impl crate::sealed::RegSpec for ClockCtl_SPEC {
type DataType = u32;
}
#[doc = "Clock control"]
pub type ClockCtl = crate::RegValueT<ClockCtl_SPEC>;
impl ClockCtl {
#[doc = "Frequency divisor for generating I2S clock frequency.\nThe selected clock with CLOCK_SEL is divided by this. \n\'0\': Bypass\n\'1\': 2 x\n\'2\': 3 x\n\'3\': 4 x\n...\n\'62\': 63 x\n\'63\': 64 x"]
#[inline(always)]
pub fn clock_div(
self,
) -> crate::common::RegisterField<0, 0x3f, 1, 0, u8, u8, ClockCtl_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0x3f,1,0,u8,u8,ClockCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Selects clock to be used by I2S:\n\'0\': Internal clock (\'clk_audio_i2s\')\n\'1\': External clock (\'clk_i2s_if\')"]
#[inline(always)]
pub fn clock_sel(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, ClockCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, ClockCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for ClockCtl {
#[inline(always)]
fn default() -> ClockCtl {
<crate::RegValueT<ClockCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cmd_SPEC;
impl crate::sealed::RegSpec for Cmd_SPEC {
type DataType = u32;
}
#[doc = "Command"]
pub type Cmd = crate::RegValueT<Cmd_SPEC>;
impl Cmd {
#[doc = "Transmitter enable:\n\'0\': Disabled.\n\'1\': Enabled."]
#[inline(always)]
pub fn tx_start(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Cmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Cmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Pause enable:\n\'0\': Disabled (TX FIFO data is sent over I2S).\n\'1\': Enabled (\'0\' data is sent over I2S, instead of TX FIFO data)."]
#[inline(always)]
pub fn tx_pause(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Cmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, Cmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Receiver enable:\n\'0\': Disabled.\n\'1\': Enabled."]
#[inline(always)]
pub fn rx_start(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Cmd_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16, 1, 0, Cmd_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Cmd {
#[inline(always)]
fn default() -> Cmd {
<crate::RegValueT<Cmd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrCtl_SPEC;
impl crate::sealed::RegSpec for TrCtl_SPEC {
type DataType = u32;
}
#[doc = "Trigger control"]
pub type TrCtl = crate::RegValueT<TrCtl_SPEC>;
impl TrCtl {
#[doc = "Trigger output (\'tr_i2s_tx_req\') enable for requests of DMA transfer in transmission\n\'0\': Disabled.\n\'1\': Enabled."]
#[inline(always)]
pub fn tx_req_en(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, TrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, TrCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Trigger output (\'tr_i2s_rx_req\') enable for requests of DMA transfer in reception\n\'0\': Disabled.\n\'1\': Enabled."]
#[inline(always)]
pub fn rx_req_en(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, TrCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16, 1, 0, TrCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for TrCtl {
#[inline(always)]
fn default() -> TrCtl {
<crate::RegValueT<TrCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxCtl_SPEC;
impl crate::sealed::RegSpec for TxCtl_SPEC {
type DataType = u32;
}
#[doc = "Transmitter control"]
pub type TxCtl = crate::RegValueT<TxCtl_SPEC>;
impl TxCtl {
#[doc = "Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode.\nWhen set to \'1\', the serial data will be transmitted 0.5 SCK cycles earlier than when set to \'0\'. \n\n1) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK falling edge\n2) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK rising edge that is 0.5 SCK cycles before the SCK falling edge in 1)\n3) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK rising edge\n4) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK falling edge that is 0.5 SCK cycles before the SCK rising edge in 3)\n\n(Note that this is only the appearance w.r.t. SCK edge, the actual timing is generated by an internal clock that runs 8x the SCK frequency). The word sync (TX_WS) signal is not affected by this bit setting. \nNote: When Master mode, must be \'0\'."]
#[inline(always)]
pub fn b_clock_inv(
self,
) -> crate::common::RegisterField<
3,
0x1,
1,
0,
tx_ctl::BClockInv,
tx_ctl::BClockInv,
TxCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
3,
0x1,
1,
0,
tx_ctl::BClockInv,
tx_ctl::BClockInv,
TxCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Specifies number of channels per frame:\n\nNote: only \'2channels\' is supported during Left Justfied or I2S mode. Hence software must set \'1\' to this field in the modes."]
#[inline(always)]
pub fn ch_nr(
self,
) -> crate::common::RegisterField<
4,
0x7,
1,
0,
tx_ctl::ChNr,
tx_ctl::ChNr,
TxCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x7,
1,
0,
tx_ctl::ChNr,
tx_ctl::ChNr,
TxCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Set interface in master or slave mode:"]
#[inline(always)]
pub fn ms(
self,
) -> crate::common::RegisterField<
7,
0x1,
1,
0,
tx_ctl::Ms,
tx_ctl::Ms,
TxCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
7,
0x1,
1,
0,
tx_ctl::Ms,
tx_ctl::Ms,
TxCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Select I2S, left-justified or TDM:"]
#[inline(always)]
pub fn i2s_mode(
self,
) -> crate::common::RegisterField<
8,
0x3,
1,
0,
tx_ctl::I2SMode,
tx_ctl::I2SMode,
TxCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0x3,
1,
0,
tx_ctl::I2SMode,
tx_ctl::I2SMode,
TxCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Set WS pulse width in TDM mode:\nNote: When not TDM mode, must be \'1\'."]
#[inline(always)]
pub fn ws_pulse(
self,
) -> crate::common::RegisterField<
10,
0x1,
1,
0,
tx_ctl::WsPulse,
tx_ctl::WsPulse,
TxCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
10,
0x1,
1,
0,
tx_ctl::WsPulse,
tx_ctl::WsPulse,
TxCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Set overhead value:\n\'0\': Set to \'0\'\n\'1\': Set to \'1\'"]
#[inline(always)]
pub fn ovhdata(
self,
) -> crate::common::RegisterFieldBool<12, 1, 0, TxCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<12, 1, 0, TxCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn wd_en(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, TxCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<13, 1, 0, TxCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Channel length in number of bits:\n\nNote: \n- When this field is configured to \'6\' or \'7\', the length is set to 32-bit (same as \'5\').\n- When TDM mode, must be 32-bit length to this field."]
#[inline(always)]
pub fn ch_len(
self,
) -> crate::common::RegisterField<
16,
0x7,
1,
0,
tx_ctl::ChLen,
tx_ctl::ChLen,
TxCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0x7,
1,
0,
tx_ctl::ChLen,
tx_ctl::ChLen,
TxCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Word length in number of bits:\n\nNote: \n- When this field is configured to \'6\' or \'7\', the length is set to 32-bit (same as \'5\').\n- Don\'t configure this field as beyond Channel length."]
#[inline(always)]
pub fn word_len(
self,
) -> crate::common::RegisterField<
20,
0x7,
1,
0,
tx_ctl::WordLen,
tx_ctl::WordLen,
TxCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
20,
0x7,
1,
0,
tx_ctl::WordLen,
tx_ctl::WordLen,
TxCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn scko_pol(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, TxCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24, 1, 0, TxCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn scki_pol(
self,
) -> crate::common::RegisterFieldBool<25, 1, 0, TxCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<25, 1, 0, TxCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for TxCtl {
#[inline(always)]
fn default() -> TxCtl {
<crate::RegValueT<TxCtl_SPEC> as RegisterValue<_>>::new(4457744)
}
}
pub mod tx_ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct BClockInv_SPEC;
pub type BClockInv = crate::EnumBitfieldStruct<u8, BClockInv_SPEC>;
impl BClockInv {
#[doc = "SDO transmitted at SCK falling edge when TX_CTL.SCKI_POL=0"]
pub const FALLING_EDGE_TX: Self = Self::new(0);
#[doc = "SDO transmitted at SCK rising edge when TX_CTL.SCKI_POL=0"]
pub const RISING_EDGE_TX: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ChNr_SPEC;
pub type ChNr = crate::EnumBitfieldStruct<u8, ChNr_SPEC>;
impl ChNr {
#[doc = "1 channel"]
pub const CH_NUM_1: Self = Self::new(0);
#[doc = "2 channels"]
pub const CH_NUM_2: Self = Self::new(1);
#[doc = "3 channels"]
pub const CH_NUM_3: Self = Self::new(2);
#[doc = "4 channels"]
pub const CH_NUM_4: Self = Self::new(3);
#[doc = "5 channels"]
pub const CH_NUM_5: Self = Self::new(4);
#[doc = "6 channels"]
pub const CH_NUM_6: Self = Self::new(5);
#[doc = "7 channels"]
pub const CH_NUM_7: Self = Self::new(6);
#[doc = "8 channels"]
pub const CH_NUM_8: Self = Self::new(7);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Ms_SPEC;
pub type Ms = crate::EnumBitfieldStruct<u8, Ms_SPEC>;
impl Ms {
#[doc = "Slave"]
pub const SLAVE: Self = Self::new(0);
#[doc = "Master"]
pub const MASTER: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct I2SMode_SPEC;
pub type I2SMode = crate::EnumBitfieldStruct<u8, I2SMode_SPEC>;
impl I2SMode {
#[doc = "Left Justified"]
pub const LEFT_JUSTIFIED: Self = Self::new(0);
#[doc = "I2S mode"]
pub const I_2_S: Self = Self::new(1);
#[doc = "TDM mode A, the 1st Channel align to WSO \nRising Edge"]
pub const TDM_A: Self = Self::new(2);
#[doc = "TDM mode B, the 1st Channel align to WSO\nRising edge with1 SCK Delay"]
pub const TDM_B: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct WsPulse_SPEC;
pub type WsPulse = crate::EnumBitfieldStruct<u8, WsPulse_SPEC>;
impl WsPulse {
#[doc = "Pulse width is 1 SCK period"]
pub const SCK_PERIOD: Self = Self::new(0);
#[doc = "Pulse width is 1 channel length"]
pub const CH_LENGTH: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ChLen_SPEC;
pub type ChLen = crate::EnumBitfieldStruct<u8, ChLen_SPEC>;
impl ChLen {
#[doc = "8-bit"]
pub const BIT_LEN_8: Self = Self::new(0);
#[doc = "16-bit"]
pub const BIT_LEN_16: Self = Self::new(1);
#[doc = "18-bit"]
pub const BIT_LEN_18: Self = Self::new(2);
#[doc = "20-bit"]
pub const BIT_LEN_20: Self = Self::new(3);
#[doc = "24-bit"]
pub const BIT_LEN_24: Self = Self::new(4);
#[doc = "32-bit"]
pub const BIT_LEN_32: Self = Self::new(5);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct WordLen_SPEC;
pub type WordLen = crate::EnumBitfieldStruct<u8, WordLen_SPEC>;
impl WordLen {
#[doc = "8-bit"]
pub const BIT_LEN_8: Self = Self::new(0);
#[doc = "16-bit"]
pub const BIT_LEN_16: Self = Self::new(1);
#[doc = "18-bit"]
pub const BIT_LEN_18: Self = Self::new(2);
#[doc = "20-bit"]
pub const BIT_LEN_20: Self = Self::new(3);
#[doc = "24-bit"]
pub const BIT_LEN_24: Self = Self::new(4);
#[doc = "32-bit"]
pub const BIT_LEN_32: Self = Self::new(5);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxWatchdog_SPEC;
impl crate::sealed::RegSpec for TxWatchdog_SPEC {
type DataType = u32;
}
#[doc = "Transmitter watchdog"]
pub type TxWatchdog = crate::RegValueT<TxWatchdog_SPEC>;
impl TxWatchdog {
#[doc = "Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock \'clk_sys\'."]
#[inline(always)]
pub fn wd_counter(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
TxWatchdog_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
TxWatchdog_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for TxWatchdog {
#[inline(always)]
fn default() -> TxWatchdog {
<crate::RegValueT<TxWatchdog_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxCtl_SPEC;
impl crate::sealed::RegSpec for RxCtl_SPEC {
type DataType = u32;
}
#[doc = "Receiver control"]
pub type RxCtl = crate::RegValueT<RxCtl_SPEC>;
impl RxCtl {
#[doc = "Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode.\nWhen set to \'1\', the serial data will be captured 0.5 SCK cycles later than when set to \'0\'.\n\n1) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK rising edge\n2) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK falling edge that is 0.5 SCK cycles after the SCK rising edge in 1)\n3) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK falling edge\n4) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK rising edge that is 0.5 SCK cycles after the SCK falling edge in 3)\n\n(Note that this is only the appearance w.r.t. SCK edge, the actual capture timing is derived from an internal clock that runs 8x the SCK frequency). The word sync (RX_WS) signal is not affected by this bit setting. \nNote: When Slave mode, must be \'0\'."]
#[inline(always)]
pub fn b_clock_inv(
self,
) -> crate::common::RegisterField<
3,
0x1,
1,
0,
rx_ctl::BClockInv,
rx_ctl::BClockInv,
RxCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
3,
0x1,
1,
0,
rx_ctl::BClockInv,
rx_ctl::BClockInv,
RxCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Specifies number of channels per frame:\n\nNote: only \'2channels\' is supported during Left Justfied or I2S mode. Hence software must set \'1\' to this field in the modes."]
#[inline(always)]
pub fn ch_nr(
self,
) -> crate::common::RegisterField<
4,
0x7,
1,
0,
rx_ctl::ChNr,
rx_ctl::ChNr,
RxCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
4,
0x7,
1,
0,
rx_ctl::ChNr,
rx_ctl::ChNr,
RxCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Set interface in master or slave mode:"]
#[inline(always)]
pub fn ms(
self,
) -> crate::common::RegisterField<
7,
0x1,
1,
0,
rx_ctl::Ms,
rx_ctl::Ms,
RxCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
7,
0x1,
1,
0,
rx_ctl::Ms,
rx_ctl::Ms,
RxCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Select I2S, left-justified or TDM:"]
#[inline(always)]
pub fn i2s_mode(
self,
) -> crate::common::RegisterField<
8,
0x3,
1,
0,
rx_ctl::I2SMode,
rx_ctl::I2SMode,
RxCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0x3,
1,
0,
rx_ctl::I2SMode,
rx_ctl::I2SMode,
RxCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Set WS pulse width in TDM mode:\nNote: When not TDM mode, must be \'1\'."]
#[inline(always)]
pub fn ws_pulse(
self,
) -> crate::common::RegisterField<
10,
0x1,
1,
0,
rx_ctl::WsPulse,
rx_ctl::WsPulse,
RxCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
10,
0x1,
1,
0,
rx_ctl::WsPulse,
rx_ctl::WsPulse,
RxCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn wd_en(
self,
) -> crate::common::RegisterFieldBool<13, 1, 0, RxCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<13, 1, 0, RxCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Channel length in number of bits:\n\nNote: \n- When this field is configured to \'6\' or \'7\', the length is set to 32-bit (same as \'5\').\n- When TDM mode, must be 32-bit length to this field."]
#[inline(always)]
pub fn ch_len(
self,
) -> crate::common::RegisterField<
16,
0x7,
1,
0,
rx_ctl::ChLen,
rx_ctl::ChLen,
RxCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
16,
0x7,
1,
0,
rx_ctl::ChLen,
rx_ctl::ChLen,
RxCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Word length in number of bits:\n\nNote: \n- When this field is configured to \'6\' or \'7\', the length is set to 32-bit (same as \'5\').\n- Don\'t configure this field as beyond Channel length."]
#[inline(always)]
pub fn word_len(
self,
) -> crate::common::RegisterField<
20,
0x7,
1,
0,
rx_ctl::WordLen,
rx_ctl::WordLen,
RxCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
20,
0x7,
1,
0,
rx_ctl::WordLen,
rx_ctl::WordLen,
RxCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "N/A"]
#[inline(always)]
pub fn bit_extension(
self,
) -> crate::common::RegisterFieldBool<23, 1, 0, RxCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<23, 1, 0, RxCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn scko_pol(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, RxCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24, 1, 0, RxCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "N/A"]
#[inline(always)]
pub fn scki_pol(
self,
) -> crate::common::RegisterFieldBool<25, 1, 0, RxCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<25, 1, 0, RxCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for RxCtl {
#[inline(always)]
fn default() -> RxCtl {
<crate::RegValueT<RxCtl_SPEC> as RegisterValue<_>>::new(4457744)
}
}
pub mod rx_ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct BClockInv_SPEC;
pub type BClockInv = crate::EnumBitfieldStruct<u8, BClockInv_SPEC>;
impl BClockInv {
#[doc = "SDI received at SCK rising edge when RX_CTL.SCKO_POL=0"]
pub const RISING_EDGE_RX: Self = Self::new(0);
#[doc = "SDI received at SCK falling edge when RX_CTL.SCKO_POL=0"]
pub const FALLING_EDGE_RX: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ChNr_SPEC;
pub type ChNr = crate::EnumBitfieldStruct<u8, ChNr_SPEC>;
impl ChNr {
#[doc = "1 channel"]
pub const CH_NUM_1: Self = Self::new(0);
#[doc = "2 channels"]
pub const CH_NUM_2: Self = Self::new(1);
#[doc = "3 channels"]
pub const CH_NUM_3: Self = Self::new(2);
#[doc = "4 channels"]
pub const CH_NUM_4: Self = Self::new(3);
#[doc = "5 channels"]
pub const CH_NUM_5: Self = Self::new(4);
#[doc = "6 channels"]
pub const CH_NUM_6: Self = Self::new(5);
#[doc = "7 channels"]
pub const CH_NUM_7: Self = Self::new(6);
#[doc = "8 channels"]
pub const CH_NUM_8: Self = Self::new(7);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct Ms_SPEC;
pub type Ms = crate::EnumBitfieldStruct<u8, Ms_SPEC>;
impl Ms {
#[doc = "Slave"]
pub const SLAVE: Self = Self::new(0);
#[doc = "Master"]
pub const MASTER: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct I2SMode_SPEC;
pub type I2SMode = crate::EnumBitfieldStruct<u8, I2SMode_SPEC>;
impl I2SMode {
#[doc = "Left Justified"]
pub const LEFT_JUSTIFIED: Self = Self::new(0);
#[doc = "I2S mode"]
pub const I_2_S: Self = Self::new(1);
#[doc = "TDM mode A, the 1st Channel align to WSO \nRising Edge"]
pub const TDM_A: Self = Self::new(2);
#[doc = "TDM mode B, the 1st Channel align to WSO\nRising edge with1 SCK Delay"]
pub const TDM_B: Self = Self::new(3);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct WsPulse_SPEC;
pub type WsPulse = crate::EnumBitfieldStruct<u8, WsPulse_SPEC>;
impl WsPulse {
#[doc = "Pulse width is 1 SCK period"]
pub const SCK_PERIOD: Self = Self::new(0);
#[doc = "Pulse width is 1 channel length"]
pub const CH_LENGTH: Self = Self::new(1);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct ChLen_SPEC;
pub type ChLen = crate::EnumBitfieldStruct<u8, ChLen_SPEC>;
impl ChLen {
#[doc = "8-bit"]
pub const BIT_LEN_8: Self = Self::new(0);
#[doc = "16-bit"]
pub const BIT_LEN_16: Self = Self::new(1);
#[doc = "18-bit"]
pub const BIT_LEN_18: Self = Self::new(2);
#[doc = "20-bit"]
pub const BIT_LEN_20: Self = Self::new(3);
#[doc = "24-bit"]
pub const BIT_LEN_24: Self = Self::new(4);
#[doc = "32-bit"]
pub const BIT_LEN_32: Self = Self::new(5);
}
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct WordLen_SPEC;
pub type WordLen = crate::EnumBitfieldStruct<u8, WordLen_SPEC>;
impl WordLen {
#[doc = "8-bit"]
pub const BIT_LEN_8: Self = Self::new(0);
#[doc = "16-bit"]
pub const BIT_LEN_16: Self = Self::new(1);
#[doc = "18-bit"]
pub const BIT_LEN_18: Self = Self::new(2);
#[doc = "20-bit"]
pub const BIT_LEN_20: Self = Self::new(3);
#[doc = "24-bit"]
pub const BIT_LEN_24: Self = Self::new(4);
#[doc = "32-bit"]
pub const BIT_LEN_32: Self = Self::new(5);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxWatchdog_SPEC;
impl crate::sealed::RegSpec for RxWatchdog_SPEC {
type DataType = u32;
}
#[doc = "Receiver watchdog"]
pub type RxWatchdog = crate::RegValueT<RxWatchdog_SPEC>;
impl RxWatchdog {
#[doc = "Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock \'clk_sys\'."]
#[inline(always)]
pub fn wd_counter(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
RxWatchdog_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
RxWatchdog_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RxWatchdog {
#[inline(always)]
fn default() -> RxWatchdog {
<crate::RegValueT<RxWatchdog_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxFifoCtl_SPEC;
impl crate::sealed::RegSpec for TxFifoCtl_SPEC {
type DataType = u32;
}
#[doc = "TX FIFO control"]
pub type TxFifoCtl = crate::RegValueT<TxFifoCtl_SPEC>;
impl TxFifoCtl {
#[doc = "Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated."]
#[inline(always)]
pub fn trigger_level(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, TxFifoCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,TxFifoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When \'1\', the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for as long as this field is \'1\'. If a quick clear/invalidation is required, the field should be set to \'1\' and be followed by a set to \'0\'. If a clear/invalidation is required for an extended time period, the field should be set to \'1\' during the complete time period."]
#[inline(always)]
pub fn clear(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, TxFifoCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,TxFifoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When \'1\', hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. This field is used only for debugging purposes."]
#[inline(always)]
pub fn freeze(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, TxFifoCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,TxFifoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TxFifoCtl {
#[inline(always)]
fn default() -> TxFifoCtl {
<crate::RegValueT<TxFifoCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxFifoStatus_SPEC;
impl crate::sealed::RegSpec for TxFifoStatus_SPEC {
type DataType = u32;
}
#[doc = "TX FIFO status"]
pub type TxFifoStatus = crate::RegValueT<TxFifoStatus_SPEC>;
impl TxFifoStatus {
#[doc = "Number of entries in the TX FIFO. The field value is in the range \\[0, 256\\]."]
#[inline(always)]
pub fn used(
self,
) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, TxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,TxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes."]
#[inline(always)]
pub fn rd_ptr(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, TxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,TxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "TX FIFO write pointer: FIFO location at which a new data frame is written by the host. This field is used only for debugging purposes."]
#[inline(always)]
pub fn wr_ptr(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, TxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,TxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for TxFifoStatus {
#[inline(always)]
fn default() -> TxFifoStatus {
<crate::RegValueT<TxFifoStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TxFifoWr_SPEC;
impl crate::sealed::RegSpec for TxFifoWr_SPEC {
type DataType = u32;
}
#[doc = "TX FIFO write"]
pub type TxFifoWr = crate::RegValueT<TxFifoWr_SPEC>;
impl TxFifoWr {
#[doc = "Data written into the TX FIFO. Behavior is similar to that of a PUSH operation. \nNote: Don\'t access to this register while TX_FIFO_CTL.CLEAR is \'1\'."]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, TxFifoWr_SPEC, crate::common::W>
{
crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,TxFifoWr_SPEC,crate::common::W>::from_register(self,0)
}
}
impl ::core::default::Default for TxFifoWr {
#[inline(always)]
fn default() -> TxFifoWr {
<crate::RegValueT<TxFifoWr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxFifoCtl_SPEC;
impl crate::sealed::RegSpec for RxFifoCtl_SPEC {
type DataType = u32;
}
#[doc = "RX FIFO control"]
pub type RxFifoCtl = crate::RegValueT<RxFifoCtl_SPEC>;
impl RxFifoCtl {
#[doc = "Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated.\nNote: software can configure up to 253 in I2S mode or Left Justified (RX_CTL.I2S_MODE = \'0\' or \'1\'). In TDM mode (RX_CTL.I2S_MODE = \'2\' or \'3\'), it can configure up to \\[256 - (RX_CTL.CH_NR+2)\\]."]
#[inline(always)]
pub fn trigger_level(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, RxFifoCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,RxFifoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When \'1\', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is \'1\'. If a quick clear/invalidation is required, the field should be set to \'1\' and be followed by a set to \'0\'. If a clear/invalidation is required for an extended time period, the field should be set to \'1\' during the complete time period."]
#[inline(always)]
pub fn clear(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, RxFifoCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,RxFifoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "When \'1\', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee."]
#[inline(always)]
pub fn freeze(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, RxFifoCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17,1,0,RxFifoCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RxFifoCtl {
#[inline(always)]
fn default() -> RxFifoCtl {
<crate::RegValueT<RxFifoCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxFifoStatus_SPEC;
impl crate::sealed::RegSpec for RxFifoStatus_SPEC {
type DataType = u32;
}
#[doc = "RX FIFO status"]
pub type RxFifoStatus = crate::RegValueT<RxFifoStatus_SPEC>;
impl RxFifoStatus {
#[doc = "Number of entries in the RX FIFO. The field value is in the range \\[0, 256\\]."]
#[inline(always)]
pub fn used(
self,
) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, RxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,RxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "RX FIFO read pointer: FIFO location from which a data frame is read by the host. This field is used only for debugging purposes."]
#[inline(always)]
pub fn rd_ptr(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, RxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,RxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware. This field is used only for debugging purposes."]
#[inline(always)]
pub fn wr_ptr(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, RxFifoStatus_SPEC, crate::common::R>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,RxFifoStatus_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for RxFifoStatus {
#[inline(always)]
fn default() -> RxFifoStatus {
<crate::RegValueT<RxFifoStatus_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxFifoRd_SPEC;
impl crate::sealed::RegSpec for RxFifoRd_SPEC {
type DataType = u32;
}
#[doc = "RX FIFO read"]
pub type RxFifoRd = crate::RegValueT<RxFifoRd_SPEC>;
impl RxFifoRd {
#[doc = "Data read from the RX FIFO. Reading a data frame will remove the data frame from the RX FIFO; i.e. behavior is similar to that of a POP operation. \nNotes: \n - Don\'t access to this register while RX_FIFO_CTL.CLEAR is \'1\'. \n - Two stored data may be not valid after CMD.RX_START is set \'1\'. Therefore we recommend software discard those data."]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, RxFifoRd_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,RxFifoRd_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for RxFifoRd {
#[inline(always)]
fn default() -> RxFifoRd {
<crate::RegValueT<RxFifoRd_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RxFifoRdSilent_SPEC;
impl crate::sealed::RegSpec for RxFifoRdSilent_SPEC {
type DataType = u32;
}
#[doc = "RX FIFO silent read"]
pub type RxFifoRdSilent = crate::RegValueT<RxFifoRdSilent_SPEC>;
impl RxFifoRdSilent {
#[doc = "Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes.\nNotes: \n - Don\'t access to this register while RX_FIFO_CTL.CLEAR is \'1\'. \n - Two stored data may be not valid after CMD.RX_START is set \'1\'. Therefore we recommend software discard those data."]
#[inline(always)]
pub fn data(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
RxFifoRdSilent_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
RxFifoRdSilent_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RxFifoRdSilent {
#[inline(always)]
fn default() -> RxFifoRdSilent {
<crate::RegValueT<RxFifoRdSilent_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Intr_SPEC;
impl crate::sealed::RegSpec for Intr_SPEC {
type DataType = u32;
}
#[doc = "Interrupt register"]
pub type Intr = crate::RegValueT<Intr_SPEC>;
impl Intr {
#[doc = "Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL."]
#[inline(always)]
pub fn tx_trigger(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "TX FIFO is not full."]
#[inline(always)]
pub fn tx_not_full(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "TX FIFO is empty; i.e. it has 0 entries."]
#[inline(always)]
pub fn tx_empty(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Attempt to write to a full TX FIFO."]
#[inline(always)]
pub fn tx_overflow(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and TX_EMPTY is \'1\'."]
#[inline(always)]
pub fn tx_underflow(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Triggers (sets to \'1\') when the Tx watchdog event occurs."]
#[inline(always)]
pub fn tx_wd(self) -> crate::common::RegisterFieldBool<8, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL."]
#[inline(always)]
pub fn rx_trigger(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "RX FIFO is not empty."]
#[inline(always)]
pub fn rx_not_empty(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "RX FIFO is full."]
#[inline(always)]
pub fn rx_full(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Attempt to write to a full RX FIFO."]
#[inline(always)]
pub fn rx_overflow(
self,
) -> crate::common::RegisterFieldBool<21, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<21, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Attempt to read from an empty RX FIFO."]
#[inline(always)]
pub fn rx_underflow(
self,
) -> crate::common::RegisterFieldBool<22, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<22, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Triggers (sets to \'1\') when the Rx watchdog event occurs."]
#[inline(always)]
pub fn rx_wd(self) -> crate::common::RegisterFieldBool<24, 1, 0, Intr_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24, 1, 0, Intr_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Intr {
#[inline(always)]
fn default() -> Intr {
<crate::RegValueT<Intr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrSet_SPEC;
impl crate::sealed::RegSpec for IntrSet_SPEC {
type DataType = u32;
}
#[doc = "Interrupt set register"]
pub type IntrSet = crate::RegValueT<IntrSet_SPEC>;
impl IntrSet {
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_trigger(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_not_full(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_empty(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_overflow(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_underflow(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_wd(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_trigger(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_not_empty(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_full(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_overflow(
self,
) -> crate::common::RegisterFieldBool<21, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<21, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_underflow(
self,
) -> crate::common::RegisterFieldBool<22, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<22, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Write with \'1\' to set corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_wd(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, IntrSet_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24, 1, 0, IntrSet_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for IntrSet {
#[inline(always)]
fn default() -> IntrSet {
<crate::RegValueT<IntrSet_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMask_SPEC;
impl crate::sealed::RegSpec for IntrMask_SPEC {
type DataType = u32;
}
#[doc = "Interrupt mask register"]
pub type IntrMask = crate::RegValueT<IntrMask_SPEC>;
impl IntrMask {
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_trigger(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_not_full(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_empty(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_overflow(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<5, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_underflow(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<6, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn tx_wd(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<8, 1, 0, IntrMask_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_trigger(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_not_empty(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_full(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<19,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_overflow(
self,
) -> crate::common::RegisterFieldBool<21, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<21,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_underflow(
self,
) -> crate::common::RegisterFieldBool<22, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<22,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Mask bit for corresponding bit in interrupt request register."]
#[inline(always)]
pub fn rx_wd(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, IntrMask_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<24,1,0,IntrMask_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMask {
#[inline(always)]
fn default() -> IntrMask {
<crate::RegValueT<IntrMask_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IntrMasked_SPEC;
impl crate::sealed::RegSpec for IntrMasked_SPEC {
type DataType = u32;
}
#[doc = "Interrupt masked register"]
pub type IntrMasked = crate::RegValueT<IntrMasked_SPEC>;
impl IntrMasked {
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tx_trigger(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tx_not_full(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tx_empty(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tx_overflow(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<5,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tx_underflow(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<6,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn tx_wd(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<8,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn rx_trigger(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn rx_not_empty(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<18,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn rx_full(
self,
) -> crate::common::RegisterFieldBool<19, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<19,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn rx_overflow(
self,
) -> crate::common::RegisterFieldBool<21, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<21,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn rx_underflow(
self,
) -> crate::common::RegisterFieldBool<22, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<22,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Logical and of corresponding request and mask bits."]
#[inline(always)]
pub fn rx_wd(
self,
) -> crate::common::RegisterFieldBool<24, 1, 0, IntrMasked_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<24,1,0,IntrMasked_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for IntrMasked {
#[inline(always)]
fn default() -> IntrMasked {
<crate::RegValueT<IntrMasked_SPEC> as RegisterValue<_>>::new(0)
}
}