/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"CPU subsystem (CPUSS)"]
unsafe impl ::core::marker::Send for super::Cpuss {}
unsafe impl ::core::marker::Sync for super::Cpuss {}
impl super::Cpuss {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "CM0+ control"]
#[inline(always)]
pub const fn cm0_ctl(
&self,
) -> &'static crate::common::Reg<self::Cm0Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "CM0+ status"]
#[inline(always)]
pub const fn cm0_status(
&self,
) -> &'static crate::common::Reg<self::Cm0Status_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::Cm0Status_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(8usize),
)
}
}
#[doc = "CM0+ clock control"]
#[inline(always)]
pub const fn cm0_clock_ctl(
&self,
) -> &'static crate::common::Reg<self::Cm0ClockCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0ClockCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16usize),
)
}
}
#[doc = "CM0+ interrupt control 0"]
#[inline(always)]
pub const fn cm0_int_ctl0(
&self,
) -> &'static crate::common::Reg<self::Cm0IntCtl0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0IntCtl0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "CM0+ interrupt control 1"]
#[inline(always)]
pub const fn cm0_int_ctl1(
&self,
) -> &'static crate::common::Reg<self::Cm0IntCtl1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0IntCtl1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
#[doc = "CM0+ interrupt control 2"]
#[inline(always)]
pub const fn cm0_int_ctl2(
&self,
) -> &'static crate::common::Reg<self::Cm0IntCtl2_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0IntCtl2_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(40usize),
)
}
}
#[doc = "CM0+ interrupt control 3"]
#[inline(always)]
pub const fn cm0_int_ctl3(
&self,
) -> &'static crate::common::Reg<self::Cm0IntCtl3_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0IntCtl3_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(44usize),
)
}
}
#[doc = "CM0+ interrupt control 4"]
#[inline(always)]
pub const fn cm0_int_ctl4(
&self,
) -> &'static crate::common::Reg<self::Cm0IntCtl4_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0IntCtl4_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(48usize),
)
}
}
#[doc = "CM0+ interrupt control 5"]
#[inline(always)]
pub const fn cm0_int_ctl5(
&self,
) -> &'static crate::common::Reg<self::Cm0IntCtl5_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0IntCtl5_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(52usize),
)
}
}
#[doc = "CM0+ interrupt control 6"]
#[inline(always)]
pub const fn cm0_int_ctl6(
&self,
) -> &'static crate::common::Reg<self::Cm0IntCtl6_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0IntCtl6_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(56usize),
)
}
}
#[doc = "CM0+ interrupt control 7"]
#[inline(always)]
pub const fn cm0_int_ctl7(
&self,
) -> &'static crate::common::Reg<self::Cm0IntCtl7_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0IntCtl7_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(60usize),
)
}
}
#[doc = "CM4 power control"]
#[inline(always)]
pub const fn cm4_pwr_ctl(
&self,
) -> &'static crate::common::Reg<self::Cm4PwrCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm4PwrCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(128usize),
)
}
}
#[doc = "CM4 power control"]
#[inline(always)]
pub const fn cm4_pwr_delay_ctl(
&self,
) -> &'static crate::common::Reg<self::Cm4PwrDelayCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm4PwrDelayCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(132usize),
)
}
}
#[doc = "CM4 status"]
#[inline(always)]
pub const fn cm4_status(
&self,
) -> &'static crate::common::Reg<self::Cm4Status_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::Cm4Status_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(136usize),
)
}
}
#[doc = "CM4 clock control"]
#[inline(always)]
pub const fn cm4_clock_ctl(
&self,
) -> &'static crate::common::Reg<self::Cm4ClockCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm4ClockCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(144usize),
)
}
}
#[doc = "CM4 NMI control"]
#[inline(always)]
pub const fn cm4_nmi_ctl(
&self,
) -> &'static crate::common::Reg<self::Cm4NmiCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm4NmiCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(160usize),
)
}
}
#[doc = "RAM 0 control 0"]
#[inline(always)]
pub const fn ram0_ctl0(
&self,
) -> &'static crate::common::Reg<self::Ram0Ctl0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Ram0Ctl0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(256usize),
)
}
}
#[doc = "RAM 0 power control"]
#[inline(always)]
pub const fn ram0_pwr_macro_ctl(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<self::Ram0PwrMacroCtl_SPEC, crate::common::RW>,
16,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x140usize))
}
}
#[doc = "RAM 1 control 0"]
#[inline(always)]
pub const fn ram1_ctl0(
&self,
) -> &'static crate::common::Reg<self::Ram1Ctl0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Ram1Ctl0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(384usize),
)
}
}
#[doc = "RAM1 power control"]
#[inline(always)]
pub const fn ram1_pwr_ctl(
&self,
) -> &'static crate::common::Reg<self::Ram1PwrCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Ram1PwrCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(400usize),
)
}
}
#[doc = "RAM 2 control 0"]
#[inline(always)]
pub const fn ram2_ctl0(
&self,
) -> &'static crate::common::Reg<self::Ram2Ctl0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Ram2Ctl0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(416usize),
)
}
}
#[doc = "RAM2 power control"]
#[inline(always)]
pub const fn ram2_pwr_ctl(
&self,
) -> &'static crate::common::Reg<self::Ram2PwrCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Ram2PwrCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(432usize),
)
}
}
#[doc = "Power up delay used for all SRAM power domains"]
#[inline(always)]
pub const fn ram_pwr_delay_ctl(
&self,
) -> &'static crate::common::Reg<self::RamPwrDelayCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::RamPwrDelayCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(448usize),
)
}
}
#[doc = "ROM control"]
#[inline(always)]
pub const fn rom_ctl(
&self,
) -> &'static crate::common::Reg<self::RomCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::RomCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(464usize),
)
}
}
#[doc = "UDB power control"]
#[inline(always)]
pub const fn udb_pwr_ctl(
&self,
) -> &'static crate::common::Reg<self::UdbPwrCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::UdbPwrCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(496usize),
)
}
}
#[doc = "UDB power control"]
#[inline(always)]
pub const fn udb_pwr_delay_ctl(
&self,
) -> &'static crate::common::Reg<self::UdbPwrDelayCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::UdbPwrDelayCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(500usize),
)
}
}
#[doc = "Debug port status"]
#[inline(always)]
pub const fn dp_status(
&self,
) -> &'static crate::common::Reg<self::DpStatus_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::DpStatus_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(520usize),
)
}
}
#[doc = "Buffer control"]
#[inline(always)]
pub const fn buff_ctl(
&self,
) -> &'static crate::common::Reg<self::BuffCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::BuffCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(544usize),
)
}
}
#[doc = "DDFT control"]
#[inline(always)]
pub const fn ddft_ctl(
&self,
) -> &'static crate::common::Reg<self::DdftCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::DdftCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(560usize),
)
}
}
#[doc = "SysTick timer control"]
#[inline(always)]
pub const fn systick_ctl(
&self,
) -> &'static crate::common::Reg<self::SystickCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::SystickCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(576usize),
)
}
}
#[doc = "CM0+ vector table base"]
#[inline(always)]
pub const fn cm0_vector_table_base(
&self,
) -> &'static crate::common::Reg<self::Cm0VectorTableBase_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0VectorTableBase_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(688usize),
)
}
}
#[doc = "CM4 vector table base"]
#[inline(always)]
pub const fn cm4_vector_table_base(
&self,
) -> &'static crate::common::Reg<self::Cm4VectorTableBase_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm4VectorTableBase_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(704usize),
)
}
}
#[doc = "CM0+ protection context 0 handler"]
#[inline(always)]
pub const fn cm0_pc0_handler(
&self,
) -> &'static crate::common::Reg<self::Cm0Pc0Handler_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0Pc0Handler_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(800usize),
)
}
}
#[doc = "Identity"]
#[inline(always)]
pub const fn identity(
&self,
) -> &'static crate::common::Reg<self::Identity_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::Identity_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1024usize),
)
}
}
#[doc = "Protection status"]
#[inline(always)]
pub const fn protection(
&self,
) -> &'static crate::common::Reg<self::Protection_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Protection_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1280usize),
)
}
}
#[doc = "CM0+ NMI control"]
#[inline(always)]
pub const fn cm0_nmi_ctl(
&self,
) -> &'static crate::common::Reg<self::Cm0NmiCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::Cm0NmiCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1312usize),
)
}
}
#[doc = "Access port control"]
#[inline(always)]
pub const fn ap_ctl(&self) -> &'static crate::common::Reg<self::ApCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::ApCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(1344usize),
)
}
}
#[doc = "Memory BIST status"]
#[inline(always)]
pub const fn mbist_stat(
&self,
) -> &'static crate::common::Reg<self::MbistStat_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<self::MbistStat_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(1440usize),
)
}
}
#[doc = "ROM trim control"]
#[inline(always)]
pub const fn trim_rom_ctl(
&self,
) -> &'static crate::common::Reg<self::TrimRomCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TrimRomCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(61440usize),
)
}
}
#[doc = "RAM trim control"]
#[inline(always)]
pub const fn trim_ram_ctl(
&self,
) -> &'static crate::common::Reg<self::TrimRamCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<self::TrimRamCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(61444usize),
)
}
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0Ctl_SPEC;
impl crate::sealed::RegSpec for Cm0Ctl_SPEC {
type DataType = u32;
}
#[doc = "CM0+ control"]
pub type Cm0Ctl = crate::RegValueT<Cm0Ctl_SPEC>;
impl Cm0Ctl {
#[doc = "Processor debug access control:\n\'0\': Access.\n\'1\': Stall access.\n\nThis field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses."]
#[inline(always)]
pub fn slv_stall(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Cm0Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, Cm0Ctl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Processor enable:\n\'0\': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to \'0\', HW automatically sets this field to \'1\'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot.\n\'1\': Enabled.\nNote: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to \'0\' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented).\n\nNote: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar \'built-in protection\' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details)."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Cm0Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, Cm0Ctl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Register key (to prevent accidental writes).\n- Should be written with a 0x05fa key value for the write to take effect.\n- Always reads as 0xfa05."]
#[inline(always)]
pub fn vectkeystat(
self,
) -> crate::common::RegisterField<16, 0xffff, 1, 0, u16, u16, Cm0Ctl_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xffff,1,0,u16,u16,Cm0Ctl_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Cm0Ctl {
#[inline(always)]
fn default() -> Cm0Ctl {
<crate::RegValueT<Cm0Ctl_SPEC> as RegisterValue<_>>::new(4194631682)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0Status_SPEC;
impl crate::sealed::RegSpec for Cm0Status_SPEC {
type DataType = u32;
}
#[doc = "CM0+ status"]
pub type Cm0Status = crate::RegValueT<Cm0Status_SPEC>;
impl Cm0Status {
#[doc = "Specifies if the CPU is in Active, Sleep or DeepSleep power mode:\n- Active power mode: SLEEPING is \'0\'.\n- Sleep power mode: SLEEPING is \'1\' and SLEEPDEEP is \'0\'.\n- DeepSleep power mode: SLEEPING is \'1\' and SLEEPDEEP is \'1\'."]
#[inline(always)]
pub fn sleeping(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Cm0Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, Cm0Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field."]
#[inline(always)]
pub fn sleepdeep(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Cm0Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1, 1, 0, Cm0Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Cm0Status {
#[inline(always)]
fn default() -> Cm0Status {
<crate::RegValueT<Cm0Status_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0ClockCtl_SPEC;
impl crate::sealed::RegSpec for Cm0ClockCtl_SPEC {
type DataType = u32;
}
#[doc = "CM0+ clock control"]
pub type Cm0ClockCtl = crate::RegValueT<Cm0ClockCtl_SPEC>;
impl Cm0ClockCtl {
#[doc = "Specifies the slow clock divider (from the peripheral clock \'clk_peri\' to the slow clock \'clk_slow\'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range \\[1, 256\\] (SLOW_INT_DIV is in the range \\[0, 255\\]).\n \nNote that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to \'0\' when transitioning from DeepSleep to Active power mode."]
#[inline(always)]
pub fn slow_int_div(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Cm0ClockCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,Cm0ClockCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies the peripheral clock divider (from the high frequency clock \'clk_hf\' to the peripheral clock \'clk_peri\'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range \\[1, 256\\] (PERI_INT_DIV is in the range \\[0, 255\\]).\n \nNote that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to \'0\' when transitioning from DeepSleep to Active power mode.\n\nNote that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to \'0\'."]
#[inline(always)]
pub fn peri_int_div(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, Cm0ClockCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,Cm0ClockCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cm0ClockCtl {
#[inline(always)]
fn default() -> Cm0ClockCtl {
<crate::RegValueT<Cm0ClockCtl_SPEC> as RegisterValue<_>>::new(16777216)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0IntCtl0_SPEC;
impl crate::sealed::RegSpec for Cm0IntCtl0_SPEC {
type DataType = u32;
}
#[doc = "CM0+ interrupt control 0"]
pub type Cm0IntCtl0 = crate::RegValueT<Cm0IntCtl0_SPEC>;
impl Cm0IntCtl0 {
#[doc = "System interrupt select for CPU interrupt source 0. If the field value is 240, no system interrupt is connected and the CPU interrupt source is always \'0\'/de-activated."]
#[inline(always)]
pub fn mux0_sel(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Cm0IntCtl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Cm0IntCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 1."]
#[inline(always)]
pub fn mux1_sel(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Cm0IntCtl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,Cm0IntCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 2."]
#[inline(always)]
pub fn mux2_sel(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, Cm0IntCtl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,Cm0IntCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 3."]
#[inline(always)]
pub fn mux3_sel(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, Cm0IntCtl0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,Cm0IntCtl0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cm0IntCtl0 {
#[inline(always)]
fn default() -> Cm0IntCtl0 {
<crate::RegValueT<Cm0IntCtl0_SPEC> as RegisterValue<_>>::new(4042322160)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0IntCtl1_SPEC;
impl crate::sealed::RegSpec for Cm0IntCtl1_SPEC {
type DataType = u32;
}
#[doc = "CM0+ interrupt control 1"]
pub type Cm0IntCtl1 = crate::RegValueT<Cm0IntCtl1_SPEC>;
impl Cm0IntCtl1 {
#[doc = "System interrupt select for CPU interrupt source 4."]
#[inline(always)]
pub fn mux0_sel(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Cm0IntCtl1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Cm0IntCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 5."]
#[inline(always)]
pub fn mux1_sel(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Cm0IntCtl1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,Cm0IntCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 6."]
#[inline(always)]
pub fn mux2_sel(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, Cm0IntCtl1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,Cm0IntCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 7."]
#[inline(always)]
pub fn mux3_sel(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, Cm0IntCtl1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,Cm0IntCtl1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cm0IntCtl1 {
#[inline(always)]
fn default() -> Cm0IntCtl1 {
<crate::RegValueT<Cm0IntCtl1_SPEC> as RegisterValue<_>>::new(4042322160)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0IntCtl2_SPEC;
impl crate::sealed::RegSpec for Cm0IntCtl2_SPEC {
type DataType = u32;
}
#[doc = "CM0+ interrupt control 2"]
pub type Cm0IntCtl2 = crate::RegValueT<Cm0IntCtl2_SPEC>;
impl Cm0IntCtl2 {
#[doc = "System interrupt select for CPU interrupt source 8."]
#[inline(always)]
pub fn mux0_sel(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Cm0IntCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Cm0IntCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 9."]
#[inline(always)]
pub fn mux1_sel(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Cm0IntCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,Cm0IntCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 10."]
#[inline(always)]
pub fn mux2_sel(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, Cm0IntCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,Cm0IntCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 11."]
#[inline(always)]
pub fn mux3_sel(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, Cm0IntCtl2_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,Cm0IntCtl2_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cm0IntCtl2 {
#[inline(always)]
fn default() -> Cm0IntCtl2 {
<crate::RegValueT<Cm0IntCtl2_SPEC> as RegisterValue<_>>::new(4042322160)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0IntCtl3_SPEC;
impl crate::sealed::RegSpec for Cm0IntCtl3_SPEC {
type DataType = u32;
}
#[doc = "CM0+ interrupt control 3"]
pub type Cm0IntCtl3 = crate::RegValueT<Cm0IntCtl3_SPEC>;
impl Cm0IntCtl3 {
#[doc = "System interrupt select for CPU interrupt source 12."]
#[inline(always)]
pub fn mux0_sel(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Cm0IntCtl3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Cm0IntCtl3_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 13."]
#[inline(always)]
pub fn mux1_sel(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Cm0IntCtl3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,Cm0IntCtl3_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 14."]
#[inline(always)]
pub fn mux2_sel(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, Cm0IntCtl3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,Cm0IntCtl3_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 15."]
#[inline(always)]
pub fn mux3_sel(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, Cm0IntCtl3_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,Cm0IntCtl3_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cm0IntCtl3 {
#[inline(always)]
fn default() -> Cm0IntCtl3 {
<crate::RegValueT<Cm0IntCtl3_SPEC> as RegisterValue<_>>::new(4042322160)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0IntCtl4_SPEC;
impl crate::sealed::RegSpec for Cm0IntCtl4_SPEC {
type DataType = u32;
}
#[doc = "CM0+ interrupt control 4"]
pub type Cm0IntCtl4 = crate::RegValueT<Cm0IntCtl4_SPEC>;
impl Cm0IntCtl4 {
#[doc = "System interrupt select for CPU interrupt source 16."]
#[inline(always)]
pub fn mux0_sel(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Cm0IntCtl4_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Cm0IntCtl4_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 17."]
#[inline(always)]
pub fn mux1_sel(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Cm0IntCtl4_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,Cm0IntCtl4_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 18."]
#[inline(always)]
pub fn mux2_sel(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, Cm0IntCtl4_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,Cm0IntCtl4_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 19."]
#[inline(always)]
pub fn mux3_sel(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, Cm0IntCtl4_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,Cm0IntCtl4_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cm0IntCtl4 {
#[inline(always)]
fn default() -> Cm0IntCtl4 {
<crate::RegValueT<Cm0IntCtl4_SPEC> as RegisterValue<_>>::new(4042322160)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0IntCtl5_SPEC;
impl crate::sealed::RegSpec for Cm0IntCtl5_SPEC {
type DataType = u32;
}
#[doc = "CM0+ interrupt control 5"]
pub type Cm0IntCtl5 = crate::RegValueT<Cm0IntCtl5_SPEC>;
impl Cm0IntCtl5 {
#[doc = "System interrupt select for CPU interrupt source 20."]
#[inline(always)]
pub fn mux0_sel(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Cm0IntCtl5_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Cm0IntCtl5_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 21."]
#[inline(always)]
pub fn mux1_sel(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Cm0IntCtl5_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,Cm0IntCtl5_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 22."]
#[inline(always)]
pub fn mux2_sel(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, Cm0IntCtl5_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,Cm0IntCtl5_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 23."]
#[inline(always)]
pub fn mux3_sel(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, Cm0IntCtl5_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,Cm0IntCtl5_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cm0IntCtl5 {
#[inline(always)]
fn default() -> Cm0IntCtl5 {
<crate::RegValueT<Cm0IntCtl5_SPEC> as RegisterValue<_>>::new(4042322160)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0IntCtl6_SPEC;
impl crate::sealed::RegSpec for Cm0IntCtl6_SPEC {
type DataType = u32;
}
#[doc = "CM0+ interrupt control 6"]
pub type Cm0IntCtl6 = crate::RegValueT<Cm0IntCtl6_SPEC>;
impl Cm0IntCtl6 {
#[doc = "System interrupt select for CPU interrupt source 24."]
#[inline(always)]
pub fn mux0_sel(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Cm0IntCtl6_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Cm0IntCtl6_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 25."]
#[inline(always)]
pub fn mux1_sel(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Cm0IntCtl6_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,Cm0IntCtl6_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 26."]
#[inline(always)]
pub fn mux2_sel(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, Cm0IntCtl6_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,Cm0IntCtl6_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 27."]
#[inline(always)]
pub fn mux3_sel(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, Cm0IntCtl6_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,Cm0IntCtl6_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cm0IntCtl6 {
#[inline(always)]
fn default() -> Cm0IntCtl6 {
<crate::RegValueT<Cm0IntCtl6_SPEC> as RegisterValue<_>>::new(4042322160)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0IntCtl7_SPEC;
impl crate::sealed::RegSpec for Cm0IntCtl7_SPEC {
type DataType = u32;
}
#[doc = "CM0+ interrupt control 7"]
pub type Cm0IntCtl7 = crate::RegValueT<Cm0IntCtl7_SPEC>;
impl Cm0IntCtl7 {
#[doc = "System interrupt select for CPU interrupt source 28."]
#[inline(always)]
pub fn mux0_sel(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Cm0IntCtl7_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Cm0IntCtl7_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 29."]
#[inline(always)]
pub fn mux1_sel(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Cm0IntCtl7_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,Cm0IntCtl7_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 30."]
#[inline(always)]
pub fn mux2_sel(
self,
) -> crate::common::RegisterField<16, 0xff, 1, 0, u8, u8, Cm0IntCtl7_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xff,1,0,u8,u8,Cm0IntCtl7_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "System interrupt select for CPU interrupt source 31."]
#[inline(always)]
pub fn mux3_sel(
self,
) -> crate::common::RegisterField<24, 0xff, 1, 0, u8, u8, Cm0IntCtl7_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0xff,1,0,u8,u8,Cm0IntCtl7_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cm0IntCtl7 {
#[inline(always)]
fn default() -> Cm0IntCtl7 {
<crate::RegValueT<Cm0IntCtl7_SPEC> as RegisterValue<_>>::new(4042322160)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm4PwrCtl_SPEC;
impl crate::sealed::RegSpec for Cm4PwrCtl_SPEC {
type DataType = u32;
}
#[doc = "CM4 power control"]
pub type Cm4PwrCtl = crate::RegValueT<Cm4PwrCtl_SPEC>;
impl Cm4PwrCtl {
#[doc = "Set Power mode for CM4"]
#[inline(always)]
pub fn pwr_mode(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
cm4_pwr_ctl::PwrMode,
cm4_pwr_ctl::PwrMode,
Cm4PwrCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
cm4_pwr_ctl::PwrMode,
cm4_pwr_ctl::PwrMode,
Cm4PwrCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Register key (to prevent accidental writes).\n- Should be written with a 0x05fa key value for the write to take effect.\n- Always reads as 0xfa05."]
#[inline(always)]
pub fn vectkeystat(
self,
) -> crate::common::RegisterField<16, 0xffff, 1, 0, u16, u16, Cm4PwrCtl_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xffff,1,0,u16,u16,Cm4PwrCtl_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Cm4PwrCtl {
#[inline(always)]
fn default() -> Cm4PwrCtl {
<crate::RegValueT<Cm4PwrCtl_SPEC> as RegisterValue<_>>::new(4194631681)
}
}
pub mod cm4_pwr_ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PwrMode_SPEC;
pub type PwrMode = crate::EnumBitfieldStruct<u8, PwrMode_SPEC>;
impl PwrMode {
#[doc = "Switch CM4 off\nPower off, clock off, isolate, reset and no retain."]
pub const OFF: Self = Self::new(0);
#[doc = "Reset CM4\nClock off, no isolated, no retain and reset.\n..."]
pub const RESET: Self = Self::new(1);
#[doc = "Put CM4 in Retained mode\nThis can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached.\nPower off, clock off, isolate, no reset and retain."]
pub const RETAINED: Self = Self::new(2);
#[doc = "Switch CM4 on.\nPower on, clock on, no isolate, no reset and no retain."]
pub const ENABLED: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm4PwrDelayCtl_SPEC;
impl crate::sealed::RegSpec for Cm4PwrDelayCtl_SPEC {
type DataType = u32;
}
#[doc = "CM4 power control"]
pub type Cm4PwrDelayCtl = crate::RegValueT<Cm4PwrDelayCtl_SPEC>;
impl Cm4PwrDelayCtl {
#[doc = "Number clock cycles delay needed after power domain power up"]
#[inline(always)]
pub fn up(
self,
) -> crate::common::RegisterField<
0,
0x3ff,
1,
0,
u16,
u16,
Cm4PwrDelayCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3ff,
1,
0,
u16,
u16,
Cm4PwrDelayCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Cm4PwrDelayCtl {
#[inline(always)]
fn default() -> Cm4PwrDelayCtl {
<crate::RegValueT<Cm4PwrDelayCtl_SPEC> as RegisterValue<_>>::new(300)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm4Status_SPEC;
impl crate::sealed::RegSpec for Cm4Status_SPEC {
type DataType = u32;
}
#[doc = "CM4 status"]
pub type Cm4Status = crate::RegValueT<Cm4Status_SPEC>;
impl Cm4Status {
#[doc = "Specifies if the CPU is in Active, Sleep or DeepSleep power mode:\n- Active power mode: SLEEPING is \'0\'.\n- Sleep power mode: SLEEPING is \'1\' and SLEEPDEEP is \'0\'.\n- DeepSleep power mode: SLEEPING is \'1\' and SLEEPDEEP is \'1\'."]
#[inline(always)]
pub fn sleeping(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Cm4Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, Cm4Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field."]
#[inline(always)]
pub fn sleepdeep(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Cm4Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1, 1, 0, Cm4Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. \nNote: this flag can also change as a result of a change in debug power up req"]
#[inline(always)]
pub fn pwr_done(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Cm4Status_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<4, 1, 0, Cm4Status_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for Cm4Status {
#[inline(always)]
fn default() -> Cm4Status {
<crate::RegValueT<Cm4Status_SPEC> as RegisterValue<_>>::new(19)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm4ClockCtl_SPEC;
impl crate::sealed::RegSpec for Cm4ClockCtl_SPEC {
type DataType = u32;
}
#[doc = "CM4 clock control"]
pub type Cm4ClockCtl = crate::RegValueT<Cm4ClockCtl_SPEC>;
impl Cm4ClockCtl {
#[doc = "Specifies the fast clock divider (from the high frequency clock \'clk_hf\' to the peripheral clock \'clk_fast\'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range \\[1, 256\\] (FAST_INT_DIV is in the range \\[0, 255\\]).\n \nNote that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to \'0\' when transitioning from DeepSleep to Active power mode."]
#[inline(always)]
pub fn fast_int_div(
self,
) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Cm4ClockCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0xff,1,0,u8,u8,Cm4ClockCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cm4ClockCtl {
#[inline(always)]
fn default() -> Cm4ClockCtl {
<crate::RegValueT<Cm4ClockCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm4NmiCtl_SPEC;
impl crate::sealed::RegSpec for Cm4NmiCtl_SPEC {
type DataType = u32;
}
#[doc = "CM4 NMI control"]
pub type Cm4NmiCtl = crate::RegValueT<Cm4NmiCtl_SPEC>;
impl Cm4NmiCtl {
#[doc = "System interrupt select for CPU NMI. The reset value ensure that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset."]
#[inline(always)]
pub fn mux0_sel(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Cm4NmiCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Cm4NmiCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cm4NmiCtl {
#[inline(always)]
fn default() -> Cm4NmiCtl {
<crate::RegValueT<Cm4NmiCtl_SPEC> as RegisterValue<_>>::new(240)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ram0Ctl0_SPEC;
impl crate::sealed::RegSpec for Ram0Ctl0_SPEC {
type DataType = u32;
}
#[doc = "RAM 0 control 0"]
pub type Ram0Ctl0 = crate::RegValueT<Ram0Ctl0_SPEC>;
impl Ram0Ctl0 {
#[doc = "Memory wait states for the slow clock domain (\'clk_slow\'). The number of wait states is expressed in \'clk_hf\' clock domain cycles."]
#[inline(always)]
pub fn slow_ws(
self,
) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, Ram0Ctl0_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0x3,1,0,u8,u8,Ram0Ctl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Memory wait states for the fast clock domain (\'clk_fast\'). The number of wait states is expressed in \'clk_hf\' clock domain cycles."]
#[inline(always)]
pub fn fast_ws(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ram0Ctl0_SPEC, crate::common::RW> {
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ram0Ctl0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ram0Ctl0 {
#[inline(always)]
fn default() -> Ram0Ctl0 {
<crate::RegValueT<Ram0Ctl0_SPEC> as RegisterValue<_>>::new(1)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ram0PwrMacroCtl_SPEC;
impl crate::sealed::RegSpec for Ram0PwrMacroCtl_SPEC {
type DataType = u32;
}
#[doc = "RAM 0 power control"]
pub type Ram0PwrMacroCtl = crate::RegValueT<Ram0PwrMacroCtl_SPEC>;
impl Ram0PwrMacroCtl {
#[doc = "Set Power mode for 1 SRAM0 Macro"]
#[inline(always)]
pub fn pwr_mode(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
ram0_pwr_macro_ctl::PwrMode,
ram0_pwr_macro_ctl::PwrMode,
Ram0PwrMacroCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
ram0_pwr_macro_ctl::PwrMode,
ram0_pwr_macro_ctl::PwrMode,
Ram0PwrMacroCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Register key (to prevent accidental writes).\n- Should be written with a 0x05fa key value for the write to take effect.\n- Always reads as 0xfa05."]
#[inline(always)]
pub fn vectkeystat(
self,
) -> crate::common::RegisterField<
16,
0xffff,
1,
0,
u16,
u16,
Ram0PwrMacroCtl_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
16,
0xffff,
1,
0,
u16,
u16,
Ram0PwrMacroCtl_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Ram0PwrMacroCtl {
#[inline(always)]
fn default() -> Ram0PwrMacroCtl {
<crate::RegValueT<Ram0PwrMacroCtl_SPEC> as RegisterValue<_>>::new(4194631683)
}
}
pub mod ram0_pwr_macro_ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PwrMode_SPEC;
pub type PwrMode = crate::EnumBitfieldStruct<u8, PwrMode_SPEC>;
impl PwrMode {
#[doc = "See CM4_PWR_CTL"]
pub const OFF: Self = Self::new(0);
#[doc = "undefined"]
pub const RSVD: Self = Self::new(1);
#[doc = "See CM4_PWR_CTL"]
pub const RETAINED: Self = Self::new(2);
#[doc = "See CM4_PWR_CTL"]
pub const ENABLED: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ram1Ctl0_SPEC;
impl crate::sealed::RegSpec for Ram1Ctl0_SPEC {
type DataType = u32;
}
#[doc = "RAM 1 control 0"]
pub type Ram1Ctl0 = crate::RegValueT<Ram1Ctl0_SPEC>;
impl Ram1Ctl0 {
#[doc = "Memory wait states for the slow clock domain (\'clk_slow\'). The number of wait states is expressed in \'clk_hf\' clock domain cycles."]
#[inline(always)]
pub fn slow_ws(
self,
) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, Ram1Ctl0_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0x3,1,0,u8,u8,Ram1Ctl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Memory wait states for the fast clock domain (\'clk_fast\'). The number of wait states is expressed in \'clk_hf\' clock domain cycles."]
#[inline(always)]
pub fn fast_ws(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ram1Ctl0_SPEC, crate::common::RW> {
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ram1Ctl0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ram1Ctl0 {
#[inline(always)]
fn default() -> Ram1Ctl0 {
<crate::RegValueT<Ram1Ctl0_SPEC> as RegisterValue<_>>::new(1)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ram1PwrCtl_SPEC;
impl crate::sealed::RegSpec for Ram1PwrCtl_SPEC {
type DataType = u32;
}
#[doc = "RAM1 power control"]
pub type Ram1PwrCtl = crate::RegValueT<Ram1PwrCtl_SPEC>;
impl Ram1PwrCtl {
#[doc = "Set Power mode for SRAM1"]
#[inline(always)]
pub fn pwr_mode(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
ram1_pwr_ctl::PwrMode,
ram1_pwr_ctl::PwrMode,
Ram1PwrCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
ram1_pwr_ctl::PwrMode,
ram1_pwr_ctl::PwrMode,
Ram1PwrCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Register key (to prevent accidental writes).\n- Should be written with a 0x05fa key value for the write to take effect.\n- Always reads as 0xfa05."]
#[inline(always)]
pub fn vectkeystat(
self,
) -> crate::common::RegisterField<16, 0xffff, 1, 0, u16, u16, Ram1PwrCtl_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xffff,1,0,u16,u16,Ram1PwrCtl_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Ram1PwrCtl {
#[inline(always)]
fn default() -> Ram1PwrCtl {
<crate::RegValueT<Ram1PwrCtl_SPEC> as RegisterValue<_>>::new(4194631683)
}
}
pub mod ram1_pwr_ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PwrMode_SPEC;
pub type PwrMode = crate::EnumBitfieldStruct<u8, PwrMode_SPEC>;
impl PwrMode {
#[doc = "See CM4_PWR_CTL"]
pub const OFF: Self = Self::new(0);
#[doc = "undefined"]
pub const RSVD: Self = Self::new(1);
#[doc = "See CM4_PWR_CTL"]
pub const RETAINED: Self = Self::new(2);
#[doc = "See CM4_PWR_CTL"]
pub const ENABLED: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ram2Ctl0_SPEC;
impl crate::sealed::RegSpec for Ram2Ctl0_SPEC {
type DataType = u32;
}
#[doc = "RAM 2 control 0"]
pub type Ram2Ctl0 = crate::RegValueT<Ram2Ctl0_SPEC>;
impl Ram2Ctl0 {
#[doc = "Memory wait states for the slow clock domain (\'clk_slow\'). The number of wait states is expressed in \'clk_hf\' clock domain cycles."]
#[inline(always)]
pub fn slow_ws(
self,
) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, Ram2Ctl0_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0x3,1,0,u8,u8,Ram2Ctl0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Memory wait states for the fast clock domain (\'clk_fast\'). The number of wait states is expressed in \'clk_hf\' clock domain cycles."]
#[inline(always)]
pub fn fast_ws(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ram2Ctl0_SPEC, crate::common::RW> {
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ram2Ctl0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ram2Ctl0 {
#[inline(always)]
fn default() -> Ram2Ctl0 {
<crate::RegValueT<Ram2Ctl0_SPEC> as RegisterValue<_>>::new(1)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ram2PwrCtl_SPEC;
impl crate::sealed::RegSpec for Ram2PwrCtl_SPEC {
type DataType = u32;
}
#[doc = "RAM2 power control"]
pub type Ram2PwrCtl = crate::RegValueT<Ram2PwrCtl_SPEC>;
impl Ram2PwrCtl {
#[doc = "Set Power mode for SRAM2"]
#[inline(always)]
pub fn pwr_mode(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
ram2_pwr_ctl::PwrMode,
ram2_pwr_ctl::PwrMode,
Ram2PwrCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
ram2_pwr_ctl::PwrMode,
ram2_pwr_ctl::PwrMode,
Ram2PwrCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Register key (to prevent accidental writes).\n- Should be written with a 0x05fa key value for the write to take effect.\n- Always reads as 0xfa05."]
#[inline(always)]
pub fn vectkeystat(
self,
) -> crate::common::RegisterField<16, 0xffff, 1, 0, u16, u16, Ram2PwrCtl_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xffff,1,0,u16,u16,Ram2PwrCtl_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Ram2PwrCtl {
#[inline(always)]
fn default() -> Ram2PwrCtl {
<crate::RegValueT<Ram2PwrCtl_SPEC> as RegisterValue<_>>::new(4194631683)
}
}
pub mod ram2_pwr_ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PwrMode_SPEC;
pub type PwrMode = crate::EnumBitfieldStruct<u8, PwrMode_SPEC>;
impl PwrMode {
#[doc = "See CM4_PWR_CTL"]
pub const OFF: Self = Self::new(0);
#[doc = "undefined"]
pub const RSVD: Self = Self::new(1);
#[doc = "See CM4_PWR_CTL"]
pub const RETAINED: Self = Self::new(2);
#[doc = "See CM4_PWR_CTL"]
pub const ENABLED: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RamPwrDelayCtl_SPEC;
impl crate::sealed::RegSpec for RamPwrDelayCtl_SPEC {
type DataType = u32;
}
#[doc = "Power up delay used for all SRAM power domains"]
pub type RamPwrDelayCtl = crate::RegValueT<RamPwrDelayCtl_SPEC>;
impl RamPwrDelayCtl {
#[doc = "Number clock cycles delay needed after power domain power up"]
#[inline(always)]
pub fn up(
self,
) -> crate::common::RegisterField<
0,
0x3ff,
1,
0,
u16,
u16,
RamPwrDelayCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3ff,
1,
0,
u16,
u16,
RamPwrDelayCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for RamPwrDelayCtl {
#[inline(always)]
fn default() -> RamPwrDelayCtl {
<crate::RegValueT<RamPwrDelayCtl_SPEC> as RegisterValue<_>>::new(150)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct RomCtl_SPEC;
impl crate::sealed::RegSpec for RomCtl_SPEC {
type DataType = u32;
}
#[doc = "ROM control"]
pub type RomCtl = crate::RegValueT<RomCtl_SPEC>;
impl RomCtl {
#[doc = "Memory wait states for the slow clock domain (\'clk_slow\'). The number of wait states is expressed in \'clk_hf\' clock domain cycles.\n\nTiming paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The \'clk_hf\' clock domain frequency determines this field\'s value such that the timing paths minimum duration is met. A table/formula will be provided for this field\'s values for different \'clk_hf\' frequencies."]
#[inline(always)]
pub fn slow_ws(
self,
) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, RomCtl_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0x3,1,0,u8,u8,RomCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Memory wait states for the fast clock domain (\'clk_fast\'). The number of wait states is expressed in \'clk_hf\' clock domain cycles."]
#[inline(always)]
pub fn fast_ws(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, RomCtl_SPEC, crate::common::RW> {
crate::common::RegisterField::<8,0x3,1,0,u8,u8,RomCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for RomCtl {
#[inline(always)]
fn default() -> RomCtl {
<crate::RegValueT<RomCtl_SPEC> as RegisterValue<_>>::new(1)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UdbPwrCtl_SPEC;
impl crate::sealed::RegSpec for UdbPwrCtl_SPEC {
type DataType = u32;
}
#[doc = "UDB power control"]
pub type UdbPwrCtl = crate::RegValueT<UdbPwrCtl_SPEC>;
impl UdbPwrCtl {
#[doc = "Set Power mode for UDBs"]
#[inline(always)]
pub fn pwr_mode(
self,
) -> crate::common::RegisterField<
0,
0x3,
1,
0,
udb_pwr_ctl::PwrMode,
udb_pwr_ctl::PwrMode,
UdbPwrCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3,
1,
0,
udb_pwr_ctl::PwrMode,
udb_pwr_ctl::PwrMode,
UdbPwrCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Register key (to prevent accidental writes).\n- Should be written with a 0x05fa key value for the write to take effect.\n- Always reads as 0xfa05."]
#[inline(always)]
pub fn vectkeystat(
self,
) -> crate::common::RegisterField<16, 0xffff, 1, 0, u16, u16, UdbPwrCtl_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xffff,1,0,u16,u16,UdbPwrCtl_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for UdbPwrCtl {
#[inline(always)]
fn default() -> UdbPwrCtl {
<crate::RegValueT<UdbPwrCtl_SPEC> as RegisterValue<_>>::new(4194631681)
}
}
pub mod udb_pwr_ctl {
#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
pub struct PwrMode_SPEC;
pub type PwrMode = crate::EnumBitfieldStruct<u8, PwrMode_SPEC>;
impl PwrMode {
#[doc = "See CM4_PWR_CTL"]
pub const OFF: Self = Self::new(0);
#[doc = "See CM4_PWR_CTL"]
pub const RESET: Self = Self::new(1);
#[doc = "See CM4_PWR_CTL"]
pub const RETAINED: Self = Self::new(2);
#[doc = "See CM4_PWR_CTL"]
pub const ENABLED: Self = Self::new(3);
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct UdbPwrDelayCtl_SPEC;
impl crate::sealed::RegSpec for UdbPwrDelayCtl_SPEC {
type DataType = u32;
}
#[doc = "UDB power control"]
pub type UdbPwrDelayCtl = crate::RegValueT<UdbPwrDelayCtl_SPEC>;
impl UdbPwrDelayCtl {
#[doc = "Number clock cycles delay needed after power domain power up"]
#[inline(always)]
pub fn up(
self,
) -> crate::common::RegisterField<
0,
0x3ff,
1,
0,
u16,
u16,
UdbPwrDelayCtl_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0x3ff,
1,
0,
u16,
u16,
UdbPwrDelayCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for UdbPwrDelayCtl {
#[inline(always)]
fn default() -> UdbPwrDelayCtl {
<crate::RegValueT<UdbPwrDelayCtl_SPEC> as RegisterValue<_>>::new(300)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DpStatus_SPEC;
impl crate::sealed::RegSpec for DpStatus_SPEC {
type DataType = u32;
}
#[doc = "Debug port status"]
pub type DpStatus = crate::RegValueT<DpStatus_SPEC>;
impl DpStatus {
#[doc = "Specifies if the SWJ debug port is connected; i.e. debug host interface is active:\n\'0\': Not connected/not active.\n\'1\': Connected/active."]
#[inline(always)]
pub fn swj_connected(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, DpStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, DpStatus_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is \'1\' and thus debug clocks are on:\n\'0\': Disabled.\n\'1\': Enabled."]
#[inline(always)]
pub fn swj_debug_en(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, DpStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1, 1, 0, DpStatus_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is \'0\' (SWJ mode selected) and SWJ_CONNECTED is \'1\' (SWJ is connected).\n\'0\': SWD selected.\n\'1\': JTAG selected."]
#[inline(always)]
pub fn swj_jtag_sel(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, DpStatus_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<2, 1, 0, DpStatus_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for DpStatus {
#[inline(always)]
fn default() -> DpStatus {
<crate::RegValueT<DpStatus_SPEC> as RegisterValue<_>>::new(4)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct BuffCtl_SPEC;
impl crate::sealed::RegSpec for BuffCtl_SPEC {
type DataType = u32;
}
#[doc = "Buffer control"]
pub type BuffCtl = crate::RegValueT<BuffCtl_SPEC>;
impl BuffCtl {
#[doc = "Specifies if write transfer can be buffered in the bus infrastructure bridges:\n\'0\': Write transfers are not buffered, independent of the transfer\'s bufferable attribute.\n\'1\': Write transfers can be buffered, if the transfer\'s bufferable attribute indicates that the transfer is a bufferable/posted write."]
#[inline(always)]
pub fn write_buff(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, BuffCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, BuffCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for BuffCtl {
#[inline(always)]
fn default() -> BuffCtl {
<crate::RegValueT<BuffCtl_SPEC> as RegisterValue<_>>::new(1)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DdftCtl_SPEC;
impl crate::sealed::RegSpec for DdftCtl_SPEC {
type DataType = u32;
}
#[doc = "DDFT control"]
pub type DdftCtl = crate::RegValueT<DdftCtl_SPEC>;
impl DdftCtl {
#[doc = "Select signal for CPUSS DDFT\\[0\\]\n0: clk_r of the Main flash (which is clk_hf for SONOS Flash)\n1: Flash data output bit \'0\' (r_q\\[0\\])\n2: Flash data output bit \'32\' (r_q\\[32\\])\n3: Flash data output bit \'64\' (r_q\\[64\\])\n4: Flash data output bit \'127\' (r_q\\[127\\])\n5: bist_fm_enabled\n6: bist_fail\n7: cm0_sleeping\n8: cm0_sleepdeep\n9: cm0_sleep_hold_ack_n\n10: cm4_sleeping\n11: cm4_sleepdeep\n12: cm4_sleep_hold_ack_n\n13: cm4_power\n14: cm4_act_retain_n\n15: cm4_act_isolate_n\n16: cm4_enabled\n17: cm4_reset_n\n18: cm4_pwr_done\n19: mmio_ram0_ctl1_power\\[0\\] (Power control for SRAM0 macro0)\n20: mmio_ram0_ctl1_retain_n\\[0\\] (Retention control for SRAM0 macro0)\n21: mmio_ram0_ctl1_isolate_n\\[0\\] (Isolation control for SRAM0 macro0)"]
#[inline(always)]
pub fn ddft_out0_sel(
self,
) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, DdftCtl_SPEC, crate::common::RW> {
crate::common::RegisterField::<0,0x1f,1,0,u8,u8,DdftCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Select signal for CPUSS DDFT\\[0\\]\n0: clk_r of the Main flash (which is clk_hf for SONOS Flash)\n1: Flash data output bit \'0\' (r_q\\[0\\])\n2: Flash data output bit \'32\' (r_q\\[32\\])\n3: Flash data output bit \'64\' (r_q\\[64\\])\n4: Flash data output bit \'127\' (r_q\\[127\\])\n5: bist_fm_enabled\n6: bist_fail\n7: cm0_sleeping\n8: cm0_sleepdeep\n9: cm0_sleep_hold_ack_n\n10: cm4_sleeping\n11: cm4_sleepdeep\n12: cm4_sleep_hold_ack_n\n13: cm4_power\n14: cm4_act_retain_n\n15: cm4_act_isolate_n\n16: cm4_enabled\n17: cm4_reset_n\n18: cm4_pwr_done\n19: mmio_ram0_ctl1_power\\[0\\] (Power control for SRAM0 macro0)\n20: mmio_ram0_ctl1_retain_n\\[0\\] (Retention control for SRAM0 macro0)\n21: mmio_ram0_ctl1_isolate_n\\[0\\] (Isolation control for SRAM0 macro0)"]
#[inline(always)]
pub fn ddft_out1_sel(
self,
) -> crate::common::RegisterField<8, 0x1f, 1, 0, u8, u8, DdftCtl_SPEC, crate::common::RW> {
crate::common::RegisterField::<8,0x1f,1,0,u8,u8,DdftCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for DdftCtl {
#[inline(always)]
fn default() -> DdftCtl {
<crate::RegValueT<DdftCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SystickCtl_SPEC;
impl crate::sealed::RegSpec for SystickCtl_SPEC {
type DataType = u32;
}
#[doc = "SysTick timer control"]
pub type SystickCtl = crate::RegValueT<SystickCtl_SPEC>;
impl SystickCtl {
#[doc = "Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327."]
#[inline(always)]
pub fn tenms(
self,
) -> crate::common::RegisterField<0, 0xffffff, 1, 0, u32, u32, SystickCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
0,
0xffffff,
1,
0,
u32,
u32,
SystickCtl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "Specifies an external clock source:\n\'0\': The low frequency clock \'clk_lf\' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise).\n\'1\': The internal main oscillator (IMO) clock \'clk_imo\' is selected. The MXS40 platform uses a fixed frequency IMO clock.\no \'2\': The external crystal oscillator (ECO) clock \'clk_eco\' is selected.\n\'3\': The SRSS \'clk_timer\' is selected (\'clk_timer\' is a divided/gated version of \'clk_hf\' or \'clk_imo\').\n\nNote: If NOREF is \'1\', the CLOCK_SOURCE value is NOT used.\nNote: It is SW\'s responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source."]
#[inline(always)]
pub fn clock_source(
self,
) -> crate::common::RegisterField<24, 0x3, 1, 0, u8, u8, SystickCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0x3,1,0,u8,u8,SystickCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock:\n\'0\': Precise.\n\'1\': Imprecise."]
#[inline(always)]
pub fn skew(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, SystickCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<30,1,0,SystickCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Specifies if an external clock source is provided:\n\'0\': An external clock source is provided. \n\'1\': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source."]
#[inline(always)]
pub fn noref(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, SystickCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<31,1,0,SystickCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for SystickCtl {
#[inline(always)]
fn default() -> SystickCtl {
<crate::RegValueT<SystickCtl_SPEC> as RegisterValue<_>>::new(1073742151)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0VectorTableBase_SPEC;
impl crate::sealed::RegSpec for Cm0VectorTableBase_SPEC {
type DataType = u32;
}
#[doc = "CM0+ vector table base"]
pub type Cm0VectorTableBase = crate::RegValueT<Cm0VectorTableBase_SPEC>;
impl Cm0VectorTableBase {
#[doc = "Address of CM0+ vector table.\n\nNote: the CM0+ vector table is at an address that is a 256 B multiple."]
#[inline(always)]
pub fn addr24(
self,
) -> crate::common::RegisterField<
8,
0xffffff,
1,
0,
u32,
u32,
Cm0VectorTableBase_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0xffffff,
1,
0,
u32,
u32,
Cm0VectorTableBase_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Cm0VectorTableBase {
#[inline(always)]
fn default() -> Cm0VectorTableBase {
<crate::RegValueT<Cm0VectorTableBase_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm4VectorTableBase_SPEC;
impl crate::sealed::RegSpec for Cm4VectorTableBase_SPEC {
type DataType = u32;
}
#[doc = "CM4 vector table base"]
pub type Cm4VectorTableBase = crate::RegValueT<Cm4VectorTableBase_SPEC>;
impl Cm4VectorTableBase {
#[doc = "Address of CM4 vector table.\n\nNote: the CM4 vector table is at an address that is a 1024 B multiple."]
#[inline(always)]
pub fn addr22(
self,
) -> crate::common::RegisterField<
10,
0x3fffff,
1,
0,
u32,
u32,
Cm4VectorTableBase_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
10,
0x3fffff,
1,
0,
u32,
u32,
Cm4VectorTableBase_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Cm4VectorTableBase {
#[inline(always)]
fn default() -> Cm4VectorTableBase {
<crate::RegValueT<Cm4VectorTableBase_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0Pc0Handler_SPEC;
impl crate::sealed::RegSpec for Cm0Pc0Handler_SPEC {
type DataType = u32;
}
#[doc = "CM0+ protection context 0 handler"]
pub type Cm0Pc0Handler = crate::RegValueT<Cm0Pc0Handler_SPEC>;
impl Cm0Pc0Handler {
#[doc = "Address of the protection context 0 handler. This field is used to detect entry to Cypress \'trusted\' code through an exception/interrupt."]
#[inline(always)]
pub fn addr(
self,
) -> crate::common::RegisterField<
0,
0xffffffff,
1,
0,
u32,
u32,
Cm0Pc0Handler_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
0,
0xffffffff,
1,
0,
u32,
u32,
Cm0Pc0Handler_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Cm0Pc0Handler {
#[inline(always)]
fn default() -> Cm0Pc0Handler {
<crate::RegValueT<Cm0Pc0Handler_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Identity_SPEC;
impl crate::sealed::RegSpec for Identity_SPEC {
type DataType = u32;
}
#[doc = "Identity"]
pub type Identity = crate::RegValueT<Identity_SPEC>;
impl Identity {
#[doc = "This field specifies the privileged setting (\'0\': user mode; \'1\': privileged mode) of the transfer that reads the register."]
#[inline(always)]
pub fn p(self) -> crate::common::RegisterFieldBool<0, 1, 0, Identity_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, Identity_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "This field specifies the security setting (\'0\': secure mode; \'1\': non-secure mode) of the transfer that reads the register."]
#[inline(always)]
pub fn ns(self) -> crate::common::RegisterFieldBool<1, 1, 0, Identity_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1, 1, 0, Identity_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "This field specifies the protection context of the transfer that reads the register."]
#[inline(always)]
pub fn pc(
self,
) -> crate::common::RegisterField<4, 0xf, 1, 0, u8, u8, Identity_SPEC, crate::common::R> {
crate::common::RegisterField::<4,0xf,1,0,u8,u8,Identity_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This field specifies the bus master identifier of the transfer that reads the register."]
#[inline(always)]
pub fn ms(
self,
) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, Identity_SPEC, crate::common::R> {
crate::common::RegisterField::<8,0xf,1,0,u8,u8,Identity_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for Identity {
#[inline(always)]
fn default() -> Identity {
<crate::RegValueT<Identity_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Protection_SPEC;
impl crate::sealed::RegSpec for Protection_SPEC {
type DataType = u32;
}
#[doc = "Protection status"]
pub type Protection = crate::RegValueT<Protection_SPEC>;
impl Protection {
#[doc = "Protection state:\n\'0\': UNKNOWN.\n\'1\': VIRGIN.\n\'2\': NORMAL.\n\'3\': SECURE.\n\'4\': DEAD.\n\nThe following state transitions are allowed (and enforced by HW):\n- UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD\n- NORMAL => DEAD\n- SECURE => DEAD\nAn attempt to make a NOT allowed state transition will NOT affect this register field."]
#[inline(always)]
pub fn state(
self,
) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, Protection_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0x7,1,0,u8,u8,Protection_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Protection {
#[inline(always)]
fn default() -> Protection {
<crate::RegValueT<Protection_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cm0NmiCtl_SPEC;
impl crate::sealed::RegSpec for Cm0NmiCtl_SPEC {
type DataType = u32;
}
#[doc = "CM0+ NMI control"]
pub type Cm0NmiCtl = crate::RegValueT<Cm0NmiCtl_SPEC>;
impl Cm0NmiCtl {
#[doc = "System interrupt select for CPU NMI. The reset value ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset."]
#[inline(always)]
pub fn mux0_sel(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Cm0NmiCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Cm0NmiCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Cm0NmiCtl {
#[inline(always)]
fn default() -> Cm0NmiCtl {
<crate::RegValueT<Cm0NmiCtl_SPEC> as RegisterValue<_>>::new(240)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct ApCtl_SPEC;
impl crate::sealed::RegSpec for ApCtl_SPEC {
type DataType = u32;
}
#[doc = "Access port control"]
pub type ApCtl = crate::RegValueT<ApCtl_SPEC>;
impl ApCtl {
#[doc = "Enables the CM0 AP interface:\n\'0\': Disabled.\n\'1\': Enabled."]
#[inline(always)]
pub fn cm0_enable(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, ApCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0, 1, 0, ApCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Enables the CM4 AP interface:\n\'0\': Disabled.\n\'1\': Enabled."]
#[inline(always)]
pub fn cm4_enable(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, ApCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1, 1, 0, ApCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Enables the system AP interface:\n\'0\': Disabled.\n\'1\': Enabled."]
#[inline(always)]
pub fn sys_enable(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, ApCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<2, 1, 0, ApCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Disables the CM0 AP interface:\n\'0\': Enabled.\n\'1\': Disabled.\n\nTypically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is \'0\' and CM0_ENABLE is \'1\'."]
#[inline(always)]
pub fn cm0_disable(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, ApCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<16, 1, 0, ApCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Disables the CM4 AP interface:\n\'0\': Enabled.\n\'1\': Disabled.\n\nTypically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM4_DISABLE is \'0\' and CM4_ENABLE is \'1\'."]
#[inline(always)]
pub fn cm4_disable(
self,
) -> crate::common::RegisterFieldBool<17, 1, 0, ApCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<17, 1, 0, ApCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
#[doc = "Disables the system AP interface:\n\'0\': Enabled.\n\'1\': Disabled.\n\nTypically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is \'0\' and SYS_ENABLE is \'1\'."]
#[inline(always)]
pub fn sys_disable(
self,
) -> crate::common::RegisterFieldBool<18, 1, 0, ApCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<18, 1, 0, ApCtl_SPEC, crate::common::RW>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for ApCtl {
#[inline(always)]
fn default() -> ApCtl {
<crate::RegValueT<ApCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MbistStat_SPEC;
impl crate::sealed::RegSpec for MbistStat_SPEC {
type DataType = u32;
}
#[doc = "Memory BIST status"]
pub type MbistStat = crate::RegValueT<MbistStat_SPEC>;
impl MbistStat {
#[doc = "Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0."]
#[inline(always)]
pub fn sfp_ready(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, MbistStat_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<0, 1, 0, MbistStat_SPEC, crate::common::R>::from_register(
self, 0,
)
}
#[doc = "Report status of the BIST run, only valid if SFP_READY=1"]
#[inline(always)]
pub fn sfp_fail(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, MbistStat_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<1, 1, 0, MbistStat_SPEC, crate::common::R>::from_register(
self, 0,
)
}
}
impl ::core::default::Default for MbistStat {
#[inline(always)]
fn default() -> MbistStat {
<crate::RegValueT<MbistStat_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrimRomCtl_SPEC;
impl crate::sealed::RegSpec for TrimRomCtl_SPEC {
type DataType = u32;
}
#[doc = "ROM trim control"]
pub type TrimRomCtl = crate::RegValueT<TrimRomCtl_SPEC>;
impl TrimRomCtl {
#[doc = "N/A"]
#[inline(always)]
pub fn rm(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, TrimRomCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,TrimRomCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Read-Write margin enable control. This selects between the default Read-Write margin setting, and the external pin Read-Write margin setting."]
#[inline(always)]
pub fn rme(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, TrimRomCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,TrimRomCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TrimRomCtl {
#[inline(always)]
fn default() -> TrimRomCtl {
<crate::RegValueT<TrimRomCtl_SPEC> as RegisterValue<_>>::new(2)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct TrimRamCtl_SPEC;
impl crate::sealed::RegSpec for TrimRamCtl_SPEC {
type DataType = u32;
}
#[doc = "RAM trim control"]
pub type TrimRamCtl = crate::RegValueT<TrimRamCtl_SPEC>;
impl TrimRamCtl {
#[doc = "N/A"]
#[inline(always)]
pub fn rm(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, TrimRamCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,TrimRamCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Read-Write margin enable control. This selects between the default Read-Write margin setting, and the external RM\\[3:0\\] Read-Write margin setting."]
#[inline(always)]
pub fn rme(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, TrimRamCtl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<4,1,0,TrimRamCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write Assist Pulse to control pulse width of negative voltage on SRAM bitline."]
#[inline(always)]
pub fn wpulse(
self,
) -> crate::common::RegisterField<5, 0x7, 1, 0, u8, u8, TrimRamCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<5,0x7,1,0,u8,u8,TrimRamCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Read Assist control for WL under-drive."]
#[inline(always)]
pub fn ra(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, TrimRamCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,TrimRamCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Write assist enable control (Active High).\n- WA\\[1:0\\] Write Assist pins to control negative voltage on SRAM bitline."]
#[inline(always)]
pub fn wa(
self,
) -> crate::common::RegisterField<12, 0x7, 1, 0, u8, u8, TrimRamCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<12,0x7,1,0,u8,u8,TrimRamCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for TrimRamCtl {
#[inline(always)]
fn default() -> TrimRamCtl {
<crate::RegValueT<TrimRamCtl_SPEC> as RegisterValue<_>>::new(24578)
}
}