/*
(c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// Generated from SVD 1.0, with svd2pac 0.6.0 on Tue, 27 May 2025 19:21:54 +0000
#![allow(clippy::identity_op)]
#![allow(clippy::module_inception)]
#![allow(clippy::derivable_impls)]
#[allow(unused_imports)]
use crate::common::sealed;
#[allow(unused_imports)]
use crate::common::*;
#[doc = r"Protection"]
unsafe impl ::core::marker::Send for super::Prot {}
unsafe impl ::core::marker::Sync for super::Prot {}
impl super::Prot {
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self.ptr
}
#[doc = "SMPU"]
#[inline(always)]
pub const fn smpu(self) -> crate::prot::Smpu {
unsafe { crate::prot::_Smpu::_svd2pac_from_ptr(self._svd2pac_as_ptr().add(0usize)) }
}
#[doc = "MPU"]
#[inline(always)]
pub fn mpu(self) -> &'static crate::common::ClusterRegisterArray<crate::prot::_Mpu, 16, 0x400> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x4000usize))
}
}
}
#[doc = "SMPU"]
#[non_exhaustive]
pub struct _Smpu;
#[doc = "SMPU"]
pub type Smpu = &'static _Smpu;
unsafe impl ::core::marker::Sync for _Smpu {}
impl _Smpu {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "Master 0 protection context control"]
#[inline(always)]
pub const fn ms0_ctl(
&self,
) -> &'static crate::common::Reg<smpu::Ms0Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu::Ms0Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Master 1 protection context control"]
#[inline(always)]
pub const fn ms1_ctl(
&self,
) -> &'static crate::common::Reg<smpu::Ms1Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu::Ms1Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "Master 2 protection context control"]
#[inline(always)]
pub const fn ms2_ctl(
&self,
) -> &'static crate::common::Reg<smpu::Ms2Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu::Ms2Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(8usize),
)
}
}
#[doc = "Master 3 protection context control"]
#[inline(always)]
pub const fn ms3_ctl(
&self,
) -> &'static crate::common::Reg<smpu::Ms3Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu::Ms3Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(12usize),
)
}
}
#[doc = "Master 4 protection context control"]
#[inline(always)]
pub const fn ms4_ctl(
&self,
) -> &'static crate::common::Reg<smpu::Ms4Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu::Ms4Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(16usize),
)
}
}
#[doc = "Master 5 protection context control"]
#[inline(always)]
pub const fn ms5_ctl(
&self,
) -> &'static crate::common::Reg<smpu::Ms5Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu::Ms5Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(20usize),
)
}
}
#[doc = "Master 6 protection context control"]
#[inline(always)]
pub const fn ms6_ctl(
&self,
) -> &'static crate::common::Reg<smpu::Ms6Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu::Ms6Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(24usize),
)
}
}
#[doc = "Master 7 protection context control"]
#[inline(always)]
pub const fn ms7_ctl(
&self,
) -> &'static crate::common::Reg<smpu::Ms7Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu::Ms7Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(28usize),
)
}
}
#[doc = "Master 8 protection context control"]
#[inline(always)]
pub const fn ms8_ctl(
&self,
) -> &'static crate::common::Reg<smpu::Ms8Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu::Ms8Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "Master 9 protection context control"]
#[inline(always)]
pub const fn ms9_ctl(
&self,
) -> &'static crate::common::Reg<smpu::Ms9Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu::Ms9Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
#[doc = "Master 10 protection context control"]
#[inline(always)]
pub const fn ms10_ctl(
&self,
) -> &'static crate::common::Reg<smpu::Ms10Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu::Ms10Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(40usize),
)
}
}
#[doc = "Master 11 protection context control"]
#[inline(always)]
pub const fn ms11_ctl(
&self,
) -> &'static crate::common::Reg<smpu::Ms11Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu::Ms11Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(44usize),
)
}
}
#[doc = "Master 12 protection context control"]
#[inline(always)]
pub const fn ms12_ctl(
&self,
) -> &'static crate::common::Reg<smpu::Ms12Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu::Ms12Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(48usize),
)
}
}
#[doc = "Master 13 protection context control"]
#[inline(always)]
pub const fn ms13_ctl(
&self,
) -> &'static crate::common::Reg<smpu::Ms13Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu::Ms13Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(52usize),
)
}
}
#[doc = "Master 14 protection context control"]
#[inline(always)]
pub const fn ms14_ctl(
&self,
) -> &'static crate::common::Reg<smpu::Ms14Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu::Ms14Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(56usize),
)
}
}
#[doc = "Master 15 protection context control"]
#[inline(always)]
pub const fn ms15_ctl(
&self,
) -> &'static crate::common::Reg<smpu::Ms15Ctl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu::Ms15Ctl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(60usize),
)
}
}
#[doc = "SMPU structure"]
#[inline(always)]
pub fn smpu_struct(
self,
) -> &'static crate::common::ClusterRegisterArray<crate::prot::smpu::_SmpuStruct, 16, 0x40>
{
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x2000usize))
}
}
}
pub mod smpu {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ms0Ctl_SPEC;
impl crate::sealed::RegSpec for Ms0Ctl_SPEC {
type DataType = u32;
}
#[doc = "Master 0 protection context control"]
pub type Ms0Ctl = crate::RegValueT<Ms0Ctl_SPEC>;
impl Ms0Ctl {
#[doc = "Privileged setting (\'0\': user mode; \'1\': privileged mode).\n\nNotes:\nThis field is ONLY used for masters that do NOT provide their own user/privileged access control attribute.\nThe default/reset field value provides privileged mode access capabilities."]
#[inline(always)]
pub fn p(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ms0Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Ms0Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Security setting (\'0\': secure mode; \'1\': non-secure mode).\n\nNotes:\nThis field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute.\nNote that the default/reset field value provides non-secure mode access capabilities to all masters."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ms0Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,Ms0Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Device wide bus arbitration priority setting (\'0\': highest priority, \'3\': lowest priority).\n\nNotes: \nThe AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth).\nThe AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency).\nMasters with the same priority setting form a \'priority group\'. Within a \'priority group\', round robin arbitration is performed."]
#[inline(always)]
pub fn prio(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ms0Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ms0Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Protection context mask for protection context \'0\'. This field is a constant \'0\':\n- PC_MASK_0 is \'0\': MPU MS_CTL.PC\\[3:0\\] can NOT be set to \'0\' and PC\\[3:0\\] is not changed. If the protection context of the write transfer is \'0\', protection is not applied and PC\\[3:0\\] can be changed."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ms0Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,Ms0Ctl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Protection context mask for protection contexts \'15\' down to \'1\'. Bit PC_MASK_15_TO_1\\[i\\] indicates if the MPU MS_CTL.PC\\[3:0\\] protection context field can be set to the value \'i+1\':\n- PC_MASK_15_TO_1\\[i\\] is \'0\': MPU MS_CTL.PC\\[3:0\\] can NOT be set to \'i+1\'; and PC\\[3:0\\] is not changed. If the protection context of the write transfer is \'0\', protection is not applied and PC\\[3:0\\] can be changed.\n- PC_MASK_15_TO_1\\[i\\] is \'1\': MPU MS_CTL.PC\\[3:0\\] can be set to \'i+1\'.\n\nNote: When CPUSS_CM0_PC_CTL.VALID\\[i\\] is \'1\' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1\\[i-1\\] always write \'0\', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC\\[3:0\\] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC\\[3:0\\])."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<17, 0x7fff, 1, 0, u16, u16, Ms0Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<17,0x7fff,1,0,u16,u16,Ms0Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ms0Ctl {
#[inline(always)]
fn default() -> Ms0Ctl {
<crate::RegValueT<Ms0Ctl_SPEC> as RegisterValue<_>>::new(771)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ms1Ctl_SPEC;
impl crate::sealed::RegSpec for Ms1Ctl_SPEC {
type DataType = u32;
}
#[doc = "Master 1 protection context control"]
pub type Ms1Ctl = crate::RegValueT<Ms1Ctl_SPEC>;
impl Ms1Ctl {
#[doc = "See MS0_CTL.P."]
#[inline(always)]
pub fn p(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ms1Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Ms1Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.NS."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ms1Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,Ms1Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PRIO"]
#[inline(always)]
pub fn prio(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ms1Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ms1Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_0."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ms1Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,Ms1Ctl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_15_TO_1."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<17, 0x7fff, 1, 0, u16, u16, Ms1Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<17,0x7fff,1,0,u16,u16,Ms1Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ms1Ctl {
#[inline(always)]
fn default() -> Ms1Ctl {
<crate::RegValueT<Ms1Ctl_SPEC> as RegisterValue<_>>::new(771)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ms2Ctl_SPEC;
impl crate::sealed::RegSpec for Ms2Ctl_SPEC {
type DataType = u32;
}
#[doc = "Master 2 protection context control"]
pub type Ms2Ctl = crate::RegValueT<Ms2Ctl_SPEC>;
impl Ms2Ctl {
#[doc = "See MS0_CTL.P."]
#[inline(always)]
pub fn p(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ms2Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Ms2Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.NS."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ms2Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,Ms2Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PRIO"]
#[inline(always)]
pub fn prio(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ms2Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ms2Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_0."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ms2Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,Ms2Ctl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_15_TO_1."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<17, 0x7fff, 1, 0, u16, u16, Ms2Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<17,0x7fff,1,0,u16,u16,Ms2Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ms2Ctl {
#[inline(always)]
fn default() -> Ms2Ctl {
<crate::RegValueT<Ms2Ctl_SPEC> as RegisterValue<_>>::new(771)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ms3Ctl_SPEC;
impl crate::sealed::RegSpec for Ms3Ctl_SPEC {
type DataType = u32;
}
#[doc = "Master 3 protection context control"]
pub type Ms3Ctl = crate::RegValueT<Ms3Ctl_SPEC>;
impl Ms3Ctl {
#[doc = "See MS0_CTL.P."]
#[inline(always)]
pub fn p(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ms3Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Ms3Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.NS."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ms3Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,Ms3Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PRIO"]
#[inline(always)]
pub fn prio(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ms3Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ms3Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_0."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ms3Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,Ms3Ctl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_15_TO_1."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<17, 0x7fff, 1, 0, u16, u16, Ms3Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<17,0x7fff,1,0,u16,u16,Ms3Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ms3Ctl {
#[inline(always)]
fn default() -> Ms3Ctl {
<crate::RegValueT<Ms3Ctl_SPEC> as RegisterValue<_>>::new(771)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ms4Ctl_SPEC;
impl crate::sealed::RegSpec for Ms4Ctl_SPEC {
type DataType = u32;
}
#[doc = "Master 4 protection context control"]
pub type Ms4Ctl = crate::RegValueT<Ms4Ctl_SPEC>;
impl Ms4Ctl {
#[doc = "See MS0_CTL.P."]
#[inline(always)]
pub fn p(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ms4Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Ms4Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.NS."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ms4Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,Ms4Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PRIO"]
#[inline(always)]
pub fn prio(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ms4Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ms4Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_0."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ms4Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,Ms4Ctl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_15_TO_1."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<17, 0x7fff, 1, 0, u16, u16, Ms4Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<17,0x7fff,1,0,u16,u16,Ms4Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ms4Ctl {
#[inline(always)]
fn default() -> Ms4Ctl {
<crate::RegValueT<Ms4Ctl_SPEC> as RegisterValue<_>>::new(771)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ms5Ctl_SPEC;
impl crate::sealed::RegSpec for Ms5Ctl_SPEC {
type DataType = u32;
}
#[doc = "Master 5 protection context control"]
pub type Ms5Ctl = crate::RegValueT<Ms5Ctl_SPEC>;
impl Ms5Ctl {
#[doc = "See MS0_CTL.P."]
#[inline(always)]
pub fn p(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ms5Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Ms5Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.NS."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ms5Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,Ms5Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PRIO"]
#[inline(always)]
pub fn prio(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ms5Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ms5Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_0."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ms5Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,Ms5Ctl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_15_TO_1."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<17, 0x7fff, 1, 0, u16, u16, Ms5Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<17,0x7fff,1,0,u16,u16,Ms5Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ms5Ctl {
#[inline(always)]
fn default() -> Ms5Ctl {
<crate::RegValueT<Ms5Ctl_SPEC> as RegisterValue<_>>::new(771)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ms6Ctl_SPEC;
impl crate::sealed::RegSpec for Ms6Ctl_SPEC {
type DataType = u32;
}
#[doc = "Master 6 protection context control"]
pub type Ms6Ctl = crate::RegValueT<Ms6Ctl_SPEC>;
impl Ms6Ctl {
#[doc = "See MS0_CTL.P."]
#[inline(always)]
pub fn p(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ms6Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Ms6Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.NS."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ms6Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,Ms6Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PRIO"]
#[inline(always)]
pub fn prio(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ms6Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ms6Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_0."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ms6Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,Ms6Ctl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_15_TO_1."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<17, 0x7fff, 1, 0, u16, u16, Ms6Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<17,0x7fff,1,0,u16,u16,Ms6Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ms6Ctl {
#[inline(always)]
fn default() -> Ms6Ctl {
<crate::RegValueT<Ms6Ctl_SPEC> as RegisterValue<_>>::new(771)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ms7Ctl_SPEC;
impl crate::sealed::RegSpec for Ms7Ctl_SPEC {
type DataType = u32;
}
#[doc = "Master 7 protection context control"]
pub type Ms7Ctl = crate::RegValueT<Ms7Ctl_SPEC>;
impl Ms7Ctl {
#[doc = "See MS0_CTL.P."]
#[inline(always)]
pub fn p(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ms7Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Ms7Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.NS."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ms7Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,Ms7Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PRIO"]
#[inline(always)]
pub fn prio(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ms7Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ms7Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_0."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ms7Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,Ms7Ctl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_15_TO_1."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<17, 0x7fff, 1, 0, u16, u16, Ms7Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<17,0x7fff,1,0,u16,u16,Ms7Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ms7Ctl {
#[inline(always)]
fn default() -> Ms7Ctl {
<crate::RegValueT<Ms7Ctl_SPEC> as RegisterValue<_>>::new(771)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ms8Ctl_SPEC;
impl crate::sealed::RegSpec for Ms8Ctl_SPEC {
type DataType = u32;
}
#[doc = "Master 8 protection context control"]
pub type Ms8Ctl = crate::RegValueT<Ms8Ctl_SPEC>;
impl Ms8Ctl {
#[doc = "See MS0_CTL.P."]
#[inline(always)]
pub fn p(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ms8Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Ms8Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.NS."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ms8Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,Ms8Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PRIO"]
#[inline(always)]
pub fn prio(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ms8Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ms8Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_0."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ms8Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,Ms8Ctl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_15_TO_1."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<17, 0x7fff, 1, 0, u16, u16, Ms8Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<17,0x7fff,1,0,u16,u16,Ms8Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ms8Ctl {
#[inline(always)]
fn default() -> Ms8Ctl {
<crate::RegValueT<Ms8Ctl_SPEC> as RegisterValue<_>>::new(771)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ms9Ctl_SPEC;
impl crate::sealed::RegSpec for Ms9Ctl_SPEC {
type DataType = u32;
}
#[doc = "Master 9 protection context control"]
pub type Ms9Ctl = crate::RegValueT<Ms9Ctl_SPEC>;
impl Ms9Ctl {
#[doc = "See MS0_CTL.P."]
#[inline(always)]
pub fn p(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ms9Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Ms9Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.NS."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ms9Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,Ms9Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PRIO"]
#[inline(always)]
pub fn prio(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ms9Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ms9Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_0."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ms9Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,Ms9Ctl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_15_TO_1."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<17, 0x7fff, 1, 0, u16, u16, Ms9Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<17,0x7fff,1,0,u16,u16,Ms9Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Ms9Ctl {
#[inline(always)]
fn default() -> Ms9Ctl {
<crate::RegValueT<Ms9Ctl_SPEC> as RegisterValue<_>>::new(771)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ms10Ctl_SPEC;
impl crate::sealed::RegSpec for Ms10Ctl_SPEC {
type DataType = u32;
}
#[doc = "Master 10 protection context control"]
pub type Ms10Ctl = crate::RegValueT<Ms10Ctl_SPEC>;
impl Ms10Ctl {
#[doc = "See MS0_CTL.P."]
#[inline(always)]
pub fn p(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ms10Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Ms10Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.NS."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ms10Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,Ms10Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PRIO"]
#[inline(always)]
pub fn prio(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ms10Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ms10Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_0."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ms10Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,Ms10Ctl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_15_TO_1."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<17, 0x7fff, 1, 0, u16, u16, Ms10Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
17,
0x7fff,
1,
0,
u16,
u16,
Ms10Ctl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Ms10Ctl {
#[inline(always)]
fn default() -> Ms10Ctl {
<crate::RegValueT<Ms10Ctl_SPEC> as RegisterValue<_>>::new(771)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ms11Ctl_SPEC;
impl crate::sealed::RegSpec for Ms11Ctl_SPEC {
type DataType = u32;
}
#[doc = "Master 11 protection context control"]
pub type Ms11Ctl = crate::RegValueT<Ms11Ctl_SPEC>;
impl Ms11Ctl {
#[doc = "See MS0_CTL.P."]
#[inline(always)]
pub fn p(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ms11Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Ms11Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.NS."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ms11Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,Ms11Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PRIO"]
#[inline(always)]
pub fn prio(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ms11Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ms11Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_0."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ms11Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,Ms11Ctl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_15_TO_1."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<17, 0x7fff, 1, 0, u16, u16, Ms11Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
17,
0x7fff,
1,
0,
u16,
u16,
Ms11Ctl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Ms11Ctl {
#[inline(always)]
fn default() -> Ms11Ctl {
<crate::RegValueT<Ms11Ctl_SPEC> as RegisterValue<_>>::new(771)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ms12Ctl_SPEC;
impl crate::sealed::RegSpec for Ms12Ctl_SPEC {
type DataType = u32;
}
#[doc = "Master 12 protection context control"]
pub type Ms12Ctl = crate::RegValueT<Ms12Ctl_SPEC>;
impl Ms12Ctl {
#[doc = "See MS0_CTL.P."]
#[inline(always)]
pub fn p(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ms12Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Ms12Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.NS."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ms12Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,Ms12Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PRIO"]
#[inline(always)]
pub fn prio(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ms12Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ms12Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_0."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ms12Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,Ms12Ctl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_15_TO_1."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<17, 0x7fff, 1, 0, u16, u16, Ms12Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
17,
0x7fff,
1,
0,
u16,
u16,
Ms12Ctl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Ms12Ctl {
#[inline(always)]
fn default() -> Ms12Ctl {
<crate::RegValueT<Ms12Ctl_SPEC> as RegisterValue<_>>::new(771)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ms13Ctl_SPEC;
impl crate::sealed::RegSpec for Ms13Ctl_SPEC {
type DataType = u32;
}
#[doc = "Master 13 protection context control"]
pub type Ms13Ctl = crate::RegValueT<Ms13Ctl_SPEC>;
impl Ms13Ctl {
#[doc = "See MS0_CTL.P."]
#[inline(always)]
pub fn p(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ms13Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Ms13Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.NS."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ms13Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,Ms13Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PRIO"]
#[inline(always)]
pub fn prio(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ms13Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ms13Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_0."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ms13Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,Ms13Ctl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_15_TO_1."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<17, 0x7fff, 1, 0, u16, u16, Ms13Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
17,
0x7fff,
1,
0,
u16,
u16,
Ms13Ctl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Ms13Ctl {
#[inline(always)]
fn default() -> Ms13Ctl {
<crate::RegValueT<Ms13Ctl_SPEC> as RegisterValue<_>>::new(771)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ms14Ctl_SPEC;
impl crate::sealed::RegSpec for Ms14Ctl_SPEC {
type DataType = u32;
}
#[doc = "Master 14 protection context control"]
pub type Ms14Ctl = crate::RegValueT<Ms14Ctl_SPEC>;
impl Ms14Ctl {
#[doc = "See MS0_CTL.P."]
#[inline(always)]
pub fn p(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ms14Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Ms14Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.NS."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ms14Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,Ms14Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PRIO"]
#[inline(always)]
pub fn prio(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ms14Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ms14Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_0."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ms14Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,Ms14Ctl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_15_TO_1."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<17, 0x7fff, 1, 0, u16, u16, Ms14Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
17,
0x7fff,
1,
0,
u16,
u16,
Ms14Ctl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Ms14Ctl {
#[inline(always)]
fn default() -> Ms14Ctl {
<crate::RegValueT<Ms14Ctl_SPEC> as RegisterValue<_>>::new(771)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ms15Ctl_SPEC;
impl crate::sealed::RegSpec for Ms15Ctl_SPEC {
type DataType = u32;
}
#[doc = "Master 15 protection context control"]
pub type Ms15Ctl = crate::RegValueT<Ms15Ctl_SPEC>;
impl Ms15Ctl {
#[doc = "See MS0_CTL.P."]
#[inline(always)]
pub fn p(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Ms15Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<0,1,0,Ms15Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.NS."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Ms15Ctl_SPEC, crate::common::RW> {
crate::common::RegisterFieldBool::<1,1,0,Ms15Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PRIO"]
#[inline(always)]
pub fn prio(
self,
) -> crate::common::RegisterField<8, 0x3, 1, 0, u8, u8, Ms15Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<8,0x3,1,0,u8,u8,Ms15Ctl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_0."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<16, 1, 0, Ms15Ctl_SPEC, crate::common::R> {
crate::common::RegisterFieldBool::<16,1,0,Ms15Ctl_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "See MS0_CTL.PC_MASK_15_TO_1."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<17, 0x7fff, 1, 0, u16, u16, Ms15Ctl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
17,
0x7fff,
1,
0,
u16,
u16,
Ms15Ctl_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Ms15Ctl {
#[inline(always)]
fn default() -> Ms15Ctl {
<crate::RegValueT<Ms15Ctl_SPEC> as RegisterValue<_>>::new(771)
}
}
#[doc = "SMPU structure"]
#[non_exhaustive]
pub struct _SmpuStruct;
#[doc = "SMPU structure"]
pub type SmpuStruct = &'static _SmpuStruct;
unsafe impl ::core::marker::Sync for _SmpuStruct {}
impl _SmpuStruct {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "SMPU region address 0 (slave structure)"]
#[inline(always)]
pub const fn addr0(
&self,
) -> &'static crate::common::Reg<smpu_struct::Addr0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu_struct::Addr0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "SMPU region attributes 0 (slave structure)"]
#[inline(always)]
pub const fn att0(
&self,
) -> &'static crate::common::Reg<smpu_struct::Att0_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu_struct::Att0_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
#[doc = "SMPU region address 1 (master structure)"]
#[inline(always)]
pub const fn addr1(
&self,
) -> &'static crate::common::Reg<smpu_struct::Addr1_SPEC, crate::common::R> {
unsafe {
crate::common::Reg::<smpu_struct::Addr1_SPEC, crate::common::R>::from_ptr(
self._svd2pac_as_ptr().add(32usize),
)
}
}
#[doc = "SMPU region attributes 1 (master structure)"]
#[inline(always)]
pub const fn att1(
&self,
) -> &'static crate::common::Reg<smpu_struct::Att1_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<smpu_struct::Att1_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(36usize),
)
}
}
}
pub mod smpu_struct {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Addr0_SPEC;
impl crate::sealed::RegSpec for Addr0_SPEC {
type DataType = u32;
}
#[doc = "SMPU region address 0 (slave structure)"]
pub type Addr0 = crate::RegValueT<Addr0_SPEC>;
impl Addr0 {
#[doc = "This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:\nBit 0: subregion 0 disable.\nBit 1: subregion 1 disable.\nBit 2: subregion 2 disable.\nBit 3: subregion 3 disable.\nBit 4: subregion 4 disable.\nBit 5: subregion 5 disable.\nBit 6: subregion 6 disable.\nBit 7: subregion 7 disable.\nE.g., a 64 KByte address region (ATT0.REGION_SIZE is \'15\') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B."]
#[inline(always)]
pub fn subregion_disable(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Addr0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Addr0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is \'15\') is 64 KByte aligned, and ADDR24\\[7:0\\] are ignored."]
#[inline(always)]
pub fn addr24(
self,
) -> crate::common::RegisterField<
8,
0xffffff,
1,
0,
u32,
u32,
Addr0_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0xffffff,
1,
0,
u32,
u32,
Addr0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Addr0 {
#[inline(always)]
fn default() -> Addr0 {
<crate::RegValueT<Addr0_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Att0_SPEC;
impl crate::sealed::RegSpec for Att0_SPEC {
type DataType = u32;
}
#[doc = "SMPU region attributes 0 (slave structure)"]
pub type Att0 = crate::RegValueT<Att0_SPEC>;
impl Att0 {
#[doc = "User read enable:\n\'0\': Disabled (user, read accesses are NOT allowed).\n\'1\': Enabled (user, read accesses are allowed)."]
#[inline(always)]
pub fn ur(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Att0_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "User write enable:\n\'0\': Disabled (user, write accesses are NOT allowed).\n\'1\': Enabled (user, write accesses are allowed)."]
#[inline(always)]
pub fn uw(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Att0_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "User execute enable:\n\'0\': Disabled (user, execute accesses are NOT allowed).\n\'1\': Enabled (user, execute accesses are allowed)."]
#[inline(always)]
pub fn ux(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, Att0_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Privileged read enable:\n\'0\': Disabled (privileged, read accesses are NOT allowed).\n\'1\': Enabled (privileged, read accesses are allowed)."]
#[inline(always)]
pub fn pr(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Att0_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Privileged write enable:\n\'0\': Disabled (privileged, write accesses are NOT allowed).\n\'1\': Enabled (privileged, write accesses are allowed)."]
#[inline(always)]
pub fn pw(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Att0_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Privileged execute enable:\n\'0\': Disabled (privileged, execute accesses are NOT allowed).\n\'1\': Enabled (privileged, execute accesses are allowed)."]
#[inline(always)]
pub fn px(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Att0_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Non-secure:\n\'0\': Secure (secure accesses allowed, non-secure access NOT allowed).\n\'1\': Non-secure (both secure and non-secure accesses allowed)."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, Att0_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field specifies protection context identifier based access control for protection context \'0\'."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Att0_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<8,1,0,Att0_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This field specifies protection context identifier based access control.\nBit i: protection context i+1 enable. If \'0\', protection context i+1 access is disabled; i.e. not allowed. If \'1\', protection context i+1 access is enabled; i.e. allowed."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<9, 0x7fff, 1, 0, u16, u16, Att0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
9,
0x7fff,
1,
0,
u16,
u16,
Att0_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This field specifies the region size:\n\'0\'-\'6\': Undefined.\n\'7\': 256 B region\n\'8\': 512 B region\n\'9\': 1 KB region\n\'10\': 2 KB region\n\'11\': 4 KB region\n\'12\': 8 KB region\n\'13\': 16 KB region\n\'14\': 32 KB region\n\'15\': 64 KB region\n\'16\': 128 KB region\n\'17\': 256 KB region\n\'18\': 512 KB region\n\'19\': 1 MB region\n\'20\': 2 MB region\n\'21\': 4 MB region\n\'22\': 8 MB region\n\'23\': 16 MB region\n\'24\': 32 MB region\n\'25\': 64 MB region\n\'26\': 128 MB region\n\'27\': 256 MB region\n\'28\': 512 MB region\n\'39\': 1 GB region\n\'30\': 2 GB region\n\'31\': 4 GB region"]
#[inline(always)]
pub fn region_size(
self,
) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, Att0_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0x1f,1,0,u8,u8,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field specifies if the PC field participates in the \'matching\' process or the \'access evaluation\' process:\n\'0\': PC field participates in \'access evaluation\'.\n\'1\': PC field participates in \'matching\'.\n\n\'Matching\' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the \'matching\' regions.\n\'Access evaluation\' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes.\n\nNote that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to \'1\'."]
#[inline(always)]
pub fn pc_match(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, Att0_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<30,1,0,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Region enable:\n\'0\': Disabled. A disabled region will never result in a match on the bus transfer address.\n\'1\': Enabled.\n\nNote: a disabled address region performs logic gating to reduce dynamic power consumption."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Att0_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<31,1,0,Att0_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Att0 {
#[inline(always)]
fn default() -> Att0 {
<crate::RegValueT<Att0_SPEC> as RegisterValue<_>>::new(256)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Addr1_SPEC;
impl crate::sealed::RegSpec for Addr1_SPEC {
type DataType = u32;
}
#[doc = "SMPU region address 1 (master structure)"]
pub type Addr1 = crate::RegValueT<Addr1_SPEC>;
impl Addr1 {
#[doc = "This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:\nBit 0: subregion 0 disable.\nBit 1: subregion 1 disable.\nBit 2: subregion 2 disable.\nBit 3: subregion 3 disable.\nBit 4: subregion 4 disable.\nBit 5: subregion 5 disable.\nBit 6: subregion 6 disable.\nBit 7: subregion 7 disable.\n\nTwo out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. \n\nNote: this field is read-only."]
#[inline(always)]
pub fn subregion_disable(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Addr1_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Addr1_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This field specifies the most significant bits of the 32-bit address of an address region.\n\n\'ADDR_DEF1\': base address of structure.\n\nNote: this field is read-only."]
#[inline(always)]
pub fn addr24(
self,
) -> crate::common::RegisterField<
8,
0xffffff,
1,
0,
u32,
u32,
Addr1_SPEC,
crate::common::R,
> {
crate::common::RegisterField::<
8,
0xffffff,
1,
0,
u32,
u32,
Addr1_SPEC,
crate::common::R,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Addr1 {
#[inline(always)]
fn default() -> Addr1 {
<crate::RegValueT<Addr1_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Att1_SPEC;
impl crate::sealed::RegSpec for Att1_SPEC {
type DataType = u32;
}
#[doc = "SMPU region attributes 1 (master structure)"]
pub type Att1 = crate::RegValueT<Att1_SPEC>;
impl Att1 {
#[doc = "User read enable:\n\'0\': Disabled (user, read accesses are NOT allowed).\n\'1\': Enabled (user, read accesses are allowed).\n\nNote that this register is constant \'1\'; i.e. user read accesses are ALWAYS allowed."]
#[inline(always)]
pub fn ur(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Att1_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<0,1,0,Att1_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "User write enable:\n\'0\': Disabled (user, write accesses are NOT allowed).\n\'1\': Enabled (user, write accesses are allowed)."]
#[inline(always)]
pub fn uw(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Att1_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,Att1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "User execute enable:\n\'0\': Disabled (user, execute accesses are NOT allowed).\n\'1\': Enabled (user, execute accesses are allowed).\n\nNote that this register is constant \'0\'; i.e. user execute accesses are NEVER allowed."]
#[inline(always)]
pub fn ux(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, Att1_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<2,1,0,Att1_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Privileged read enable:\n\'0\': Disabled (privileged, read accesses are NOT allowed).\n\'1\': Enabled (privileged, read accesses are allowed).\n\nNote that this register is constant \'1\'; i.e. privileged read accesses are ALWAYS allowed."]
#[inline(always)]
pub fn pr(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Att1_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<3,1,0,Att1_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Privileged write enable:\n\'0\': Disabled (privileged, write accesses are NOT allowed).\n\'1\': Enabled (privileged, write accesses are allowed)."]
#[inline(always)]
pub fn pw(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Att1_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,Att1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Privileged execute enable:\n\'0\': Disabled (privileged, execute accesses are NOT allowed).\n\'1\': Enabled (privileged, execute accesses are allowed).\n\nNote that this register is constant \'0\'; i.e. privileged execute accesses are NEVER allowed."]
#[inline(always)]
pub fn px(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Att1_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<5,1,0,Att1_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Non-secure:\n\'0\': Secure (secure accesses allowed, non-secure access NOT allowed).\n\'1\': Non-secure (both secure and non-secure accesses allowed)."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, Att1_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,Att1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field specifies protection context identifier based access control for protection context \'0\'."]
#[inline(always)]
pub fn pc_mask_0(
self,
) -> crate::common::RegisterFieldBool<8, 1, 0, Att1_SPEC, crate::common::R>
{
crate::common::RegisterFieldBool::<8,1,0,Att1_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This field specifies protection context identifier based access control.\nBit i: protection context i+1 enable. If \'0\', protection context i+1 access is disabled; i.e. not allowed. If \'1\', protection context i+1 access is enabled; i.e. allowed."]
#[inline(always)]
pub fn pc_mask_15_to_1(
self,
) -> crate::common::RegisterField<9, 0x7fff, 1, 0, u16, u16, Att1_SPEC, crate::common::RW>
{
crate::common::RegisterField::<
9,
0x7fff,
1,
0,
u16,
u16,
Att1_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
#[doc = "This field specifies the region size:\n\'7\': 256 B region (8 32 B subregions)\n\nNote: this field is read-only."]
#[inline(always)]
pub fn region_size(
self,
) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, Att1_SPEC, crate::common::R>
{
crate::common::RegisterField::<24,0x1f,1,0,u8,u8,Att1_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "This field specifies if the PC field participates in the \'matching\' process or the \'access evaluation\' process:\n\'0\': PC field participates in \'access evaluation\'.\n\'1\': PC field participates in \'matching\'.\n\n\'Matching\' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the \'matching\' regions.\n\'Access evaluation\' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes.\n\nNote that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to \'1\'."]
#[inline(always)]
pub fn pc_match(
self,
) -> crate::common::RegisterFieldBool<30, 1, 0, Att1_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<30,1,0,Att1_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Region enable:\n\'0\': Disabled. A disabled region will never result in a match on the bus transfer address.\n\'1\': Enabled."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Att1_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<31,1,0,Att1_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Att1 {
#[inline(always)]
fn default() -> Att1 {
<crate::RegValueT<Att1_SPEC> as RegisterValue<_>>::new(117440777)
}
}
}
}
#[doc = "MPU"]
#[non_exhaustive]
pub struct _Mpu;
#[doc = "MPU"]
pub type Mpu = &'static _Mpu;
unsafe impl ::core::marker::Sync for _Mpu {}
impl _Mpu {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "Master control"]
#[inline(always)]
pub const fn ms_ctl(&self) -> &'static crate::common::Reg<mpu::MsCtl_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<mpu::MsCtl_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "Master control read mirror"]
#[inline(always)]
pub const fn ms_ctl_read_mir(
&self,
) -> &'static crate::common::ClusterRegisterArray<
crate::common::Reg<mpu::MsCtlReadMir_SPEC, crate::common::R>,
127,
0x4,
> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x4usize))
}
}
#[doc = "MPU structure"]
#[inline(always)]
pub fn mpu_struct(
self,
) -> &'static crate::common::ClusterRegisterArray<crate::prot::mpu::_MpuStruct, 8, 0x20> {
unsafe {
crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x200usize))
}
}
}
pub mod mpu {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MsCtl_SPEC;
impl crate::sealed::RegSpec for MsCtl_SPEC {
type DataType = u32;
}
#[doc = "Master control"]
pub type MsCtl = crate::RegValueT<MsCtl_SPEC>;
impl MsCtl {
#[doc = "N/A"]
#[inline(always)]
pub fn pc(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, MsCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,MsCtl_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Saved protection context. Modifications to this field are constrained by the associated MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1\\[\\] fields."]
#[inline(always)]
pub fn pc_saved(
self,
) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, MsCtl_SPEC, crate::common::RW>
{
crate::common::RegisterField::<16,0xf,1,0,u8,u8,MsCtl_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for MsCtl {
#[inline(always)]
fn default() -> MsCtl {
<crate::RegValueT<MsCtl_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct MsCtlReadMir_SPEC;
impl crate::sealed::RegSpec for MsCtlReadMir_SPEC {
type DataType = u32;
}
#[doc = "Master control read mirror"]
pub type MsCtlReadMir = crate::RegValueT<MsCtlReadMir_SPEC>;
impl MsCtlReadMir {
#[doc = "Read-only mirror of MS_CTL.PC"]
#[inline(always)]
pub fn pc(
self,
) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, MsCtlReadMir_SPEC, crate::common::R>
{
crate::common::RegisterField::<0,0xf,1,0,u8,u8,MsCtlReadMir_SPEC,crate::common::R>::from_register(self,0)
}
#[doc = "Read-only mirror of MS_CTL.PC_SAVED"]
#[inline(always)]
pub fn pc_saved(
self,
) -> crate::common::RegisterField<16, 0xf, 1, 0, u8, u8, MsCtlReadMir_SPEC, crate::common::R>
{
crate::common::RegisterField::<16,0xf,1,0,u8,u8,MsCtlReadMir_SPEC,crate::common::R>::from_register(self,0)
}
}
impl ::core::default::Default for MsCtlReadMir {
#[inline(always)]
fn default() -> MsCtlReadMir {
<crate::RegValueT<MsCtlReadMir_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc = "MPU structure"]
#[non_exhaustive]
pub struct _MpuStruct;
#[doc = "MPU structure"]
pub type MpuStruct = &'static _MpuStruct;
unsafe impl ::core::marker::Sync for _MpuStruct {}
impl _MpuStruct {
#[allow(unused)]
#[inline(always)]
pub(crate) const unsafe fn _svd2pac_from_ptr(ptr: *mut u8) -> &'static Self {
&*(ptr as *const _)
}
#[allow(unused)]
#[inline(always)]
pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
self as *const Self as *mut u8
}
#[doc = "MPU region address"]
#[inline(always)]
pub const fn addr(
&self,
) -> &'static crate::common::Reg<mpu_struct::Addr_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<mpu_struct::Addr_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(0usize),
)
}
}
#[doc = "MPU region attrributes"]
#[inline(always)]
pub const fn att(
&self,
) -> &'static crate::common::Reg<mpu_struct::Att_SPEC, crate::common::RW> {
unsafe {
crate::common::Reg::<mpu_struct::Att_SPEC, crate::common::RW>::from_ptr(
self._svd2pac_as_ptr().add(4usize),
)
}
}
}
pub mod mpu_struct {
#[allow(unused_imports)]
use crate::common::*;
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Addr_SPEC;
impl crate::sealed::RegSpec for Addr_SPEC {
type DataType = u32;
}
#[doc = "MPU region address"]
pub type Addr = crate::RegValueT<Addr_SPEC>;
impl Addr {
#[doc = "This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:\nBit 0: subregion 0 disable.\nBit 1: subregion 1 disable.\nBit 2: subregion 2 disable.\nBit 3: subregion 3 disable.\nBit 4: subregion 4 disable.\nBit 5: subregion 5 disable.\nBit 6: subregion 6 disable.\nBit 7: subregion 7 disable.\nE.g., a 64 KByte address region (REGION_SIZE is \'15\') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B."]
#[inline(always)]
pub fn subregion_disable(
self,
) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Addr_SPEC, crate::common::RW>
{
crate::common::RegisterField::<0,0xff,1,0,u8,u8,Addr_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is \'15\') is 64 KByte aligned, and ADDR24\\[7:0\\] are ignored."]
#[inline(always)]
pub fn addr24(
self,
) -> crate::common::RegisterField<
8,
0xffffff,
1,
0,
u32,
u32,
Addr_SPEC,
crate::common::RW,
> {
crate::common::RegisterField::<
8,
0xffffff,
1,
0,
u32,
u32,
Addr_SPEC,
crate::common::RW,
>::from_register(self, 0)
}
}
impl ::core::default::Default for Addr {
#[inline(always)]
fn default() -> Addr {
<crate::RegValueT<Addr_SPEC> as RegisterValue<_>>::new(0)
}
}
#[doc(hidden)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Att_SPEC;
impl crate::sealed::RegSpec for Att_SPEC {
type DataType = u32;
}
#[doc = "MPU region attrributes"]
pub type Att = crate::RegValueT<Att_SPEC>;
impl Att {
#[doc = "User read enable:\n\'0\': Disabled (user, read accesses are NOT allowed).\n\'1\': Enabled (user, read accesses are allowed)."]
#[inline(always)]
pub fn ur(
self,
) -> crate::common::RegisterFieldBool<0, 1, 0, Att_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<0,1,0,Att_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "User write enable:\n\'0\': Disabled (user, write accesses are NOT allowed).\n\'1\': Enabled (user, write accesses are allowed)."]
#[inline(always)]
pub fn uw(
self,
) -> crate::common::RegisterFieldBool<1, 1, 0, Att_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<1,1,0,Att_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "User execute enable:\n\'0\': Disabled (user, execute accesses are NOT allowed).\n\'1\': Enabled (user, execute accesses are allowed)."]
#[inline(always)]
pub fn ux(
self,
) -> crate::common::RegisterFieldBool<2, 1, 0, Att_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<2,1,0,Att_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Privileged read enable:\n\'0\': Disabled (privileged, read accesses are NOT allowed).\n\'1\': Enabled (privileged, read accesses are allowed)."]
#[inline(always)]
pub fn pr(
self,
) -> crate::common::RegisterFieldBool<3, 1, 0, Att_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<3,1,0,Att_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Privileged write enable:\n\'0\': Disabled (privileged, write accesses are NOT allowed).\n\'1\': Enabled (privileged, write accesses are allowed)."]
#[inline(always)]
pub fn pw(
self,
) -> crate::common::RegisterFieldBool<4, 1, 0, Att_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<4,1,0,Att_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Privileged execute enable:\n\'0\': Disabled (privileged, execute accesses are NOT allowed).\n\'1\': Enabled (privileged, execute accesses are allowed)."]
#[inline(always)]
pub fn px(
self,
) -> crate::common::RegisterFieldBool<5, 1, 0, Att_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<5,1,0,Att_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Non-secure:\n\'0\': Secure (secure accesses allowed, non-secure access NOT allowed).\n\'1\': Non-secure (both secure and non-secure accesses allowed)."]
#[inline(always)]
pub fn ns(
self,
) -> crate::common::RegisterFieldBool<6, 1, 0, Att_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<6,1,0,Att_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "This field specifies the region size:\n\'0\'-\'6\': Undefined.\n\'7\': 256 B region\n\'8\': 512 B region\n\'9\': 1 KB region\n\'10\': 2 KB region\n\'11\': 4 KB region\n\'12\': 8 KB region\n\'13\': 16 KB region\n\'14\': 32 KB region\n\'15\': 64 KB region\n\'16\': 128 KB region\n\'17\': 256 KB region\n\'18\': 512 KB region\n\'19\': 1 MB region\n\'20\': 2 MB region\n\'21\': 4 MB region\n\'22\': 8 MB region\n\'23\': 16 MB region\n\'24\': 32 MB region\n\'25\': 64 MB region\n\'26\': 128 MB region\n\'27\': 256 MB region\n\'28\': 512 MB region\n\'39\': 1 GB region\n\'30\': 2 GB region\n\'31\': 4 GB region"]
#[inline(always)]
pub fn region_size(
self,
) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, Att_SPEC, crate::common::RW>
{
crate::common::RegisterField::<24,0x1f,1,0,u8,u8,Att_SPEC,crate::common::RW>::from_register(self,0)
}
#[doc = "Region enable:\n\'0\': Disabled. A disabled region will never result in a match on the bus transfer address.\n\'1\': Enabled.\n\nNote: a disabled address region performs logic gating to reduce dynamic power consumption."]
#[inline(always)]
pub fn enabled(
self,
) -> crate::common::RegisterFieldBool<31, 1, 0, Att_SPEC, crate::common::RW>
{
crate::common::RegisterFieldBool::<31,1,0,Att_SPEC,crate::common::RW>::from_register(self,0)
}
}
impl ::core::default::Default for Att {
#[inline(always)]
fn default() -> Att {
<crate::RegValueT<Att_SPEC> as RegisterValue<_>>::new(0)
}
}
}
}