esp32c3/spi0/
timing_cali.rs

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1#[doc = "Register `TIMING_CALI` reader"]
2pub type R = crate::R<TIMING_CALI_SPEC>;
3#[doc = "Register `TIMING_CALI` writer"]
4pub type W = crate::W<TIMING_CALI_SPEC>;
5#[doc = "Field `TIMING_CLK_ENA` reader - The bit is used to enable timing adjust clock for all reading operations."]
6pub type TIMING_CLK_ENA_R = crate::BitReader;
7#[doc = "Field `TIMING_CLK_ENA` writer - The bit is used to enable timing adjust clock for all reading operations."]
8pub type TIMING_CLK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TIMING_CALI` reader - The bit is used to enable timing auto-calibration for all reading operations."]
10pub type TIMING_CALI_R = crate::BitReader;
11#[doc = "Field `TIMING_CALI` writer - The bit is used to enable timing auto-calibration for all reading operations."]
12pub type TIMING_CALI_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `EXTRA_DUMMY_CYCLELEN` reader - add extra dummy spi clock cycle length for spi clock calibration."]
14pub type EXTRA_DUMMY_CYCLELEN_R = crate::FieldReader;
15#[doc = "Field `EXTRA_DUMMY_CYCLELEN` writer - add extra dummy spi clock cycle length for spi clock calibration."]
16pub type EXTRA_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17impl R {
18    #[doc = "Bit 0 - The bit is used to enable timing adjust clock for all reading operations."]
19    #[inline(always)]
20    pub fn timing_clk_ena(&self) -> TIMING_CLK_ENA_R {
21        TIMING_CLK_ENA_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."]
24    #[inline(always)]
25    pub fn timing_cali(&self) -> TIMING_CALI_R {
26        TIMING_CALI_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bits 2:4 - add extra dummy spi clock cycle length for spi clock calibration."]
29    #[inline(always)]
30    pub fn extra_dummy_cyclelen(&self) -> EXTRA_DUMMY_CYCLELEN_R {
31        EXTRA_DUMMY_CYCLELEN_R::new(((self.bits >> 2) & 7) as u8)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("TIMING_CALI")
38            .field("timing_clk_ena", &self.timing_clk_ena())
39            .field("timing_cali", &self.timing_cali())
40            .field("extra_dummy_cyclelen", &self.extra_dummy_cyclelen())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bit 0 - The bit is used to enable timing adjust clock for all reading operations."]
46    #[inline(always)]
47    pub fn timing_clk_ena(&mut self) -> TIMING_CLK_ENA_W<TIMING_CALI_SPEC> {
48        TIMING_CLK_ENA_W::new(self, 0)
49    }
50    #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."]
51    #[inline(always)]
52    pub fn timing_cali(&mut self) -> TIMING_CALI_W<TIMING_CALI_SPEC> {
53        TIMING_CALI_W::new(self, 1)
54    }
55    #[doc = "Bits 2:4 - add extra dummy spi clock cycle length for spi clock calibration."]
56    #[inline(always)]
57    pub fn extra_dummy_cyclelen(&mut self) -> EXTRA_DUMMY_CYCLELEN_W<TIMING_CALI_SPEC> {
58        EXTRA_DUMMY_CYCLELEN_W::new(self, 2)
59    }
60}
61#[doc = "SPI0 timing calibration register\n\nYou can [`read`](crate::Reg::read) this register and get [`timing_cali::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timing_cali::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct TIMING_CALI_SPEC;
63impl crate::RegisterSpec for TIMING_CALI_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`timing_cali::R`](R) reader structure"]
67impl crate::Readable for TIMING_CALI_SPEC {}
68#[doc = "`write(|w| ..)` method takes [`timing_cali::W`](W) writer structure"]
69impl crate::Writable for TIMING_CALI_SPEC {
70    type Safety = crate::Unsafe;
71    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
73}
74#[doc = "`reset()` method sets TIMING_CALI to value 0x01"]
75impl crate::Resettable for TIMING_CALI_SPEC {
76    const RESET_VALUE: u32 = 0x01;
77}
esp32c3/spi0/timing_cali.rs

esp32c3/spi0/
timing_cali.rs
