esp32c3/apb_saradc/
clkm_conf.rs

1#[doc = "Register `CLKM_CONF` reader"]
2pub type R = crate::R<CLKM_CONF_SPEC>;
3#[doc = "Register `CLKM_CONF` writer"]
4pub type W = crate::W<CLKM_CONF_SPEC>;
5#[doc = "Field `CLKM_DIV_NUM` reader - Integral I2S clock divider value"]
6pub type CLKM_DIV_NUM_R = crate::FieldReader;
7#[doc = "Field `CLKM_DIV_NUM` writer - Integral I2S clock divider value"]
8pub type CLKM_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `CLKM_DIV_B` reader - Fractional clock divider numerator value"]
10pub type CLKM_DIV_B_R = crate::FieldReader;
11#[doc = "Field `CLKM_DIV_B` writer - Fractional clock divider numerator value"]
12pub type CLKM_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `CLKM_DIV_A` reader - Fractional clock divider denominator value"]
14pub type CLKM_DIV_A_R = crate::FieldReader;
15#[doc = "Field `CLKM_DIV_A` writer - Fractional clock divider denominator value"]
16pub type CLKM_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
17#[doc = "Field `CLK_EN` reader - reg clk en"]
18pub type CLK_EN_R = crate::BitReader;
19#[doc = "Field `CLK_EN` writer - reg clk en"]
20pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CLK_SEL` reader - Set this bit to enable clk_apll"]
22pub type CLK_SEL_R = crate::FieldReader;
23#[doc = "Field `CLK_SEL` writer - Set this bit to enable clk_apll"]
24pub type CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25impl R {
26    #[doc = "Bits 0:7 - Integral I2S clock divider value"]
27    #[inline(always)]
28    pub fn clkm_div_num(&self) -> CLKM_DIV_NUM_R {
29        CLKM_DIV_NUM_R::new((self.bits & 0xff) as u8)
30    }
31    #[doc = "Bits 8:13 - Fractional clock divider numerator value"]
32    #[inline(always)]
33    pub fn clkm_div_b(&self) -> CLKM_DIV_B_R {
34        CLKM_DIV_B_R::new(((self.bits >> 8) & 0x3f) as u8)
35    }
36    #[doc = "Bits 14:19 - Fractional clock divider denominator value"]
37    #[inline(always)]
38    pub fn clkm_div_a(&self) -> CLKM_DIV_A_R {
39        CLKM_DIV_A_R::new(((self.bits >> 14) & 0x3f) as u8)
40    }
41    #[doc = "Bit 20 - reg clk en"]
42    #[inline(always)]
43    pub fn clk_en(&self) -> CLK_EN_R {
44        CLK_EN_R::new(((self.bits >> 20) & 1) != 0)
45    }
46    #[doc = "Bits 21:22 - Set this bit to enable clk_apll"]
47    #[inline(always)]
48    pub fn clk_sel(&self) -> CLK_SEL_R {
49        CLK_SEL_R::new(((self.bits >> 21) & 3) as u8)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("CLKM_CONF")
56            .field("clkm_div_num", &self.clkm_div_num())
57            .field("clkm_div_b", &self.clkm_div_b())
58            .field("clkm_div_a", &self.clkm_div_a())
59            .field("clk_en", &self.clk_en())
60            .field("clk_sel", &self.clk_sel())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bits 0:7 - Integral I2S clock divider value"]
66    #[inline(always)]
67    pub fn clkm_div_num(&mut self) -> CLKM_DIV_NUM_W<CLKM_CONF_SPEC> {
68        CLKM_DIV_NUM_W::new(self, 0)
69    }
70    #[doc = "Bits 8:13 - Fractional clock divider numerator value"]
71    #[inline(always)]
72    pub fn clkm_div_b(&mut self) -> CLKM_DIV_B_W<CLKM_CONF_SPEC> {
73        CLKM_DIV_B_W::new(self, 8)
74    }
75    #[doc = "Bits 14:19 - Fractional clock divider denominator value"]
76    #[inline(always)]
77    pub fn clkm_div_a(&mut self) -> CLKM_DIV_A_W<CLKM_CONF_SPEC> {
78        CLKM_DIV_A_W::new(self, 14)
79    }
80    #[doc = "Bit 20 - reg clk en"]
81    #[inline(always)]
82    pub fn clk_en(&mut self) -> CLK_EN_W<CLKM_CONF_SPEC> {
83        CLK_EN_W::new(self, 20)
84    }
85    #[doc = "Bits 21:22 - Set this bit to enable clk_apll"]
86    #[inline(always)]
87    pub fn clk_sel(&mut self) -> CLK_SEL_W<CLKM_CONF_SPEC> {
88        CLK_SEL_W::new(self, 21)
89    }
90}
91#[doc = "digital saradc configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkm_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkm_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct CLKM_CONF_SPEC;
93impl crate::RegisterSpec for CLKM_CONF_SPEC {
94    type Ux = u32;
95}
96#[doc = "`read()` method returns [`clkm_conf::R`](R) reader structure"]
97impl crate::Readable for CLKM_CONF_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`clkm_conf::W`](W) writer structure"]
99impl crate::Writable for CLKM_CONF_SPEC {
100    type Safety = crate::Unsafe;
101}
102#[doc = "`reset()` method sets CLKM_CONF to value 0x04"]
103impl crate::Resettable for CLKM_CONF_SPEC {
104    const RESET_VALUE: u32 = 0x04;
105}
esp32c3/apb_saradc/clkm_conf.rs

esp32c3/apb_saradc/
clkm_conf.rs
