1#[doc = "Register `DOUT_MODE` reader"]
2pub type R = crate::R<DOUT_MODE_SPEC>;
3#[doc = "Register `DOUT_MODE` writer"]
4pub type W = crate::W<DOUT_MODE_SPEC>;
5#[doc = "Field `DOUT0_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
6pub type DOUT0_MODE_R = crate::BitReader;
7#[doc = "Field `DOUT0_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
8pub type DOUT0_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DOUT1_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
10pub type DOUT1_MODE_R = crate::BitReader;
11#[doc = "Field `DOUT1_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
12pub type DOUT1_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `DOUT2_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
14pub type DOUT2_MODE_R = crate::BitReader;
15#[doc = "Field `DOUT2_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
16pub type DOUT2_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DOUT3_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
18pub type DOUT3_MODE_R = crate::BitReader;
19#[doc = "Field `DOUT3_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
20pub type DOUT3_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22 #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
23 #[inline(always)]
24 pub fn dout0_mode(&self) -> DOUT0_MODE_R {
25 DOUT0_MODE_R::new((self.bits & 1) != 0)
26 }
27 #[doc = "Bit 1 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
28 #[inline(always)]
29 pub fn dout1_mode(&self) -> DOUT1_MODE_R {
30 DOUT1_MODE_R::new(((self.bits >> 1) & 1) != 0)
31 }
32 #[doc = "Bit 2 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
33 #[inline(always)]
34 pub fn dout2_mode(&self) -> DOUT2_MODE_R {
35 DOUT2_MODE_R::new(((self.bits >> 2) & 1) != 0)
36 }
37 #[doc = "Bit 3 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
38 #[inline(always)]
39 pub fn dout3_mode(&self) -> DOUT3_MODE_R {
40 DOUT3_MODE_R::new(((self.bits >> 3) & 1) != 0)
41 }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46 f.debug_struct("DOUT_MODE")
47 .field("dout0_mode", &self.dout0_mode())
48 .field("dout1_mode", &self.dout1_mode())
49 .field("dout2_mode", &self.dout2_mode())
50 .field("dout3_mode", &self.dout3_mode())
51 .finish()
52 }
53}
54impl W {
55 #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
56 #[inline(always)]
57 pub fn dout0_mode(&mut self) -> DOUT0_MODE_W<DOUT_MODE_SPEC> {
58 DOUT0_MODE_W::new(self, 0)
59 }
60 #[doc = "Bit 1 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
61 #[inline(always)]
62 pub fn dout1_mode(&mut self) -> DOUT1_MODE_W<DOUT_MODE_SPEC> {
63 DOUT1_MODE_W::new(self, 1)
64 }
65 #[doc = "Bit 2 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
66 #[inline(always)]
67 pub fn dout2_mode(&mut self) -> DOUT2_MODE_W<DOUT_MODE_SPEC> {
68 DOUT2_MODE_W::new(self, 2)
69 }
70 #[doc = "Bit 3 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
71 #[inline(always)]
72 pub fn dout3_mode(&mut self) -> DOUT3_MODE_W<DOUT_MODE_SPEC> {
73 DOUT3_MODE_W::new(self, 3)
74 }
75}
76#[doc = "SPI0 output delay mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dout_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dout_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct DOUT_MODE_SPEC;
78impl crate::RegisterSpec for DOUT_MODE_SPEC {
79 type Ux = u32;
80}
81#[doc = "`read()` method returns [`dout_mode::R`](R) reader structure"]
82impl crate::Readable for DOUT_MODE_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`dout_mode::W`](W) writer structure"]
84impl crate::Writable for DOUT_MODE_SPEC {
85 type Safety = crate::Unsafe;
86 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
87 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88}
89#[doc = "`reset()` method sets DOUT_MODE to value 0"]
90impl crate::Resettable for DOUT_MODE_SPEC {
91 const RESET_VALUE: u32 = 0;
92}