esp32c3/extmem/
icache_prelock_sct1_addr.rs

1#[doc = "Register `ICACHE_PRELOCK_SCT1_ADDR` reader"]
2pub type R = crate::R<ICACHE_PRELOCK_SCT1_ADDR_SPEC>;
3#[doc = "Register `ICACHE_PRELOCK_SCT1_ADDR` writer"]
4pub type W = crate::W<ICACHE_PRELOCK_SCT1_ADDR_SPEC>;
5#[doc = "Field `ICACHE_PRELOCK_SCT1_ADDR` reader - The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG"]
6pub type ICACHE_PRELOCK_SCT1_ADDR_R = crate::FieldReader<u32>;
7#[doc = "Field `ICACHE_PRELOCK_SCT1_ADDR` writer - The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG"]
8pub type ICACHE_PRELOCK_SCT1_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31 - The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG"]
11    #[inline(always)]
12    pub fn icache_prelock_sct1_addr(&self) -> ICACHE_PRELOCK_SCT1_ADDR_R {
13        ICACHE_PRELOCK_SCT1_ADDR_R::new(self.bits)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("ICACHE_PRELOCK_SCT1_ADDR")
20            .field("icache_prelock_sct1_addr", &self.icache_prelock_sct1_addr())
21            .finish()
22    }
23}
24impl W {
25    #[doc = "Bits 0:31 - The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG"]
26    #[inline(always)]
27    pub fn icache_prelock_sct1_addr(
28        &mut self,
29    ) -> ICACHE_PRELOCK_SCT1_ADDR_W<ICACHE_PRELOCK_SCT1_ADDR_SPEC> {
30        ICACHE_PRELOCK_SCT1_ADDR_W::new(self, 0)
31    }
32}
33#[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_prelock_sct1_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_prelock_sct1_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
34pub struct ICACHE_PRELOCK_SCT1_ADDR_SPEC;
35impl crate::RegisterSpec for ICACHE_PRELOCK_SCT1_ADDR_SPEC {
36    type Ux = u32;
37}
38#[doc = "`read()` method returns [`icache_prelock_sct1_addr::R`](R) reader structure"]
39impl crate::Readable for ICACHE_PRELOCK_SCT1_ADDR_SPEC {}
40#[doc = "`write(|w| ..)` method takes [`icache_prelock_sct1_addr::W`](W) writer structure"]
41impl crate::Writable for ICACHE_PRELOCK_SCT1_ADDR_SPEC {
42    type Safety = crate::Unsafe;
43}
44#[doc = "`reset()` method sets ICACHE_PRELOCK_SCT1_ADDR to value 0"]
45impl crate::Resettable for ICACHE_PRELOCK_SCT1_ADDR_SPEC {}
esp32c3/extmem/icache_prelock_sct1_addr.rs

esp32c3/extmem/
icache_prelock_sct1_addr.rs
