esp32c3/apb_saradc/
thres_ctrl.rs

1#[doc = "Register `THRES_CTRL` reader"]
2pub type R = crate::R<THRES_CTRL_SPEC>;
3#[doc = "Register `THRES_CTRL` writer"]
4pub type W = crate::W<THRES_CTRL_SPEC>;
5#[doc = "Field `THRES_ALL_EN` reader - enable thres to all channel"]
6pub type THRES_ALL_EN_R = crate::BitReader;
7#[doc = "Field `THRES_ALL_EN` writer - enable thres to all channel"]
8pub type THRES_ALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `THRES1_EN` reader - enable thres1"]
10pub type THRES1_EN_R = crate::BitReader;
11#[doc = "Field `THRES1_EN` writer - enable thres1"]
12pub type THRES1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `THRES0_EN` reader - enable thres0"]
14pub type THRES0_EN_R = crate::BitReader;
15#[doc = "Field `THRES0_EN` writer - enable thres0"]
16pub type THRES0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 27 - enable thres to all channel"]
19    #[inline(always)]
20    pub fn thres_all_en(&self) -> THRES_ALL_EN_R {
21        THRES_ALL_EN_R::new(((self.bits >> 27) & 1) != 0)
22    }
23    #[doc = "Bit 30 - enable thres1"]
24    #[inline(always)]
25    pub fn thres1_en(&self) -> THRES1_EN_R {
26        THRES1_EN_R::new(((self.bits >> 30) & 1) != 0)
27    }
28    #[doc = "Bit 31 - enable thres0"]
29    #[inline(always)]
30    pub fn thres0_en(&self) -> THRES0_EN_R {
31        THRES0_EN_R::new(((self.bits >> 31) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("THRES_CTRL")
38            .field("thres_all_en", &self.thres_all_en())
39            .field("thres1_en", &self.thres1_en())
40            .field("thres0_en", &self.thres0_en())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bit 27 - enable thres to all channel"]
46    #[inline(always)]
47    pub fn thres_all_en(&mut self) -> THRES_ALL_EN_W<THRES_CTRL_SPEC> {
48        THRES_ALL_EN_W::new(self, 27)
49    }
50    #[doc = "Bit 30 - enable thres1"]
51    #[inline(always)]
52    pub fn thres1_en(&mut self) -> THRES1_EN_W<THRES_CTRL_SPEC> {
53        THRES1_EN_W::new(self, 30)
54    }
55    #[doc = "Bit 31 - enable thres0"]
56    #[inline(always)]
57    pub fn thres0_en(&mut self) -> THRES0_EN_W<THRES_CTRL_SPEC> {
58        THRES0_EN_W::new(self, 31)
59    }
60}
61#[doc = "digital saradc configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`thres_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`thres_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct THRES_CTRL_SPEC;
63impl crate::RegisterSpec for THRES_CTRL_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`thres_ctrl::R`](R) reader structure"]
67impl crate::Readable for THRES_CTRL_SPEC {}
68#[doc = "`write(|w| ..)` method takes [`thres_ctrl::W`](W) writer structure"]
69impl crate::Writable for THRES_CTRL_SPEC {
70    type Safety = crate::Unsafe;
71    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
73}
74#[doc = "`reset()` method sets THRES_CTRL to value 0"]
75impl crate::Resettable for THRES_CTRL_SPEC {
76    const RESET_VALUE: u32 = 0;
77}
esp32c3/apb_saradc/thres_ctrl.rs

esp32c3/apb_saradc/
thres_ctrl.rs
