esp32c3/extmem/
cache_ilg_int_st.rs

1#[doc = "Register `CACHE_ILG_INT_ST` reader"]
2pub type R = crate::R<CACHE_ILG_INT_ST_SPEC>;
3#[doc = "Field `ICACHE_SYNC_OP_FAULT` reader - The bit is used to indicate interrupt by sync configurations fault."]
4pub type ICACHE_SYNC_OP_FAULT_R = crate::BitReader;
5#[doc = "Field `ICACHE_PRELOAD_OP_FAULT` reader - The bit is used to indicate interrupt by preload configurations fault."]
6pub type ICACHE_PRELOAD_OP_FAULT_R = crate::BitReader;
7#[doc = "Field `MMU_ENTRY_FAULT` reader - The bit is used to indicate interrupt by mmu entry fault."]
8pub type MMU_ENTRY_FAULT_R = crate::BitReader;
9#[doc = "Field `IBUS_ACS_CNT_OVF` reader - The bit is used to indicate interrupt by ibus access flash/spiram counter overflow."]
10pub type IBUS_ACS_CNT_OVF_R = crate::BitReader;
11#[doc = "Field `IBUS_ACS_MISS_CNT_OVF` reader - The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow."]
12pub type IBUS_ACS_MISS_CNT_OVF_R = crate::BitReader;
13#[doc = "Field `DBUS_ACS_CNT_OVF` reader - The bit is used to indicate interrupt by dbus access flash/spiram counter overflow."]
14pub type DBUS_ACS_CNT_OVF_R = crate::BitReader;
15#[doc = "Field `DBUS_ACS_FLASH_MISS_CNT_OVF` reader - The bit is used to indicate interrupt by dbus access flash miss counter overflow."]
16pub type DBUS_ACS_FLASH_MISS_CNT_OVF_R = crate::BitReader;
17impl R {
18    #[doc = "Bit 0 - The bit is used to indicate interrupt by sync configurations fault."]
19    #[inline(always)]
20    pub fn icache_sync_op_fault(&self) -> ICACHE_SYNC_OP_FAULT_R {
21        ICACHE_SYNC_OP_FAULT_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - The bit is used to indicate interrupt by preload configurations fault."]
24    #[inline(always)]
25    pub fn icache_preload_op_fault(&self) -> ICACHE_PRELOAD_OP_FAULT_R {
26        ICACHE_PRELOAD_OP_FAULT_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bit 5 - The bit is used to indicate interrupt by mmu entry fault."]
29    #[inline(always)]
30    pub fn mmu_entry_fault(&self) -> MMU_ENTRY_FAULT_R {
31        MMU_ENTRY_FAULT_R::new(((self.bits >> 5) & 1) != 0)
32    }
33    #[doc = "Bit 7 - The bit is used to indicate interrupt by ibus access flash/spiram counter overflow."]
34    #[inline(always)]
35    pub fn ibus_acs_cnt_ovf(&self) -> IBUS_ACS_CNT_OVF_R {
36        IBUS_ACS_CNT_OVF_R::new(((self.bits >> 7) & 1) != 0)
37    }
38    #[doc = "Bit 8 - The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow."]
39    #[inline(always)]
40    pub fn ibus_acs_miss_cnt_ovf(&self) -> IBUS_ACS_MISS_CNT_OVF_R {
41        IBUS_ACS_MISS_CNT_OVF_R::new(((self.bits >> 8) & 1) != 0)
42    }
43    #[doc = "Bit 9 - The bit is used to indicate interrupt by dbus access flash/spiram counter overflow."]
44    #[inline(always)]
45    pub fn dbus_acs_cnt_ovf(&self) -> DBUS_ACS_CNT_OVF_R {
46        DBUS_ACS_CNT_OVF_R::new(((self.bits >> 9) & 1) != 0)
47    }
48    #[doc = "Bit 10 - The bit is used to indicate interrupt by dbus access flash miss counter overflow."]
49    #[inline(always)]
50    pub fn dbus_acs_flash_miss_cnt_ovf(&self) -> DBUS_ACS_FLASH_MISS_CNT_OVF_R {
51        DBUS_ACS_FLASH_MISS_CNT_OVF_R::new(((self.bits >> 10) & 1) != 0)
52    }
53}
54#[cfg(feature = "impl-register-debug")]
55impl core::fmt::Debug for R {
56    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
57        f.debug_struct("CACHE_ILG_INT_ST")
58            .field("icache_sync_op_fault", &self.icache_sync_op_fault())
59            .field("icache_preload_op_fault", &self.icache_preload_op_fault())
60            .field("mmu_entry_fault", &self.mmu_entry_fault())
61            .field("ibus_acs_cnt_ovf", &self.ibus_acs_cnt_ovf())
62            .field("ibus_acs_miss_cnt_ovf", &self.ibus_acs_miss_cnt_ovf())
63            .field("dbus_acs_cnt_ovf", &self.dbus_acs_cnt_ovf())
64            .field(
65                "dbus_acs_flash_miss_cnt_ovf",
66                &self.dbus_acs_flash_miss_cnt_ovf(),
67            )
68            .finish()
69    }
70}
71#[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_ilg_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
72pub struct CACHE_ILG_INT_ST_SPEC;
73impl crate::RegisterSpec for CACHE_ILG_INT_ST_SPEC {
74    type Ux = u32;
75}
76#[doc = "`read()` method returns [`cache_ilg_int_st::R`](R) reader structure"]
77impl crate::Readable for CACHE_ILG_INT_ST_SPEC {}
78#[doc = "`reset()` method sets CACHE_ILG_INT_ST to value 0"]
79impl crate::Resettable for CACHE_ILG_INT_ST_SPEC {
80    const RESET_VALUE: u32 = 0;
81}
esp32c3/extmem/cache_ilg_int_st.rs

esp32c3/extmem/
cache_ilg_int_st.rs
