esp32c3/spi1/
int_ena.rs

1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `PER_END` reader - The enable bit for SPI_MEM_PER_END_INT interrupt."]
6pub type PER_END_R = crate::BitReader;
7#[doc = "Field `PER_END` writer - The enable bit for SPI_MEM_PER_END_INT interrupt."]
8pub type PER_END_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PES_END` reader - The enable bit for SPI_MEM_PES_END_INT interrupt."]
10pub type PES_END_R = crate::BitReader;
11#[doc = "Field `PES_END` writer - The enable bit for SPI_MEM_PES_END_INT interrupt."]
12pub type PES_END_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `WPE_END` reader - The enable bit for SPI_MEM_WPE_END_INT interrupt."]
14pub type WPE_END_R = crate::BitReader;
15#[doc = "Field `WPE_END` writer - The enable bit for SPI_MEM_WPE_END_INT interrupt."]
16pub type WPE_END_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SLV_ST_END` reader - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."]
18pub type SLV_ST_END_R = crate::BitReader;
19#[doc = "Field `SLV_ST_END` writer - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."]
20pub type SLV_ST_END_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `MST_ST_END` reader - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."]
22pub type MST_ST_END_R = crate::BitReader;
23#[doc = "Field `MST_ST_END` writer - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."]
24pub type MST_ST_END_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bit 0 - The enable bit for SPI_MEM_PER_END_INT interrupt."]
27    #[inline(always)]
28    pub fn per_end(&self) -> PER_END_R {
29        PER_END_R::new((self.bits & 1) != 0)
30    }
31    #[doc = "Bit 1 - The enable bit for SPI_MEM_PES_END_INT interrupt."]
32    #[inline(always)]
33    pub fn pes_end(&self) -> PES_END_R {
34        PES_END_R::new(((self.bits >> 1) & 1) != 0)
35    }
36    #[doc = "Bit 2 - The enable bit for SPI_MEM_WPE_END_INT interrupt."]
37    #[inline(always)]
38    pub fn wpe_end(&self) -> WPE_END_R {
39        WPE_END_R::new(((self.bits >> 2) & 1) != 0)
40    }
41    #[doc = "Bit 3 - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."]
42    #[inline(always)]
43    pub fn slv_st_end(&self) -> SLV_ST_END_R {
44        SLV_ST_END_R::new(((self.bits >> 3) & 1) != 0)
45    }
46    #[doc = "Bit 4 - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."]
47    #[inline(always)]
48    pub fn mst_st_end(&self) -> MST_ST_END_R {
49        MST_ST_END_R::new(((self.bits >> 4) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("INT_ENA")
56            .field("per_end", &self.per_end())
57            .field("pes_end", &self.pes_end())
58            .field("wpe_end", &self.wpe_end())
59            .field("slv_st_end", &self.slv_st_end())
60            .field("mst_st_end", &self.mst_st_end())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bit 0 - The enable bit for SPI_MEM_PER_END_INT interrupt."]
66    #[inline(always)]
67    pub fn per_end(&mut self) -> PER_END_W<INT_ENA_SPEC> {
68        PER_END_W::new(self, 0)
69    }
70    #[doc = "Bit 1 - The enable bit for SPI_MEM_PES_END_INT interrupt."]
71    #[inline(always)]
72    pub fn pes_end(&mut self) -> PES_END_W<INT_ENA_SPEC> {
73        PES_END_W::new(self, 1)
74    }
75    #[doc = "Bit 2 - The enable bit for SPI_MEM_WPE_END_INT interrupt."]
76    #[inline(always)]
77    pub fn wpe_end(&mut self) -> WPE_END_W<INT_ENA_SPEC> {
78        WPE_END_W::new(self, 2)
79    }
80    #[doc = "Bit 3 - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."]
81    #[inline(always)]
82    pub fn slv_st_end(&mut self) -> SLV_ST_END_W<INT_ENA_SPEC> {
83        SLV_ST_END_W::new(self, 3)
84    }
85    #[doc = "Bit 4 - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."]
86    #[inline(always)]
87    pub fn mst_st_end(&mut self) -> MST_ST_END_W<INT_ENA_SPEC> {
88        MST_ST_END_W::new(self, 4)
89    }
90}
91#[doc = "SPI1 interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct INT_ENA_SPEC;
93impl crate::RegisterSpec for INT_ENA_SPEC {
94    type Ux = u32;
95}
96#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
97impl crate::Readable for INT_ENA_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
99impl crate::Writable for INT_ENA_SPEC {
100    type Safety = crate::Unsafe;
101    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
102    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
103}
104#[doc = "`reset()` method sets INT_ENA to value 0"]
105impl crate::Resettable for INT_ENA_SPEC {
106    const RESET_VALUE: u32 = 0;
107}
esp32c3/spi1/int_ena.rs

esp32c3/spi1/
int_ena.rs
