esp32c3/extmem/
icache_ctrl.rs

1#[doc = "Register `ICACHE_CTRL` reader"]
2pub type R = crate::R<ICACHE_CTRL_SPEC>;
3#[doc = "Register `ICACHE_CTRL` writer"]
4pub type W = crate::W<ICACHE_CTRL_SPEC>;
5#[doc = "Field `ICACHE_ENABLE` reader - The bit is used to activate the data cache. 0: disable, 1: enable"]
6pub type ICACHE_ENABLE_R = crate::BitReader;
7#[doc = "Field `ICACHE_ENABLE` writer - The bit is used to activate the data cache. 0: disable, 1: enable"]
8pub type ICACHE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
9impl R {
10    #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
11    #[inline(always)]
12    pub fn icache_enable(&self) -> ICACHE_ENABLE_R {
13        ICACHE_ENABLE_R::new((self.bits & 1) != 0)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("ICACHE_CTRL")
20            .field("icache_enable", &self.icache_enable())
21            .finish()
22    }
23}
24impl W {
25    #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
26    #[inline(always)]
27    pub fn icache_enable(&mut self) -> ICACHE_ENABLE_W<ICACHE_CTRL_SPEC> {
28        ICACHE_ENABLE_W::new(self, 0)
29    }
30}
31#[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32pub struct ICACHE_CTRL_SPEC;
33impl crate::RegisterSpec for ICACHE_CTRL_SPEC {
34    type Ux = u32;
35}
36#[doc = "`read()` method returns [`icache_ctrl::R`](R) reader structure"]
37impl crate::Readable for ICACHE_CTRL_SPEC {}
38#[doc = "`write(|w| ..)` method takes [`icache_ctrl::W`](W) writer structure"]
39impl crate::Writable for ICACHE_CTRL_SPEC {
40    type Safety = crate::Unsafe;
41    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
42    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
43}
44#[doc = "`reset()` method sets ICACHE_CTRL to value 0"]
45impl crate::Resettable for ICACHE_CTRL_SPEC {
46    const RESET_VALUE: u32 = 0;
47}
esp32c3/extmem/icache_ctrl.rs

esp32c3/extmem/
icache_ctrl.rs
